Microchip MCP4341T502E/ML 7/8-bit quad spi digital pot with non-volatile memory Datasheet

MCP434X/436X
7/8-Bit Quad SPI Digital POT with
Non-Volatile Memory
© 2009 Microchip Technology Inc.
MCP43X1 Quad Potentiometers
P3A
P3W
P3B
CS
SCK
SDI
VSS
P1B
P1W
P1A
P2A
P2W
P2B
VDD
SDO
RESET
WP
P0B
P0W
P0A
20
19
18
17
16
15
14
12
12
11
1
2
3
4
5
6
7
8
9
10
P2B
P2W
P3A
P2A
P3W
TSSOP
20 19 18 17 16
1
SDI
4
VSS
5
EP
21
6
7
8
9 10
P0A
2
3
VDD
13
RESET
12
WP
11
P0B
P0W
CS
SCK
15
14 SDO
P1A
P3B
P1B
• Quad Resistor Network
• Potentiometer or Rheostat configuration options
• Resistor Network Resolution
- 7-bit: 128 Resistors (129 Taps)
- 8-bit: 256 Resistors (257 Taps)
• RAB Resistances options of:
- 5 kΩ
- 10 kΩ
- 50 kΩ
- 100 kΩ
• Zero Scale to Full Scale Wiper operation
• Low Wiper Resistance: 75 Ω (typical)
• Low Tempco:
- Absolute (Rheostat): 50 ppm typical
(0°C to 70°C)
- Ratiometric (Potentiometer): 15 ppm typical
• Non-volatile Memory
- Automatic Recall of Saved Wiper Setting
- WiperLock™ Technology
• SPI serial interface (10 MHz, modes 0,0 & 1,1)
- High-Speed Read/Writes to wiper registers
- Read/Write to Data EEPROM registers
- Serially enabled EEPROM write protect
• Resistor Network Terminal Disconnect Feature
via Terminal Control (TCON) Register
• Reset input pin
• Write Protect Feature:
- Hardware Write Protect (WP) Control pin
- Software Write Protect (WP) Configuration bit
• Brown-out reset protection (1.5V typical)
• Serial Interface Inactive current (2.5 uA typical)
• High-Voltage Tolerant Digital Inputs: Up to 12.5V
• Supports Split Rail Applications
• Internal weak pull-up on all digital inputs
• Wide Operating Voltage:
- 2.7V to 5.5V - Device Characteristics
Specified
- 1.8V to 5.5V - Device Operation
• Wide Bandwidth (-3 dB) Operation:
- 2 MHz (typical) for 5.0 kΩ device
• Extended temperature range (-40°C to +125°C)
Package Types (Top View)
P1W
Features
4x4 QFN
MCP43X2 Quad Rheostat
P3W
P3B
CS
SCK
SDI
VSS
P1B
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P2W
P2B
VDD
SDO
P0B
P0W
P1W
TSSOP
DS22233A-page 1
MCP434X/436X
Device Block Diagram
VDD
VSS
CS
SCK
SDI
SDO
WP
RESET
Power-up/
Brown-out
Control
Resistor
Network 0
(Pot 0)
SPI Serial
Interface
Module &
Control
Logic
(WiperLock™
Technology)
Wiper 0
& TCON0
Register
P0A
P0W
P0B
P1A
Resistor
Network 1
(Pot 1)
P1W
Wiper 1
& TCON0
Register
Memory (16x9)
Wiper0 (V & NV)
Wiper1 (V & NV)
Wiper2 (V & NV)
Wiper3 (V & NV)
P1B
P2A
Resistor
Network 2
(Pot 2)
TCON0
TCON1
STATUS
Data EEPROM
(5 x 9-bits)
P2W
Wiper 2
& TCON1
Register
P2B
P3A
Resistor
Network 3
(Pot 3)
P3W
Wiper 3
& TCON1
Register
P3B
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
129 1.8V to 5.5V
4
Rheostat
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
129 1.8V to 5.5V
MCP4341
4
Potentiometer (1)
SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
129 2.7V to 5.5V
MCP4342
4
Rheostat
SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
129 2.7V to 5.5V
MCP4351 (3)
4
Potentiometer (1)
SPI
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
257 1.8V to 5.5V
MCP4352 (3)
4
Rheostat
SPI
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
257 1.8V to 5.5V
MCP4361
4
Potentiometer (1)
SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
257 2.7V to 5.5V
MCP4362
4
Rheostat
SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
257 2.7V to 5.5V
Note 1:
2:
3:
SPI
Resistance (typical)
RAB Options (kΩ)
Wiper
- RW
(Ω)
# of Taps
WiperLock
Technology
4 Potentiometer (1) SPI
MCP4332 (3)
Device
Wiper
Configuration
POR Wiper
Setting
Memory
Type
MCP4331 (3)
# of POTs
Control
Interface
Device Features
VDD
Operating
Range (2)
Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).
Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted.
Please check Microchip web site for device release and availability.
DS22233A-page 2
© 2009 Microchip Technology Inc.
MCP434X/436X
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Voltage on VDD with respect to VSS ................ -0.6V to +7.0V
Voltage on CS, SCK, SDI, SDI/SDO, WP, and
RESET with respect to VSS ................................... -0.6V to 12.5V
Voltage on all other pins (PxA, PxW, PxB, and
SDO) with respect to VSS ............................ -0.3V to VDD + 0.3V
Input clamp current, IIK
(VI < 0, VI > VDD, VI > VPP ON HV pins) ......................±20 mA
Output clamp current, IOK
(VO < 0 or VO > VDD) ..................................................±20 mA
Maximum output current sunk by any Output pin
......................................................................................25 mA
Maximum output current sourced by any Output pin
......................................................................................25 mA
Maximum current out of VSS pin .................................100 mA
Maximum current into VDD pin ....................................100 mA
Maximum current into PXA, PXW & PXB pins ............±2.5 mA
Storage temperature ....................................-65°C to +150°C
Ambient temperature with power applied
.....................................................................-40°C to +125°C
Package power dissipation (TA = +50°C, TJ = +150°C)
TSSOP-14................................................................1000 mW
TSSOP-20................................................................ 1110 mW
QFN-20 (4x4) ...........................................................2320 mW
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins ................................... ≥ 4 kV (HBM),
.......................................................................... ≥ 300V (MM)
Maximum Junction Temperature (TJ) ......................... +150°C
© 2009 Microchip Technology Inc.
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
DS22233A-page 3
MCP434X/436X
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Supply Voltage
VDD
2.7
—
5.5
V
1.8
—
2.7
V
Serial Interface only.
VSS
—
12.5V
V
VDD ≥
4.5V
VSS
—
VDD +
8.0V
V
VDD <
4.5V
—
—
1.65
V
RAM retention voltage (VRAM) < VBOR
CS, SDI, SDO,
SCK, WP, RESET
pin Voltage Range
VHV
VDD Start Voltage
to ensure Wiper
Reset
VBOR
VDD Rise Rate to
ensure Power-on
Reset
VDDRR
Delay after device
exits the reset
state
(VDD > VBOR)
TBORD
—
10
20
µs
IDD
—
—
450
µA
Serial Interface Active,
VDD = 5.5V, CS = VIL, SCK @ 5 MHz,
write all 0’s to volatile Wiper 0 (address
0h)
—
—
1
mA
EE Write Current,
VDD = 5.5V, CS = VIL, SCK @ 5 MHz,
write all 0’s to non-volatile Wiper 0
(address 2h)
—
2.5
5
µA
Serial Interface Inactive,
CS = VIH, VDD = 5.5V
—
0.55
1
mA
Serial Interface Active,
VDD = 5.5V, CS = VIHH,
SCK @ 5 MHz,
decrement non-volatile Wiper 0
(address 2h)
Supply Current
(Note 10)
(Note 9)
The CS pin will be at one
of three input levels
(VIL, VIH or VIHH). (Note 6)
V/ms
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
DS22233A-page 4
© 2009 Microchip Technology Inc.
MCP434X/436X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
Parameters
Resistance
(± 20%)
Resolution
Step Resistance
Nominal
Resistance Match
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
RAB
4.0
5
6.0
kΩ
-502 devices (Note 1)
8.0
10
12.0
kΩ
-103 devices (Note 1)
(| RABWC RABMEAN |) /
RABMEAN
(| RBWWC RBWMEAN |) /
RBWMEAN
Wiper Resistance
(Note 3, Note 4)
RW
Nominal
Resistance
Tempco
ΔRAB/ΔT
Ratiometeric
Tempco
ΔVWB/ΔT
Max
Units
Conditions
40.0
50
60.0
kΩ
-503 devices (Note 1)
80.0
100
120.0
kΩ
-104 devices (Note 1)
N
RS
Typ
257
Taps
8-bit
No Missing Codes
129
Taps
7-bit
No Missing Codes
—
RAB /
(256)
—
Ω
8-bit
Note 6
—
RAB /
(128)
—
Ω
7-bit
Note 6
MCP43X1 devices only
—
0.2
1.50
%
—
0.2
1.25
%
—
0.2
1.0
%
—
0.2
1.0
%
—
0.25
1.75
%
—
0.25
1.50
%
—
0.25
1.25
%
—
0.25
1.25
%
—
75
160
Ω
VDD = 5.5 V, IW = 2.0 mA, code = 00h
—
75
300
Ω
VDD = 2.7 V, IW = 2.0 mA, code = 00h
—
50
—
ppm/°C TA = -20°C to +70°C
—
100
—
ppm/°C TA = -40°C to +85°C
—
150
—
ppm/°C TA = -40°C to +125°C
—
15
—
ppm/°C Code = Midscale (80h or 40h)
Code = Full Scale
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
© 2009 Microchip Technology Inc.
DS22233A-page 5
MCP434X/436X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Resistor Terminal
Input Voltage
Range (Terminals
A, B and W)
VA,VW,VB
Vss
—
VDD
V
Maximum current
through A, W or B
IW
—
—
2.5
mA
Note 6, Worst case current through
wiper when wiper is either Full Scale or
Zero Scale.
Leakage current
into A, W or B
IWL
—
100
—
nA
MCP43X1 PxA = PxW = PxB = VSS
—
100
—
nA
MCP43X2 PxB = PxW = VSS
Note 5, Note 6
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
DS22233A-page 6
© 2009 Microchip Technology Inc.
MCP434X/436X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Full Scale Error
(MCP43X1 only)
(8-bit code = 100h,
7-bit code = 80h)
VWFSE
-6.0
-0.1
—
LSb
-4.0
-0.1
—
LSb
-3.5
-0.1
—
LSb
-2.0
-0.1
—
LSb
Zero Scale Error
(MCP43X1 only)
(8-bit code = 00h,
7-bit code = 00h)
VWZSE
Potentiometer
Integral
Non-linearity
INL
Potentiometer
Differential
Non-linearity
DNL
Bandwidth -3 dB
(See Figure 2-54,
load = 30 pF)
BW
Conditions
5 kΩ
10 kΩ
8-bit
3.0V ≤ VDD ≤ 5.5V
7-bit
3.0V ≤ VDD ≤ 5.5V
8-bit
3.0V ≤ VDD ≤ 5.5V
7-bit
3.0V ≤ VDD ≤ 5.5V
-0.8
-0.1
—
LSb
8-bit
3.0V ≤ VDD ≤ 5.5V
-0.5
-0.1
—
LSb
7-bit
3.0V ≤ VDD ≤ 5.5V
-0.5
-0.1
—
LSb
100 kΩ 8-bit
3.0V ≤ VDD ≤ 5.5V
-0.5
-0.1
—
LSb
7-bit
3.0V ≤ VDD ≤ 5.5V
—
+0.1
+6.0
LSb
5 kΩ
8-bit
3.0V ≤ VDD ≤ 5.5V
7-bit
3.0V ≤ VDD ≤ 5.5V
10 kΩ
8-bit
3.0V ≤ VDD ≤ 5.5V
—
+0.1
+3.0
LSb
—
+0.1
+3.5
LSb
—
+0.1
+2.0
LSb
—
+0.1
+0.8
LSb
50 kΩ
50 kΩ
7-bit
3.0V ≤ VDD ≤ 5.5V
8-bit
3.0V ≤ VDD ≤ 5.5V
—
+0.1
+0.5
LSb
7-bit
3.0V ≤ VDD ≤ 5.5V
—
+0.1
+0.5
LSb
100 kΩ 8-bit
3.0V ≤ VDD ≤ 5.5V
—
+0.1
+0.5
LSb
7-bit
3.0V ≤ VDD ≤ 5.5V
-1
±0.5
+1
LSb
8-bit
-0.5
±0.25
+0.5
LSb
7-bit
3.0V ≤ VDD ≤ 5.5V
MCP43X1 devices only
(Note 2)
3.0V ≤ VDD ≤ 5.5V
MCP43X1 devices only
(Note 2)
-0.5
±0.25
+0.5
LSb
8-bit
-0.25
±0.125
+0.25
LSb
7-bit
—
2
—
MHz
5 kΩ
—
2
—
MHz
—
1
—
MHz
—
1
—
MHz
—
200
—
kHz
8-bit
Code = 80h
—
200
—
kHz
7-bit
Code = 40h
—
100
—
kHz
100 kΩ 8-bit
Code = 80h
—
100
—
kHz
7-bit
Code = 40h
10 kΩ
50 kΩ
8-bit
Code = 80h
7-bit
Code = 40h
8-bit
Code = 80h
7-bit
Code = 40h
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
© 2009 Microchip Technology Inc.
DS22233A-page 7
MCP434X/436X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Rheostat Integral
Non-linearity
MCP43X1
(Note 4, Note 8)
MCP43X2 devices
only (Note 4)
R-INL
Min
Typ
Max
Units
-1.5
±0.5
+1.5
LSb
-8.25
+4.5
+8.25
LSb
-1.125
±0.5
+1.125
LSb
-6.0
+4.5
+6.0
LSb
-1.5
±0.5
+1.5
LSb
-5.5
+2.5
+5.5
LSb
-1.125
±0.5
+1.125
LSb
-4.0
+2.5
+4.0
LSb
-1.5
±0.5
+1.5
LSb
-2.0
+1
+2.0
LSb
-1.125
±0.5
+1.125
LSb
-1.5
+1
+1.5
LSb
-1.0
±0.5
+1.0
LSb
-1.5
+0.25
+1.5
LSb
-0.8
±0.5
+0.8
LSb
-1.125
+0.25
+1.125
LSb
Conditions
5 kΩ
8-bit
5.5V, IW = 900 µA
3.0V, IW = 480 µA
(Note 7)
7-bit
5.5V, IW = 900 µA
3.0V, IW = 480 µA
(Note 7)
10 kΩ
8-bit
5.5V, IW = 450 µA
3.0V, IW = 240 µA
(Note 7)
7-bit
5.5V, IW = 450 µA
3.0V, IW = 240 µA
(Note 7)
50 kΩ
8-bit
5.5V, IW = 90 µA
3.0V, IW = 48 µA
(Note 7)
7-bit
5.5V, IW = 90 µA
3.0V, IW = 48 µA
(Note 7)
100 kΩ 8-bit
5.5V, IW = 45 µA
3.0V, IW = 24 µA
(Note 7)
7-bit
5.5V, IW = 45 µA
3.0V, IW = 24 µA
(Note 7)
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
DS22233A-page 8
© 2009 Microchip Technology Inc.
MCP434X/436X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Rheostat
Differential
Non-linearity
MCP43X1
(Note 4, Note 8)
MCP43X2 devices
only
(Note 4)
R-DNL
-0.5
±0.25
+0.5
LSb
-1.0
+0.5
+1.0
LSb
-0.375
±0.25
+0.375
LSb
-0.75
+0.5
+0.75
LSb
-0.5
±0.25
+0.5
LSb
-1.0
+0.25
+1.0
LSb
-0.375
±0.25
+0.375
LSb
-0.75
+0.5
+0.75
LSb
-0.5
±0.25
+0.5
LSb
-0.5
±0.25
+0.5
LSb
-0.375
±0.25
+0.375
LSb
-0.375
±0.25
+0.375
LSb
-0.5
±0.25
+0.5
LSb
-0.5
±0.25
+0.5
LSb
-0.375
±0.25
+0.375
LSb
-0.375
±0.25
+0.375
LSb
Conditions
5 kΩ
8-bit
5.5V, IW = 900 µA
3.0V (Note 7)
7-bit
5.5V, IW = 900 µA
3.0V (Note 7)
10 kΩ
8-bit
5.5V, IW = 450 µA
3.0V (Note 7)
7-bit
5.5V, IW = 450 µA
3.0V (Note 7)
8-bit
5.5V, IW = 90 µA
7-bit
5.5V, IW = 90 µA
100 kΩ 8-bit
5.5V, IW = 45 µA
7-bit
5.5V, IW = 45 µA
50 kΩ
3.0V (Note 7)
3.0V (Note 7)
3.0V (Note 7)
3.0V (Note 7)
Capacitance (PA)
CAW
—
75
—
pF
f =1 MHz, Code = Full Scale
Capacitance (Pw)
CW
—
120
—
pF
f =1 MHz, Code = Full Scale
Capacitance (PB)
CBW
—
75
—
pF
f =1 MHz, Code = Full Scale
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
© 2009 Microchip Technology Inc.
DS22233A-page 9
MCP434X/436X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
Parameters
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
Conditions
Digital Inputs/Outputs (CS, SDI, SDO, SCK, WP, RESET)
V
2.7V ≤ VDD ≤ 5.5V
(Allows 2.7V Digital VDD with
5V Analog VDD)
—
V
1.8V ≤ VDD ≤ 2.7V
0.2VDD
V
0.45 VDD
—
0.5 VDD
—
—
—
VHYS
—
0.1VDD
—
V
High Voltage Input
Entry Voltage
VIHH
8.5
—
12.5 (6)
V
High Voltage Input
Exit Voltage
VIHH
—
—
VDD +
0.8V
V
High Voltage Limit
VMAX
—
—
12.5 (6)
V
Pin can tolerate VMAX or less.
Schmitt Trigger
High Input
Threshold
VIH
Schmitt Trigger
Low Input
Threshold
VIL
Hysteresis of
Schmitt Trigger
Inputs
Output Low
Voltage (SDO)
VOL
Output High
Voltage (SDO)
VOH
—
Threshold for WiperLock™ Technology
VSS
—
0.3VDD
V
IOL = 5 mA, VDD = 5.5V
VSS
—
0.3VDD
V
IOL = 1 mA, VDD = 1.8V
0.7VDD
—
VDD
V
IOH = -2.5 mA, VDD = 5.5V
0.7VDD
—
VDD
V
IOL = -1 mA, VDD = 1.8V
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
DS22233A-page 10
© 2009 Microchip Technology Inc.
MCP434X/436X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Weak Pull-up
Current
IPU
—
—
1.75
mA
Internal VDD pull-up, VIHH pull-down,
VDD = 5.5V, VCS = 12.5V
—
170
—
µA
CS pin, VDD = 5.5V, VCS = 3V
CS Pull-up /
Pull-down
Resistance
RCS
—
16
—
kΩ
VDD = 5.5V, VCS = 3V
RESET Pull-up
Resistance
RRESET
—
16
—
kΩ
VDD = 5.5V, VRESET = 0V
Input Leakage
Current
IIL
-1
—
1
µA
VIN = VDD (all pins) and
VIN = VSS (all pins except RESET)
CIN, COUT
—
10
—
pF
fC = 20 MHz
0h
—
1FFh
hex
8-bit device
—
1FFh
hex
7-bit device
hex
All Terminals connected
Pin Capacitance
Conditions
RAM (Wiper, TCON) Value
Value Range
N
0h
TCON POR/BOR
Setting
1FF
EEPROM
Endurance
—
EEPROM Range
N
0h
Initial NV Wiper
POR/BOR Setting
N
080h
hex
8-bit
WiperLock Technology = Off
040h
hex
7-bit
WiperLock Technology = Off
Initial EEPROM
POR/BOR Setting
N
000h
hex
EEPROM
Programming
Write Cycle Time
tWC
—
3
10
ms
PSS
—
0.0015
0.0035
%/%
8-bit
VDD = 2.7V to 5.5V,
VA = 2.7V, Code = 80h
—
0.0015
0.0035
%/%
7-bit
VDD = 2.7V to 5.5V,
VA = 2.7V, Code = 40h
Endurance
1M
—
—
1FFh
Cycles
hex
Power Requirements
Power Supply
Sensitivity
(MCP43X1)
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
© 2009 Microchip Technology Inc.
DS22233A-page 11
MCP434X/436X
1.1
SPI Mode Timing Waveforms and Requirements
RESET
tRST
tRSTD
SCK
Wx
FIGURE 1-1:
TABLE 1-1:
RESET Waveforms.
RESET TIMING
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
Timing Characteristics
Parameters
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
RESET pulse width
tRST
50
RESET rising edge
normal mode (Wiper
driving and SPI
interface operational)
tRSTD
—
DS22233A-page 12
Max
Units
—
—
ns
—
20
ns
Conditions
© 2009 Microchip Technology Inc.
MCP434X/436X
VIHH
VIH
VIH
CS
VIL
84
70
72
SCK
83
71
78
79
80
MSb
SDO
LSb
BIT6 - - - - - -1
77
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
FIGURE 1-2:
TABLE 1-2:
#
SPI Timing Waveform (Mode = 11).
SPI REQUIREMENTS (MODE = 11)
Characteristic
SCK Input Frequency
Symbol
Min
Max Units
FSCK
—
—
60
45
500
45
500
10
20
20
—
—
10
1
—
—
—
—
—
—
—
—
50
70
170
—
70
71
CS Active (VIL or VIHH) to SCK↑ input
SCK input high time
72
SCK input low time
73
Setup time of SDI input to SCK↑ edge
TDIV2scH
74
77
80
Hold time of SDI input from SCK↑ edge
CS Inactive (VIH) to SDO output hi-impedance
SDO data output valid after SCK↓ edge
TscH2DIL
TcsH2DOZ
TscL2DOV
83
CS Inactive (VIH) after SCK↑ edge
TscH2csI
Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
Note 1: This specification by design.
84
© 2009 Microchip Technology Inc.
TcsA2scH
TscH
TscL
TcsA2csI
100
1
50
—
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Conditions
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
Note 1
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
DS22233A-page 13
MCP434X/436X
VIH
VIHH
VIH
82
CS
VIL
SCK
84
70
83
71
MSb
SDO
BIT6 - - - - - -1
LSb
75, 76
73
SDI
80
72
MSb IN
77
BIT6 - - - -1
LSb IN
74
FIGURE 1-3:
TABLE 1-3:
#
SPI Timing Waveform (Mode = 00).
SPI REQUIREMENTS (MODE = 00)
Characteristic
Symbol
Min
Max Units
FSCK
10
1
—
—
—
—
—
—
—
50
70
170
85
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
ns
ms
ns
70
71
CS Active (VIL or VIHH) to SCK↑ input
SCK input high time
72
SCK input low time
73
74
77
80
Setup time of SDI input to SCK↑ edge
Hold time of SDI input from SCK↑ edge
CS Inactive (VIH) to SDO output hi-impedance
SDO data output valid after SCK↓ edge
TDIV2scH
TscH2DIL
TcsH2DOZ
TscL2DOV
—
—
60
45
500
45
500
10
20
—
—
82
SDO data output valid after
CS Active (VIL or VIHH)
CS Inactive (VIH) after SCK↓ edge
TssL2doV
—
TscH2csI
100
1
50
SCK Input Frequency
83
Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
Note 1: This specification by design.
84
DS22233A-page 14
TcsA2scH
TscH
TscL
TcsA2csI
—
Conditions
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
Note 1
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
© 2009 Microchip Technology Inc.
MCP434X/436X
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Thermal Resistance, 20L-QFN
θJA
—
43
—
°C/W
Thermal Resistance, 20L-TSSOP
θJA
—
90
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistances
© 2009 Microchip Technology Inc.
DS22233A-page 15
MCP434X/436X
NOTES:
DS22233A-page 16
© 2009 Microchip Technology Inc.
MCP434X/436X
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
200
400
200
ICS
150
0
-200
-400
100
50
-600
-800
-1000
RCS
0
2.00
4.00
6.00
8.00
fSCK (MHz)
10.00
12.00
FIGURE 2-1:
Device Current (IDD) vs. SPI
Frequency (fSCK) and Ambient Temperature
(VDD = 2.7V and 5.5V).
2
3
4
5
6
7
VCS (V)
8
9
10
FIGURE 2-4:
CS Pull-up/Pull-down
Resistance (RCS) and Current (ICS) vs. CS Input
Voltage (VCS) (VDD = 5.5V).
12
3.0
2.5
CS VPP Threshold (V)
Standby Current (Istby) (µA)
1000
800
600
250
2.7V -40°C
2.7V 25°C
2.7V 85°C
2.7V 125°C
5.5V -40°C
5.5V 25°C
5.5V 85°C
5.5V 125°C
ICS (µA)
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
0.00
RCS (kOhms)
Operating Current (IDD) (µA)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
5.5V
2.0
1.5
1.0
2.7V
0.5
0.0
10
5.5V Entry
8
2.7V Entry
5.5V Exit
6
4
2.7V Exit
2
0
-40
25
85
125
Ambient Temperature (°C)
FIGURE 2-2:
Device Current (ISHDN) and
VDD. (CS = VDD) vs. Ambient Temperature.
-40
-20
0
20
40
60
80 100
Ambient Temperature (°C)
120
FIGURE 2-5:
CS High Input Entry/Exit
Threshold vs. Ambient Temperature and VDD.
EE Write Current (Iwrite) (µA)
700.0
600.0
500.0
5.5V
400.0
300.0
2.7V
200.0
100.0
-40
25
85
125
Ambient Temperature (°C)
FIGURE 2-3:
Write Current (IWRITE) vs.
Ambient Temperature and VDD.
© 2009 Microchip Technology Inc.
DS22233A-page 17
MCP434X/436X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
0.2
0.1
80
0
60
-0.1
125°C
20
0
-40°C 25°C
85°C
-0.2
RW
260
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
180
0
140
RW
-40°C
25°C
-0.1
-0.2
85°C
20
32
85°C 25°C
DNL
-40°C
-0.75
RW
-1.25
32
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
4
2
RW
100
125°C
20
5250
5000
RWB (Ohms)
5100
32
85°C
25°C
DNL
-2
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-10:
5 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
6000
5150
0
-40°C
60
5300
2.7V
4000
3000
2000
-40°C
25°C
85°C
125°C
1000
5.5V
5050
6
INL
0
5200
125C Rw
125C INL
125C DNL
140
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-7:
5 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
Nominal Resistance (RAB)
(Ohms)
40
180
-0.3
0
-0.25
260
125°C
60
60
300
0.2
0.1
100
0.25
220
DNL
0.75
FIGURE 2-9:
5 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
0.3
INL
220
1.25
125C Rw
125C INL
125C DNL
80
0
Error (LSb)
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
85C Rw
85C INL
85C DNL
20
FIGURE 2-6:
5 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
300
25C Rw
25C INL
25C DNL
INL
125°C
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
32
-40C Rw
-40C INL
-40C DNL
100
INL
DNL
40
120
0.3
Error (LSb)
125C Rw
125C INL
125C DNL
Error (LSb)
85C Rw
85C INL
85C DNL
Wiper Resistance (RW)
(ohms)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (RW)
(ohms)
120
0
-40
0
40
80
Ambient Temperature (°C)
120
FIGURE 2-8:
5 kΩ – Nominal Resistance
(Ω) vs. Ambient Temperature and VDD.
DS22233A-page 18
0
32
64
96
128 160 192
Wiper Setting (decimal)
224
256
FIGURE 2-11:
5 kΩ – RWB (Ω) vs. Wiper
Setting and Ambient Temperature.
© 2009 Microchip Technology Inc.
MCP434X/436X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-12:
5 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-15:
5 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-13:
5 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-16:
5 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-14:
5 kΩ – Power-Up Wiper
Response Time (20 ms/Div).
© 2009 Microchip Technology Inc.
DS22233A-page 19
MCP434X/436X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
125C Rw
125C INL
125C DNL
INL
DNL
0.2
0.1
80
0
60
-0.1
25°C -40°C
125°C 85°C
-0.2
RW
20
-40C Rw
-40C INL
-40C DNL
260
220
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
INL
DNL
0.1
0
140
100
300
-0.1
RW
-0.2
-40°C
25°C
125°C 85°C
20
32
85°C 25°C
2
0
100
-40°C
60
DNL
RW
-1
20
-2
25 50 75 100 125 150 175 200 225 250
Wiper Setting (decimal)
FIGURE 2-21:
10 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
RWB (Ohms)
10000
8000
6000
4000
-40°C
25°C
85°C
125°C
5.5V
2000
10000
3
INL
1
10200
10050
4
125C Rw
125C INL
125C DNL
140
12000
10100
85C Rw
85C INL
85C DNL
180
10250
2.7V
25C Rw
25C INL
25C DNL
220
0
10150
-0.5
DNL
-1
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
260
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-18:
10 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
32
RW
-40°C
125°C 85°C 25°C
-0.3
0
Nominal Resistance (RAB)
(Ohms)
40
FIGURE 2-20:
10 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
0.3
180
60
0
60
0
0.2
1
125C Rw
125C INL
125C DNL
0.5
20
Error (LSb)
Wiper Resistance (RW)
(ohms)
300
85C Rw
85C INL
85C DNL
80
25 50 75 100 125 150 175 200 225 250
Wiper Setting (decimal)
FIGURE 2-17:
10 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
25C Rw
25C INL
25C DNL
INL
125°C
-0.3
0
-40C Rw
-40C INL
-40C DNL
100
Wiper Resistance (RW)
(ohms)
40
120
0.3
Error (LSb)
85C Rw
85C INL
85C DNL
Error (LSb)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (RW)
(ohms)
120
0
-40
0
40
80
Ambient Temperature (°C)
120
FIGURE 2-19:
10 kΩ – Nominal Resistance
(Ω) vs. Ambient Temperature and VDD.
DS22233A-page 20
0
32
64
96 128 160 192
Wiper Setting (decimal)
224
256
FIGURE 2-22:
10 kΩ – RWB (Ω) vs. Wiper
Setting and Ambient Temperature.
© 2009 Microchip Technology Inc.
MCP434X/436X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-23:
10 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-25:
10 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-24:
10 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-26:
10 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
© 2009 Microchip Technology Inc.
DS22233A-page 21
MCP434X/436X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
INL
DNL
0.2
0.1
80
0
60
-0.1
40
125°C
25°C
85°C
20
0
-40°C
120
0.3
100
-0.2
RW
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
32
260
220
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
INL
DNL
180
0
140
RW
100
-40°C
60
0
-0.1
40
32
-0.2
1
0.75
0.5
0.25
0
140
RW
100
-0.25
-0.5
-40°C
60
85°C 25°C
20
0
32
64
-0.75
-1
96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-31:
50 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
50800
60000
50600
50000
50400
RWB (Ohms)
Nominal Resistance (RAB)
(Ohms)
125C Rw
125C INL
125C DNL
DNL
125°C
FIGURE 2-28:
50 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
2.7V
50000
5.5V
49800
85C Rw
85C INL
85C DNL
INL
64 96 128 160 192 224 256
Wiper Setting (decimal)
50200
25C Rw
25C INL
25C DNL
180
-0.3
0
RW
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
32
-40C Rw
-40C INL
-40C DNL
125°C 85°C 25°C
20
-40°C
85°C 25°C
125°C
260
-0.2
0.1
60
300
-0.1
0.2
DNL
220
0.1
0.3
125C Rw
125C INL
125C DNL
FIGURE 2-30:
50 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
0.3
0.2
85C Rw
85C INL
85C DNL
80
0
Error (LSb)
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
INL
20
FIGURE 2-27:
50 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
300
-40C Rw
-40C INL
-40C DNL
Error (LSb)
125C Rw
125C INL
125C DNL
Error (LSb)
85C Rw
85C INL
85C DNL
Wiper Resistance (RW)
(ohms)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (RW)
(ohms)
120
40000
30000
20000
-40°C
25°C
85°C
125°C
10000
49600
49400
0
-40
0
40
80
Ambient Temperature (°C)
120
FIGURE 2-29:
50 kΩ – Nominal Resistance
(Ω) vs. Ambient Temperature and VDD.
DS22233A-page 22
0
32
64
96 128 160 192
Wiper Setting (decimal)
224
256
FIGURE 2-32:
50 kΩ – RWB (Ω) vs. Wiper
Setting and Ambient Temperature.
© 2009 Microchip Technology Inc.
MCP434X/436X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-33:
50 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-35:
50 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-34:
50 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-36:
50 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
© 2009 Microchip Technology Inc.
DS22233A-page 23
MCP434X/436X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
125C Rw
125C INL
125C DNL
DNL
0
60
-0.1
40
25°C -40°C
-40C Rw
-40C INL
-40C DNL
100
0.1
INL
80
120
0.2
RW
-0.2
64 96 128 160 192 224 256
Wiper Setting (decimal)
32
-40C Rw
-40C INL
-40C DNL
260
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
INL
-0.1
40
-40°C
220
DNL
0.15
0
140
RW
60
-40°C
20
0
32
-0.1
-0.15
125°C 85°C 25°C
FIGURE 2-38:
100 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
85C Rw
85C INL
85C DNL
0.6
125C Rw
125C INL
125C DNL
0.4
INL
0
60
-0.4
-40°C
125°C 85°C 25°C
20
-0.6
0
32
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-41:
100 kΩ Rheo Mode – RW
(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
101000
100000
100000
-0.2
RW
100
120000
2.7V
0.2
DNL
101500
80000
60000
40000
-40°C
25°C
85°C
125°C
5.5V
99500
25C Rw
25C INL
25C DNL
140
Rwb (Ohms)
Nominal Resistance (RAB)
(Ohms)
-40C Rw
-40C INL
-40C DNL
180
-0.2
64 96 128 160 192 224 256
Wiper Setting (decimal)
100500
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
32
220
-0.05
100
-0.2
FIGURE 2-40:
100 kΩ Rheo Mode – RW
(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
260
0.05
180
RW
125°C 85°C 25°C
300
0.1
0.1
0
0.2
Error (LSb)
Wiper Resistance (RW)
(ohms)
300
0.2
60
0
FIGURE 2-37:
100 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
0.3
125C Rw
125C INL
125C DNL
DNL
80
20
Wiper Resistance (Rw)
(ohms)
0
85C Rw
85C INL
85C DNL
INL
125°C 85°C
20
25C Rw
25C INL
25C DNL
Error (LSb)
85C Rw
85C INL
85C DNL
Error (LSb)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (RW)
(ohms)
120
20000
0
99000
-40
0
40
80
Ambient Temperature (°C)
120
FIGURE 2-39:
100 kΩ – Nominal
Resistance (Ω) vs. Ambient Temperature and
VDD .
DS22233A-page 24
0
32
64
96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-42:
100 kΩ – RWB (Ω) vs. Wiper
Setting and Ambient Temperature.
© 2009 Microchip Technology Inc.
MCP434X/436X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-43:
100 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-45:
100 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-44:
100 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-46:
100 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
© 2009 Microchip Technology Inc.
DS22233A-page 25
MCP434X/436X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
2.4
0
-5
2.2
5.5V
IOH (mA)
VIH (V)
2
1.8
1.6
1.4
2.7V
-10
-15
2.7V
-20
5.5V
-25
-30
-35
1.2
-40
1
-45
-40
0
40
80
-40
120
0
Temperature (°C)
FIGURE 2-47:
VIH (SDI, SCK, CS, and
RESET) vs. VDD and Temperature.
1.3
5.5V
IOL (mA)
VIL (V)
1.1
1
0.9
0.8
2.7V
0.7
0.6
-40
0
40
80
120
50
45
40
35
30
25
20
15
10
5
0
120
5.5V
2.7V
-40
Temperature (°C)
FIGURE 2-48:
VIL (SDI, SCK, CS, and
RESET) vs. VDD and Temperature.
DS22233A-page 26
80
IOH (SDO) vs. VDD and
FIGURE 2-49:
Temperature.
1.4
1.2
40
Temperature (°C)
0
40
80
120
Temperature (°C)
FIGURE 2-50:
Temperature.
IOL (SDO) vs. VDD and
© 2009 Microchip Technology Inc.
MCP434X/436X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
4.0
14.2
14.1
3.5
5.5V
3.0
fsck (MHz)
tWC (ms)
14.0
2.7V
2.5
2.0
2.7V
13.8
13.7
13.6
5.5V
1.5
13.9
13.5
1.0
13.4
-40
0
40
80
120
-40
Temperature (°C)
0
40
80
120
Temperature (°C)
FIGURE 2-51:
Nominal EEPROM Write
Cycle Time vs. VDD and Temperature.
FIGURE 2-53:
SCK Input Frequency vs.
Voltage and Temperature.
2.1
Test Circuits
2
VDD (V)
1.6
+5V
1.2
VIN
0.8
0.4
0
-40
0
40
80
120
Offset
GND
W
B
+
VOUT
-
2.5V DC
Temperature (°C)
FIGURE 2-52:
and Temperature.
A
POR/BOR Trip point vs. VDD
FIGURE 2-54:
Test.
© 2009 Microchip Technology Inc.
-3 db Gain vs. Frequency
DS22233A-page 27
MCP434X/436X
NOTES:
DS22233A-page 28
© 2009 Microchip Technology Inc.
MCP434X/436X
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follows.
TABLE 3-1:
PINOUT DESCRIPTION FOR THE MCP434X/436X
Pin
TSSOP
Symbol
I/O
Buffer
Type
Weak
Pull-up/
down
(Note 1)
QFN
Standard Function
14L
20L
20L
—
1
19
P3A
A
Analog
No
Potentiometer 3 Terminal A
1
2
20
P3W
A
Analog
No
Potentiometer 3 Wiper Terminal
A
Analog
No
Potentiometer 3 Terminal B
2
3
1
P3B
3
4
2
CS
I
HV w/ST
“smart”
SPI Chip Select Input
4
5
3
SCK
I
HV w/ST
“smart”
SPI Clock Input
5
6
4
SDI
I
HV w/ST
“smart”
SPI Serial Data Input
5
VSS
—
P
—
Ground
A
Analog
No
Potentiometer 1 Terminal B
6
7
7
8
6
P1B
8
9
7
P1W
A
Analog
No
Potentiometer 1 Wiper Terminal
—
10
8
P1A
A
Analog
No
Potentiometer 1 Terminal A
—
11
9
P0A
A
Analog
No
Potentiometer 0 Terminal A
9
12
10
P0W
A
Analog
No
Potentiometer 0 Wiper Terminal
10
13
11
P0B
A
Analog
No
Potentiometer 0 Terminal B
—
14
12
WP
I
I
“smart”
I
HV w/ST
Yes
Hardware Reset Pin
Hardware EEPROM Write Protect
—
15
13
RESET
11
16
14
SDO
O
O
No
SPI Serial Data Output
12
17
15
VDD
—
P
—
Positive Power Supply Input
13
18
16
P2B
A
Analog
No
Potentiometer 2 Terminal B
17
P2W
A
Analog
No
Potentiometer 2 Wiper Terminal
A
Analog
No
Potentiometer 2 Terminal A
—
—
—
Exposed Pad. (Note 2)
14
19
—
20
18
P2A
—
—
21
EP
Legend:
Note 1:
2:
HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)
A = Analog pins (Potentiometer terminals)
I = digital input (high Z)
O = digital output
I/O = Input / Output
P = Power
The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and
shut-down current.
The QFN package has a contact on the bottom of the package. This contact is conductively connected to
the die substrate, and therefore should be unconnected or connected to the same ground as the device’s
VSS pin.
© 2009 Microchip Technology Inc.
DS22233A-page 29
MCP434X/436X
3.1
Chip Select (CS)
The CS pin is the serial interface’s chip select input.
Forcing the CS pin to VIL enables the serial commands.
Forcing the CS pin to VIHH enables the high-voltage
serial commands.
3.2
Serial Data In (SDI)
The SDI pin is the serial interfaces Serial Data In pin.
This pin is connected to the Host Controllers SDO pin.
3.3
Ground (VSS)
The VSS pin is the device ground reference.
3.4
Potentiometer Terminal B
The terminal B pin is connected to the internal
potentiometer’s terminal B.
3.6
Potentiometer Terminal A
The terminal A pin is available on the MCP43X1
devices, and is connected to the internal
potentiometer’s terminal A.
The potentiometer’s terminal A is the fixed connection
to the Full Scale wiper value of the digital
potentiometer. This corresponds to a wiper value of
0x100 for 8-bit devices or 0x80 for 7-bit devices.
The terminal A pin does not have a polarity relative to
the terminal W or B pins. The terminal A pin can
support both positive and negative current. The voltage
on terminal A must be between VSS and VDD.
The terminal A pin is not available on the MCP43X2
devices, and the internally terminal A signal is floating.
MCP43X1 devices have four terminal A pins, one for
each resistor network.
The potentiometer’s terminal B is the fixed connection
to the Zero Scale wiper value of the digital
potentiometer. This corresponds to a wiper value of
0x00 for both 7-bit and 8-bit devices.
3.7
The terminal B pin does not have a polarity relative to
the terminal W or A pins. The terminal B pin can
support both positive and negative current. The voltage
on terminal B must be between VSS and VDD.
3.8
Write Protect (WP)
The WP pin is used to force the non-volatile memory to
be write protected.
Reset (RESET)
The RESET pin is used to force the device into the
POR/BOR state.
MCP43XX devices have four terminal B pins, one for
each resistor network.
3.9
3.5
The SDO pin is the serial interfaces Serial Data Out pin.
This pin is connected to the Host Controllers SDI pin.
Potentiometer Wiper (W) Terminal
Serial Data Out (SDO)
The terminal W pin is connected to the internal
potentiometer’s terminal W (the wiper). The wiper
terminal is the adjustable terminal of the digital
potentiometer. The terminal W pin does not have a
polarity relative to terminals A or B pins. The terminal
W pin can support both positive and negative current.
The voltage on terminal W must be between VSS and
VDD.
This pin allows the Host Controller to read the digital
potentiometers registers, or monitor the state of the
command error bit.
MCP43XX devices have four terminal W pins, one for
each resistor network.
While the device VDD < Vmin (2.7V), the electrical
performance of the device may not meet the data sheet
specifications.
3.10
Positive Power Supply Input (VDD)
The VDD pin is the device’s positive power supply input.
The input power supply is relative to VSS.
3.11
Exposed Pad (EP)
This pad is conductively connected to the device's
substrate. This pad should be tied to the same potential
as the VSS pin (or left unconnected). This pad could be
used to assist as a heat sink for the device when
connected to a PCB heat sink.
DS22233A-page 30
© 2009 Microchip Technology Inc.
MCP434X/436X
4.0
FUNCTIONAL OVERVIEW
This Data Sheet covers a family of four non-volatile
Digital Potentiometer and Rheostat devices that will be
referred to as MCP43XX. The MCP43X1 devices are
the Potentiometer configuration, while the MCP43X2
devices are the Rheostat configuration.
As the Device Block Diagram shows, there are four
main functional blocks. These are:
•
•
•
•
POR/BOR and RESET Operation
Memory Map
Resistor Network
Serial Interface (SPI)
The POR/BOR operation and the Memory Map are
discussed in this section and the Resistor Network and
SPI operation are described in their own sections. The
Device Commands commands are discussed in
Section 7.0.
4.1.2
When the device powers down, the device VDD will
cross the VPOR/VBOR voltage.
Once the VDD voltage decreases below the VPOR/VBOR
voltage the following happens:
• Serial Interface is disabled
• EEPROM Writes are disabled
If the VDD voltage decreases below the VRAM voltage,
the following happens:
• Volatile wiper registers may become corrupted
• TCON registers may become corrupted
As the voltage recovers above the VPOR/VBOR voltage
see Section 4.1.1 “Power-on Reset”.
Serial commands not completed due to a brown-out
condition may cause the memory location (volatile and
non-volatile) to become corrupted.
4.1.3
4.1
POR/BOR and RESET Operation
The Power-on Reset is the case where the device is
having power applied to it from VSS. The Brown-out
Reset occurs when a device had power applied to it,
and that power (voltage) drops below the specified
range.
The devices RAM retention voltage (VRAM) is lower
than the POR/BOR voltage trip point (VPOR/VBOR). The
maximum VPOR/VBOR voltage is less then 1.8V.
When VPOR/VBOR < VDD < 2.7V, the electrical
performance may not meet the data sheet
specifications. In this region, the device is capable of
reading and writing to its EEPROM and incrementing,
decrementing, reading and writing to its volatile
memory if the proper serial command is executed.
When VDD < VPOR/VBOR or the RESET pin is Low, the
pin weak pull-ups are enabled.
4.1.1
POWER-ON RESET
When the device powers up, the device VDD will cross
the VPOR/VBOR voltage. Once the VDD voltage crosses
the VPOR/VBOR voltage, the following happens:
• Volatile wiper register is loaded with value in the
corresponding non-volatile wiper register
• The TCON registers are loaded their default value
• The device is capable of digital operation
© 2009 Microchip Technology Inc.
BROWN-OUT RESET
RESET PIN
The RESET pin can be used to force the device into
the POR/BOR state of the device. When the RESET
pin is forced Low, the device is forced into the reset
state. This means that the TCON and STATUS
registers are forced to their default values and the
volatile wiper registers are loaded with the value in the
corresponding Non-Volatile wiper register. Also the
SPI interface is disabled. Any non-volatile write cycle
is not interrupted, and allowed to complete.
This feature allows a hardware method for all registers
to be updated at the same time.
4.1.4
INTERACTION OF RESET PIN AND BOR/
POR CIRCUITRY
Figure 4-1 shows how the RESET pin signal and the
POR/BOR signal interact to control the hardware reset
state of the device.
RESET (from pin)
Device reset
POR/BOR signal
FIGURE 4-1:
POR/BOR Signal and
RESET Pin Interaction.
DS22233A-page 31
MCP434X/436X
4.2
Memory Map
The device memory is 16 locations that are 9-bits wide
(16x9 bits). This memory space contains both volatile
and non-volatile locations (see Table 4-1).
TABLE 4-1:
Address
00h
MEMORY MAP AND THE SUPPORTED COMMANDS
Function
Allowed Commands
02h
Read, Write,
Increment, Decrement
Volatile Wiper 1
RAM
Read, Write,
Increment, Decrement
Non-Volatile Wiper 0 EEPROM
Read, Write (1)
03h
Non-Volatile Wiper 1 EEPROM
04h
Volatile
TCON0 Register
Status Register
Volatile Wiper 2
01h
05h
06h
Volatile Wiper 0
Memory
Type
RAM
RAM
Disallowed Commands (2)
Factory
Initialization
—
—
—
—
Increment, Decrement
Read, Write (1)
Increment, Decrement
Read, Write
Increment, Decrement
8-bit
7-bit
8-bit
7-bit
80h
40h
80h
40h
—
08h
Read
Write, Increment, Decrement
Read, Write,
—
Increment, Decrement
Volatile Wiper 3
RAM
Read, Write,
—
Increment, Decrement
Non-Volatile Wiper 2 EEPROM
Read, Write (1)
Increment, Decrement
09h
Non-Volatile Wiper 3 EEPROM
0Ah
—
Volatile
RAM
Read, Write
Increment, Decrement
TCON1 Register
Data EEPROM
EEPROM
Read, Write (1)
Increment, Decrement
000h
Data EEPROM
EEPROM
Read, Write (1)
Increment, Decrement
000h
Increment, Decrement
000h
Data EEPROM
EEPROM
Read, Write (1)
(1)
Increment, Decrement
000h
Data EEPROM
EEPROM
Read, Write
Increment, Decrement
000h
Data EEPROM
EEPROM
Read, Write (1)
When an EEPROM write is active, these are invalid commands and will generate an error condition. The
user should use a read of the Status register to determine when the write cycle has completed. To exit the
error condition, the user must take the CS pin to the VIH level and then back to the active state (VIL or
VIHH).
This command on this address will generate an error condition. To exit the error condition, the user must
take the CS pin to the VIH level and then back to the active state (VIL or VIHH).
07h
0Bh
0Ch
0Dh
0Eh
0Fh
Note 1:
2:
DS22233A-page 32
RAM
RAM
Read, Write (1)
Increment, Decrement
—
—
—
8-bit
7-bit
8-bit
7-bit
80h
40h
80h
40h
© 2009 Microchip Technology Inc.
MCP434X/436X
4.2.1
NON-VOLATILE MEMORY
(EEPROM)
4.2.1.4
This memory can be grouped into two uses of
non-volatile memory. These are:
• General Purpose Registers
• Non-Volatile Wiper Registers
The non-volatile wipers starts functioning below the
devices VPOR/VBOR trip point.
4.2.1.1
General Purpose Registers
These locations allow the user to store up to 5 (9-bit)
locations worth of information.
4.2.1.2
Non-Volatile Wiper Registers
These locations contain the wiper values that are
loaded into the corresponding volatile wiper register
whenever the device has a POR/BOR event. There are
four registers, one for each resistor network.
The non-volatile wiper register enables stand-alone
operation of the device (without Microcontroller control)
after being programmed to the desired value.
4.2.1.3
Factory Initialization of Non-Volatile
Memory (EEPROM)
The Non-Volatile Wiper values will be initialized to
mid-scale value. This is shown in Table 4-2.
The General purpose EEPROM memory will be
programmed to a default value of 0x000.
It is good practice in the manufacturing flow to
configure the device to your desired settings.
-502
5.0 kΩ
Mid scale
80h
40h
Disabled
-103
10.0 kΩ
Mid scale
80h
40h
Disabled
-503
50.0 kΩ
Mid scale
80h
40h
Disabled
-104
100.0 kΩ Mid scale
80h
40h
Disabled
Resistance
Code
Default POR
Wiper Setting
Wiper
Code
WiperLock™
Technology and
Write Protect Setting
DEFAULT FACTORY
SETTINGS SELECTION
Typical
RAB Value
TABLE 4-2:
© 2009 Microchip Technology Inc.
8-bit 7-bit
Special Features
There are 5 non-volatile bits that are not directly
mapped into the address space. These bits control the
following functions:
•
•
•
•
•
EEPROM Write Protect
WiperLock Technology for Non-Volatile Wiper 0
WiperLock Technology for Non-Volatile Wiper 1
WiperLock Technology for Non-Volatile Wiper 2
WiperLock Technology for Non-Volatile Wiper 3
The operation of WiperLock Technology is discussed in
Section 5.3. The state of the WL0, WL1, WL2, WL3,
and WP bits is reflected in the STATUS register (see
Register 4-1).
EEPROM Write Protect
All internal EEPROM memory can be Write Protected.
When EEPROM memory is Write Protected, Write
commands to the internal EEPROM are prevented.
Write Protect (WP) can be enabled/disabled by two
methods. These are:
• External WP Hardware pin (MCP43X1 devices
only)
• Non-Volatile configuration bit (WP)
High Voltage commands are required to enable and
disable the non-volatile WP bit. These commands are
shown in Section 7.9 “Modify Write Protect or
WiperLock Technology (High Voltage)”.
To write to EEPROM, both the external WP pin and the
internal WP EEPROM bit must be disabled. Write
Protect does not block commands to the volatile
registers.
4.2.2
VOLATILE MEMORY (RAM)
There are seven Volatile Memory locations. These are:
•
•
•
•
•
•
•
Volatile Wiper 0
Volatile Wiper 1
Volatile Wiper 2
Volatile Wiper 3
Status Register
Terminal Control (TCON0) Register 0
Terminal Control (TCON)1 Register 1
The volatile memory starts functioning at the RAM
retention voltage (VRAM).
DS22233A-page 33
MCP434X/436X
4.2.2.1
Status (STATUS) Register
This register contains 7 status bits. These bits show the
state of the WiperLock bits, the Write Protect bit, and if
an EEPROM write cycle is active. The STATUS register
can be accessed via the READ commands.
Register 4-1 describes each STATUS register bit.
The STATUS register is placed at Address 05h.
REGISTER 4-1:
R-1
STATUS REGISTER
R-1
D8:D7
R-1
WL3
R-1
(1)
WL2
R-0
(1)
EEWA
R-x
WL1
R-x
(1)
WL0
(1)
R-1
R-x
—
WP (1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 8-7
D8:D7: Reserved. Forced to “1”
bit 6
WL3: WiperLock Status bit for Resistor Network 3 (Refer to Section 5.3 “WiperLock™ Technology”
for further information)
The WiperLock Technology bit (WL3) prevents the Volatile and Non-Volatile Wiper 3 addresses and the
TCON1 register bits R3HW, R3A, R3W, and R3B from being written to. High Voltage commands are
required to enable and disable WiperLock Technology.
1 = Wiper and TCON1 register bits R3HW, R3A, R3W, and R3B of Resistor Network 3 (Pot 3) are
“Locked” (Write Protected)
0 = Wiper and TCON1 of Resistor Network 3 (Pot 3) can be modified
Note:
bit 5
WL2: WiperLock Status bit for Resistor Network 2 (Refer to Section 5.3 “WiperLock™ Technology”
for further information)
The WiperLock Technology bit (WL2) prevents the Volatile and Non-Volatile Wiper 2 addresses and the
TCON1 register bits R2HW, R2A, R2W, and R2B from being written to. High Voltage commands are
required to enable and disable WiperLock Technology.
1 = Wiper and TCON1 register bits R2HW, R2A, R2W, and R2B of Resistor Network 2 (Pot 2) are
“Locked” (Write Protected)
0 = Wiper and TCON1 of Resistor Network 2 (Pot 2) can be modified
Note:
bit 4
Note 1:
The WL3 bit always reflects the result of the last programming cycle to the non-volatile WL3
bit. After a POR/BOR or RESET pin event, the WL3 bit is loaded with the non-volatile WL3
bit value.
The WL0 bit always reflects the result of the last programming cycle to the non-volatile WL0
bit. After a POR/BOR or RESET pin event, the WL0 bit is loaded with the non-volatile WL0
bit value.
EEWA: EEPROM Write Active Status bit
This bit indicates if the EEPROM Write Cycle is occurring.
1 = An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memory
locations are allowed (addresses 00h, 01h, 04h, and 05h)
0 = An EEPROM Write cycle is NOT currently occurring
Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit is
Not directly written, but reflects the system state (for this feature).
DS22233A-page 34
© 2009 Microchip Technology Inc.
MCP434X/436X
REGISTER 4-1:
bit 3
WL1: WiperLock Status bit for Resistor Network 1 (Refer to Section 5.3 “WiperLock™ Technology”
for further information)
The WiperLock Technology bit (WL1) prevents the Volatile and Non-Volatile Wiper 1 addresses and the
TCON0 register bits R1HW, R1A, R1W, and R1B from being written to. High Voltage commands are
required to enable and disable WiperLock Technology.
1 = Wiper and TCON0 register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are
“Locked” (Write Protected)
0 = Wiper and TCON0 of Resistor Network 1 (Pot 1) can be modified
Note:
bit 2
STATUS REGISTER (CONTINUED)
The WL1 bit always reflects the result of the last programming cycle to the non-volatile WL1
bit. After a POR/BOR or RESET pin event, the WL1 bit is loaded with the non-volatile WL1
bit value.
WL0: WiperLock Status bit for Resistor Network 0 (Refer to Section 5.3 “WiperLock™ Technology”
for further information)
The WiperLock Technology bit (WL0) prevents the Volatile and Non-Volatile Wiper 0 addresses and the
TCON0 register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands are
required to enable and disable WiperLock Technology.
1 = Wiper and TCON0 register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are
“Locked” (Write Protected)
0 = Wiper and TCON0 of Resistor Network 0 (Pot 0) can be modified
Note:
The WL0 bit always reflects the result of the last programming cycle to the non-volatile WL0
bit. After a POR/BOR or RESET pin event, the WL0 bit is loaded with the non-volatile WL0
bit value.
bit 1
Reserved: Forced to “1”
bit 0
WP: EEPROM Write Protect Status bit (Refer to Section “EEPROM Write Protect” for further
information)
This bit indicates the status of the write protection on the EEPROM memory. When Write Protect is
enabled, writes to all non-volatile memory are prevented. This includes the General Purpose EEPROM
memory, and the non-volatile Wiper registers. Write Protect does not block modification of the volatile
wiper register values or the volatile TCON0 and TCON1 register values (via Increment, Decrement, or
Write commands).
This status bit is an OR of the devices Write Protect pin (WP) and the internal non-volatile WP bit. High
Voltage commands are required to enable and disable the internal WP EEPROM bit.
1 = EEPROM memory is Write Protected
0 = EEPROM memory can be written
Note 1:
Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit is
Not directly written, but reflects the system state (for this feature).
© 2009 Microchip Technology Inc.
DS22233A-page 35
MCP434X/436X
4.2.2.2
Terminal Control (TCON) Registers
There are two Terminal Control (TCON) Registers.
These are called TCON0 and TCON1. Each register
contains 8 control bits. Four bits for each Wiper.
Register 4-2 describes each bit of the TCON0 register,
while Register 4-3 describes each bit of the TCON1
register.
The state of each resistor network terminal connection
is individually controlled. That is, each terminal
connection (A, B and W) can be individually connected/
disconnected from the resistor network. This allows the
system to minimize the currents through the digital
potentiometer.
DS22233A-page 36
The value that is written to the specified TCON register
will appear on the appropriate resistor network
terminals when the serial command has completed.
When the WL1 bit is enabled, writes to the TCON0
register bits R1HW, R1A, R1W, and R1B are inhibited.
When the WL0 bit is enabled, writes to the TCON0
register bits R0HW, R0A, R0W, and R0B are inhibited.
When the WL3 bit is enabled, writes to the TCON1
register bits R3HW, R3A, R3W, and R3B are inhibited.
When the WL2 bit is enabled, writes to the TCON1
register bits R2HW, R2A, R2W, and R2B are inhibited.
On a POR/BOR these registers are loaded with
1FFh (9-bits), for all terminals connected. The Host
Controller needs to detect the POR/BOR event and
then update the Volatile TCON register values.
© 2009 Microchip Technology Inc.
MCP434X/436X
REGISTER 4-2:
TCON0 BITS (1)
R-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
D8
R1HW
R1A
R1W
R1B
R0HW
R0A
R0W
R0B
bit 8
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 8
D8: Reserved. Forced to “1”
bit 7
R1HW: Resistor 1 Hardware Configuration Control bit
This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin
1 = Resistor 1 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 1 is forced to the hardware pin “shutdown” configuration
bit 6
R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network
1 = P1A pin is connected to the Resistor 1 Network
0 = P1A pin is disconnected from the Resistor 1 Network
bit 5
R1W: Resistor 1 Wiper (P1W pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network
1 = P1W pin is connected to the Resistor 1 Network
0 = P1W pin is disconnected from the Resistor 1 Network
bit 4
R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network
1 = P1B pin is connected to the Resistor 1 Network
0 = P1B pin is disconnected from the Resistor 1 Network
bit 3
R0HW: Resistor 0 Hardware Configuration Control bit
This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin
1 = Resistor 0 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 0 is forced to the hardware pin “shutdown” configuration
bit 2
R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network
1 = P0A pin is connected to the Resistor 0 Network
0 = P0A pin is disconnected from the Resistor 0 Network
bit 1
R0W: Resistor 0 Wiper (P0W pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network
1 = P0W pin is connected to the Resistor 0 Network
0 = P0W pin is disconnected from the Resistor 0 Network
bit 0
R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network
1 = P0B pin is connected to the Resistor 0 Network
0 = P0B pin is disconnected from the Resistor 0 Network
Note 1:
These bits do not affect the wiper register values.
© 2009 Microchip Technology Inc.
DS22233A-page 37
MCP434X/436X
REGISTER 4-3:
TCON1 BITS (1)
R-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
D8
R3HW
R3A
R3W
R3B
R2HW
R2A
R2W
R2B
bit 8
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 8
D8: Reserved. Forced to “1”
bit 7
R3HW: Resistor 3 Hardware Configuration Control bit
This bit forces Resistor 3 into the “shutdown” configuration of the Hardware pin
1 = Resistor 3 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 3 is forced to the hardware pin “shutdown” configuration
bit 6
R3A: Resistor 3 Terminal A (P3A pin) Connect Control bit
This bit connects/disconnects the Resistor 3 Terminal A to the Resistor 3 Network
1 = P3A pin is connected to the Resistor 3 Network
0 = P3A pin is disconnected from the Resistor 3 Network
bit 5
R3W: Resistor 3 Wiper (P3W pin) Connect Control bit
This bit connects/disconnects the Resistor 3 Wiper to the Resistor 3 Network
1 = P3W pin is connected to the Resistor 3 Network
0 = P3W pin is disconnected from the Resistor 3 Network
bit 4
R3B: Resistor 3 Terminal B (P3B pin) Connect Control bit
This bit connects/disconnects the Resistor 3 Terminal B to the Resistor 3 Network
1 = P3B pin is connected to the Resistor 3 Network
0 = P3B pin is disconnected from the Resistor 3 Network
bit 3
R2HW: Resistor 2 Hardware Configuration Control bit
This bit forces Resistor 2 into the “shutdown” configuration of the Hardware pin
1 = Resistor 2 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 2 is forced to the hardware pin “shutdown” configuration
bit 2
R2A: Resistor 2 Terminal A (P0A pin) Connect Control bit
This bit connects/disconnects the Resistor 2 Terminal A to the Resistor 2 Network
1 = P2A pin is connected to the Resistor 2 Network
0 = P2A pin is disconnected from the Resistor 2 Network
bit 1
R2W: Resistor 2 Wiper (P0W pin) Connect Control bit
This bit connects/disconnects the Resistor 2 Wiper to the Resistor 2 Network
1 = P2W pin is connected to the Resistor 2 Network
0 = P2W pin is disconnected from the Resistor 2 Network
bit 0
R2B: Resistor 2 Terminal B (P2B pin) Connect Control bit
This bit connects/disconnects the Resistor 2 Terminal B to the Resistor 2 Network
1 = P2B pin is connected to the Resistor 2 Network
0 = P2B pin is disconnected from the Resistor 2 Network
Note 1:
These bits do not affect the wiper register values.
DS22233A-page 38
© 2009 Microchip Technology Inc.
MCP434X/436X
5.0
RESISTOR NETWORK
5.1
The Resistor Network has either 7-bit or 8-bit
resolution. Each Resistor Network allows zero scale to
full scale connections. Figure 5-1 shows a block
diagram for the resistive network of a device.
The Resistor Network is made up of several parts.
These include:
• Resistor Ladder
• Wiper
• Shutdown (Terminal Connections)
Devices have either four resistor networks. These are
referred to as Pot 0, Pot 1 Pot 2, and Pot 3.
A
RW
RS
8-Bit
N=
257
(1) (100h)
7-Bit
N=
128
(80h)
256
(FFh)
127
(7Fh)
255
(FEh)
126
(7Eh)
RW (1)
RS
RW
R
RAB S
(1)
RW
RS
RW
1
(01h)
0
(00h)
0
(00h)
(1)
The resistor ladder is a series of equal value resistors
(RS) with a connection point (tap) between the two
resistors. The total number of resistors in the series
(ladder) determines the RAB resistance (see
Figure 5-1). The end points of the resistor ladder are
connected to analog switches which are connected to
the device Terminal A and Terminal B pins. The RAB
(and RS) resistance has small variations over voltage
and temperature.
For an 8-bit device, there are 256 resistors in a string
between terminal A and terminal B. The wiper can be
set to tap onto any of these 256 resistors thus providing
257 possible settings (including terminal A and terminal
B).
For a 7-bit device, there are 128 resistors in a string
between terminal A and terminal B. The wiper can be
set to tap onto any of these 128 resistors thus providing
129 possible settings (including terminal A and terminal
B).
Equation 5-1 shows the calculation for the step
resistance.
EQUATION 5-1:
W
1
(1) (01h)
Resistor Ladder Module
RS CALCULATION
R AB
R S = ------------( 256 )
8-bit Device
R AB
R S = ------------( 128 )
7-bit Device
Analog Mux
B
Note 1:
The wiper resistance is dependent on
several factors including, wiper code,
device VDD, Terminal voltages (on A, B,
and W), and temperature.
Also for the same conditions, each tap
selection resistance has a small variation.
This RW variation has greater effects on
some specifications (such as INL) for the
smaller resistance devices (5.0 kΩ)
compared to larger resistance devices
(100.0 kΩ).
FIGURE 5-1:
Resistor Block Diagram.
© 2009 Microchip Technology Inc.
DS22233A-page 39
MCP434X/436X
5.2
Wiper
5.3
Each tap point (between the RS resistors) is a
connection point for an analog switch. The opposite
side of the analog switch is connected to a common
signal which is connected to the Terminal W (Wiper)
pin.
A value in the volatile wiper register selects which
analog switch to close, connecting the W terminal to
the selected node of the resistor ladder.
The wiper can connect directly to Terminal B or to
Terminal A. A zero scale connections, connects the
Terminal W (wiper) to Terminal B (wiper setting of
000h). A full scale connections, connects the Terminal
W (wiper) to Terminal A (wiper setting of 100h or 80h).
In these configurations the only resistance between the
Terminal W and the other Terminal (A or B) is that of the
analog switches.
A wiper setting value greater than full scale (wiper
setting of 100h for 8-bit device or 80h for 7-bit devices)
will also be a Full Scale setting (Terminal W (wiper)
connected to Terminal A). Table 5-1 illustrates the full
wiper setting map.
Equation 5-2 illustrates the calculation used to
determine the resistance between the wiper and
terminal B.
EQUATION 5-2:
RWB CALCULATION
R AB N
R WB = ------------- + RW
( 256 )
N = 0 to 256 (decimal)
R WB
R AB N
- + RW
= ------------( 128 )
7-bit Device
N = 0 to 128 (decimal)
TABLE 5-1:
The MCP43XX device’s WiperLock technology allows
application-specific calibration settings to be secured in
the EEPROM without requiring the use of an additional
write-protect pin. There are four WiperLock Technology
configuration bits (WL0, WL1, WL2, and WL3). These
bits prevent the Non-Volatile and Volatile addresses
and bits for the specified resistor network from being
written.
The WiperLock technology prevents
commands from doing the following:
the
serial
• Changing a volatile wiper value
• Writing to the specified non-volatile wiper memory
location
• Changing the related volatile TCON register bits
For either Resistor Network 0, Resistor Network 1,
Resistor Network 2, or Resistor Network 3 (Potx), the
WLx bit controls the following:
• Non-Volatile Wiper Register
• Volatile Wiper Register
• Volatile TCON register bits RxHW, RxA, RxW, and
RxB
High Voltage commands are required to enable and
disable WiperLock. Please refer to the Modify Write
Protect or WiperLock Technology (High Voltage)
command for operation.
5.3.1
8-bit Device
WiperLock™ Technology
POR/BOR OPERATION WHEN
WIPERLOCK TECHNOLOGY
ENABLED
The WiperLock Technology state is not affected by a
POR/BOR event. A POR/BOR event will load the
Volatile Wiper register value with the Non-Volatile
Wiper register value, refer to Section 4.1.
VOLATILE WIPER VALUE VS.
WIPER POSITION MAP
Wiper Setting
Properties
7-bit
8-bit
3FFh – 3FFh – Reserved (Full Scale (W = A)),
081h
101h Increment and Decrement
commands ignored
080h
100h Full Scale (W = A),
Increment commands ignored
07Fh – 0FFh – W = N
041h
081h
040h
080h W = N (Mid Scale)
03Fh – 07Fh – W = N
001h
001h
000h
000h Zero Scale (W = B)
Decrement command ignored
DS22233A-page 40
© 2009 Microchip Technology Inc.
MCP434X/436X
Shutdown
Shutdown is used to minimize the device’s current
consumption. The MCP43XX has one method to
achieve this. This is:
• Terminal Control Register (TCON)
This is different from the MCP42XXX devices in that the
Hardware Shutdown Pin (SHDN) has been replaced by
a RESET pin. The Hardware Shutdown Pin function is
still available via software commands to the TCON
register.
5.4.1
TERMINAL CONTROL REGISTER
(TCON)
The Terminal Control (TCON) register is a volatile
register used to configure the connection of each
resistor network terminal pin (A, B, and W) to the
Resistor Network. These registers are shown in
Register 4-2 and Register 4-3.
The RxHW bit does NOT corrupt the values in the
Volatile Wiper Registers nor the TCON register. When
the Shutdown mode is exited (RxHW bit = “1”):
• The device returns to the Wiper setting specified
by the Volatile Wiper value
• The TCON register bits return to controlling the
terminal connection state
A
Resistor Network
5.4
W
B
FIGURE 5-2:
Resistor Network Shutdown
State (RxHW = ‘0’).
The RxHW bits forces the selected resistor network
into the same state as the MCP42X1’s SHDN pin.
Alternate low power configurations may be achieved
with the RxA, RxW, and RxB bits.
When the RxHW bit is “0”:
• The P0A, P1A, P2A, and P3A terminals are
disconnected
• The P0W, P1W, P2W, and P3W terminals are
simultaneously connect to the P0B, P1B, P2B,
and P3B terminals, respectively (see Figure 5-2)
Note:
When the RxHW bit forces the resistor
network into the hardware SHDN state,
the state of the TCON0 or TCON1
register’s RxA, RxW, and RxB bits is
overridden (ignored). When the state of
the RxHW bit no longer forces the resistor
network into the hardware SHDN state,
the TCON0 or TCON1 register’s RxA,
RxW, and RxB bits return to controlling the
terminal connection state. In other words,
the RxHW bit does not corrupt the state of
the RxA, RxW, and RxB bits.
© 2009 Microchip Technology Inc.
DS22233A-page 41
MCP434X/436X
NOTES:
DS22233A-page 42
© 2009 Microchip Technology Inc.
MCP434X/436X
6.0
SERIAL INTERFACE (SPI)
The MCP43XX devices support the SPI serial protocol.
This SPI operates in the slave mode (does not
generate the serial clock).
The SPI interface uses up to four pins. These are:
•
•
•
•
CS - Chip Select
SCK - Serial Clock
SDI - Serial Data In
SDO - Serial Data Out
Typical SPI Interface is shown in Figure 6-1. In the SPI
interface, the Master’s Output pin is connected to the
Slave’s Input pin and the Master’s Input pin is
connected to the Slave’s Output pin.
The MCP4XXX SPI’s module supports two (of the four)
standard SPI modes. These are Mode 0,0 and 1,1.
The SPI mode is determined by the state of the SCK
pin (VIH or VIL) on the when the CS pin transitions from
inactive (VIH) to active (VIL or VIHH).
All SPI interface signals are high-voltage tolerant.
Typical SPI Interface Connections
Host
Controller
MCP4XXX
SDO
(Master Out - Slave In (MOSI))
SDI
SDI
(Master In - Slave Out (MISO))
SDO
SCK
SCK
I/O (1)
CS
Note 1: If High voltage commands are desired, some type of external circuitry needs to be implemented.
FIGURE 6-1:
Typical SPI Interface Block Diagram.
© 2009 Microchip Technology Inc.
DS22233A-page 43
MCP434X/436X
6.1
SDI, SDO, SCK, and CS Operation
The operation of the four SPI interface pins are
discussed in this section. These pins are:
•
•
•
•
SDI (Serial Data In)
SDO (Serial Data Out)
SCK (Serial Clock)
CS (Chip Select)
The serial interface works on either 8-bit or 16-bit
boundaries depending on the selected command. The
Chip Select (CS) pin frames the SPI commands.
6.1.1
SERIAL DATA IN (SDI)
The Serial Data In (SDI) signal is the data signal into
the device. The value on this pin is latched on the rising
edge of the SCK signal.
6.1.2
SERIAL DATA OUT (SDO)
The Serial Data Out (SDO) signal is the data signal out
of the device. The value on this pin is driven on the
falling edge of the SCK signal.
Once the CS pin is forced to the active level (VIL or
VIHH), the SDO pin will be driven. The state of the SDO
pin is determined by the serial bit’s position in the
command, the command selected, and if there is a
command error state (CMDERR).
6.1.3
SERIAL CLOCK (SCK)
(SPI FREQUENCY OF OPERATION)
The SPI interface is specified to operate up to 10 MHz.
The actual clock rate depends on the configuration of
the system and the serial command used. Table 6-1
shows the SCK frequency for different configurations.
TABLE 6-1:
6.1.4
THE CS SIGNAL
The Chip Select (CS) signal is used to select the device
and frame a command sequence. To start a command,
or sequence of commands, the CS signal must
transition from the inactive state (VIH) to an active state
(VIL or VIHH).
After the CS signal has gone active, the SDO pin is
driven and the clock bit counter is reset.
Note:
There is a required delay after the CS pin
goes active to the 1st edge of the SCK pin.
If an error condition occurs for an SPI command, then
the Command byte’s Command Error (CMDERR) bit
(on the SDO pin) will be driven low (VIL). To exit the
error condition, the user must take the CS pin to the VIH
level.
When the CS pin returns to the inactive state (VIH) the
SPI module resets (including the address pointer).
While the CS pin is in the inactive state (VIH), the serial
interface is ignored. This allows the Host Controller to
interface to other SPI devices using the same SDI,
SDO, and SCK signals.
The CS pin has an internal pull-up resistor. The resistor
is disabled when the voltage on the CS pin is at the VIL
level. This means that when the CS pin is not driven,
the internal pull-up resistor will pull this signal to the VIH
level. When the CS pin is driven low (VIL), the
resistance becomes very large to reduce the device
current consumption.
The high voltage capability of the CS pin allows High
Voltage commands. High Voltage commands allow the
device’s WiperLock Technology and write protect
features to be enabled and disabled.
SCK FREQUENCY
Command
Memory Type Access
Read
Write,
Increment,
Decrement
Non-Volatile SDI, SDO
10 MHz
10 MHz (1, 2)
Memory
Volatile
SDI, SDO
10 MHz
10 MHz
Memory
Note 1: Non-Volatile memory does not support the
Increment or Decrement command.
2: After a Write command, the internal write
cycle must complete before the next SPI
command is received.
3: This is the maximum clock frequency
without an external pull-up resistor.
DS22233A-page 44
© 2009 Microchip Technology Inc.
MCP434X/436X
6.2
The SPI Modes
6.2.2
In Mode 1,1: SCK idle state = high (VIH), data is
clocked in on the SDI pin on the rising edge of SCK and
clocked out on the SDO pin on the falling edge of SCK.
The SPI module supports two (of the four) standard SPI
modes. These are Mode 0,0 and 1,1. The mode is
determined by the state of the SDI pin on the rising
edge of the 1st clock bit (of the 8-bit byte).
6.3
6.2.1
MODE 0,0
VIH
SPI Waveforms
Figure 6-2 through Figure 6-5 show the different SPI
command waveforms. Figure 6-2 and Figure 6-3 are
read and write commands. Figure 6-4 and Figure 6-5
are increment and decrement commands. The high
voltage increment and decrement commands are used
to enable and disable WiperLock Technology and Write
Protect.
In Mode 0,0: SCK idle state = low (VIL), data is clocked
in on the SDI pin on the rising edge of SCK and clocked
out on the SDO pin on the falling edge of SCK.
CS
MODE 1,1
VIHH
VIL
SCK
Write to
SSPBUF
CMDERR bit
SDO
bit15 bit14 bit13 bit12 bit11
SDI
AD3 AD2 AD1 AD0
bit15 bit14 bit13 bit12
C1
bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
X
bit9
D8
bit8
D7
bit7
D6
bit6
D5
bit5
D4
bit4
D3
bit3
D2
D1
bit2 bit1
C0
bit1
bit0
D0
bit0
Input
Sample
FIGURE 6-2:
VIH
CS
16-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1).
VIHH
VIL
SCK
Write to
SSPBUF
SDO
SDI
CMDERR bit
bit15
bit14 bit13 bit12 bit11
AD3 AD2 AD1 AD0
bit15 bit14 bit13 bit12
C1
bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
X
bit9
D8
bit8
D7
bit7
D6
bit6
D5
bit5
D4
bit4
D3
bit3
D2
D1
bit2 bit1
C0
bit1
bit0
D0
bit0
Input
Sample
FIGURE 6-3:
16-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0).
© 2009 Microchip Technology Inc.
DS22233A-page 45
MCP434X/436X
CS
VIH
VIHH
VIL
SCK
Write to
SSPBUF
CMDERR bit
“1” = Valid Command
“0” = Invalid Command
SDO
bit7
SDI
AD3
bit6
AD2
bit5
AD1
bit4
AD0
bit3
C1
bit2
C0
bit1
X
bit0
X
bit0
bit7
Input
Sample
FIGURE 6-4:
8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock
Technology) - SPI Waveform with PIC MCU (Mode 1,1).
VIH
CS
VIHH
VIL
SCK
Write to
SSPBUF
SDO
SDI
CMDERR bit
“1” = Valid Command
“0” = Invalid Command
bit7
AD3
bit7
bit6
AD2
bit5
AD1
bit4
AD0
bit3
C1
bit2
C0
bit1
X
bit0
X
bit0
Input
Sample
FIGURE 6-5:
8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock
Technology) - SPI Waveform with PIC MCU (Mode 0,0).
DS22233A-page 46
© 2009 Microchip Technology Inc.
MCP434X/436X
7.0
DEVICE COMMANDS
7.1
Command Byte
The Command Byte has three fields, the Address, the
Command, and 2 Data bits, see Figure 7-1. Currently
only one of the data bits is defined (D8). This is for the
Write command.
The MCP43XX’s SPI command format supports 16
memory address locations and four commands. Each
command has two modes. These are:
• Normal Serial Commands
• High-Voltage Serial Commands
The device memory is accessed when the master
sends a proper Command Byte to select the desired
operation. The memory location getting accessed is
contained in the Command Byte’s AD3:AD0 bits. The
action desired is contained in the Command Byte’s
C1:C0 bits, see Table 7-1. C1:C0 determines if the
desired memory location will be read, written,
Incremented (wiper setting +1) or Decremented (wiper
setting -1). The Increment and Decrement commands
are only valid on the volatile wiper registers, and in
High Voltage commands to enable/disable WiperLock
Technology and Software Write Protect.
Normal serial commands are those where the CS pin is
driven to VIL. With High-Voltage Serial Commands, the
CS pin is driven to VIHH. In each mode, there are four
possible commands. These commands are shown in
Table 7-1.
The 8-bit commands (Increment Wiper and
Decrement Wiper commands) contain a Command
Byte, see Figure 7-1, while 16-bit commands (Read
Data and Write Data commands) contain a Command
Byte and a Data Byte. The Command Byte contains
two data bits, see Figure 7-1.
As the Command Byte is being loaded into the device
(on the SDI pin), the device’s SDO pin is driving. The
SDO pin will output high bits for the first six bits of that
command. On the 7th bit, the SDO pin will output the
CMDERR bit state (see Section 7.3 “Error
Condition”). The 8th bit state depends on the
command selected.
Table 7-2 shows the supported commands for each
memory location and the corresponding values on the
SDI and SDO pins.
Table 7-3 shows an overview of all the SPI commands
and their interaction with other device features.
TABLE 7-1:
COMMAND BIT OVERVIEW
C1:C0
Bit
Command
States
# of
Bits
Operates on
Volatile/
Non-Volatile
memory
11
Read Data
16-Bits Both
00
Write Data
16-Bits Both
8-Bits Volatile Only
01
Increment (1)
10
Decrement (1)
8-Bits Volatile Only
Note 1: High Voltage Increment and Decrement
commands on select non-volatile memory
locations
enable/disable
WiperLock
Technology and the software Write
Protect feature.
16-bit Command
8-bit Command
Command Byte
A A A A C C D D
D D D D 1 0 9 8
3 2 1 0
Memory
Address
Data
Bits
Command
Bits
FIGURE 7-1:
Command Byte
Data Byte
A A A A C C D D D D D D D D D D
D D D D 1 0 9 8 7 6 5 4 3 2 1 0
3 2 1 0
Data
Bits
Memory
Address
Command
Bits
Command
Bits
CC
1 0
0 0 = Write Data
0 1 = INCR
1 0 = DECR
1 1 = Read Data
General SPI Command Formats.
© 2009 Microchip Technology Inc.
DS22233A-page 47
MCP434X/436X
TABLE 7-2:
MEMORY MAP AND THE SUPPORTED COMMANDS
Address
Value
Function
00h
Volatile Wiper 0
01h
Volatile Wiper 1
02h
NV Wiper 0
03h
NV Wiper 1
Command
Data
(10-bits) (1)
SPI String (Binary)
MOSI (SDI pin)
MISO (SDO pin) (2)
Write Data
nn nnnn nnnn
0000 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
0000 11nn nnnn nnnn
1111 111n nnnn nnnn
Increment Wiper
—
0000 0100
1111 1111
Decrement Wiper
—
0000 1000
1111 1111
Write Data
nn nnnn nnnn
0001 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
0001 11nn nnnn nnnn
1111 111n nnnn nnnn
Increment Wiper
—
0001 0100
1111 1111
Decrement Wiper
—
0001 1000
1111 1111
Write Data
nn nnnn nnnn
0010 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
0010 11nn nnnn nnnn
1111 111n nnnn nnnn
1111 1111
HV Inc. (WL0 DIS) (3)
—
0010 0100
HV Dec. (WL0 EN) (4)
—
0010 1000
1111 1111
Write Data
nn nnnn nnnn
0011 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
0011 11nn nnnn nnnn
1111 111n nnnn nnnn
HV Inc. (WL1 DIS) (3)
—
0011 0100
1111 1111
HV Dec. (WL1 EN) (4)
—
0011 1000
1111 1111
04h (5) Volatile
TCON 0 Register
Write Data
nn nnnn nnnn
0100 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
0100 11nn nnnn nnnn
1111 111n nnnn nnnn
05h (5) Status Register
Read Data
nn nnnn nnnn
0101 11nn nnnn nnnn
1111 111n nnnn nnnn
Write Data
nn nnnn nnnn
0110 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
0110 11nn nnnn nnnn
1111 111n nnnn nnnn
06h
Volatile Wiper 2
07h
Volatile Wiper 3
08h
NV Wiper 2
09h
NV Wiper 3
Increment Wiper
—
0110 0100
1111 1111
Decrement Wiper
—
0110 1000
1111 1111
Write Data
nn nnnn nnnn
0111 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
0111 11nn nnnn nnnn
1111 111n nnnn nnnn
Increment Wiper
—
0111 0100
1111 1111
Decrement Wiper
—
0111 1000
1111 1111
Write Data
nn nnnn nnnn
1000 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
1000 11nn nnnn nnnn
1111 111n nnnn nnnn
1111 1111
HV Inc. (WL2 DIS) (3)
—
1000 0100
HV Dec. (WL2 EN) (4)
—
1000 1000
1111 1111
Write Data
nn nnnn nnnn
1001 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
1001 11nn nnnn nnnn
1111 111n nnnn nnnn
HV Inc. (WL3 DIS) (3)
—
1001 0100
1111 1111
HV Dec. (WL3 EN) (4)
—
1001 1000
1111 1111
0Ah (5) Volatile
TCON 1 Register
Write Data
nn nnnn nnnn
1010 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
1010 11nn nnnn nnnn
1111 111n nnnn nnnn
0Bh (5) Data EEPROM
Write Data
nn nnnn nnnn
1011 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
1011 11nn nnnn nnnn
1111 111n nnnn nnnn
Write Data
nn nnnn nnnn
1100 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
1100 11nn nnnn nnnn
1111 111n nnnn nnnn
Write Data
nn nnnn nnnn
1101 00nn nnnn nnnn
1111 1111 1111 1111
0Ch (5) Data EEPROM
0Dh (5) Data EEPROM
0Eh (5) Data EEPROM
0Fh
Note
Data EEPROM
1:
2:
3:
4:
5:
Read Data
nn nnnn nnnn
1101 11nn nnnn nnnn
1111 111n nnnn nnnn
Write Data
nn nnnn nnnn
1110 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
1110 11nn nnnn nnnn
1111 111n nnnn nnnn
Write Data
nn nnnn nnnn
1111 00nn nnnn nnnn
1111 1111 1111 1111
Read Data
nn nnnn nnnn
1111 11nn nnnn nnnn
1111 111n nnnn nnnn
HV Inc. (WP DIS) (3)
—
1111 0100
1111 1111
HV Dec. (WP EN) (4)
—
1111 1000
1111 1111
The Data Memory is only 9-bits wide, so the MSb is ignored by the device.
All these Address/Command combinations are valid, so the CMDERR bit is set. Any other Address/Command combination is a
command error state and the CMDERR bit will be clear.
Disables WiperLock Technology for wiper 0, wiper 1, wiper 2, wiper3, or disables Write Protect.
Enables WiperLock Technology for wiper 0, wiper 1, wiper 2, wiper3, or enables Write Protect.
Increment or Decrement commands are invalid for these addresses.
DS22233A-page 48
© 2009 Microchip Technology Inc.
MCP434X/436X
7.2
Data Byte
Only the Read Command and the Write Command use
the Data Byte, see Figure 7-1. These commands
concatenate the 8 bits of the Data Byte with the one
data bit (D8) contained in the Command Byte to form
9-bits of data (D8:D0). The Command Byte format
supports up to 9-bits of data so that the 8-bit resistor
network can be set to Full Scale (100h or greater). This
allows wiper connections to Terminal A and to
Terminal B.
The D9 bit is currently unused, and corresponds to the
position on the SDO data of the CMDERR bit.
7.3
Error Condition
The CMDERR bit indicates if the four address bits
received (AD3:AD0) and the two command bits
received (C1:C0) are a valid combination (see
Table 4-1). The CMDERR bit is high if the combination
is valid and low if the combination is invalid.
The command error bit will also be low if a write to a
Non-Volatile Address has been specified and another
SPI command occurs before the CS pin is driven
inactive (VIH).
SPI commands that do not have a multiple of 8 clocks
are ignored.
Once an error condition has occurred, any following
commands are ignored. All following SDO bits will be
low until the CMDERR condition is cleared by forcing
the CS pin to the inactive state (VIH).
© 2009 Microchip Technology Inc.
7.3.1
ABORTING A TRANSMISSION
All SPI transmissions must have the correct number of
SCK pulses to be executed. The command is not
executed until the complete number of clocks have
been received. Some commands also require the CS
pin to be forced inactive (VIH). If the CS pin is forced to
the inactive state (VIH) the serial interface is reset.
Partial commands are not executed.
SPI is more susceptible to noise than other bus
protocols. The most likely case is that this noise
corrupts the value of the data being clocked into the
MCP43XX or the SCK pin is injected with extra clock
pulses. This may cause data to be corrupted in the
device, or a command error to occur, since the address
and command bits were not a valid combination. The
extra SCK pulse will also cause the SPI data (SDI) and
clock (SCK) to be out of sync. Forcing the CS pin to the
inactive state (VIH) resets the serial interface. The SPI
interface will ignore activity on the SDI and SCK pins
until the CS pin transition to the active state is detected
(VIH to VIL or VIH to VIHH).
Note 1: When data is not being received by the
MCP43XX, It is recommended that the
CS pin be forced to the inactive level (VIL)
2: It is also recommended that long
continuous command strings should be
broken down into single commands or
shorter continuous command strings.
This reduces the probability of noise on
the SCK pin corrupting the desired SPI
commands.
DS22233A-page 49
MCP434X/436X
7.4
Continuous Commands
The device supports the ability to execute commands
continuously. While the CS pin is in the active state (VIL
or VIHH). Any sequence of valid commands may be
received.
The following example is a valid sequence of events:
1.
2.
3.
4.
5.
6.
7.
8.
CS pin driven active (VIL or VIHH).
Read Command.
Increment Command (Wiper 0).
Increment Command (Wiper 0).
Decrement Command (Wiper 1).
Write Command (Volatile memory).
Write Command (Non-Volatile memory).
CS pin driven inactive (VIH).
DS22233A-page 50
Note 1: It is recommended that while the CS pin is
active, only one type of command should
be issued. When changing commands, it
is recommended to take the CS pin
inactive then force it back to the active
state.
2: It is also recommended that long
command strings should be broken down
into shorter command strings. This
reduces the probability of noise on the
SCK pin corrupting the desired SPI
command string.
© 2009 Microchip Technology Inc.
MCP434X/436X
TABLE 7-3:
COMMANDS
Command Name
Write Data
Read Data
# of
Bits
16-Bits
16-Bits
Impact on
WiperLock or
Write Protect
Works
when
Wiper is
“locked”?
—
unlocked (1)
No
—
unlocked
(1)
No
(1)
No
Operates on
High
Writes
Volatile/
Voltage
Value in
Non-Volatile (VIHH) on
EEPROM
CS pin?
memory
Yes (1)
—
Both
Both
Increment Wiper
8-Bits
—
Volatile Only
—
unlocked
Decrement Wiper
8-Bits
—
Volatile Only
—
unlocked (1)
No
High Voltage Write Data
16-Bits
Yes
Both
Yes
unchanged
No
High Voltage Read Data
16-Bits
—
Both
Yes
unchanged
Yes
High Voltage Increment Wiper
8-Bits
—
Volatile Only
Yes
unchanged
No
High Voltage Decrement Wiper
8-Bits
—
Volatile Only
Yes
unchanged
No
(2)
Non-Volatile
Only (2)
Yes
locked/
protected (2)
Yes
Non-Volatile
Only (3)
Yes
unlocked/
unprotected (3)
Yes
Modify Write Protect or WiperLock Technology (High Voltage) Enable
8-Bits
—
Modify Write Protect or WiperLock Technology (High Voltage) Disable
8-Bits
— (3)
Note 1: This command will only complete if wiper is “unlocked” (WiperLock Technology is Disabled).
2: If the command is executed using address 02h, 03h, 08h, or 09h then that corresponding wiper is locked or
if with address 0Fh, then Write Protect is enabled.
3: If the command is executed using with address 02h, 03h, 08h, or 09h, then that corresponding wiper is
unlocked or if with address 0Fh, then Write Protect is disabled.
© 2009 Microchip Technology Inc.
DS22233A-page 51
MCP434X/436X
7.5
Write Data
Normal and High Voltage
7.5.2
The sequence to write to a single non-volatile memory
location is the same as a single write to volatile memory
with the exception that after the CS pin is driven
inactive (VIH), the EEPROM write cycle (tWC) is started.
A write cycle will not start if the write command isn’t
exactly 16 clocks pulses. This protects against system
issues from corrupting the Non-Volatile memory
locations.
The Write command is a 16-bit command. The Write
Command can be issued to both the Volatile and
Non-Volatile memory locations. The format of the
command is shown in Figure 7-2.
A Write command to a Volatile memory location
changes that location after a properly formatted Write
Command (16-clock) have been received.
A Write command to a Non-Volatile memory location
will only start a write cycle after a properly formatted
Write Command (16-clock) have been received and the
CS pin transitions to the inactive state (VIH).
Note:
7.5.1
SINGLE WRITE TO NON-VOLATILE
MEMORY
After the CS pin is driven inactive (VIH), the serial
interface may immediately be re-enabled by driving the
CS pin to the active state (VILor VIHH).
During an EEPROM write cycle, only serial commands
to Volatile memory (addresses 00h, 01h, 04h, 05h, 06h,
07h, and 0Ah) are accepted. All other serial commands
are ignored until the EEPROM write cycle (twc) completes. This allows the Host Controller to operate on the
Volatile Wiper registers and the TCON register, and to
Read the Status Register. The EEWA bit in the Status
register indicates the status of an EEPROM Write
Cycle.
Writes to certain memory locations will be
dependant on the state of the WiperLock
Technology bits and the Write Protect bit.
SINGLE WRITE TO VOLATILE
MEMORY
The write operation requires that the CS pin be in the
active state (VILor VIHH). Typically, the CS pin will be in
the inactive state (VIH) and is driven to the active state
(VIL). The 16-bit Write Command (Command Byte and
Data Byte) is then clocked in on the SCK and SDI pins.
Once all 16 bits have been received, the specified
volatile address is updated. A write will not occur if the
write command isn’t exactly 16 clocks pulses. This
protects against system issues from corrupting the
Non-Volatile memory locations.
Once a write command to a Non-Volatile memory
location has been received, NO other SPI commands
should be received before the CS pin transitions to the
inactive state (VIH) or the current SPI command will
have a Command Error (CMDERR) occur.
Figure 6-2 and Figure 6-3 show possible waveforms
for a single write.
COMMAND BYTE
A
D
3
1
SDO
1
SDI
A
D
2
1
1
A
D
1
1
1
A
D
0
1
1
DATA BYTE
0
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1 Valid Address/Command combination
0 Invalid Address/Command combination (1)
Note 1: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-2:
DS22233A-page 52
Write Command - SDI and SDO States.
© 2009 Microchip Technology Inc.
MCP434X/436X
7.5.3
CONTINUOUS WRITES TO
VOLATILE MEMORY
7.5.4
Continuous writes are possible only when writing to the
volatile memory registers (address 00h, 01h, and 04h).
Continuous writes to non-volatile memory are not
allowed, and attempts to do so will result in a command
error (CMDERR) condition.
Figure 7-3 shows the sequence for three continuous
writes. The writes do not need to be to the same volatile
memory address.
COMMAND BYTE
SDI
SDO
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
CONTINUOUS WRITES TO
NON-VOLATILE MEMORY
DATA BYTE
0
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
1*
1
1
1
1
1
1
1
1
1
0
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
1*
1
1
1
1
1
1
1
1
1
0
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
1*
1
1
1
1
1
1
1
1
1
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be
driven low until the CS pin is driven inactive (VIH).
FIGURE 7-3:
Continuous Write Sequence (Volatile Memory only).
© 2009 Microchip Technology Inc.
DS22233A-page 53
MCP434X/436X
7.6
Read Data
Normal and High Voltage
7.6.1
SINGLE READ
The read operation requires that the CS pin be in the
active state (VILor VIHH). Typically, the CS pin will be in
the inactive state (VIH) and is driven to the active state
(VILor VIHH). The 16-bit Read Command (Command
Byte and Data Byte) is then clocked in on the SCK and
SDI pins. The SDO pin starts driving data on the 7th bit
(CMDERR bit) and the addressed data comes out on
the 8th through 16th clocks. Figure 6-2 through
Figure 6-3 show possible waveforms for a single read.
The Read command is a 16-bit command. The Read
Command can be issued to both the Volatile and
Non-Volatile memory locations. The format of the
command is shown in Figure 7-4.
The first 6 bits of the Read command determine the
address and the command. The 7th clock will output
the CMDERR bit on the SDO pin. The remaining
9-clocks the device will transmit the 9 data bits (D8:D0)
of the specified address (AD3:AD0).
Figure 7-4 shows the SDI and SDO information for a
Read command.
During a write cycle (Write or High Voltage Write to a
Non-Volatile memory location) the Read command can
only read the Volatile memory locations. By reading the
Status Register (04h), the Host Controller can
determine when the write cycle has completed (via the
state of the EEWA bit).
COMMAND BYTE
SDI
SDO
DATA BYTE
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
0
D
8
0
D
7
0
D
6
0
D
5
0
D
4
0
D
3
0
D
2
0
D
1
0
D Valid Address/Command combination
0
0 Attempted Non-Volatile Memory Read
during Non-Volatile Memory Write Cycle
READ DATA
FIGURE 7-4:
DS22233A-page 54
Read Command - SDI and SDO States.
© 2009 Microchip Technology Inc.
MCP434X/436X
7.6.2
CONTINUOUS READS
Figure 7-5 shows the sequence for three continuous
reads. The reads do not need to be to the same
memory address.
Continuous reads allow the devices memory to be read
quickly. Continuous reads are possible to all memory
locations. If a non-volatile memory write cycle is
occurring, then Read commands may only access the
volatile memory locations.
COMMAND BYTE
SDI
SDO
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
DATA BYTE
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1* D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1* D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1* D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be
driven low until the CS pin is driven inactive (VIH).
FIGURE 7-5:
Continuous Read Sequence.
© 2009 Microchip Technology Inc.
DS22233A-page 55
MCP434X/436X
7.7
Increment Wiper
Normal and High Voltage
The Increment Command is an 8-bit command. The
Increment Command can only be issued to volatile
memory locations. The format of the command is
shown in Figure 7-6.
An Increment Command to the volatile memory
location changes that location after a properly
formatted command (8-clocks) have been received.
Increment commands provide a quick and easy
method to modify the value of the volatile wiper location
by +1 with minimal overhead.
COMMAND BYTE
(INCR COMMAND (n+1))
A
D
3
1
SDO
1
SDI
A
D
2
1
1
A
D
1
1
1
A
D
0
1
1
0
1
X
X
1
1
1
1
1*
0
1 Note 1, 2
0 Note 1, 3
Note 1: Only functions when writing the volatile
wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination
all following SDO bits will be low until the
CMDERR condition is cleared.
(the CS pin is forced to the inactive
state).
4: If a Command Error (CMDERR) occurs
at this bit location (*), then all following
SDO bits will be driven low until the CS
pin is driven inactive (VIH).
FIGURE 7-6:
Increment Command SDI and SDO States.
Note:
Table 7-2 shows the valid addresses for
the Increment Wiper command. Other
addresses are invalid.
DS22233A-page 56
7.7.1
SINGLE INCREMENT
Typically, the CS pin starts at the inactive state (VIH),
but may be already be in the active state due to the
completion of another command.
Figure 6-4 through Figure 6-5 show possible
waveforms for a single increment. The increment
operation requires that the CS pin be in the active state
(VILor VIHH). Typically, the CS pin will be in the inactive
state (VIH) and is driven to the active state (VILor VIHH).
The 8-bit Increment Command (Command Byte) is
then clocked in on the SDI pin by the SCK pins. The
SDO pin drives the CMDERR bit on the 7th clock.
The wiper value will increment up to 100h on 8-bit
devices and 80h on 7-bit devices. After the wiper value
has reached Full Scale (8-bit =100h, 7-bit =80h), the
wiper value will not be incremented further. If the Wiper
register has a value between 101h and 1FFh, the
Increment command is disabled. See Table 7-4 for
additional information on the Increment Command
versus the current volatile wiper value.
The Increment operations only require the Increment
command byte while the CS pin is active (VILor VIHH)
for a single increment.
After the wiper is incremented to the desired position,
the CS pin should be forced to VIH to ensure that
unexpected transitions on the SCK pin do not cause
the wiper setting to change. Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired increment occurs.
TABLE 7-4:
Current Wiper
Setting
7-bit
Pot
8-bit
Pot
3FFh
081h
080h
07Fh
041h
040h
03Fh
001h
000h
3FFh
101h
100h
0FFh
081
080h
07Fh
001
000h
INCREMENT OPERATION VS.
VOLATILE WIPER VALUE
Wiper (W)
Properties
Reserved
(Full Scale (W = A))
Full Scale (W = A)
W=N
Increment
Command
Operates?
No
No
W = N (Mid Scale)
W=N
Yes
Zero Scale (W = B)
Yes
© 2009 Microchip Technology Inc.
MCP434X/436X
7.7.2
CONTINUOUS INCREMENTS
Increment commands can be sent repeatedly without
raising CS until a desired condition is met. The value in
the Volatile Wiper register can be read using a Read
Command and written to the corresponding
Non-Volatile Wiper EEPROM using a Write Command.
Continuous Increments are possible only when writing
to the volatile memory registers (address 00h, and
01h).
Figure 7-7 shows a Continuous Increment sequence
for three continuous writes. The writes do not need to
be to the same volatile memory address.
When executing a continuous command string, the
Increment command can be followed by any other valid
command.
When executing an continuous Increment commands,
the selected wiper will be altered from n to n+1 for each
Increment command received. The wiper value will
increment up to 100h on 8-bit devices and 80h on 7-bit
devices. After the wiper value has reached Full Scale
(8-bit =100h, 7-bit =80h), the wiper value will not be
incremented further. If the Wiper register has a value
between 101h and 1FFh, the Increment command is
disabled.
(INCR COMMAND (n+1))
A
D
3
1
1
SDO
1
1
A
D
2
1
1
1
1
A
D
1
1
1
1
1
A
D
0
1
1
1
1
After the wiper is incremented to the desired position,
the CS pin should be forced to VIH to ensure that
unexpected transitions (on the SCK pin do not cause
the wiper setting to change). Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired increment occurs.
COMMAND BYTE
COMMAND BYTE
COMMAND BYTE
SDI
The wiper terminal will move after the command has
been received (8th clock).
(INCR COMMAND (n+2))
0
1
X
X
1
1
1
1
1
1
1
1
1*
0
1
1
1
0
1
1
A
D
3
1
0
1
1
A
D
2
1
0
1
1
A
D
1
1
0
1
1
A
D
0
1
0
1
1
(INCR COMMAND (n+3))
0
1
X
X
1
0
1
1
1
0
1
1
1*
0
0
1
1
0
0
1
A
D
3
1
0
0
1
A
D
2
1
0
0
1
A
D
1
1
0
0
1
A
D
0
1
0
0
1
0
1
X
X
1
0
0
1
1
0
0
1
1*
0
0
0
1
0
0
0
Note 1, 2
Note 3, 4
Note 3, 4
Note 3, 4
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination.
4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-7:
Continuous Increment Command - SDI and SDO States.
© 2009 Microchip Technology Inc.
DS22233A-page 57
MCP434X/436X
7.8
Decrement Wiper
Normal and High Voltage
The Decrement Command is an 8-bit command. The
Decrement Command can only be issued to volatile
memory locations. The format of the command is
shown in Figure 7-6.
A Decrement Command to the volatile memory location
changes that location after a properly formatted
command (8 clocks) have been received.
Decrement commands provide a quick and easy
method to modify the value of the volatile wiper location
by -1 with minimal overhead.
COMMAND BYTE
(DECR COMMAND (n+1))
A
D
3
1
SDO
1
SDI
A
D
2
1
1
A
D
1
1
1
A
D
0
1
1
1
0
X
X
1
1
1
1
1*
0
1 Note 1, 2
0 Note 1, 3
Note 1: Only functions when writing the volatile
wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination
all following SDO bits will be low until the
CMDERR condition is cleared.
(the CS pin is forced to the inactive
state).
4: If a Command Error (CMDERR) occurs
at this bit location (*), then all following
SDO bits will be driven low until the CS
pin is driven inactive (VIH).
FIGURE 7-8:
Decrement Command SDI and SDO States.
Note:
Table 7-2 shows the valid addresses for
the Decrement Wiper command. Other
addresses are invalid.
DS22233A-page 58
7.8.1
SINGLE DECREMENT
Typically, the CS pin starts at the inactive state (VIH),
but may already be in the active state due to the
completion of another command.
Figure 6-4 through Figure 6-5 show possible
waveforms for a single Decrement. The decrement
operation requires that the CS pin be in the active state
(VILor VIHH). Typically, the CS pin will be in the inactive
state (VIH) and is driven to the active state (VILor VIHH).
Then the 8-bit Decrement Command (Command Byte)
is clocked in on the SDI pin by the SCK pins. The SDO
pin drives the CMDERR bit on the 7th clock.
The wiper value will decrement from the wiper’s Full
Scale value (100h on 8-bit devices and 80h on 7-bit
devices). Above the wiper’s Full Scale value
(8-bit =101h to 1FFh, 7-bit = 81h to FFh), the
decrement command is disabled. If the Wiper register
has a Zero Scale value (000h), then the wiper value will
not decrement. See Table 7-4 for additional information
on the Decrement Command vs. the current volatile
wiper value.
The Decrement commands only require the Decrement
command byte, while the CS pin is active (VILor VIHH)
for a single decrement.
After the wiper is decremented to the desired position,
the CS pin should be forced to VIH to ensure that
unexpected transitions on the SCK pin do not cause
the wiper setting to change. Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired decrement occurs.
TABLE 7-5:
Current Wiper
Setting
7-bit
Pot
8-bit
Pot
3FFh
081h
080h
07Fh
041h
040h
03Fh
001h
000h
3FFh
101h
100h
0FFh
081
080h
07Fh
001
000h
DECREMENT OPERATION VS.
VOLATILE WIPER VALUE
Wiper (W)
Properties
Reserved
(Full Scale (W = A))
Full Scale (W = A)
W=N
Decrement
Command
Operates?
No
Yes
W = N (Mid Scale)
W=N
Yes
Zero Scale (W = B)
No
© 2009 Microchip Technology Inc.
MCP434X/436X
7.8.2
CONTINUOUS DECREMENTS
Decrement commands can be sent repeatedly without
raising CS until a desired condition is met. The value in
the Volatile Wiper register can be read using a Read
Command and written to the corresponding
Non-Volatile Wiper EEPROM using a Write Command.
Continuous Decrements are possible only when writing
to the volatile memory registers (address 00h, 01h, and
04h).
Figure 7-9 shows a continuous Decrement sequence
for three continuous writes. The writes do not need to
be to the same volatile memory address.
When executing a continuous command string, the
Decrement command can be followed by any other
valid command.
When executing continuous Decrement commands,
the selected wiper will be altered from n to n-1 for each
Decrement command received. The wiper value will
decrement from the wiper’s Full Scale value (100h on
8-bit devices and 80h on 7-bit devices). Above the
wiper’s Full Scale value (8-bit =101h to 1FFh,
7-bit = 81h to FFh), the decrement command is
disabled. If the Wiper register has a Zero Scale value
(000h), then the wiper value will not decrement. See
Table 7-4 for additional information on the Decrement
Command vs. the current volatile wiper value.
(DECR COMMAND (n-1))
A
D
3
1
1
SDO
1
1
A
D
2
1
1
1
1
A
D
1
1
1
1
1
A
D
0
1
1
1
1
After the wiper is decremented to the desired position,
the CS pin should be forced to VIH to ensure that
“unexpected” transitions (on the SCK pin do not cause
the wiper setting to change). Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired decrement occurs.
COMMAND BYTE
COMMAND BYTE
COMMAND BYTE
SDI
The wiper terminal will move after the command has
been received (8th clock).
(DECR COMMAND (n-1))
1
0
X
X
1
1
1
1
1
1
1
1
1*
0
1
1
1
0
1
1
A
D
3
1
0
1
1
A
D
2
1
0
1
1
A
D
1
1
0
1
1
A
D
0
1
0
1
1
(DECR COMMAND (n-1))
1
0
X
X
1
0
1
1
1
0
1
1
1*
0
0
1
1
0
0
1
A
D
3
1
0
0
1
A
D
2
1
0
0
1
A
D
1
1
0
0
1
A
D
0
1
0
0
1
1
0
X
X
1
0
0
1
1
0
0
1
1*
0
0
0
1
0
0
0
Note 1, 2
Note 3, 4
Note 3, 4
Note 3, 4
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination.
4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-9:
Continuous Decrement Command - SDI and SDO States.
© 2009 Microchip Technology Inc.
DS22233A-page 59
MCP434X/436X
7.9
Modify Write Protect or WiperLock
Technology (High Voltage)
Enable and Disable
This command is a special case of the High Voltage
Decrement Wiper and High Voltage Increment Wiper
commands to the non-volatile memory locations 02h,
03h, and 0Fh. This command is used to enable or
disable either the software Write Protect, wiper 0, wiper
1, wiper 2 and wiper 3 WiperLock Technology.
Table 7-6 shows the memory addresses, the High
Voltage command and the result of those commands
on the non-volatile WP, WL0 WL1, WL2, or WL3 bits.
The format of the command is shown in Figure 7-8
(Enable) or Figure 7-6 (Disable).
7.9.1
SINGLE ENABLE WRITE PROTECT
OR WIPERLOCK TECHNOLOGY
(HIGH VOLTAGE)
Figure 6-4 through Figure 6-5 show possible
waveforms for a single Modify Write Protect or
WiperLock Technology command.
A Modify Write Protect or WiperLock Technology
Command will only start an EEPROM write cycle (twc)
after a properly formatted Command (8-clocks) has
been received and the CS pin transitions to the inactive
state (VIH).
After the CS pin is driven inactive (VIH), the serial
interface may immediately be re-enabled by driving the
CS pin to the active state (VILor VIHH).
During an EEPROM write cycle, only serial commands
to Volatile memory (addresses 00h, 01h, 04h, 05h, 06h,
07h, and 0Ah) are accepted. All other serial commands
are ignored until the EEPROM write cycle (twc) completes. This allows the Host Controller to operate on the
Volatile Wiper registers and the TCON register, and to
Read the Status Register. The EEWA bit in the Status
register indicates the status of an EEPROM Write
Cycle.
TABLE 7-6:
Memory
Address
ADDRESS MAP TO MODIFY WRITE PROTECT AND WIPERLOCK TECHNOLOGY
Command’s and Result
High Voltage Decrement Wiper
High Voltage Increment Wiper
00h
01h
02h
03h
04h (1)
Wiper 0 register is decremented
Wiper 0 register is incremented
Wiper 1 register is decremented
Wiper 1 register is incremented
WL0 is enabled
WL0 is disabled
WL1 is enabled
WL1 is disabled
TCON0 register not changed, CMDERR bit is
TCON0 register not changed, CMDERR bit is
set
set
05h (1)
STATUS register not changed, CMDERR bit is
STATUS register not changed, CMDERR bit is
set
set
06h
Wiper 2 register is decremented
Wiper 2 register is incremented
07h
Wiper 3 register is decremented
Wiper 3 register is incremented
08h
WL2 is enabled
WL2 is disabled
09h
WL3 is enabled
WL3 is disabled
0Ah (1)
TCON1 register not changed, CMDERR bit is
TCON1 register not changed, CMDERR bit is
set
set
0Bh - 0Eh (1)
Reserved
Reserved
0Fh
WP is enabled
WP is disabled
Note 1: Reserved addresses: Increment or Decrement commands are invalid for these addresses.
DS22233A-page 60
© 2009 Microchip Technology Inc.
MCP434X/436X
8.0
APPLICATIONS EXAMPLES
Non-volatile digital potentiometers have a multitude of
practical uses in modern electronic circuits. The most
popular uses include precision calibration of set point
thresholds, sensor trimming, LCD bias trimming, audio
attenuation, adjustable power supplies, motor control
overcurrent trip setting, adjustable gain amplifiers and
offset trimming. The MCP434X/436X devices can be
used to replace the common mechanical trim pot in
applications where the operating and terminal voltages
are within CMOS process limitations (VDD = 2.7V to
5.5V).
8.1
Split Rail Applications
5V
SDI
CS
SCK
WP
I/O
SDO
FIGURE 8-1:
System 1.
In Example #1 (Figure 8-1), the MCP43XX interface
input signals need to be able to support the PIC MCU
output high voltage (VOH). If the split rail voltage delta
becomes too large, then the customer may be required
to do some level shifting due to MCP43XX VOH levels
related to Host Controller VIH levels.
In Example #2 (Figure 8-2), the MCP43XX interface
input signals need to be able to support the lower
voltage of the PIC MCU output high voltage level (VOH).
Table 8-1 shows an example PIC microcontroller I/O
voltage
specifications
and
the
MCP43XX
specifications. So this PIC MCU operating at 3.3V will
drive a VOH at 2.64V, and for the MCP43XX operating
at 5.5V, the VIH is 2.47V. Therefore, the interface
signals meet specifications.
© 2009 Microchip Technology Inc.
Example Split Rail
5V
3V
MCP4XXX
PIC MCU
For SPI applications, these inputs are:
Figure 8-1 through Figure 8-2 show three example split
rail systems. In this system, the MCP43XX interface
input signals need to be able to support the PIC MCU
output high voltage (VOH).
SDI
CS
SCK
WP
RESET
SDO
Voltage
Regulator
An example of this is a battery application where the
PIC® MCU is directly powered by the battery supply
(4.8V) and the MCP43XX device is powered by the
3.3V regulated voltage.
CS
SCK
SDI (or SDI/SDO)
WP
RESET
MCP4XXX
PIC MCU
All inputs that would be used to interface to a Host
Controller support High Voltage on their input pin. This
allows the MCP43XX device to be used in split power
rail applications.
•
•
•
•
•
3V
Voltage
Regulator
SDI
CS
SCK
WP
I/O
SDI
CS
SCK
WP
RESET
SDO
SDO
FIGURE 8-2:
System 2.
Example Split Rail
TABLE 8-1:
VOH - VIH COMPARISONS
PIC
(1)
MCP4XXX (2)
Comment
VDD
5.5
5.0
4.5
3.3
3.0
2.7
Note
VIH
VOH VDD
VIH
VOH
4.4
4.4
2.7 1.215 — (3)
4.0
4.0
3.0 1.35 — (3)
3.6
3.6
3.3 1.485 — (3)
2.64 2.64 4.5 2.025 — (3)
2.4
2.4
5.0 2.25 — (3)
2.16 2.16 5.5 2.475 — (3)
1: VOH minimum = 0.8 * VDD;
VOL maximum = 0.6V
VIH minimum = 0.8 * VDD;
VIL maximum = 0.2 * VDD;
2: VOH minimum (SDA only) =;
VOL maximum = 0.2 * VDD
VIH minimum = 0.45 * VDD;
VIL maximum = 0.2 * VDD
3: The only MCP4XXX output pin is SDO,
which is Open-Drain (or Open-Drain with
Internal Pull-up) with High Voltage Support
DS22233A-page 61
MCP434X/436X
8.2
Techniques to Force the CS Pin to
VIHH
PIC10F206
The circuit in Figure 8-3 shows a method using the
TC1240A doubling charge pump. When the SHDN pin
is high, the TC1240A is off, and the level on the CS pin
is controlled by the PIC® microcontrollers (MCUs) IO2
pin.
When the SHDN pin is low, the TC1240A is on and the
VOUT voltage is 2 * VDD. The resistor R1 allows the CS
pin to go higher than the voltage such that the PIC
MCU’s IO2 pin “clamps” at approximately VDD.
PIC MCU
TC1240A
C+
VIN
CSHDN
C1
VOUT
IO1
MCP4XXX
R1
CS
IO2
C2
FIGURE 8-3:
Using the TC1240A to
Generate the VIHH Voltage.
The circuit in Figure 8-4 shows the method used on the
MCP402X
Non-volatile
Digital
Potentiometer
Evaluation Board (Part Number: MCP402XEV). This
method requires that the system voltage be
approximately 5V. This ensures that when the
PIC10F206 enters a brown-out condition, there is an
insufficient voltage level on the CS pin to change the
stored value of the wiper. The MCP402X Non-volatile
Digital Potentiometer Evaluation Board User’s Guide
(DS51546) contains a complete schematic.
R1
GP0
MCP4XXX
GP2
CS
C1
FIGURE 8-4:
MCP4XXX Non-volatile
Digital Potentiometer Evaluation Board
(MCP402XEV) implementation to generate the
VIHH voltage.
8.3
Using Shutdown Modes
Figure 8-5 shows a possible application circuit where
the independent terminals could be used.
Disconnecting the wiper allows the transistor input to
be taken to the Bias voltage level (disconnecting A and
or B may be desired to reduce system current).
Disconnecting Terminal A modifies the transistor input
by the RBW rheostat value to the Common B.
Disconnecting Terminal B modifies the transistor input
by the RAW rheostat value to the Common A. The
Common A and Common B connections could be
connected to VDD and VSS.
Common A
Input
A
GP0 is a general purpose I/O pin, while GP2 can either
be a general purpose I/O pin or it can output the internal
clock.
To base
of Transistor
(or Amplifier)
W
For the serial commands, configure the GP2 pin as an
input (high impedance). The output state of the GP0 pin
will determine the voltage on the CS pin (VIL or VIH).
For high-voltage serial commands, force the GP0
output pin to output a high level (VOH) and configure the
GP2 pin to output the internal clock. This will form a
charge pump and increase the voltage on the CS pin
(when the system voltage is approximately 5V).
C2
B
Input
Common B
Balance
Bias
FIGURE 8-5:
Example Application Circuit
using Terminal Disconnects.
DS22233A-page 62
© 2009 Microchip Technology Inc.
MCP434X/436X
8.4
Design Considerations
8.4.2
In the design of a system with the MCP43XX devices,
the following considerations should be taken into
account:
LAYOUT CONSIDERATIONS
Several layout considerations may be applicable to
your application. These may include:
• Power Supply Considerations
• Layout Considerations
• Noise
• Footprint Compatibility
• PCB Area Requirements
8.4.1
8.4.2.1
POWER SUPPLY
CONSIDERATIONS
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-6 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
VDD
Noise
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP43XX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the silicon
is capable of providing. Particularly harsh
environments may require shielding of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
8.4.2.2
Footprint Compatibility
The specification of the MCP43XX pinouts was done to
allow systems to be designed to easily support the use
of either the dual (MCP42XX) or quad (MCP43XX)
device.
Figure 8-7 shows how the dual pinout devices fit on the
quad device footprint. For the Rheostat devices, the
dual device is in the MSOP package, so the footprints
would need to be offset from each other.
0.1 µF
VDD
W
B
MCP434X/436X
A
VSS
FIGURE 8-6:
Connections.
U/D
PICTM Microcontroller
MCP43X1 Quad Potentiometers
0.1 µF
P3A
P3W
P3B
CS
SCK
SDI
VSS
P1B
P1W
P1A
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
12
12
11
P2A
P2W
P2B
VDD
SDO
RESET
WP
P0B
P0W
P0A
MCP42X1 Pinout (1)
TSSOP
MCP43X2 Quad Rheostat
CS
VSS
Typical Microcontroller
P3W
P3B
CS
SCK
SDI
VSS
P1B
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P2W
P2B
VDD
SDO
P0B
P0W
P1W
MCP42X2 Pinout
TSSOP
Note 1: Pin 15 (RESET) is the Shutdown (SHDN)
pin on the MCP42x1 device.
FIGURE 8-7:
Quad Pinout (TSSOP
Package) vs. Dual Pinout.
© 2009 Microchip Technology Inc.
DS22233A-page 63
MCP434X/436X
MCP43X1
In some applications, PCB area is a criteria for device
selection. Table 8-2 shows the package dimensions
and area for the different package options. The table
also shows the relative area factor compared to the
smallest area. For space critical applications, the QFN
package would be the suggested package.
PACKAGE FOOTPRINT (1)
TABLE 8-2:
Package
Pins
MCP42X1
PCB Area Requirements
Package Footprint
Dimensions
(mm)
Type
Code
X
Rheostat Devices
MCP42X2
MCP43X2
14
TSSOP
ST
5.10
QFN
ML
4.00
20
TSSOP
ST
6.60
Note 1: Does not include
pattern dimensions.
8.4.3
FIGURE 8-8:
Dual Devices.
Layout to support Quad and
Y
Relative Area
Potentiometers Devices
8.4.2.3
Area (mm2)
Figure 8-8 shows possible layout implementations for
an application to support the quad and dual options on
the same PCB.
6.40 32.64 2.04
4.00 16.00
1
6.40 42.24 2.64
recommended land
RESISTOR TEMPCO
Characterization curves of the resistor temperature
coefficient (Tempco) are shown in Figure 2-8,
Figure 2-19, Figure 2-29, and Figure 2-39.
These curves show that the resistor network is
designed to correct for the change in resistance as
temperature increases. This technique reduces the
end to end change is RAB resistance.
8.4.4
HIGH VOLTAGE TOLERANT PINS
High Voltage support (VIHH) on the Serial Interface pins
supports two features. These are:
• In-Circuit Accommodation of split rail applications
and power supply sync issues
• User configuration of the Non-Volatile EEPROM,
Write Protect, and WiperLock feature
Note:
DS22233A-page 64
In many applications, the High Voltage will
only be present at the manufacturing
stage so as to “lock” the Non-Volatile wiper
value (after calibration) and the contents
of the EEPROM. This ensures that since
High Voltage is not present under normal
operating conditions, these values can not
be modified.
© 2009 Microchip Technology Inc.
MCP434X/436X
9.0
DEVELOPMENT SUPPORT
9.1
Development Tools
9.2
Technical Documentation
Several additional technical documents are available to
assist you in your design and development. These
technical documents include Application Notes,
Technical Briefs, and Design Guides. Table 9-2 shows
some of these documents.
Several development tools are available to assist in
your design and evaluation of the MCP43XX devices.
The currently available tools are shown in Table 9-1.
These boards may be purchased directly from the
Microchip web site at www.microchip.com.
TABLE 9-1:
DEVELOPMENT TOOLS
Board Name
Part #
Supported Devices
20-pin TSSOP and SSOP Evaluation Board
TSSOP20EV
MCP43XX
MCP4361 Evaluation Board (1)
MCP43XXEV
MCP4361
MCP42XX Digital Potentiometer PICtail Plus Demo MCP42XXDM-PTPLS
Board
MCP42XX
MCP4XXX Digital Potentiometer Daughter Board (2)
MCP42XXX, MCP42XX, MCP4021,
and MCP4011
MCP4XXXDM-DB
Note 1: This Evaluation Board is planned to be available by March 2010. This board uses the TSSOP20EV PCB
and requires the PICkit Serial Analyzer (see User’s Guide for details). This kit also includes 1 blank
TSSOP20EV PCB.
2: Requires the use of a PICDEM Demo board (see User’s Guide for details)
TABLE 9-2:
TECHNICAL DOCUMENTATION
Application
Note Number
Title
Literature #
AN1080
Understanding Digital Potentiometers Resistor Variations
DS01080
AN737
Using Digital Potentiometers to Design Low-Pass Adjustable Filters
DS00737
AN692
Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect
DS00692
AN691
Optimizing the Digital Potentiometer in Precision Circuits
DS00691
AN219
Comparing Digital Potentiometers to Mechanical Potentiometers
DS00219
—
Digital Potentiometer Design Guide
DS22017
—
Signal Chain Design Guide
DS21825
© 2009 Microchip Technology Inc.
DS22233A-page 65
MCP434X/436X
NOTES:
DS22233A-page 66
© 2009 Microchip Technology Inc.
MCP434X/436X
10.0
PACKAGING INFORMATION
10.1
Package Marking Information
14-Lead TSSOP
Example
XXXXXXXX
4362502E
YYWW
0940
NNN
256
20-Lead QFN (4x4)
XXXXX
XXXXXX
XXXXXX
YYWWNNN
4361
502EML
e3 0940
^^
256
20-Lead TSSOP
Example
XXXXXXXX
MCP4361
XXXXX NNN
YYWW
e3 256
EST ^^
0940
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
DS22233A-page 67
MCP434X/436X
" #
!
2& '!&" & 3
&& 144***' '4
# * !( 3 ! !
& 3
% & & # &
D
N
E
E1
NOTE 1
1 2
e
b
c
φ
A2
A
A1
5&!
' !6'&!
7"') %!
66++
7
7
3 !!
& #%%
8
9
:,/0
; &
# # 3
78
&
8
L
L1
=#&
<
<
,
,
<
,
+
:/0
# # 3
=#&
+
-
# # 3
6 &
,
,
2&6 &
6
,
:
,
2& &
6
2& >
<
>
6
<
#3 !!
,
+2
6 #=#&
)
<
-
" #
!" # $% &" ' ()"&'"!&) & #*&& & # ' !! #+#&"# '#% ! &"!!#% ! &"!!! & $ #,''
- ' ! #& +.,
/01 / !' ! & $ & " !**&"&& !
+21 % ' !("!" *&"&& (%%' & " ! !
!# * 0 /
DS22233A-page 68
© 2009 Microchip Technology Inc.
MCP434X/436X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2009 Microchip Technology Inc.
DS22233A-page 69
MCP434X/436X
$%
" #
& ' ( " ) * ++%, &'"!
2& '!&" & 3
&& 144***' '4
# * !( 3 ! !
& 3
D
% & & # &
D2
EXPOSED
PAD
e
E2
2
E
b
2
1
1
K
N
N
NOTE 1
TOP VIEW
L
BOTTOM VIEW
A
A1
A3
5&!
' !6'&!
7"') %!
66++
7
7
,/0
& #%%
,
0& &3 !!
-
8
; &
9
&
8
78
=#&
+
+$ ! # #=#&
+
8
6 &
+$ ! # #6 &
+2
/0
:
/0
:
0& &=#&
)
,
-
0& &6 &
6
-
,
0& & & +$ ! # #
?
<
<
" #
!" # $% &" ' ()"&'"!&) & #*&& & # 3
!! *! " & #
- ' ! #& +.,
/01 / !' ! & $ & " !**&"&& !
+21 % ' !("!" *&"&& (%%' & " ! !
* 0 :/
DS22233A-page 70
© 2009 Microchip Technology Inc.
MCP434X/436X
" #
2& '!&" & 3
&& 144***' '4
© 2009 Microchip Technology Inc.
# * !( 3 ! !
& 3
% & & # &
DS22233A-page 71
MCP434X/436X
$%
" #
!
2& '!&" & 3
&& 144***' '4
# * !( 3 ! !
& 3
% & & # &
D
N
E
E1
NOTE 1
1 2
e
b
c
φ
A2
A
A1
L
L1
5&!
' !6'&!
7"') %!
66++
7
7
:,/0
; &
# # 3
3 !!
& #%%
8
9
&
8
78
=#&
<
<
,
,
<
,
+
:/0
# # 3
=#&
+
-
# # 3
6 &
:
:,
::
2&6 &
6
,
:
,
2& &
6
2& >
<
>
6
<
#3 !!
,
+2
6 #=#&
)
<
-
" #
!" # $% &" ' ()"&'"!&) & #*&& & # ' !! #+#&"# '#% ! &"!!#% ! &"!!! & $ #,''
- ' ! #& +.,
/01 / !' ! & $ & " !**&"&& !
+21 % ' !("!" *&"&& (%%' & " ! !
!# * 0 /
DS22233A-page 72
© 2009 Microchip Technology Inc.
MCP434X/436X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2009 Microchip Technology Inc.
DS22233A-page 73
MCP434X/436X
NOTES:
DS22233A-page 74
© 2009 Microchip Technology Inc.
MCP434X/436X
APPENDIX A:
REVISION HISTORY
Revision A (December 2009)
• Original Release of this Document.
© 2009 Microchip Technology Inc.
DS22233A-page 75
MCP434X/436X
NOTES:
DS22233A-page 76
© 2009 Microchip Technology Inc.
MCP434X/436X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
-XXX
X
/XX
Device
Resistance
Version
Temperature
Range
Package
Device
MCP4341:
MCP4341T:
MCP4342:
MCP4342T:
MCP4361:
MCP4361T:
MCP4362:
MCP4362T:
Quad Non-Volatile 7-bit Potentiometer
Quad Non-Volatile 7-bit Potentiometer
(Tape and Reel)
Quad Non-Volatile 7-bit Rheostat
Quad Non-Volatile 7-bit Rheostat
(Tape and Reel)
Quad Non-Volatile 8-bit Potentiometer
Quad Non-Volatile 8-bit Potentiometer
(Tape and Reel)
Quad Non-Volatile 8-bit Rheostat
Quad Non-Volatile 8-bit Rheostat
(Tape and Reel)
Resistance Version:
502
103
503
104
=
=
=
=
5 kΩ
10 kΩ
50 kΩ
100 kΩ
Temperature Range
E
= -40°C to +125°C (Extended)
Package
ST
= Plastic Thin Shrink Small Outline (TSSOP),
14/20-lead
ML = Plastic Quad Flat No-lead (4x4 QFN), 20-lead
© 2009 Microchip Technology Inc.
Examples:
a)
b)
c)
d)
e)
f)
g)
h)
MCP4341-502E/XX:
MCP4341T-502E/XX:
MCP4341-103E/XX:
MCP4341T-103E/XX:
MCP4341-503E/XX:
MCP4341T-503E/XX:
MCP4341-104E/XX:
MCP4341T-104E/XX:
5 kΩ, 20-LD Device
T/R, 5 kΩ, 20-LD Device
10 kΩ, 20-LD Device
T/R, 10 kΩ, 20-LD Device
50 kΩ, 20-LD Device
T/R, 50 kΩ, 20-LD Device
100 kΩ, 20-LD Device
T/R, 100 kΩ,
20-LD Device
a)
b)
c)
d)
e)
f)
g)
h)
MCP4342-502E/XX:
MCP4342T-502E/XX:
MCP4342-103E/XX:
MCP4342T-103E/XX:
MCP4342-503E/XX:
MCP4342T-503E/XX:
MCP4342-104E/XX:
MCP4342T-104E/XX:
5 kΩ, 14-LD Device
T/R, 5 kΩ, 14-LD Device
10 kΩ, 14-LD Device
T/R, 10 kΩ, 14-LD Device
50 kΩ, 8LD Device
T/R, 50 kΩ, 14-LD Device
100 kΩ, 14-LD Device
T/R, 100 kΩ,
14-LD Device
a)
b)
c)
d)
e)
f)
g)
h)
MCP4361-502E/XX:
MCP4361T-502E/XX:
MCP4361-103E/XX:
MCP4361T-103E/XX:
MCP4361-503E/XX:
MCP4361T-503E/XX:
MCP4361-104E/XX:
MCP4361T-104E/XX:
5 kΩ, 20-LD Device
T/R, 5 kΩ, 20-LD Device
10 kΩ, 20-LD Device
T/R, 10 kΩ, 20-LD Device
50 kΩ, 20-LD Device
T/R, 50 kΩ, 20-LD Device
100 kΩ, 20-LD Device
T/R, 100 kΩ,
20-LD Device
a)
b)
c)
d)
e)
f)
g)
h)
MCP4362-502E/XX:
MCP4362T-502E/XX:
MCP4362-103E/XX:
MCP4362T-103E/XX:
MCP4362-503E/XX:
MCP4362T-503E/XX:
MCP4362-104E/XX:
MCP4362T-104E/XX:
5 kΩ, 14-LD Device
T/R, 5 kΩ, 14-LD Device
10 kΩ, 14-LD Device
T/R, 10 kΩ, 14-LD Device
50 kΩ, 14-LD Device
T/R, 50 kΩ, 14-LD Device
100 kΩ, 14-LD Device
T/R, 100 kΩ,
14-LD Device
XX
= ST for 14/20-lead TSSOP
= ML for 20-lead QFN
DS22233A-page 77
MCP434X/436X
NOTES:
DS22233A-page 78
© 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc.
DS22233A-page 79
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
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Tel: 852-2401-1200
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Fax: 91-80-3090-4080
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Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
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Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
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Tel: 45-4450-2828
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Tel: 91-20-2566-1512
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Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/26/09
DS22233A-page 80
© 2009 Microchip Technology Inc.