LTC2757 18-Bit SoftSpan IOUT DAC with Parallel I/O FEATURES DESCRIPTION n The LTC®2757 is an 18-bit multiplying parallel-input, current-output digital-to-analog converter that provides full 18bit performance—INL and DNL of ±1LSB maximum—over temperature without any adjustments. 18-bit monotonicity is guaranteed in all performance grades. This SoftSpan™ DAC operates from a single 3V to 5V supply and offers six output ranges (up to ±10V) that can be programmed through the parallel interface or pin-strapped for operation in a single range. n n n n n n n n n n Maximum 18-Bit INL Error: ±1 LSB Over Temperature Program or Pin-Strap Six Output Ranges: 0V to 5V, 0V to 10V, –2.5V to 7.5V, ±2.5V, ±5V, ±10V Guaranteed Monotonic Over Temperature Low Glitch Impulse 1.4nV • s (3V), 3nV • s (5V) 18-Bit Settling Time: 2.1μs 2.7V to 5.5V Single Supply Operation Reference Current Constant for All Codes Voltage-Controlled Offset and Gain Trims Parallel Interface with Readback of All Registers Clear and Power-On-Reset to 0V Regardless of Output Range 48-Pin 7mm × 7mm LQFP Package APPLICATIONS n n n n Instrumentation Medical Devices Automatic Test Equipment Process Control and Industrial Automation In addition to its precision DC specifications, the LTC2757 also offers excellent AC specifications, including 2.1μs full-scale settling to 1LSB and 1.4nV • s glitch impulse. The LTC2757 uses a bidirectional input/output parallel interface that allows readback of any on-chip register, including DAC output-range settings; and a CLR pin and power-on reset circuit that each reset the DAC output to 0V regardless of output range. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 18-Bit Voltage Output DAC with Software-Selectable Ranges LTC2757 Integral Nonlinearity REF 5V 1.0 0.6 LT1012 0.4 – 150pF RCOM REF ROFS INL (LSB) RIN RFB 27pF WR WR UPD UPD READ READ D/S D/S CLR CLR M-SPAN ±10V RANGE 0.8 + LTC2757 IOUT1 – IOUT2 + 18-BIT DAC WITH SPAN SELECT VOSADJ 0 –0.2 –0.4 –0.6 90°C 25°C –45°C –0.8 LT1468 GND GEADJ 0.2 VOUT –1.0 0 65536 131072 CODE 196608 262143 2757 TA01b 5V VDD 0.1μF 2757 TA01 GAIN ADJUST SPAN I/O S2-S0 DATA I/O D17-D0 OFFSET ADJUST 2757f 1 LTC2757 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) 48 47 46 45 44 43 42 41 40 39 38 37 GEADJ RCOM REF REF ROFS ROFS RFB RFB IOUT1 VOSADJ S1 S0 TOP VIEW 1 2 3 4 IOUT2S 5 IOUT2F 6 GND 7 D17 8 D16 9 D15 10 D14 11 D13 12 36 35 34 33 32 31 30 29 28 27 26 25 RIN RIN S2 GND WR UPD READ D/S DNC D0 D1 D2 D3 D4 D5 D6 D12 13 D11 14 D10 15 D9 16 VDD 17 GND 18 GND 19 CLR 20 M-SPAN 21 DNC 22 D8 23 D7 24 IOUT1, IOUT2, RCOM to GND .....................................±0.3V RFB, ROFS, RIN, REF, VOSADJ, GEADJ to GND ........... ±15V VDD to GND .................................................. –0.3V to 7V S2, S1, S0, D17-D0 to GND ............... –0.3V to VDD + 0.3V (7V Max) WR, UPD, D/S, READ, M-SPAN, CLR to GND .................................. –0.3V to 7V Operating Temperature Range LTC2757C .................................................... 0°C to 70°C LTC2757I..................................................–40°C to 85°C Maximum Junction Temperature .......................... 150°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec)................... 300°C LX PACKAGE 48-LEAD (7mm s 7mm) PLASTIC LQFP TJMAX = 150°C, θJA = 53°C/W ORDER INFORMATION LEAD FREE FINISH PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2757BCLX#PBF LTC2757LX 48-Lead (7mm × 7mm) Plastic LQFP 0°C to 70°C LTC2757BILX#PBF LTC2757LX 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 85°C LTC2757ACLX#PBF LTC2757LX 48-Lead (7mm × 7mm) Plastic LQFP 0°C to 70°C LTC2757AILX#PBF LTC2757LX 48-Lead (7mm × 7mm) Plastic LQFP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ 2757f 2 LTC2757 ELECTRICAL CHARACTERISTICS VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. LTC2757B SYMBOL PARAMETER CONDITIONS MIN TYP LTC2757A MAX MIN TYP MAX UNITS Static Performance Resolution l 18 18 18 Bits Monotonicity l DNL Differential Nonlinearity l ±1 ±0.4 ±1 LSB INL Integral Nonlinearity l ±2 ±0.4 ±1 LSB ±5 ±32 18 l GE Gain Error GEADJ: 0V, All Output Ranges GETC Gain Error Temperature Coefficient (Note 3) BZE Bipolar Zero Error All Bipolar Ranges BZSTC Bipolar Zero Temperature Coefficient (Note 3) PSR Power Supply Rejection VDD = 5V, ±10% VDD = 3V, ±10% l l ILKG IOUT1 Leakage Current TA = 25°C TMIN to TMAX l Bits ±48 ±0.25 l ±0.25 ±36 ±3 ±1.6 ±4 ±0.15 ±0.4 ±0.8 ±2 ±2 ±5 ±0.05 ±2 ±5 ±0.15 ±0.05 LSB ppm/°C ±24 ±0.15 LSB ppm/°C LSB/V nA VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP R1, R2 Reference Inverting Resistors (Note 4) RREF DAC Input Resistance RFB Feedback Resistor MAX UNITS l 16 20 kΩ (Note 5) l 8 10 kΩ (Note 6) l 8 10 kΩ (Note 6) l Analog Pins ROFS Bipolar Offset Resistor 16 20 kΩ RVOSADJ Offset Adjust Resistor l 1024 1280 kΩ RGEADJ Gain Adjust Resistor l 2048 2560 kΩ CIOUT1 Output Capacitance Full-Scale Zero-Scale 90 40 pF pF Output Settling Time Span Code = 000, 10V Step (Note 7) To ±0.0004% FS 2.1 μs Glitch Impulse VDD = 5V (Note 8) VDD = 3V (Note 8) 3 1.4 nV•s nV•s Digital-to-Analog Glitch Impulse VDD = 5V (Note 9) VDD = 3V (Note 9) 4 1.8 nV•s nV•s Reference Multiplying Bandwidth 0V to 5V Range, Code = Full-Scale, –3dB Bandwidth 1 MHz Multiplying Feedthrough Error 0V to 5V Range, VREF = ±10V, 10kHz Sine Wave 0.4 mV Total Harmonic Distortion (Note 10) Multiplying –110 dB Output Noise Voltage Density (Note 11) at IOUT1 Dynamic Performance THD 13 nV/√Hz 2757f 3 LTC2757 ELECTRICAL CHARACTERISTICS VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply VDD Supply Voltage IDD Supply Current, VDD l Digital Inputs = 0V or VDD l 2.7 0.5 5.5 V 1 μA Digital Inputs VIH Digital Input High Voltage 3.3V ≤ VDD ≤ 5.5V 2.7V ≤ VDD < 3.3V l l VIL Digital Input Low Voltage 4.5V < VDD ≤ 5.5V 2.7V ≤ VDD ≤ 4.5V l l 2.4 2 Hysteresis Voltage V V 0.8 0.6 V V 0.1 V IIN Digital Input Current VIN = GND to VDD l ±1 μA CIN Digital Input Capacitance VIN = 0V (Note 12) l 6 pF Digital Outputs VOH IOH = 200μA l VOL IOL = 200μA l VDD – 0.4 V 0.4 V TIMING CHARACTERISTICS VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD = 4.5V to 5.5V Write and Update Timing t1 I/O Valid to WR Rising Edge Set-Up l 9 ns t2 I/O Valid to WR Rising Edge Hold l 9 ns t3 WR Pulse Width l 20 ns t4 UPD Pulse Width l 20 ns t5 UPD Falling Edge to WR Falling Edge No Data Shoot-Through l 0 ns t6 WR Rising Edge to UPD Rising Edge (Note 12) l 0 ns t7 D/S Valid to WR Falling Edge Set-Up Time l 9 ns t8 WR Rising Edge to D/S Valid Hold Time l 9 ns Readback Timing t13 WR Rising Edge to READ Rising Edge l 9 ns t14 READ Falling Edge to WR Falling Edge (Note 12) l 20 ns t15 READ Rising Edge to I/O Propagation Delay CL = 10pF l 30 ns t17 UPD Valid to I/O Propagation Delay CL = 10pF l 30 ns t18 D/S Valid to READ Rising Edge (Note 12) l 9 ns t19 READ Rising Edge to UPD Rising Edge No Update l 9 ns t20 UPD Falling Edge to READ Falling Edge No Update l 9 ns t22 READ Falling Edge to UPD Rising Edge (Note 12) l 9 ns t23 I/O Bus Hi-Z to READ Rising Edge (Note 12) l 0 ns t24 READ Falling Edge to I/O Bus Active (Note 12) l 20 ns 2757f 4 LTC2757 TIMING CHARACTERISTICS VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CLR Timing t25 CLR Pulse Width Low l 20 ns VDD = 2.7V to 3.3V Write and Update Timing t1 I/O Valid to WR Rising Edge Set-Up l 18 ns t2 I/O Valid to WR Rising Edge Hold l 18 ns t3 WR Pulse Width l 30 ns t4 UPD Pulse Width l 30 ns t5 UPD Falling Edge to WR Falling Edge No Data Shoot-Through l 0 ns t6 WR Rising Edge to UPD Rising Edge (Note 12) l 0 ns t7 D/S Valid to WR Falling Edge Set-Up Time l 18 ns t8 WR Rising Edge to D/S Valid Hold Time l 18 ns ns Readback Timing t13 WR Rising Edge to Read Rising Edge l 18 t14 Read Falling Edge to WR Falling Edge (Note 12) l 40 t15 Read Rising Edge to I/O Propagation Delay CL = 10pF l 48 ns t17 UPD Valid to I/O Propagation Delay CL = 10pF l 48 ns t18 D/S Valid to Read Rising Edge (Note 12) l 18 ns t19 Read Rising Edge to UPD Rising Edge No Update l 9 ns ns t20 UPD Falling Edge to Read Falling Edge No Update l 9 ns t22 READ Falling Edge to UPD Rising Edge (Note 12) l 18 ns t23 I/O Bus Hi-Z to Read Rising Edge (Note 12) l 0 ns t24 Read Falling Edge to I/O Bus Active (Note 12) l 40 ns l 30 ns CLR Timing t25 CLR Pulse Width Low Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: Temperature Coefficient is calculated by dividing the maximum change in the parameter by the specified temperature range. Note 4: R1 is measured from RIN to RCOM ; R2 is measured from REF to RCOM . Note 5: Parallel combination of the resistances from REF to IOUT1 and from REF to IOUT2. DAC input resistance is independent of code. Note 6: Because of the proprietary SoftSpan switching architecture, the measured resistance looking into each of the specified pins is constant for all output ranges if the IOUT1 and IOUT2 pins are held at ground. Note 7: Using LT1468 with CFEEDBACK = 27pF. A ±0.0004% settling time of 1.8μs can be achieved by optimizing the time constant on an individual basis. See Application Note 120, 1ppm Settling Time Measurement for a Monolithic 18-Bit DAC. Note 8: Measured at the major carry transition, 0V to 5V range. Output amplifier: LT1468; CFB = 50pF. Note 9: Zero-code to full-code transition; REF = 0V. Falling transition is similar or better. Note 10: REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output amplifier = LT1468. Note 11: Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K (Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B = bandwidth (Hz). Note 12: Guaranteed by design. Not production tested. 2757f 5 LTC2757 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 5V, V(RIN) = 5V, TA = 25°C, unless otherwise noted. Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 ±10V RANGE ±10V RANGE 0.8 0.6 0.6 0.6 0.4 0.4 0.4 0.2 0.2 0.2 0 –0.2 INL (LSB) 0.8 0 –0.2 0 –0.2 –0.4 –0.4 –0.4 –0.6 –0.6 –0.6 –0.8 –0.8 –0.8 –1.0 –1.0 0 131072 CODE 65536 196608 262143 –1.0 0 65536 131072 CODE 196608 2757 G01 DNL vs Temperature 1.0 0V TO 10V RANGE 0.8 0V TO 10V RANGE –INL –0.4 0.2 +DNL 0 –0.2 –0.6 –0.6 –0.8 –0.8 –20 0 20 40 TEMPERATURE (°C) 60 ±2.5V –12 –20 0 20 40 TEMPERATURE (°C) 60 ±0.15ppm/°C TYP ±5V RANGE 0.4 INL (LSB) –2.5V TO 7.5V 0 –INL –INL 0.2 –0.6 –12 –0.8 –0.8 –16 –40 –1.0 –10 –8 –6 –4 –2 0 2 V(RIN) (V) 60 80 85 2757 G07 4 6 8 10 2757 G08 +DNL –DNL –DNL –0.2 –0.4 40 0 20 TEMPERATURE (°C) +DNL 0 –0.6 –20 ±5V RANGE 0.4 0.2 –0.2 80 85 0.6 +INL +INL –0.4 –8 60 0.8 DNL (LSB) ±5V –4 40 0 20 TEMPERATURE (°C) DNL vs Reference Voltage 1.0 0.6 ±2.5V ±10V –20 2757 G06 0.8 12 BZE (LSB) –16 –40 80 85 INL vs Reference Voltage 1.0 4 0V TO 10V 0V TO 5V 2757 G05 Bipolar Zero Error vs Temperature 0 0 –8 2757 G04 8 4 –4 –1.0 –40 80 85 ±10V ±5V ±2.5V TO 7.5V –DNL –0.4 –1.0 –40 GE (LSB) DNL (LSB) 0 –0.2 2757 G03 ±0.25ppm/°C TYP 8 0.4 0.2 –10V TO 10V 12 0.6 +INL 0.4 0V –5V 0V TO TO TO 5V 5V 10V OUTPUT RANGE Gain Error vs Temperature 16 0.8 0.6 16 –2.5V –2.5V TO TO 2.5V 7.5V 262143 2757 G02 INL vs Temperature 1.0 INL (LSB) INL vs Output Range 1.0 0.8 DNL (LSB) INL (LSB) 1.0 –1.0 –10 –8 –6 –4 –2 0 2 V(RIN) (V) 4 6 8 10 2757 G09 2757f 6 LTC2757 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 5V, V(RIN) = 5V, TA = 25°C, unless otherwise noted. INL vs VDD 1.0 ±10V RANGE 0.8 0.6 ALL BITS ON D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0.4 0.4 0.2 0.2 0 –INL –0.2 –20 0.6 +INL DNL (LSB) INL (LSB) ±10V RANGE 0.8 ATTENUATION (dB) 1.0 Multiplying Frequency Response vs Digital Code DNL vs VDD +DNL 0 –0.2 –DNL –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 2.5 –1.0 2.5 –40 –60 –80 –100 0V TO 5V OUTPUT RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 15pF –120 ALL BITS OFF 3 3.5 4.5 4 V(RIN) (V) 5 5.5 3 3.5 4.5 4 V(RIN) (V) 5 2757 G10 –140 100 5.5 1M Mid-Scale Glitch (VDD = 3V) UPD 5V/DIV GATED SETTLING WAVEFORM 100μV/DIV (AVERAGED) 10M 2757 G12 Mid-Scale Glitch (VDD = 5V) 1.4nV•s TYP 3nV•s TYP UPD 5V/DIV UPD 5V/DIV VOUT 10mV/DIV VOUT 10mV/DIV 2757 G13 2757 G14 500ns/DIV 500ns/DIV 2757 G15 LT1468 AMP; CFEEDBACK = 20pF 0V TO 10V STEP VREF = –10V; SPAN CODE = 000 tSETTLE = 1.8μs to 0.0004% (18 BITS) 0V TO 5V RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 50pF RISING MAJOR CARRY TRANSITION. FALLING TRANSITION IS SIMILAR OR BETTER. 0V TO 5V RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 50pF RISING MAJOR CARRY TRANSITION. FALLING TRANSITION IS SIMILAR OR BETTER. Supply Current vs Logic Input Voltage Logic Threshold vs Supply Voltage Supply Current vs Update Frequency 2 ALL DIGITAL PINS TIED TOGETHER (EXCEPT READ TIED TO GND) ALTERNATING ZERO-SCALE/FULL-SCALE 1.75 LOGIC THRESHOLD (V) 10 1000 8 VDD = 5V 6 4 1.5 SUPPLY CURRENT (μA) 12 IDD (mA) 10k 100k FREQUENCY (Hz) 2757 G11 Settling Full-Scale Step 500ns/DIV 1k RISING 1.25 FALLING 1 100 10 1 VDD = 5V 0.75 2 VDD = 3V VDD = 3V 0.5 0 0 1 2 3 LOGIC VOLTAGE (V) 4 5 2757 G16 2.5 3 3.5 4 4.5 VDD (V) 5 5.5 0.1 10 100 10k 100k 1k UPD FREQUENCY (Hz) 1M 2757 G18 2757 G17 2757f 7 LTC2757 PIN FUNCTIONS RIN (Pins 1, 2): Input Resistor for External Reference Inverting Amplifier. Normally tied to the external reference voltage. Typically 5V; accepts up to ±15V. These pins are internally shorted together. S2 (Pin 3): Span I/O Bit 2. Pins S0, S1 and S2 are used to program and to read back the output range of the DAC. See Table 2. GND (Pins 4, 7, 18, 19): Ground. Tie to ground. IOUT2S, IOUT2F (Pins 5, 6): DAC Output Current Complement Sense and Force Pins. Tie to ground via a clean, low-impedance path. These pins may also be used with a precision ground buffer amp as a Kelvin sensing pair (see the Typical Applications section). D17-D9 (Pins 8-16): DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D17 (Pin 8) is the MSB. VDD (Pin 17): Positive Supply Input. 2.7V ≤ VDD ≤ 5.5V. Requires a 0.1μF bypass capacitor to GND. CLR (Pin 20): Asynchronous Clear Input. When CLR is asserted low, the DAC output resets to VOUT = 0V. The LTC2757 selects the appropriate reset code according to the active output range—zero-scale for 0V to 5V and 0V to 10V spans, half scale for ±2.5V, ±5V and ±10V spans, or quarter scale for –2.5V to 7.5V span. M-SPAN (Pin 21): Manual Span Control Input. M-SPAN can be pin-strapped to configure the LTC2757 for operation in a single, fixed output range. To configure the part for single-span use, tie M-SPAN directly to VDD. The output range is then set via hardware pin strapping; and the Span I/O port ignores Write, Update and Read commands. If M-SPAN is instead connected to ground (SoftSpan configuration), the output ranges are set and verified by using Write, Update and Read operations. See Manual Span Configuration in the Operation section. M-SPAN must be connected either directly to GND (for SoftSpan operation) or VDD (for single-span operation). DNC (Pins 22, 32): Do Not Connect. D8-D0 (Pins 23-31): DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D0 is the LSB. D/S (Pin 33): Data/Span Select Input. This pin is used to select activation of the Data (D/S = 0) or Span (D/S = 1) Input I/O pins (D0 to D17 or S0 to S2, respectively), along with their respective dedicated registers, for Write or Read operations. Update operations are unaffected by D/S, since all updates affect both Data and Span registers. For single-span operation, tie D/S to GND. READ (Pin 34): Read Input. When READ is asserted high, the Data I/O pins (D0-D17) or Span I/O pins (S0-S2) output the contents of a selected Input or DAC register (see Table 1). Data/Span ports are selected for readback with the D/S pin; the Input/DAC registers within those ports are selected for readback with the UPD pin. The readback function of the Span I/O pins is disabled when M-SPAN is tied to VDD. UPD (Pin 35): Update/Register Select Input. READ = low: Update function. When UPD is asserted high, the contents of the Input registers are copied into their respective DAC registers. The output of the DAC is updated, reflecting the new DAC register values. READ = high: Register selector function. The Update function is disabled and the UPD pin functions as a register selector. UPD = low selects Input registers for readback, high selects DAC registers. See Readback in the Operation section. WR (Pin 36): Active-Low Write Input. A Write operation copies the data present on the Data or Span I/O pins (D0D17 or S0-S2, respectively) into the Input register. The Write function is disabled when READ is high. S0 (Pin 37): Span I/O Bit 0. Pins S0, S1 and S2 are used to program and to read back the output range of the DAC. See Table 2. S1 (Pin 38): Span I/O Bit 1. Pins S0, S1 and S2 are used to program and to read back the output range of the DAC. See Table 2. 2757f 8 LTC2757 PIN FUNCTIONS VOSADJ (Pin 39): DAC Offset Adjust Pin. This voltage-control pin can be used to null unipolar offset or bipolar zero error. The offset change expressed in LSB is the same for any output range. See System Offset and Gain Adjustments in the Operation section. Tie to ground if not used. REF (Pins 45, 46): Feedback Resistor for the Reference Inverting Amplifier, and Reference Input for the DAC. Normally tied to the output of the reference inverting amplifier. Typically –5V; accepts up to ±15V. These pins are internally shorted together. IOUT1 (Pin 40): DAC current output; normally tied to the negative input (summing junction) of the I/V converter amplifier. RCOM (Pin 47): Center Tap Point of RIN and REF. Normally tied to the negative input of the external reference inverting amplifier. RFB (Pins 41, 42): DAC Feedback Resistor. Normally tied to the output of the I/V converter amplifier. The DAC output current from IOUT1 flows through the feedback resistor to the RFB pins. These pins are internally shorted together. GEADJ (Pin 48): Gain Adjust Pin. This voltage-control pin can be used to null gain error or to compensate for reference errors. The gain error change expressed in LSB is the same for any output range. See System Offset and Gain Adjustments in the Operation section. Tie to ground if not used. ROFS (Pins 43, 44): Bipolar Offset Network. These pins provide the translation of the output voltage range for bipolar spans. Accepts up to ±15V; normally tied to the positive reference voltage. These pins are internally shorted together. BLOCK DIAGRAM 48 GEADJ 47 RCOM REF 45, 46 RFB 41, 42 ROFS 43, 44 2.56M RIN R1 20k VOSADJ R2 20k IOUT1 1, 2 36 35 34 33 20 21 18-BIT DAC WITH SPAN SELECT WR 3 UPD READ D/S CONTROL LOGIC DAC REGISTER 3 18 IOUT2F IOUT2S 39 40 6 5 DAC REGISTER 18 CLR M-SPAN INPUT REGISTER INPUT REGISTER I/O PORT I/O PORT 3 18 3, 37, 38 8-16, 23-31 SPAN I/O S2-S0 2757 BD DATA I/O D17-D0 2757f 9 LTC2757 TIMING DIAGRAMS Write, Update and Clear Timing t3 t1 t2 WR I/O INPUT VALID t5 t6 UPD t4 t7 t8 D/S VALID t25 CLR 2757 TD01 Readback Timing READ WR t14 t13 t23 t24 I/O INPUT t15 I/O OUTPUT VALID VALID t17 t20 t19 t22 UPD t18 D/S VALID 2757 TD02 2757f 10 LTC2757 OPERATION Output Ranges The LTC2757 is a current-output, parallel-input precision multiplying DAC offering ±1LSB INL and DNL over six software-selectable output ranges. Ranges can either be programmed in software for maximum flexibility or hardwired through pin-strapping. Two unipolar ranges are available (0V to 5V and 0V to 10V), and four bipolar ranges (±2.5V, ±5V, ±10V and –2.5V to 7.5V). These ranges are obtained when an external precision 5V reference is used. The output ranges for other reference voltages are easy to calculate by observing that each range is a multiple of the external reference voltage. The ranges can then be expressed: 0 to 1×, 0 to 2×, ±0.5×, ±1×, ±2×, and –0.5× to 1.5×. Digital Section The LTC2757 has four internal interface registers (see Block Diagram). Two of these—one Input and one DAC register—are dedicated to the Data I/O port, and two to the Span I/O port. Each port is thus double buffered. Double buffering provides the capability to simultaneously update the Span and Code registers, which allows smooth voltage transitions when changing output ranges. It also permits the simultaneous updating of multiple DACs or other parts on the data bus. Write and Update Operations Load the data input register directly from an 18-bit bus by holding the D/S pin low and then pulsing the WR pin low (Write operation). Load the Span Input register by holding the D/S pin high and then pulsing the WR pin low (Write operation). The Span and Data register structures are the same except for the number of parallel bits—the Span registers have three bits, while the Data registers have 18 bits. The DAC registers are loaded by pulsing the UPD pin high (Update operation), which copies the data held in the Input registers of both ports into the DAC registers. Note that Update operations always include both Data and Span registers; but the DAC register values will not change unless the Input register values have previously been changed by a Write operation. To make both registers transparent for flowthrough mode, tie WR low and UPD high. However, this defeats the deglitcher operation and output glitch impulse may increase. The deglitcher is activated on the rising edge of the UPD pin. The interface also allows the use of the Input and DAC registers in a master-slave, or edge-triggered, configuration. This mode of operation occurs when WR and UPD are tied together and driven by a single clock signal. The data bits are loaded into the Input register on the falling edge of the clock and then loaded into the DAC register on the rising edge. It is possible to control both ports on one 18-bit wide data bus by allowing Span pins S2 to S0 to share bus lines with the Data LSBs (D2 to D0). No Write or Read operation acts on both span and data, so there cannot be a signal conflict. The asynchronous clear pin (CLR) resets the LTC2757 to 0V (zero-, half- or quarter-scale code) in any output range. CLR resets both the Input and DAC data registers, but leaves the Span registers unchanged. The device also has a power-on reset that initializes the DAC to VOUT = 0V in any output range. The DAC powers up in the 0V to 5V range at zero-scale if the part is in SoftSpan configuration. For manual span (M-SPAN tied to VDD; see Manual Span Configuration), the DACs power-up in the manually-chosen range at the appropriate code. Manual Span Configuration Multiple output ranges are not needed in some applications. To configure the LTC2757 for single-span operation, tie the M-SPAN pin to VDD and the D/S pin to GND. The desired output range is programmed by tying S0, S1 and S2 to GND or VDD (see Figure 1 and Table 2). In this configuration, no range-setting software routine is needed; the part will initialize to the chosen output range at power-up, with VOUT = 0V. When configured for manual span operation, Span port readback is disabled. 2757f 11 LTC2757 OPERATION Readback The contents of any one of the four interface registers can be read back from the I/O ports by using the READ pin in conjunction with the D/S and UPD pins. The I/O pins and registers are grouped into two ports—Data and Span. The Data I/O port consists of pins D0-D17, and the Span I/O port consists of pins S0, S1 and S2. Each I/O port has one dedicated Input register and one dedicated DAC register. The register structure is shown in the Block Diagram. A Readback operation is initiated by asserting READ to logic high after selecting the desired I/O port. The most common readback task is to check the contents of an Input register after writing to it, and before updating the new data to the DAC register. To do this, hold UPD low and assert READ high. The contents of the selected port’s Input register are output to its I/O pins. To read back the contents of a DAC register, hold UPD low and assert READ high, then bring UPD high to select the DAC register. The contents of the selected DAC register are output by the selected port’s I/O pins. Note: if no update is desired after the readback operation, UPD must be returned low before bringing READ low, otherwise the UPD pin will revert to its primary function and update the DAC. Table 2. Span Codes Select the I/O port (Data or Span) to be read back with the D/S pin. The selected I/O port’s pins become logic outputs during readback, while the unselected I/O port’s pins remain high-impedance digital inputs. S2 S1 S0 SPAN 0 0 0 Unipolar 0V to 5V 0 0 1 Unipolar 0V to 10V 0 1 0 Bipolar –5V to 5V With the I/O port selected, assert READ high and select the desired Input or DAC register using the UPD pin. Note that UPD is a two function pin—the Update function is only available when READ is low. If READ is high, the Update function is disabled and the UPD pin instead functions as a register selector, selecting an Input or DAC register for readback. Table 1 shows the readback functions for the LTC2757. 0 1 1 Bipolar –10V to 10V 1 0 0 Bipolar –2.5V to 2.5V 1 0 1 Bipolar –2.5V to 7.5V Codes not shown are reserved and should not be used. VDD M-SPAN WR UPD LTC2757 S1 Table 1. Write, Update and Read Functions READ D/S VDD S2 S0 SPAN I/O DATA I/O 0 0 0 0 - Write to Input Register 0 0 0 1 - Write/Update (Transparent) 0 0 1 0 - - 0 0 1 1 Update DAC Register Update DAC Register 0 1 0 0 Write to Input Register - 0 1 0 1 Write/Update (Transparent) - 0 1 1 0 - - 0 1 1 1 Update DAC register Update DAC Register 1 0 X 0 - Read Input Register 1 0 X 1 - Read DAC Register 1 1 X 0 Read Input Register - 1 1 X 1 Read DAC Register - D/S WR UPD READ 18 2757 F01 DATA I/O Figure 1. Configuring the LTC2757 for Single-Span Operation (±10V Range) System Offset and Gain Adjustments Many systems require compensation for overall system offset. This may be an order of magnitude or more greater than the offset of the LTC2757, which is so low as to be dominated by external output amplifier errors even when using the most precise op amps. X = Don’t Care 2757f 12 LTC2757 OPERATION The offset adjust pin VOSADJ can be used to null unipolar offset or bipolar zero error. The offset change expressed in LSB is the same for any output range: –V(VOSADJ ) ΔVOS [LSB] = • 2048 V(RIN ) A 5V control voltage applied to VOSADJ produces ΔVOS = –2048 LSB in any output range, assuming a 5V reference voltage at RIN. In voltage terms, the offset delta is attenuated by a factor of 32, 64 or 128, depending on the output range. (These functions hold regardless of reference voltage.) ΔVOS = –(1/128)VOSADJ [0V to 5V, ±2.5V spans] ΔVOS = –(1/64)VOSADJ [0V to 10V, ±5V, –2.5V to 7.5V spans] ΔVOS = –(1/32)VOSADJ [±10V span] The gain error adjust pin GEADJ can be used to null gain error or to compensate for reference errors. The gain error change expressed in LSB is the same for any output range: V(GE ADJ ) ΔGE = • 2048 V(RIN ) The gain-error delta is non-inverting for positive reference voltages. Note that this pin compensates the gain by altering the inverted reference voltage V(REF). In voltage terms, the V(REF) delta is inverted and attenuated by a factor of 128. ΔV(REF) = –(1/128)GEADJ The nominal input range of these pins is ±5V; other voltages of up to ±15V may be used if needed. However, do not use voltages divided down from power supplies; reference-quality, low-noise inputs are required to maintain the best DAC performance. The VOSADJ pin has an input impedance of 1.28MΩ. This pin should be driven with a Thevenin-equivalent impedance of 10k or less to preserve the settling performance of the LTC2757. It should be shorted to GND if not used. The GEADJ pin has an input impedance of 2.56MΩ, and is intended for use with fixed reference voltages only. It should be shorted to GND if not used. OPERATION—EXAMPLES 1. Load ±5V range with the output at 0V. Note that since span and code are updated together, the output, if started at 0V, will stay there. The 18-bit DAC code is shown in hex for compactness. WR SPAN I/O INPUT 010 DATA I/O INPUT 20000H UPD UPDATE (±5V RANGE, VOUT = 0V) D/S READ = LOW VOUT 0V (00000H IN 0V to 5V RANGE) 0V (20000H IN ±5V RANGE) 2757 TD03 2757f 13 LTC2757 OPERATION—EXAMPLES 2. Load ±10V range with the output at 5V, changing to –5V. WR SPAN I/O INPUT 011 DATA I/O INPUT 30000H 10000H UPD UPDATE (5V) UPDATE (–5V) D/S READ = LOW +5V 0V VOUT –5V 2757 TD04 3. Write and update mid-scale code in 0V to 5V range (VOUT = 2.5V) using readback to check the contents of the input and DAC registers before updating. WR DATA I/O INPUT 20000H DATA I/O HI-Z OUTPUT HI-Z 20000H INPUT REGISTER UPD 00000H DAC REGISTER UPDATE (2.5V) D/S READ +2.5V VOUT 0V 2757 TD05 2757f 14 LTC2757 APPLICATIONS INFORMATION Op Amp Selection Table 3. Coefficients for the Equations of Table 4 Because of the extremely high accuracy of the 18-bit LTC2757, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Tables 3 and 4 contain equations for evaluating the effects of op amp parameters on the LTC2757’s accuracy. These are the changes the op amp can cause to the INL, DNL, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. OUTPUT RANGE A1 A2 A3 A4 A5 5V 1.1 2 1 10V 2.2 3 0.5 ±5V 2 2 1 1 1.5 ±10V 4 4 0.83 1 2.5 ±2.5V 1 1 1.4 1 1 –2.5V to 7.5V 1.9 3 0.7 0.5 1.5 1 1.5 Table 4. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1 Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp. OP AMP INL (LSB) DNL (LSB) VOS1 (mV) VOS1•12.1• ⎛ 5V ⎞ ⎜⎝ V ⎟⎠ REF IB1 (nA) IB1•0.0012• ⎛ 5V ⎞ ⎛ ⎞ I •0.00032• 5V ⎜⎝ V ⎟⎠ B1 ⎜⎝ V ⎟⎠ REF REF ⎛ 5V ⎞ VOS1 •3.1• ⎜ ⎝ VREF ⎟⎠ UNIPOLAR OFFSET (LSB) A3•VOS1 •52.4• IB1•0.524• BIPOLAR ZERO ERROR (LSB) ⎛ 5V ⎞ ⎛ ⎞ A3•VOS1 •78.6• 5V ⎜⎝ V ⎟⎠ ⎜⎝ V ⎟⎠ REF REF ⎛ 5V ⎞ ⎜⎝ V ⎟⎠ REF IB1•0.524• ⎛ 5V ⎞ ⎜⎝ V ⎟⎠ REF UNIPOLAR GAIN ERROR (LSB) VOS1 •52.4• ⎛ 5V ⎞ ⎜⎝ V ⎟⎠ REF VOS1 •52.4• ⎛ 5V ⎞ ⎜⎝ V ⎟⎠ REF IB1•0.0072• ⎛ 5V ⎞ ⎜⎝ V ⎟⎠ REF IB1•0.0072• ⎛ 5V ⎞ ⎜⎝ V ⎟⎠ REF AVOL1 (V/mV) ⎛ 66 ⎞ A1• ⎜ ⎟ ⎝ A VOL1 ⎠ ⎛ ⎞ A2• ⎜ 6 ⎟ ⎝ A VOL1 ⎠ 0 ⎛ ⎞ A5• ⎜ 524 ⎟ ⎝ A VOL1 ⎠ VOS2 (mV) 0 0 0 A4•VOS2•52.4• ⎛ 5V ⎞ ⎛ ⎞ V •104.8• 5V ⎜⎝ V ⎟⎠ OS2 ⎜⎝ V ⎟⎠ REF REF IB2 (nA) 0 0 0 A4•IB2 •0.524• ⎛ 5V ⎞ ⎜⎝ V ⎟⎠ REF AVOL2 (V/mV) 0 0 0 0 ⎛ 262 ⎞ A4• ⎜ ⎟ ⎝ A VOL2 ⎠ BIPOLAR GAIN ERROR (LSB) IB2 •1.048• ⎛ 5V ⎞ ⎜⎝ V ⎟⎠ REF ⎛ 524 ⎞ ⎜A ⎟ ⎝ VOL2 ⎠ ⎛ ⎞ A5• ⎜ 524 ⎟ ⎝ A VOL1 ⎠ VOS2 •104.8• IB2 •1.048• ⎛ 5V ⎞ ⎜⎝ V ⎟⎠ REF ⎛ 5V ⎞ ⎜⎝ V ⎟⎠ REF ⎛ 524 ⎞ ⎜A ⎟ ⎝ VOL2 ⎠ 2757f 15 LTC2757 APPLICATIONS INFORMATION Table 5. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2757 with Relevant Specifications AMPLIFIER SPECIFICATIONS AMPLIFIER VOS μV IB nA A VOL V/mV VOLTAGE NOISE nV/√Hz CURRENT NOISE pA/√Hz SLEW RATE V/μs GAIN BANDWIDTH PRODUCT MHz tSETTLING with LTC2757 μs POWER DISSIPATION mW LTC1150 10 0.05 5600 90 0.0018 3 2.5 10ms 24 LT1001 25 2 800 10 0.12 0.25 0.8 120 46 LT1012 25 0.1 2000 14 0.02 0.2 1 120 11.4 LT1097 50 0.35 2500 14 0.008 0.2 0.7 120 11 LT1468 75 10 5000 5 0.6 22 90 2.1 117 Table 5 contains a partial list of LTC precision op amps recommended for use with the LTC2757. The easy-to-use design equations simplify the selection of op amps to meet the system’s specified error budget. Select the amplifier from Table 5 and insert the specified op amp parameters in Table 4. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the part. Arithmetic summation gives an (unlikely) worst-case effect. A root-sum-square (RMS) summation produces a more realistic estimate. Op amp offset contributes mostly to DAC output offset and gain error, and has minimal effect on INL and DNL. For example, consider the LTC2757 in unipolar 5V output range. (Note that for this example, the LSB size is 19μV.) An op amp offset of 35μV will cause 1.8LSB of output offset, and 1.8LSB of gain error; but 0.4LSB of INL, and just 0.1LSB of DNL. While not directly addressed by the simple equations in Tables 3 and 4, temperature effects can be handled just as easily for unipolar and bipolar applications. First, consult an op amp’s data sheet to find the worst-case VOS and IB over temperature. Then, plug these numbers in the VOS and IB equations from Table 4 and calculate the temperature-induced effects. For applications where fast settling time is important, Application Note 120, 1ppm Settling Time Measurement for a Monolithic 18-Bit DAC, offers a thorough discussion of 18-bit DAC settling time and op amp selection. Recommendations To achieve the full specified static and dynamic performance of the LTC2757, the LT1468 amplifier is recommended; it offers a unique combination of fast settling and excellent DC precision. When using the LT1468 as an output amp, however, the offset voltage (75μV max) must be nulled to avoid degrading the linearity of the LTC2757. The LT1468 datasheet shows how to do this with a digital potentiometer. For DC or low-frequency applications, the LTC1150 is the simplest 18-bit accurate output amplifier. An auto-zero amp, its exceptionally low offset (10μV max) and offset drift (0.01μV/°C) make nulling unnecessary. Note: for swings above 8V, use an LT1010 buffer to boost the load current capability of the LTC1150. The settling of auto-zero amps is a special case; see Application Note 120, 1ppm Settling Time Measurement for a Monolithic 18-Bit DAC, Appendix E, for details. The LT1012 and LT1001 are good intermediate output-amp solutions that achieve moderate speed and good accuracy. They are also excellent choices for the reference inverting amplifier in fixed-reference applications. Figure 3 shows a composite output amplifier that achieves fast settling (8μs) and very low offset (3μV max) without offset nulling. This circuit offers high open-loop gain (1000V/mV min), low input bias current (0.15nA max), fast slew rate (25V/μs min), and a high gain-bandwidth product (30MHz typ). The high speed path consists of an LTC6240, which is an 18MHz ultra-low bias current amplifier, followed by an LT1360, a 50MHz fast-slewing amplifier which provides additional gain and the ability to 2757f 16 LTC2757 APPLICATIONS INFORMATION swing to ±10V at the output. Compensation is taken from the output of the LTC6240, allowing the use of a much larger compensation capacitor than if taken after the gain-of-five stage. An LTC2054 auto-zero amplifier senses the voltage at IOUT1 and drives the non-inverting input of the LTC6240 to eliminate the offset of the high speed path. The 100:1 attenuator and input filter reduce the low frequency noise in this stage while maintaining low DC offset. should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. Precision voltage references like the LT1236 produce low output noise in the 0.1Hz to 10Hz region, well below the 18-bit LSB level in 5V or 10V fullscale systems. However, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise. Precision Voltage Reference Considerations Table 6. Partial List of LTC Precision References Recommended for Use with the LTC2757 with Relevant Specifications Much in the same way selecting an operational amplifier for use with the LTC2757 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. The output voltage of the LTC2757 is directly affected by the voltage reference; thus, any voltage reference error will appear as a DAC output voltage error. There are three primary error sources to consider when selecting a precision voltage reference for 18-bit applications: output voltage initial tolerance, output voltage temperature coefficient and output voltage noise. Initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. Choosing a reference with low output voltage initial tolerance, like the LT1236 (±0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. A reference’s output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuit’s INL and DNL performance. If a reference is chosen with a loose output voltage temperature coefficient, then the DAC output voltage along its transfer characteristic will be very dependent on ambient conditions. Minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. As precision DAC applications move to 18-bit performance, reference output voltage noise may contribute a dominant share of the system’s noise floor. This in turn can degrade system dynamic range and signal-to-noise ratio. Care REFERENCE INITIAL TOLERANCE TEMPERATURE DRIFT 0.1Hz to 10Hz NOISE LT1019A-5, LT1019A-10 ±0.05% Max 5ppm/°C Max 12μVP-P LT1236A-5, LT1236A-10 ±0.05% Max 5ppm/°C Max 3μVP-P LT1460A-5, LT1460A-10 ±0.075% Max 10ppm/°C Max 20μVP-P LT1790A-2.5 ±0.05% Max 10ppm/°C Max 12μVP-P LTC6655-2.5 LTC6655-5 ±0.025% Max 2ppm/°C Max 0.62μVP-P Grounding As with any high-resolution converter, clean grounding is important. A low-impedance analog ground plane is necessary, as are star grounding techniques. Keep the board layer used for star ground continuous to minimize ground resistances; that is, use the star-ground concept without using separate star traces. The IOUT2 pins are of particular concern; INL will be degraded by the code-dependent currents carried by the IOUT2F and IOUT2S pins if voltage drops to ground are allowed to develop. The best strategy here is to tie the pins to the star ground plane by multiple vias located directly underneath the part. Alternatively, the pins may be routed to the star ground point if necessary; join them together at the part and route a single trace of no more than 30 squares of 1oz copper. In the rare case in which neither of these alternatives is practicable, a force/sense amplifier should be used as a ground buffer (see the Typical Applications section). Note, however, that the voltage offset of the ground buffer amp directly contributes to the effects on accuracy specified in Table 4 under ‘VOS1’. The combined effects of the offsets can be calculated by substituting the total offset from IOUT1 to IOUT2S for VOS1 in the equations. 2757f 17 LTC2757 TYPICAL APPLICATIONS ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE 5 – 6 IOUT2F 6 1 5 IOUT2S 1000pF LT1468 3 + ZETEX BAT54S 2 200Ω 200Ω 6 IOUT2F 3 6 5 6 GEADJ 1, 2 RIN 48 3 LT1012 1 REF 5V 2 + 2 – IOUT2S ZETEX* BAT54S + U2 LT1012 2 7 C2 150pF – 47 RCOM 3 *SCHOTTKY BARRIER DIODE 45, 46 43, 44 REF ROFS 41, 42 RFB C1 27pF R2 R1 15V 0.1μF 8 WR UPD READ D/S CLR 36 35 34 33 20 21 WR UPD LTC2757 2 – IOUT2 5, 6 3 + 18-BIT DAC WITH SPAN SELECT READ D/S CLR IOUT1 40 GND 3 16 M-SPAN VOSADJ 3, 37, 38 SPAN I/O S2-S0 8-16, 23-31 DATA I/O D17-D0 39 VOSADJ VDD 2757 F02 U1 LT1468 VOUT 0.1μF 4, 7 17 1 5V C3 0.1μF 4 –15V FOR MULTIPLYING APPLICATIONS, U2 = LT1468 AND C2 = 15pF Figure 2. Basic Connections for SoftSpan VOUT DAC with Two Optional Circuits for Driving IOUT2 from GND with a Force/Sense Amplifier 2757f 18 LTC2757 PACKAGE DESCRIPTION LX Package 48-Lead Plastic LQFP (7mm × 7mm) (Reference LTC DWG # 05-08-1760 Rev Ø) 7.15 – 7.25 9.00 BSC 5.50 REF 7.00 BSC 48 0.50 BSC 1 2 48 SEE NOTE: 4 1 2 9.00 BSC 5.50 REF 7.00 BSC 7.15 – 7.25 0.20 – 0.30 A A PACKAGE OUTLINE C0.30 – 0.50 1.30 MIN RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 1.60 1.35 – 1.45 MAX 11° – 13° R0.08 – 0.20 GAUGE PLANE 0.25 0° – 7° 11° – 13° 0.09 – 0.20 1.00 REF 0.50 BSC 0.17 – 0.27 0.05 – 0.15 LX48 LQFP 0907 REVØ 0.45 – 0.75 SECTION A – A NOTE: 1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE 2. DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT 4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER 5. DRAWING IS NOT TO SCALE 2757f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2757 TYPICAL APPLICATION 12V IN LTC6655-5 OUT 0.1μF 10μF 15V + VOUT LT1012 – 1k –15V 10k – 5V – 1k LTC2054 1μF TO MICROCONTROLLER RIN RCOM REF D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S2 S1 S0 REF ROFS ROFS RFB RFB 15V + LTC6240 + + VDD GEADJ RIN 100pF 5V 10k 100pF LTC1360 – –5V –5V –15V 10Ω 1μF 5pF 4.02k IOUT1 1k IOUT2F LTC2757 IOUT2S GND VOSADJ D/S READ UPD WR CLR M-SPAN GND GND GND 2757 F03 Figure 3. Composite Amplifier Provides 18-Bit Precision and Fast Settling RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1591/ LTC1597 Parallel 14-/16-Bit IOUT Single DAC Integrated 4-Quadrant Resistors LTC1592 Serial 16-Bit IOUT Single DAC Software-Selectable (SoftSpan) Ranges, ±1LSB INL, DNL, 16-Lead SSOP Package LTC1821 Parallel 16-Bit VOUT Single DAC ±1LSB INL, DNL, 0V to 10V, 0V to –10V, ±10V Output Ranges LTC2641/ LTC2642 Serial 12-/14-/16-Bit Unbuffered VOUT Single DACs ±1LSB INL, ±1LSB DNL, 1μs Settling, Tiny MSOP-10, 3mm × 3mm DFN-10 Packages LTC2704 Serial 12-/14-/16-Bit VOUT SoftSpan Quad DACs Software-Selectable Ranges, Integrated Amplifiers LTC2751 Parallel 12-/14-/16-Bit IOUT SoftSpan Single DAC ±1LSB INL, DNL, Software-Selectable Ranges, 5mm × 7mm QFN-38 Package LTC2753 Parallel 12-/14-/16-Bit IOUT SoftSpan Dual DACs ±1LSB INL, DNL, Software-Selectable Ranges, 7mm × 7mm QFN-48 Package LTC2754 Serial 12-/16-Bit IOUT SoftSpan Quad DACs ±1LSB INL, DNL, Software-Selectable Ranges, 7mm × 8mm QFN-52 Package LTC2755 Parallel 12-/14-/16-Bit IOUT SoftSpan Quad DACs ±1LSB INL, DNL, Software-Selectable Ranges, 9mm × 9mm QFN-64 Package LT1027 Precision Reference 1ppm/°C Maximum Drift LT1236A-5 Precision Reference 0.05% Maximum Tolerance, 1ppm 0.1Hz to 10Hz Noise LTC1150 ±15V Zero-Drift Op Amp 10μV Maximum Offset Voltage, 1.8μVP-P (0.1Hz to 10Hz) Noise, 0.8mA Supply Current LT1468 16-Bit Accurate Op Amp 90MHz GBW, 22V/μs Slew Rate 2757f 20 Linear Technology Corporation LT 0410 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010