ON NCP3102MNTXG Wide input voltage synchronous buck converter Datasheet

NCP3102
Wide Input Voltage
Synchronous Buck Converter
The NCP3102 is a high efficiency, 10 A DC-DC buck converter
designed to operate from a 5 V to 13.2 V supply. The device is capable
of producing an output voltage as low as 0.8 V. The NCP3102 can
continuously output 10 A through MOSFET switches driven by an
internally set 275 kHz oscillator. The 40-pin device provides an
optimal level of integration to reduce size and cost of the power
supply. The NCP3102 also incorporates an externally compensated
transconductance error amplifier and a capacitor programmable
soft-start function. Protection features include programmable short
circuit protection and under voltage lockout (UVLO). The NCP3102
is available in a 40-pin QFN package.
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MARKING
DIAGRAM
QFN40
CASE 485AK
1 40
A
WL
YY
WW
G
Features
•Input Voltage Range from 4.5 V to 13.2 V
•275 kHz Internal Oscillator
•Greater than 90% Maximum Efficiency
•Boost Pin Operates to 25 V
•Voltage Mode PWM Control
•0.8 V $1% Internal Reference Voltage
•Adjustable Output Voltage by Resistor Divider
•Capacitor Programmable Soft-Start
•80% Maximum Duty Cycle
•Input Undervoltage Lockout
•Resistor Programmable Current Limit
•This is a Pb-Free Device
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
NCP3102
AWLYYWWG
PIN CONNECTIONS
Applications
•Servers/Networking
•DSP and FPGA Power Supply
•DC-DC Regulator Modules
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
100
Vin
95
Vout
90
VCC
BST
EFFICIENCY (%)
PWRVCC CPHS
PWRPHS
NCP3102
COMP/DIS
FB
AGND
TGOUT
TGIN
BG PWRGND
VIN = 5.0 V
85
VIN = 12 V
80
75
70
65
60
55
GND
GND
50
0
Figure 1. Typical Application Diagram
© Semiconductor Components Industries, LLC, 2007
November, 2007 - Rev. 2
1
2
3
4
5
6
7
OUTPUT CURRENT (A)
8
9
10
Figure 2. Efficiency
1
Publication Order Number:
NCP3102/D
NCP3102
VCC
13
BST
24
+
FB
PWRVCC
26-37
R
PWM
OUT
+
Vref
TGIN
25
FAULT
POR
UVLO
16
TGOUT
21
Q
0.8V
PWRPHS
1-4
36-40
+
-
S
CLOCK
2V
CPHS
COMP
DIS
22
RAMP
VCC
17
OSC
+
FAULT
OSC
LATCH
VOCTH
SET
0.4V
50mV-550mV
VOCTH
+
2V
+
10mA
CPHS
14,15,19,20,23
AGND
35
BG
5-12
PWRGND
Figure 3. Detailed Block Diagram
PIN FUNCTION DESCRIPTION
Pin No
Symbol
1-4 , 36-40
PWRPHS
Power phase node. Drain of the low side power MOSFET and source of the high side
MOSFET.
5-12
PWRGND
Power ground. Source of the low side power MOSFET. Connected with large copper
area. High current return for the low side MOSFET.
13
VCC
14,15,19,20,23
AGND
16
FB
17
COMP/DIS
18
NC
21
TGOUT
22
CPHS
24
BST
Supply rail for the floating top gate driver.
Gate high side MOSFET
25
TGIN
26-34
PWRVCC
35
BG
Description
Supply for the internal driver. Decouple with a 0.1 mF - 1 mF capacitor to AGND as close
to the IC as possible.
Internal driver ground. Reference ground for FB, COMP and other driver circuits.
The input pin to the error amplifier.(inverted input error amplifier) Connect this pin to the
output resistor divider (if used) or directly to the output voltage near the load connection.
Compensation or disable pin. (output error amplifier) Use this pin to compensate the
voltage control feedback loop. The compensation capacitor also acts as a soft-start
capacitor. Pulling the pin below 400 mV will disable the controller.
No connect. This pin can be connected to AGND or not connected.
Output high side MOSFET driver.
The controller phase sensing.
Input supply pins for the high side MOSFET. (Drain)
The current limit set pin.
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NCP3102
ABSOLUTE MAXIMUM RATINGS
Pin Name
Symbol
VMAX
VMIN
VCC
15 V
-0.3 V
PWRVCC
30V
-0.3 V
BST
30 V wrt/GND
15 V wrt/PHASE
-0.3 V
PWRPHS
25 V
-0.7 V
-5 V for < 50 nsec
CPHS
25 V
-0.7 V
-5 V for < 50 nsec
Current Limit Set
BG
15V
-0.3V
-2.0 V for < 200 nsec
Feedback
FB
5.5 V
-0.3 V
COMP/DIS
5.5 V
-0.3 V
Control Circuitry Input Voltage
Main Supply Voltage Input
Bootstrap Supply Voltage Input
Phase Node
Phase Node (Bootstrap Supply Return)
COMP/DISABLE
MAXIMUM RATINGS
Pin Name
Symbol
Value
Unit
RqJA
35
°C/W
Operating Junction Temperature Range
TJ
-40 to 150
°C
Storage Ambient Temperature
Tstg
-55 to 150
°C
Thermal Characteristics
6X6 QFN Plastic Package
Maximum Power Dissipation @ TA = 25°C
PD
3000
mW
260 peak
°C
3
-
Thermal Resistance Junction-to-Ambient (Note 2)
Lead Temperature Soldering (10 sec): Reflow (SMD
Styles Only) Pb_Free (Note 1)
Moisture Sensitivity Level
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: These devices have limited built-in ESD protection. The devices should be shorted together or the device placed in conductive
foam during storage or handling to prevent electrostatic damage to the device.
1. 60-180 seconds minimum above 237°C
2. Based on 110*100 mm double layer PCB with 35 mm thick copper plating.
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NCP3102
ELECTRICAL CHARACTERISTICS (0°C < TJ < 70°C for NCP3102, -40°C < TJ < 125°C for NCP3102B, 4.5 V < VCC < 13.2 V,
BST = VCC * 2)
Conditions
Min
Input Voltage Range
-
Boost Voltage Range
-
Characteristic
Typ
Max
Unit
4.5
13.2
V
4.5
26.5
V
3.5
mA
Quiescent Supply Current
VFB = 1.0 V , No Switching, VCC = 13.2 V
Quiescent Supply Current
VFB = 1.0 V , No Switching, VCC = 5 V
1.8
VCC Supply Current
VFB = 0.5 V , Switching, VCC = 13.2 V
10.3
25
mA
VCC Supply Current
VFB = 0.5 V , Switching, VCC = 5 V
5.6
12.5
mA
VFB = 1.0 V , No Switching, VBST = 25 V
600
mA
4
V
0.4
V
Boost Quiescent Current
UVLO threshold
VCC Rising Edge
2.3
3.6
UVLO hysteresis
mA
VFB Feedback Voltage
TJ = 0°C to 70°C
0.792
0.8
0.808
V
VFB Feedback Voltage
TJ = -40°C to 125°C
0.788
0.8
0.812
V
Oscillator Frequency
TJ = 0°C to 70°C
250
275
300
kHz
Oscillator Frequency
TJ = -40°C to 125°C
233
275
317
kHz
Minimum Duty Cycle
4
Maximum Duty Cycle
70
Blanking Time
75
%
80
%
5
mS
50
Transconductance
ns
2
3
Guaranteed by Design
55
70
dB
Output Source Current
VFB - 100 mV
80
120
mA
Output Sink Current
VFB + 100 mV
80
120
mA
Open Loop DC Gain
Input Bias Current
Unity Gain Bandwidth
Soft-Start Source Current
Transient Response*
0.1
Guaranteed by Design
VFB = 0.8 V
1
4
7
10
mA
MHz
17
mA
Undershot VOUT
Recovery Time
71
180
mV
ms
RBG = 5 kW
50
mV
OVERCURRENT PROTECTION
OC Threshold
Fixed OC Threshold
OCSET Current Source
Sourced from BG Pin before Soft-Start
OC Switch-Over Threshold
-375
-
mV
10
mA
700
mV
OUTPUT POWER MOSFETS
RDS(on) Low-Side
V = 12.0 V ID = 10 A
8
mW
RDS(on) High-Side
V = 12.0 V ID = 10 A
8
mW
*Transient response with 2.5 A/ms load step 50% - 100% defined at output parts: COUT= 2x100 uF MLCC + 1 mF OS-CON.
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NCP3102
282
11
281
10
ICC, SUPPLY CURRENT
SWITCHING (mA)
FSW, FREQUENCY (kHz)
TYPICAL OPERATING CHARACTERISTICS
280
Vin = 4.5 V
279
Vin = 12 V
278
277
276
8
7
6
Vin = 4.5 V
4
274
-25
0
25
50
75
100
125
-25
0
25
50
75
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. Oscillator Frequency (FSW) vs.
Temperature
Figure 5. ICC vs. Temperature
801.5
4.1
801
4
800.5
UVLO RISING/FALLING (V)
Vref, REFERENCE VOLTAGE (mV)
9
5
276
Vin = 12 V
800
Vin = 4.5 V
799.5
799
798.5
798
100
125
100
125
RISING
3.9
3.8
3.7
FALLING
3.6
3.5
797.5
-25
0
25
50
75
100
-25
125
0
25
50
75
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Reference Voltage (Vref) vs. Temperature
Figure 7. UVLO vs. Temperature
16
10
15
9.5
LOW-SIDE RDS(on) (mW)
SOFT-START SOURCING CURRENT (mA)
Vin = 12 V
14
13
12
11
10
9
8.5
8
7.5
7
-25
0
25
50
75
100
-25
125
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 8. Soft-Start Sourcing Current vs.
Temperature
Figure 9. I-Limit vs. Temperature
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125
NCP3102
DETAILED OPERATING DESCRIPTION
General
NCP3102 is a high efficiency integrated wide input
voltage 10 A synchronous PWM buck converter designed to
operate from a 5 V to 13.2 V supply. The output voltage of
the converter can be precisely regulated down to 800 mV
$1.0% when the VFB pin is tied to VOUT. The switching
frequency is internally set to 275 kHz. A high gain
Operational Transconductance Error Amplifier (OTA) is
used for feedback and stabilizing the loop.
OUTPUT VOLTAGE (V)
10
Duty Cycle and Maximum Pulse Width Limits
8
7
DMAX = 0.8
6
DMAX = 0.7
5
4
In steady state DC operation, the duty cycle will stabilize
at an operating point defined by the ratio of the input to the
output voltage. The NCP3102 can achieve an 80% duty
cycle. There is a built in off-time which ensures that the
bootstrap supply is charged every cycle. The NCP3102,
which is capable of a 100 nsec pulse width (minimum), can
allow a 12 V to 0.8 V conversion at 275 kHz. The duty cycle
limit and the corresponding output voltage are shown below
in graphical format in Figure 10 and 12. The light gray area
represents the safe operating area for the lowest maximum
operational duty cycle and the dark grey area represents the
absolute maximum duty cycle and corresponding output
voltage.
0.8
9
3
4.5
5.5
6.5
7.5 8.5 9.5 10.5 11.5 12.5 13.5
INPUT VOLTAGE (V)
Figure 11. Maximum Input to Output Voltage
External Enable/Disable
When the Comp Pin voltage falls or is pulled externally
below the 400 mV threshold as shown in Figure 12, it
disables the PWM Logic and the gate drive outputs. In this
disabled mode, the operational transconductance
amplifier's (EOTA) output source current is reduced and
limited to the Soft-Start mode of 10 mA. Always start
normal operation condition after disable mode begins by
soft-start sequence. This is mentioned in the next section.
Max-Maximum
0.7
Min-Maximum
DUTY CYCLE
0.6
FB 16
4.5 V
0.5
+
VREF
0.8 V
0.4
COMP/DIS
13.2 V
0.3
17
0.2
0.1
Minimum
0
0.8
2.8
4.8
6.8
OUTPUT VOLTAGE (V)
8.8
10.8
Figure 12. Disable Circuit
Figure 10. Duty Cycle to Output Voltage
Normal Shutdown Behavior
Normal shutdown occurs when the IC stops switching
because the input supply reaches UVLO threshold. In this
case, switching stops, the internal soft-start, SS, is
discharged, and all GATE pins go low. The switch node
enters a high impedance state and the output capacitors
Input Voltage Range (VCC and BST)
The input voltage range for both VCC and BST is 4.5 V to
13.2 V with reference to GND and PHS, respectively.
Although BST is rated at 13.2 V with reference to PHS, it can
also tolerate 25 V with respect to GND.
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NCP3102
condition has been removed. The minimum turn-on time of
the LS-FET is set to 500 ns. The trip thresholds have a
-95 mV, +45 mV process and temperature variation when
set to -375 mV. The operation of key nodes is displayed in
Figure 14 for both normal operation and during over current
conditions.
discharge through the load with no ringing on the output
voltage.
External Soft-Start
The NCP3102 features an external soft-start function,
which reduces inrush current and overshoot of the output
voltage. Soft-Start is achieved by using the internal current
source of charges the external integrator capacitor of the
transconductance amplifier. Figure 13 is a typical soft-start
sequence. This sequence begins once VCC surpasses its
UVLO threshold. During soft-start, as the Comp Pin rises
through 400 mV, the PWM Logic and gate drives are
enabled. When the feedback voltage crosses 800 mV, the
EOTA will be given control to switch to its higher regulation
mode output current of 120 mA. In the event of an over
current during the soft-start, the overcurrent logic will
override the soft-start sequence and will shut down the
PWM logic and both the high side and low side gates of the
switching MOSFETS. If the voltage on the Comp Pin
reaches the value of 1.1 V, the device will start switching
MOSFETs. The voltage on the Comp Pin is proportional to
Duty Cycle in case of the device working in regulated mode.
LS Gate Drive
BO Comparator
2V
HS Gate Drive
Switch Node Comparator
2V
Switch Node
SCP Trip Voltage
C Phase
SCP Comparated Latch Output
1.1 V
0.4 V
Figure 14. Switching and Current Limit Timing
Overcurrent Protection Setting
0.4 V
NCP3102 allows the setting of Overcurrent Threshold
ranging from 50 mV to 550 mV, simply by adding a resistor
(ROCSET) between BG and GND. During a short period of
time following VCC rising over UVLO threshold, an internal
10 mA current (IOCSET) is sourced from BG Pin,
determining a voltage drop across ROCSET. This voltage
drop will be sampled and internally held by the device as
Overcurrent Threshold. The OC setting procedure overall
time length is approximately 6 ms. When a ROCSET
resistor is connected between BG and GND, the
programmed threshold is set with an RSET values range
from 5 kW to 55 kW.
Vcomp
Enable
Vfb
SS
120 mA
10 mA
10 mA
Isource/
Sink
-10 mA
Startup
Normal
Figure 13. Soft-Start Implementation
IOCth +
UVLO
Undervoltage Lockout (UVLO) is provided to ensure that
unexpected behavior does not occur when VCC is too low to
support the internal rails and power the converter. For the
NCP3102, the UVLO is set to ensure that the IC will startup
when VCC reaches 4.0 V and shutdown when VCC drops
below 3.6 V. This permits smooth operation from a varying
5.0 V input source.
IOCSET * ROCSET
R DS(on)
(eq. 1)
In case ROCSET is not connected, the device switches the
OCP threshold to a fixed 375 mV value: an internal safety
clamp on BG is triggered as soon as BG voltage reaches
700 mV, enabling the 375 mV fixed threshold and ending
OC setting phase. In case of the OCP activation, it is
necessary to turn off input supply and start new soft-start
sequence. Even though the DISABLE function initiates
soft-start sequencing, it is impossible to reset the activated
OCP by using this DISABLE function.
Current Limit Protection
In case of a short circuit or overload, the low side LS-FET
will conduct large currents. The controller will shut down
the regulator in this situation for protection against
overcurrent. The low side RDS(on) sense is implemented by
comparing the voltage at the phase node when BG starts
going low to an internally generated fixed voltage. If the
phase voltage is lower than OC trip voltage, an overcurrent
condition occurs and a counter is initiated. When the counter
completes, the PWM logic and both HS-FET and LS-FET
are turned off. The converter will reinitialize through the
soft-start cycle to determine if the short circuit or overload
Drivers
The NCP3102 drives the internal High and Low side
Switching MOSFETS with 1 A gate drivers. The gate
drivers also include adaptive nonoverlap circuitry. The
nonoverlap circuitry increase efficiency, which minimizes
power dissipation, by minimizing the body diode
conduction time.
A detailed block diagram of the nonoverlap and gate drive
circuitry used in the chip is shown in Figure 15.
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NCP3102
where Iinrush is the input current during startup, COUT is the
total output capacitance, VOUT is the desired output voltage,
and tSS is the soft-start interval.
If the inrush current is higher than the steady state input
current during maximum load, then the input fuse should be
rated accordingly, if one is used.
BST
UVLO
FAULT
TG
+
-
PHASE
2V
Calculating Soft-Start Time
+
-
To calculate the soft-start time, the following equation
can be used.
2V
VCC
t SS +
BG
PWM
OUT
UVLO
FAULT
Figure 15. Block Diagram
Careful selection and layout of external components is
required, to realize the full benefit of the onboard drivers.
The capacitors between VCC and GND and between BST
and PHASE must be placed as close as possible to the
device. A ground plane should be placed on the closest layer
for return currents to GND in order to reduce loop area and
inductance in the gate drive circuit.
DV
1.1 V
Vcomp
Vout
APPLICATION SECTION
Figure 16. Soft-Start
Input Capacitor Selection
The input capacitor has to sustain the ripple current
produced during the on time of the upper MOSFET, so it
must have a low ESR to minimize the losses. The RMS value
of this ripple is:
(1 * D )
The above calculation includes the delay from comp
rising to when output voltage becomes valid.
To calculate the time of output voltage rising to when it
reaches regulation; DV is the difference between the comp
voltage reaching regulation and 1.1 V.
(eq. 2)
Output Capacitor Selection
Where D is the duty cycle, IinRMS is the input RMS current,
and IOUT is the load current. The equation reaches its
maximum value with D = 0.5. Losses in the input capacitors
can be calculated with the following equation:
P CIN + ESR CIN
Iin RMS 2
Selection of the right value of input and output capacitors
determines the behavior of the buck converter. In most high
power density applications the capacitor size is most
important. Ceramic capacitor is necessary to reduce the high
frequency ripple voltage at the input of converter. This
capacitor should be located near the device as possible.
Added electrolytic capacitor improved response of relative
slow load change.
The required output capacitor will be determined by
planned transient deviation requirements. Usually a
combination of two types of capacitors is recommended to
meet the requirements. First, a ceramic output capacitor is
needed for bypassing high frequency noise. Second, an
electrolytic output capacitor is needed to achieve good
transient response.
In fact, during load transient, for the first few
microseconds the bulk capacitance supplies current to the
load. The controller immediately recognizes the load
(eq. 3)
Where PCIN is the power loss in the input capacitors and
ESRCIN is the effective series resistance of the input
capacitance. Due to large di/dt through the input capacitors,
electrolytic or ceramics should be used. If a tantalum
capacitor has to be used, surge protection is needed.
Otherwise, capacitor failure could occur.
Calculating Input Startup current
To calculate the input startup current, the following
equation can be used:
I inrush +
C OUT
V OUT
t SS
(eq. 5)
I SS
Where CC is the compensation as well as the soft-start
capacitor.
CP is the additional capacitor that forms the second pole.
ISS is the soft-start current
DV is the comp voltage from zero to until it reaches
regulation.
GND
Iin RMS + I OUT ǸD
ǒC p ) C cǓ * DV
(eq. 4)
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NCP3102
transient and sets the duty cycle to maximum, but the current
slope is limited by the inductor value.
During a load step transient the output voltage initially
drops due to the current variation inside the capacitor and the
ESR. (neglecting the effect of the effective series inductance
(ESL)):
DV OUT-ESR + DI out
ESR COUT
A minimum capacitor value is required to sustain the
current during the load transient without discharging it. The
voltage drop due to the output capacitor discharge is given
by the following equation:
DV OUT-DISCHARGE +
(eq. 6)
Recovery Time (ms)
100
226
504
150
182
424
220
170
264
270
149
233
560
112
180
680
100
180
820
96
180
1000
71
180
2x680
60
284
2x820
48
224
C OUT
ǒV IN
(eq. 7)
D * V OUTǓ
Inductor Selection
Both mechanical and electrical considerations influence
the selection of an output inductor. From a mechanical
perspective, smaller inductor values generally correspond to
smaller physical size. Since the inductor is often one of the
largest components in the regulation system, a minimum
inductor
value
is
particularly
important
in
space-constrained applications. From an electrical
perspective, the maximum current slew rate through the
output inductor for a buck regulator is given by:
SlewRate LOUT +
Table 1. TRANSIENT RESPONSE VERSUS OUTPUT
CAPACITANCE (50% to 100% Load Step)
Drop (mV)
2
L OUT
Where VOUT-DISCHARGE is the voltage deviation of VOUT
due to the effects of discharge, LOUT is the output inductor
value and VIN is the input voltage.
Where VOUT-ESR is the voltage deviation of VOUT due to
the effects of ESR and the ESRCOUT is the total effective
series resistance of the output capacitors.
Table 1. shows values of voltage drop and recovery time
of the NCP3102 demo board with the configuration shown
in Figure 20. The transient response was measured for the
load current step from 5 A to 10 A (50% to 100% load).
Input capacitors are 2x47 mF ceramic and 2x270 mF
OS-CON, output capacitors are 2x100 mF ceramic and
OS-CON as mentioned in Table 1. Typical transient
response waveforms are shown in Figure 17.
More information about OS-CON capacitors is available
at http://www.edc.sanyo.com.
COUT (mF) OS-CON
DI OUT 2
V IN * V OUT
L OUT
(eq. 8)
This equation implies that larger inductor values limit the
regulator's ability to slew current through the output
inductor in response to output load transients. Consequently,
output capacitors must supply the load current until the
inductor current reaches the output load current level. This
results in larger values of output capacitance to maintain
tight output voltage regulation. In contrast, smaller values of
inductance increase the regulator's maximum achievable
slew rate and decrease the necessary capacitance, at the
expense of higher ripple current. The peak-to-peak ripple
current is given by the following equation:
Ipk-pk LOUT +
V OUT(1 * D)
L OUT
(eq. 9)
275kHz
Where Ipk-pkLOUT is the peak to peak current of the output.
From this equation it is clear that the ripple current increases
as LOUT decreases, emphasizing the trade-off between
dynamic response and ripple current. In order to achieve
high efficiency, coils with a low value of Direct Current
Resistance (DCR) have to be used. For example: Coilcraft
MLC1555-302ML and SER2013-362ML).
Feedback and Compensation
The output voltage is adjustable from 0.8 V to 5 V as
shown in Table 2. The adjustment method requires an
external resistor divider with its center tap tied to the FB pin.
It is recommended to have a resistance between 1.5 kW and
5 kW. The selection of low value resistors reduces
efficiency, alternatively high value resistance of R2 causes
decrease in output voltage accuracy due to the bias current
in the error amplifier. The output voltage error of this bias
current can be estimated by using the following equation:
Figure 17. Typical Waveform of Transient Response
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NCP3102
Error(%) +
R2 * I bias
V REF
* 100
the compensation network around the OTA, the output
capacitor, output inductor and the output divider. Figure 19
shows the open loop and closed loop gain plots. It is possible
to use Compensation Calculator Software Tool from
ON Semiconductor website. This tool can be downloaded
from http://www.onsemi.com.
(eq. 10)
Error = R2 * 1.25 * 10-5 (%)
Once R2 is calculated above R3 can be calculated to select
the desired output voltage as shown in the following
equation:
R3 +
V REF
* R2
V OUT * V REF
(eq. 11)
Open Loop, Unloaded Gain
Vout
GAIN (dB)
Table 2 shows R3 values for frequently used output
voltages.
VCC
13
A
FZ
POR
UVLO
R2
Closed Loop,
Unloaded Gain
FP
Gain = GMR1
FB
B
Error Amplifier
Compensation Network
16
+
100
R3
VREF
0.8V
10 k
100 k
FREQUENCY (Hz)
1000 k
Figure 19. Gain Plot for the Error Amplifier
Thermal Considerations
COMP
DIS
The package thermal resistance can be obtained from the
specifications section of this data sheet and a calculation can
be made to determine the NCP3102 junction temperature.
However, it should be noted that the physical layout of the
board, the proximity of other heat sources such as MOSFETs
and inductors, and the amount of metal connected to the
NCP3102, impact the temperature of the device. The PCB
is used also as the heatsink. Double or multi layer PCBs with
thermal vias between places with the same electrical
potential increase cooling area. A 70 mm thick copper
plating is a good solution to eliminate the need for an
external heatsink.
17
CSOFT-START
1000
+
Rcomp
FAULT
Ccomp
Figure 18. FB circuit
Table 2. OUTPUT VOLTAGES AND DIVIDER
RESISTORS
R2 (kW)
R3 (kW) E24
0.8
1.8
None
None
Layout Considerations
1.0
0.51
2.0
2.040
1.2
0.75
1.5
1.500
1.5
1.3
1.5
1.486
1.8
1.6
1.3
1.280
2.5
1.6
0.75
0.753
3.3
1.6
0.51
0.512
5.0
2.7
0.51
0.514
When designing a high frequency switching converter,
layout is very important. Using a good layout can solve
many problems associated with these types of power
supplies as transient occur.
External compensation components (R1, C9) are needed
for converter stability. They should be placed close to the
NCP3102. The feedback trace is recommended to be kept as
far from the inductor and noisy power traces as possible. The
resistor divider and feedback acceleration circuit (R2, R3,
R6, C13) is recommended to be placed near to input FB
(Pin 16, NCP3102).
Switching current from one power device to another can
generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located together as close as possible using ground
plane construction or single point grounding. The inductor
and output capacitors should be located together as close as
possible to the NCP3102.
VOUT (V)
R3 (kW) Calculated
Figure 18 shows a typical Type II operational
transconductance error amplifier (OTA). The compensation
network consists of the internal error amplifier and the
impedance networks ZIN (R3) and external ZFB (Rcomp,
Ccomp and Csoft-start). The compensation network has to
provide a closed loop transfer function with the highest 0 dB
crossing frequency to have fast response (but always lower
than fSW/8) and the highest gain in DC conditions to
minimize the load regulation. A stable control loop has a
gain crossing with -20 dB/decade slope and a phase margin
greater than 45°. Include worst-case component variations
when determining phase margin. Loop stability is defined by
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10
11
+
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NCP3102
PWRPHS
PWRVCC
NC
AGND
FB
AGND
PWRGND
PWRGND
PWRGND
VCC
TGOUT
AGND
CPHS
AGND
BST
TGIN
Figure 20. Schematic Diagram of NCP3102 Evaluation Board
120
C10
R1
732
33n
C9
11 12 13 14 15 16 17 18 19 20
COMP
220n
C11
10
9
8
PWRPHS
7
6
5
4
3
2
1
BG
2R2
47m
OCPSET
RSN
40 39 38 37 36 35 34 33 32 31
R6
PWRVCC
IN
IN
47m
270m
C2
D3
21
22
23
24
25
26
27
28
29
30
OR
R7
10R
L1
CSN
C12
3R3
2n2
220n
RBOOST
BAT54T1
CBOOST
D1
470
3.3mH
PHASE
R3
510
1.6k
R2
1
3
2
22n
C13
R8
200
R4
20R
Q3
1m
C8 + C16
100m 100m
C5
RLO2
RLO4
Q2
CLO3
RLO9
CLO2
RLO8
CLO1
RLO7
3
2
1
3
2
1
3
2
1
+
RLO10
R5
C4
+ C15
D2
2xMBRS140T3
RLO1
RLO3
RLO5
RLO6
Q1
OUT
OUT
X1
3
2
1
NCP3102
NCP3102
Schematic diagram of the NCP3102 demoboard is shown in Figure 20 and the actual PCB layout is shown in Figure 21. The
corresponding bill of material is summarized in Table 3. Parameters of the board were tested with Input voltage Vin = 5 V to
13.2 V and with various output loads between 0 A and 10 A. The board includes a few components used for transient
measurements. The load current range can be selected by switches 1 to 3 to give a range of 0 A - 10 A with 2.5 A steps. A square
wave signal with a 10% duty cycle and a 10 V amplitude has to be connected to the X1 connector to enable the load testing.
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12
NCP3102
Table 3. BILL OF MATERIAL
Position
Value
Description
Part No:
Footprint
Quantity
Manufacturer
R1
732W
Resist. SMD
RMC1/8W 1206 1% 732R
1206
1
MULTICOMP
R2
1.6kW
Resist. SMD
RMC1/8W 1206 1% 1K6
1206
1
MULTICOMP
R3
510W
Resist. SMD
RMC1/8W 1206 1% 510R
1206
1
MULTICOMP
RBOOST
3.3W
Resist. SMD
232273463308
1206
1
PHYCOMP
R5
2.2W
Resist. SMD
232272462208
1206
1
PHYCOMP
R6
OCP set.
Resist. SMD
1206
1
R7
0W
Resist. SMD
TL2BR010FTE
1206
1
TYCO ELECT.
R8
200W
Resist. SMD
WCR 1206 200R 2%.
1206
1
WELWYN
RSN
10W
Resist. SMD
232271161109
1206
1
PHYCOMP
R4*
20W
Resist. SMD
RCA120620R0FKEA
1206
1
VISHAY
RLO1*
1.0W
Resistor 1W
MCF 1W 1R
Special
1
MULTICOMP
RLO2*
1.8W
Resistor 1W
MCF 1W 1R8
Special
1
MULTICOMP
RLO3*
2.2W
Resistor 1W
MCF 1W 2R2
Special
1
MULTICOMP
RLO4*
3.3W
Resistor 1W
MCF 1W 3R3
Special
1
MULTICOMP
RLO5*
2.2.W
Resistor 1W
MCF 1W 2R2
Special
1
MULTICOMP
RLO6*
3.3W
Resistor 1W
MCF 1W 3R3
Special
1
MULTICOMP
RLO7*
1kW
Resist. SMD
232272461002
1206
1
PHYCOMP
RLO8*
1kW
Resist. SMD
232272461002
1206
1
PHYCOMP
RLO9*
1kW
Resist. SMD
232272461002
1206
1
PHYCOMP
RLO10*
75W
Resist. SMD
RMC1/8W 1206 1% 75R
1206
1
MULTICOMP
C2, C4
47mF
Capac. Ceram
C1210C476M9PAC7800
1210
2
KEMET
C15
0.27mF
Cap.OS-CON
16SP270M
Special
1
SANYO
C16
1mF
Cap.OS-CON
4SP1000M
Special
1
SANYO
C5, C8
100mF
Capac. Ceram
CS1210C107M9PAC7800
1210
2
KEMET
CBOOST
2.2nF
Capac. Ceram
12067C222KAT2A
1206
1
AVX
C11, C12
220nF
Capac. Ceram
12065G224ZAT2A
1206
1
AVX
C9
33nF
Capac. Ceram
B37972K5333K-MR
1206
1
TYCHO ELECT.
C10
120pF
Capac. Ceram
2250 001 11537
1206
1
PHYCOMP
C13
22nF
Capac. Ceram
2238 581 15641
1206
1
PHYCOMP
CSN
470pF
Capac. Ceram
12067A471JAT1A
1206
1
AVX
CLO1-3*
470pF
Capac. Ceram
12067A471JAT1A
1206
1
AVX
D1
BAT54T1
Diode
BAT54T1G
SOD123
1
ON Semiconducor
D2-3
MBRS140T3
Diode
MBRS140T3G
SMB
2
ON Semiconducor
L1
3.3mH
Coil
DO5010H-332M
DO5010H
1
Coilcraft
Q1-3*
NTD4810
MOSFET
NTD4810NH
DPAK
3
ON Semiconductor
IC1
NCP3102
I.C.
NCP3102MNTXG
QFN40
1
ON Semiconductor
*Parts marked with “*” and highlighted in grey are only necessary for transient response and PHASE-GAIN feedback measuring.
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13
NCP3102
Figure 21. PCB Layout Evaluation Board (110mm x 100mm)
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14
NCP3102
Measured Performance of NCP3102 Demoboard is Shown in Figures 22 Through 25.
18
100
16
95
14
90
TJ = 25°C
12
10
8
6
TJ = 70°C
4
TJ = 125°C
8V
80
10 V
12 V
75
13.2 V
70
65
2
0
6V
85
4
5
6
7
8
9
10
Rocp RESISTANCE (kW)
11
12
60
13
0
2
3
4
5
6
7
OUTPUT CURRENT (A)
8
9
10
Figure 23. Efficiency (Vout = 3.3 V)
GAIN (dB)
Figure 22. Overcurrent Protection
1
50
-70
40
-80
30
-90
-100
20
Gain
-110
10
0
Phase
-120
-10
-130
-20
-140
-30
-150
-40
100
1000
10000
FREQUENCY (Hz)
Figure 25. Feedback Frequency Response
(Vin = 12 V, Vout = 3.3 V)
Figure 24. Transient Response (Vin = 12 V,
Vout = 3.3 V, Iout = 5 A to 10 A Step) Output
Capacitors: 2x MLCC 100 mF and 820 mF OS-CON
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15
PHASE (deg)
Iocp (A)
EFFICIENCY (%)
4.5 V
-160
100000
NCP3102
Figure 26. Temperature Conditions (Vin = 12 V, Vout = 3.3 V, Iout = 10 A) Steady State, No Additional Cooling
ORDERING INFORMATION
Package
Temperature Grade
Shipping†
NCP3102MNTXG
QFN40
(Pb-Free)
For 0°C to +70°C
2500 / Tape & Reel
NCP3102BMNTXG
QFN40
(Pb-Free)
For -40°C to +85°C
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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16
NCP3102
PACKAGE DIMENSIONS
QFN40 6x6, 0.5P
CASE 485AK-01
ISSUE A
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
A B
D
PIN ONE
LOCATION
2X
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
2X
TOP VIEW
0.15 C
(A3)
0.10 C
A
0.08 C
SIDE VIEW A1
C
NOTE 4
SEATING
PLANE
D3
40X
G3
D5
G2
L
11
11
G2
21
10
21
10
E4
E2
E3
1
30
e
e/2
40X
G2
0.05 C
31
40
K
b
0.10 C A B
BOTTOM VIEW
30
1
G3
31
40
D2
AUXILIARY
BOTTOM VIEW
NOTE 3
D4
G3
SOLDERING FOOTPRINT
6.30
0.72
1.86
0.72
2.62
0.92 1
0.72
1.58
1.96
0.50
PITCH
6.30
2.31
0.92
40X
0.30
40X
1.01
0.58
0.92
3.26
DIMENSIONS: MILLIMETERS
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17
DIM
A
A1
A3
b
D
D2
D3
D4
D5
E
E2
E3
E4
e
G2
G3
K
L
MILLIMETERS
MIN
MAX
0.80
1.00
--0.05
0.20 REF
0.18
0.30
6.00 BSC
2.45
2.65
3.10
3.30
1.70
1.90
0.85
1.05
6.00 BSC
1.80
2.00
1.43
1.63
2.15
2.35
0.50 BSC
2.10
2.30
2.30
2.50
0.20
--0.30
0.50
NCP3102
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
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For additional information, please contact your local
Sales Representative
NCP3102/D