ISSI IS49RL36160-107EBL 1066 mhz ddr operation (2133 mb/s/ball datarate) Datasheet

576Mb: x18, x36 RLDRAM 3
Features
RLDRAM 3
IS49RL18320 – 2 Meg x 18 x 16 Banks
IS49RL36160 – 1 Meg x 36 x 16 Banks
Features
• 1066 MHz DDR operation (2133 Mb/s/ball data
rate)
• 76.8 Gb/s peak bandwidth (x36 at 1066 MHz clock
frequency)
• Organization
– 32 Meg x 18, and 16 Meg x 36 common I/O (CIO)
– 16 banks
• 1.2V center-terminated push/pull I/O
• 2.5V VEXT, 1.35V VDD , 1.2V VDDQ I/O
• Reduced cy cle time ( t RC (MIN) = 8 - 12ns)
• SDR addressing
• Programmable READ/WRITE latency (RL/WL) and
burst length
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Free-running differential input data clocks (DKx,
DKx#) and output data clocks (QKx, QKx#)
• On-die DLL generates CK edge-aligned data and
differential output data clock signals
• 64ms refresh (128K refresh per 64ms)
• 168-ball FBGA package
• 40Ω or 60 Ω matched impedance outputs
• Integrated on-die termination (ODT)
• Single or multibank writes
• Extended operating range (200–1066 MHz)
• READ training register
• Multiplexed and non-multiplexed addressing capabilities
• Mirror function
• Output driver and ODT calibration
• JTAG interface (IEEE 1149.1-2001)
Options
• Clock cycle and t RC timing
– 0.93ns and t RC (MIN) = 8ns
(RL3-2133)
– 0.93ns and t RC (MIN) = 10ns
(RL3-2133)
– 1.07ns and t RC (MIN) = 8ns
(RL3-1866)
– 1.07ns and t RC (MIN) = 10ns
(RL3-1866)
– 1.25ns and t RC (MIN) = 10ns
(RL3-1600)
– 1.25ns and t RC (MIN) = 12ns
(RL3-1600)
• Configuration
– 32 Meg x 18
– 16 Meg x 36
• Operating temperature
– Commercial (T C = 0° to +95°C)
– Industrial (TC = –40°C to +95°C)
• Package
– 168-ball FBGA
– 168-ball FBGA (Pb-free)
• Revision
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this
specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any
information, products or services described herein. Customers are advised to obtain the latest version of this device specification
before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its
safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives
written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
01/17/2012
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576Mb: x18, x36 RLDRAM3
Features
Figure 1: 576Mb RLDRAM® 3 Part Numbers
Example Part Number: IS49RL18320-093EBL
IS49RL
Speed Package Temp
Configuration
Temperature
Configuration
32 Meg x 18
18320
Commercial
16 Meg x 36
36160
Industrial
None
I
Speed Grade
-093E t CK = 0.93ns (8ns t RC)
-093
t CK
-107E
t CK
= 0.93ns (10ns t RC)
= 1.07ns
-107
t CK
= 1.07ns (10ns t RC)
-125E
t CK
= 1.25ns
(10ns t RC)
-125
t CK
= 1.25ns (12ns t RC)
(8ns t RC)
Package
168-ball FBGA
B
168-ball FBGA (lead-free)
BL
BGA Part Marking Decoder
Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the
part number. ISSI’s BGA Part Marking Decoder is available on ISSI’s Web site at www.issi.com
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576Mb: x18, x36 RLDRAM 3
Features
Contents
General Description ......................................................................................................................................... 8
General Notes .............................................................................................................................................. 8
State Diagram .................................................................................................................................................. 9
Functional Block Diagrams ............................................................................................................................. 10
Ball Assignments and Descriptions ................................................................................................................. 12
Package Dimensions ....................................................................................................................................... 16
Electrical Characteristics – IDD Specifications .................................................................................................. 17
Electrical Specifications – Absolute Ratings and I/O Capacitance ..................................................................... 21
Absolute Maximum Ratings ........................................................................................................................ 21
Input/Output Capacitance .......................................................................................................................... 21
AC and DC Operating Conditions .................................................................................................................... 22
AC Overshoot/Undershoot Specifications .................................................................................................... 24
Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 27
Slew Rate Definitions for Differential Input Signals ...................................................................................... 29
ODT Characteristics ....................................................................................................................................... 30
ODT Resistors ............................................................................................................................................ 30
ODT Sensitivity .......................................................................................................................................... 32
Output Driver Impedance ............................................................................................................................... 33
Output Driver Sensitivity ............................................................................................................................ 35
Output Characteristics and Operating Conditions ............................................................................................ 36
Reference Output Load ............................................................................................................................... 39
Slew Rate Definitions for Single-Ended Output Signals ..................................................................................... 40
Slew Rate Definitions for Differential Output Signals ........................................................................................ 41
Speed Bin Tables ............................................................................................................................................ 42
AC Electrical Characteristics ........................................................................................................................... 43
Temperature and Thermal Impedance Characteristics ..................................................................................... 48
Command and Address Setup, Hold, and Derating ........................................................................................... 50
Data Setup, Hold, and Derating ....................................................................................................................... 56
Commands .................................................................................................................................................... 62
MODE REGISTER SET (MRS) Command ......................................................................................................... 63
Mode Register 0 (MR0) .................................................................................................................................... 64
tRC ............................................................................................................................................................. 65
Data Latency .............................................................................................................................................. 65
DLL Enable/Disable ................................................................................................................................... 65
Address Multiplexing .................................................................................................................................. 65
Mode Register 1 (MR1) .................................................................................................................................... 67
Output Drive Impedance ............................................................................................................................ 67
DQ On-Die Termination (ODT) ................................................................................................................... 67
DLL Reset ................................................................................................................................................... 67
ZQ Calibration ............................................................................................................................................ 68
ZQ Calibration Long ................................................................................................................................... 69
ZQ Calibration Short ................................................................................................................................... 69
AUTO REFRESH Protocol ............................................................................................................................ 70
Burst Length (BL) ....................................................................................................................................... 70
Mode Register 2 (MR2) .................................................................................................................................... 72
READ Training Register (RTR) ..................................................................................................................... 72
WRITE Protocol .......................................................................................................................................... 74
WRITE Command .......................................................................................................................................... 74
Multibank WRITE ....................................................................................................................................... 75
READ Command ............................................................................................................................................ 75
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576Mb: x18, x36 RLDRAM 3
Features
AUTO REFRESH Command ............................................................................................................................
INITIALIZATION Operation ............................................................................................................................
WRITE Operation ...........................................................................................................................................
READ Operation .............................................................................................................................................
AUTO REFRESH Operation .............................................................................................................................
Multiplexed Address Mode ..............................................................................................................................
Data Latency in Multiplexed Address Mode
.................................................................................................
REFRESH Command in Multiplexed Address Mode
.....................................................................................
Mirror Function ............................................................................................................................................
RESET Operation ...........................................................................................................................................
IEEE 1149.1 Serial Boundary Scan (JTAG) .......................................................................................................
Disabling the JTAG Feature ........................................................................................................................
Test Access Port (TAP) ................................................................................................................................
TAP Controller ...........................................................................................................................................
Performing a TAP RESET ............................................................................................................................
TAP Registers ............................................................................................................................................
TAP Instruction Set ....................................................................................................................................
Revision History ............................................................................................................................................
Rev. B, Advance – 10/11 ..............................................................................................................................
Rev. A, Advance – 6/11 ...............................................................................................................................
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101
102
102
102
103
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106
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576Mb: x18, x36 RLDRAM 3
Features
List of Figures
Figure 1: 576Mb RLDRAM® 3 Part Numbers ..................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 9
Figure 3: 32 Meg x 18 Functional Block Diagram ............................................................................................. 10
Figure 4: 16 Meg x 36 Functional Block Diagram ............................................................................................. 11
Figure 5: 168-Ball FBGA ................................................................................................................................. 16
Figure 6: Single-Ended Input Signal ............................................................................................................... 23
Figure 7: Overshoot ....................................................................................................................................... 24
Figure 8: Undershoot .................................................................................................................................... 24
Figure 9: V IX for Differential Signals ................................................................................................................ 25
Figure 10: Single-Ended Requirements for Differential Signals ........................................................................ 26
Figure 11: Definition of Differential AC Swing and tDVAC ................................................................................ 26
Figure 12: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 28
Figure 13: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx# .................................. 29
Figure 14: ODT Levels and I-V Characteristics ................................................................................................ 30
Figure 15: Output Driver ................................................................................................................................ 33
Figure 16: DQ Output Signal .......................................................................................................................... 38
Figure 17: Differential Output Signal .............................................................................................................. 39
Figure 18: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 39
Figure 19: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 40
Figure 20: Nominal Differential Output Slew Rate Definition for QKx, QKx# ..................................................... 41
Figure 21: Example Temperature Test Point Location ...................................................................................... 49
Figure 22: Nominal Slew Rate and tVAC for tIS (Command and Address - Clock) ............................................... 52
Figure 23: Nominal Slew Rate for tIH (Command and Address - Clock) ............................................................ 53
Figure 24: Tangent Line for tIS (Command and Address - Clock) ...................................................................... 54
Figure 25: Tangent Line for tIH (Command and Address - Clock) ..................................................................... 55
Figure 26: Nominal Slew Rate and tVAC for tDS (DQ - Strobe) .......................................................................... 58
Figure 27: Nominal Slew Rate for tDH (DQ - Strobe) ........................................................................................ 59
Figure 28: Tangent Line for tDS (DQ - Strobe) ................................................................................................. 60
Figure 29: Tangent Line for tDH (DQ - Strobe) ................................................................................................ 61
Figure 30: MRS Command Protocol ............................................................................................................... 63
Figure 31: MR0 Definition for Non-Multiplexed Address Mode ........................................................................ 64
Figure 32: MR1 Definition for Non-Multiplexed Address Mode ........................................................................ 67
Figure 33: ZQ Calibration Timing (ZQCL and ZQCS) ....................................................................................... 69
Figure 34: Read Burst Lengths ........................................................................................................................ 71
Figure 35: MR2 Definition for Non-Multiplexed Address Mode ........................................................................ 72
Figure 36: READ Training Function - Back-to-Back Readout ............................................................................ 73
Figure 37: WRITE Command ......................................................................................................................... 74
Figure 38: READ Command ........................................................................................................................... 76
Figure 39: Bank Address-Controlled AUTO REFRESH Command ..................................................................... 77
Figure 40: Multibank AUTO REFRESH Command ........................................................................................... 78
Figure 41: Power-Up/Initialization Sequence ................................................................................................. 80
Figure 42: WRITE Burst ................................................................................................................................. 82
Figure 43: Consecutive WRITE Bursts ............................................................................................................. 83
Figure 44: WRITE-to-READ ............................................................................................................................ 83
Figure 45: WRITE - DM Operation .................................................................................................................. 84
Figure 46: Consecutive Quad Bank WRITE Bursts ........................................................................................... 85
Figure 47: Interleaved READ and Quad Bank WRITE Bursts ............................................................................. 85
Figure 48: Basic READ Burst .......................................................................................................................... 86
Figure 49: Consecutive READ Bursts (BL = 2) .................................................................................................. 87
Figure 50: Consecutive READ Bursts (BL = 4) .................................................................................................. 87
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576Mb: x18, x36 RLDRAM 3
Features
Figure 51:
Figure 52:
Figure 53:
Figure 54:
Figure 55:
Figure 56:
Figure 57:
Figure 58:
Figure 59:
Figure 60:
Figure 61:
Figure 62:
Figure 63:
Figure 64:
Figure 65:
Figure 66:
Figure 67:
Figure 68:
Figure 69:
Figure 70:
Figure 71:
READ-to-WRITE ............................................................................................................................ 88
Read Data Valid Window ................................................................................................................ 88
Bank Address-Controlled AUTO REFRESH Cycle ............................................................................. 89
Multibank AUTO REFRESH Cycle ................................................................................................... 89
READ Burst with ODT .................................................................................................................... 90
READ-NOP-READ with ODT .......................................................................................................... 91
Command Description in Multiplexed Address Mode ..................................................................... 92
Power-Up/Initialization Sequence in Multiplexed Address Mode ..................................................... 93
MR0 Definition for Multiplexed Address Mode ................................................................................ 94
MR1 Definition for Multiplexed Address Mode ................................................................................ 95
MR2 Definition for Multiplexed Address Mode ................................................................................ 96
Bank Address-Controlled AUTO REFRESH Operation with Multiplexed Addressing .......................... 97
Multibank AUTO REFRESH Operation with Multiplexed Addressing ................................................ 97
Consecutive WRITE Bursts with Multiplexed Addressing ................................................................. 98
WRITE-to-READ with Multiplexed Addressing ................................................................................ 99
Consecutive READ Bursts with Multiplexed Addressing ................................................................... 99
READ-to-WRITE with Multiplexed Addressing ............................................................................... 100
TAP Controller State Diagram ........................................................................................................ 104
TAP Controller Functional Block Diagram ..................................................................................... 104
JTAG Operation - Loading Instruction Code and Shifting Out Data ................................................. 107
TAP Timing .................................................................................................................................. 108
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576Mb: x18, x36 RLDRAM 3
Features
List of Tables
Table 1: 32 Meg x 18 B all Assignments – 168-B all FBGA (Top View) ..................................................................
Table 2: 16 Meg x 36 Ball Assignments – 168-Ball FBGA (Top View)
..................................................................
Table 3: Ball Descriptions ..............................................................................................................................
................................................................................
Table 4: I DD Operating Conditions and Maximum Limits
Table 5: Absolute Maximum Ratings
..............................................................................................................
Table 6: Input/Output Capacitance
................................................................................................................
Table 7: DC Electrical Characteristics and Operating Conditions
.....................................................................
Table 8: Input AC Logic Levels ........................................................................................................................
Table 9: Control and Address Balls
.................................................................................................................
Table 10: Clock, Data, Strobe, and Mask Balls
.................................................................................................
Table 11: Differential Input Operating Conditions (CK, CK# and DKx, DKx#)
...................................................
Table 12: Allowed Time Before Ringback ( t DVAC) for CK, CK#, DKx, and DK x# .................................................
Table 13: Single-Ended Input Slew Rate Definition
..........................................................................................
Table 14: Differential Input Slew Rate Definition
.............................................................................................
Table 15: ODT DC Electrical Characteristics
...................................................................................................
Table 16: R TT Effective Impedances ................................................................................................................
Table 17: ODT Sensitivity Definition
..............................................................................................................
Table 18: ODT Temperature and Voltage Sensitivity
........................................................................................
Table 19: Driver Pull-Up and Pull-Down Impedance Calculations
...................................................................
Table 20: Output Driver Sensitivity Definition
.................................................................................................
Table 21: Output Driver Voltage and Temperature Sensitivity
..........................................................................
Table 22: Single-Ended Output Driver Characteristics
.....................................................................................
Table 23: Differential Output Driver Characteristics
........................................................................................
Table 24: Single-Ended Output Slew Rate Definition
.......................................................................................
Table 25: Differential Output Slew Rate Definition
..........................................................................................
Table 26: RL3 Speed Bins ...............................................................................................................................
Table 27: AC Electrical Characteristics
............................................................................................................
Table 28: Temperature Limits
.........................................................................................................................
Table 29: Thermal Impedance
........................................................................................................................
Table 30: Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based
........................
Table 31: Derating Values for t IS/ t IH – AC150/DC100-Based
............................................................................
Table 32: Minimum Required Time t VAC Above VIH(AC) (or Below V IL(AC)) for Valid Transition
............................
Table 33: Data Setup and Hold Values at 1 V/ns (DKx, DKx# at 2V/ns) – AC/DC-Based
.....................................
Table 34: Derating Values for t DS/ t DH – AC150/DC100-Based
.........................................................................
Table 35: Minimum Required Time t VAC Above VIH(AC) (or Below V IL(AC)) for Valid Transition
............................
Table 36: Command Descriptions
..................................................................................................................
Table 37: Command Table
.............................................................................................................................
Table 38: tRC_MRS MR0[3:0] values ...............................................................................................................
Table 39: Address Widths of Different Burst Lengths
.......................................................................................
Table 40: Address Mapping in Multiplexed Address Mode
...............................................................................
Table 41: 32 Meg x 18 Ball Assignments with MF Ball Tied HIGH
.....................................................................
Table 42: TAP Input AC Logic Levels ..............................................................................................................
Table 43: TAP AC Electrical Characteristics
....................................................................................................
Table 44: TAP DC Electrical Characteristics and Operating Conditions
............................................................
Table 45: Identification Register Definitions
..................................................................................................
Table 46: Scan Register Sizes .........................................................................................................................
Table 47: Instruction Codes
..........................................................................................................................
Table 48: Boundary Scan (Exit)
.....................................................................................................................
Table 49: Ordering Information
.....................................................................................................................
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12
13
14
17
21
21
22
22
24
24
25
27
27
29
30
31
32
32
34
35
35
36
37
40
41
42
43
48
48
50
51
51
56
57
57
62
62
65
70
96
101
108
108
109
109
110
110
110
112
576Mb: x18, x36 RLDRAM 3
General Description
General Description
The ISSI RLDRAM® 3 is a high-speed memory device designed for high-bandwidth
data storage—telecommunications, networking, cache applications, etc. The chip’s 16bank architecture is optimized for sustainable high-speed operation.
The DDR I/O interface transfers two data bits per clock cycle at the I/O balls. Output
data is referenced to the READ strobes.
Commands, addresses, and control signals are also registered at every positive edge of
the differential input clock, while input data is registered at both positive and negative
edges of the input data strobes.
Read and write accesses to the RL3 device are burst-oriented. The burst length (BL) is
programmable to 2, 4, or 8 by a setting in the mode register.
The device is supplied with 1.35V for the core and 1.2V for the output drivers. The 2.5V
supply is used for an internal supply.
Bank-scheduled refresh is supported with the row address generated internally.
The 168-ball FBGA package is used to enable ultra-high-speed data transfer rates.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL enable mode of operation.
• Any functionality not specifically stated is considered undefined, illegal, and not supported, and can result in unknown operation.
• Nominal conditions are assumed for specifications not defined within the figures
shown in this data sheet.
• Throughout this data sheet, the terms "RLDRAM," "DRAM,” and "RLDRAM 3" are all
used interchangeably and refer to the RLDRAM 3 SDRAM device.
• References to DQ, DK, QK, DM, and QVLD are to be interpeted as each group collectively, unless specifically stated otherwise. This includes true and complement signals
of differential signals.
• Non-multiplexed operation is assumed if not specified as multiplexed.
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576Mb: x18, x36 RLDRAM 3
State Diagram
State Diagram
Figure 2: Simplified State Diagram
Initialization
sequence
NOP
READ
WRITE
RESET#
MRS
AREF
Automatic sequence
Command sequence
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Figure 3: 32 Meg x 18 Functional Block Diagram
ZQ
ZQ CAL
RZQ
ZQ CAL
ZQCL, ZQCS
ODT control
CK
CK#
CS#
Command
decode
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Functional Block Diagrams
REF#
WE#
Control
logic
VDDQ/2
Bank 15
Bank 14
RTT
MF
RESET#
Mode register
Refresh
counter
24
ODT control
Bank 1
Bank 0
13
Rowaddress
MUX
13
13
Bank 0
rowaddress
latch
and
decoder
8192
DLL
ZQ CAL
144
SENSE
AMPLIFIERS
Sense amplifiers
READ n
logic
n
18
18
18
DQ
latch
4
144
24
Address
register
Bank
control
logic
4
RTT
ODT control
18
8
TMS
TDI
JTAG
Logic and
Boundary
Scan Register
71
Column
decoder
CLK
in
71
(0...3)
RCVRS
18
18
Input
logic
5
WRITE
FIFO
and
drivers
4
DK0/DK0#, DK1/DK1#
VDDQ/2
RTT
21
ODT control
2
DM[1:0]
TDO
Notes:
1. Example for BL = 2; column address will be reduced with an increase in burst length.
2. 8 = (length of burst) x 2^ (number of column addresses to WRITE FIFO and READ logic).
10
DRAFT 12/19/2011
576Mb: x18, x36 RLDRAM 3
Functional Block Diagrams
144
TCK
DQ[17:0]
16
32
Columnaddress
counter/
latch
QK0/QK0#,QK1/QK1#
VDDQ/2
1
2
I/O gating
DQM mask logic
16
QVLD
READ
Drivers
QK/QK#
generator
8192
A[19:0]1
BA[3:0]
(0 ....17)
CK/CK#
Bank 0
memory
array
(8192 x 32 x 8 x 18)2
Figure 4: 16 Meg x 36 Functional Block Diagram
ZQ
ZQ CAL
RZQ
ZQ CAL
ZQCL, ZQCS
ODT control
CK
CK#
CS#
Command
decode
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Functional Block Diagrams
REF#
WE#
Control
logic
VDDQ/2
Bank 15
Bank 14
RTT
MF
RESET#
Refresh
counter
Mode register
23
ODT control
Bank 1
Bank 0
13
Rowaddress
MUX
13
13
Bank 0
rowaddress
latch
and
decoder
8192
144
READ n
logic
n
36
36
READ
Drivers
DQ
latch
36
Bank
control
logic
4
ODT control
(0...3)
16
4
32
8
TCK
TMS
TDI
61
WRITE
FIFO
and
drivers
CLK
in
61
36
36
36
RCVRS
Input
logic
Column
decoder
VDDQ/2
RTT
11
JTAG
Logic and
Boundary
Scan Register
DK0/DK0#, DK1/DK1#
ODT control
2
DM[1:0]
TDO
Notes:
1. Example for BL = 2; column address will be reduced with an increase in burst length.
2. 4 = (length of burst) x 2^ (number of column addresses to WRITE FIFO and READ logic).
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DRAFT 12/19/2011
576Mb: x18, x36 RLDRAM 3
Functional Block Diagrams
144
5
Columnaddress
counter/
latch
DQ[35:0]
RTT
11
I/O gating
DQM mask logic
16
QK0/QK0#, QK1/QK1#
QK2/QK2#, QK3/QK3#
VDDQ/2
144
Address
register
QVLD[1:0]
8
QK/QK#
generator
8192
23
DLL
ZQ CAL
SENSEamplifiers
AMPLIFIERS
Sense
A[18:0]1
(0 ....35)
CK/CK#
Bank 0
memory
array
(8192 x 32 x 4 x 36)2
576Mb: x18, x36 RLDRAM 3
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Table 1: 32 Meg x 18 Ball Assignments – 168-Ball FBGA (Top View)
1
A
2
3
4
5
6
7
8
9
10
11
12
13
VSS
VDD
NF
VDDQ
NF
VREF
DQ7
VDDQ
DQ8
VDD
VSS
RESET#
B
VEXT
VSS
NF
VSSQ
NF
VDDQ
DM0
VDDQ
DQ5
VSSQ
DQ6
VSS
VEXT
C
VDD
NF
VDDQ
NF
VSSQ
NF
DK0#
DQ2
VSSQ
DQ3
VDDQ
DQ4
VDD
D
A11
VSSQ
NF
VDDQ
NF
VSSQ
DK0
VSSQ
QK0
VDDQ
DQ0
VSSQ
A13
E
VSS
A0
VSSQ
NF
VDDQ
NF
MF
QK0#
VDDQ
DQ1
VSSQ
CS#
VSS
1
F
A7
NF(A20)
VDD
A2
A1
WE#
ZQ
REF#
A3
A4
VDD
A5
A9
G
VSS
A15
A6
VSS
BA1
VSS
CK#
VSS
BA0
VSS
A8
A18
VSS
H
A19
VDD
A14
A16
VDD
BA3
CK
BA2
VDD
A17
A12
VDD
A10
J
VDDQ
NF
VSSQ
NF
VDDQ
NF
VSS
QK1#
VDDQ
DQ9
VSSQ
QVLD
VDDQ
K
NF
VSSQ
NF
VDDQ
NF
VSSQ
DK1
VSSQ
QK1
VDDQ
DQ10
VSSQ
DQ11
L
VDD
NF
VDDQ
NF
VSSQ
NF
DK1#
DQ12
VSSQ
DQ13
VDDQ
DQ14
VDD
M
VEXT
VSS
NF
VSSQ
NF
VDDQ
DM1
VDDQ
DQ15
VSSQ
DQ16
VSS
VEXT
N
VSS
TCK
VDD
TDO
VDDQ
NF
VREF
DQ17
VDDQ
TDI
VDD
TMS
VSS
Notes:
1. Location of the additional address signal (A20) required on the 1Gb RLDRAM 3 x18 configuration. Internally connected so it can mirror the A5 address signal when MF is asserted HIGH. Has parasitic characteristics of an address pin.
2. NF balls for the x18 configuration are internally connected and have parasitic characteristics of an I/O. Balls may be connected to VSSQ.
3. MF is assumed to be tied LOW for this ball assignment.
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01/17/2012
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576Mb: x18, x36 RLDRAM 3
Ball Assignments and Descriptions
Table 2: 16 Meg x 36 Ball Assignments – 168-Ball FBGA (Top View)
1
A
2
3
4
5
6
7
8
9
10
11
12
13
VSS
VDD
DQ26
VDDQ
DQ25
VREF
DQ7
VDDQ
DQ8
VDD
VSS
RESET#
B
VEXT
VSS
DQ24
VSSQ
DQ23
VDDQ
DM0
VDDQ
DQ5
VSSQ
DQ6
VSS
VEXT
C
VDD
DQ22
VDDQ
DQ21
VSSQ
DQ20
DK0#
DQ2
VSSQ
DQ3
VDDQ
DQ4
VDD
D
A11
VSSQ
DQ18
VDDQ
QK2
VSSQ
DK0
VSSQ
QK0
VDDQ
DQ0
VSSQ
A13
E
VSS
A0
VSSQ
DQ19
VDDQ
QK2#
MF
QK0#
VDDQ
DQ1
VSSQ
CS#
VSS
1
F
A7
NF(A20)
VDD
A2
A1
WE#
ZQ
REF#
A3
A4
VDD
A5
A9
G
VSS
A15
A6
VSS
BA1
VSS
CK#
VSS
BA0
VSS
A8
A18
VSS
H
NF(A19)2
VDD
A14
A16
VDD
BA3
CK
BA2
VDD
A17
A12
VDD
A10
J
VDDQ
QVLD1
VSSQ
DQ27
VDDQ
QK3#
VSS
QK1#
VDDQ
DQ9
VSSQ
QVLD0
VDDQ
K
DQ29
VSSQ
DQ28
VDDQ
QK3
VSSQ
DK1
VSSQ
QK1
VDDQ
DQ10
VSSQ
DQ11
L
VDD
DQ32
VDDQ
DQ31
VSSQ
DQ30
DK1#
DQ12
VSSQ
DQ13
VDDQ
DQ14
VDD
M
VEXT
VSS
DQ34
VSSQ
DQ33
VDDQ
DM1
VDDQ
DQ15
VSSQ
DQ16
VSS
VEXT
N
VSS
TCK
VDD
TDO
VDDQ
DQ35
VREF
DQ17
VDDQ
TDI
VDD
TMS
VSS
Notes:
1. Location of the additional address signal (A20) required on the 1Gb RLDRAM 3 x18 configuration. Internally connected so it can mirror the A5 address signal when MF is asserted HIGH. Has parasitic characteristics of an address pin.
2. NF ball for x36 configuration is internally connected and has parasitic characteristics of
an address (A19 for x18 configuration). Ball may be connected to VSSQ.
3. MF is assumed to be tied LOW for this ball assignment.
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576Mb: x18, x36 RLDRAM 3
Ball Assignments and Descriptions
Table 3: Ball Descriptions
Symbol
Type
Description
A[19:0]
Input
Address inputs: A[19:0] define the row and column addresses for READ and WRITE operations.
During a MODE REGISTER SET, the address inputs define the register settings along with BA[3:0].
They are sampled at the rising edge of CK.
BA[3:0]
Input
Bank address inputs: Select the internal bank to which a command is being applied.
CK/CK#
Input
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on
the rising edge of CK.
CS#
Input
Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When
the command decoder is disabled, new commands are ignored, but internal operations continue.
DQ[35:0]
I/O
Data input: The DQ signals form the 36-bit data bus. During READ commands, the data is referenced to both edges of QK. During WRITE commands, the data is sampled at both edges of DK.
DKx, DKx#
Input
Input data clock: DKx and DKx# are differential input data clocks. All input data is referenced
to both edges of DKx. For the x36 device, DQ[8:0] and DQ[26:18] are referenced to DK0 and
DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1 and DK1#. For the x18 device, DQ[8:0]
are referenced to DK0 and DK0#, and DQ[17:9] are referenced to DK1 and DK1#. DKx and DKx#
are free-running signals and must always be supplied to the device.
DM[1:0]
Input
Input data mask: DM is the input mask signal for WRITE data. Input data is masked when DM
is sampled HIGH. DM0 is used to mask the lower byte for the x18 device and DQ[8:0] and
DQ[26:18] for the x36 device. DM1 is used to mask the upper byte for the x18 device and
DQ[17:9] and DQ[35:27] for the x36 device. Tie DM[1:0] to VSS if not used.
TCK
Input
IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used.
TMS, TDI
Input
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
WE#, REF#
Input
Command inputs: Sampled at the positive edge of CK, WE# and REF# (together with CS#) define the command to be executed.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. RESET# assertion and deassertion
are asynchronous. RESET# is a CMOS input defined with DC HIGH ≥ 0.8 x VDD and DC LOW ≤ 0.2 x
VDDQ.
ZQ
Input
External impedance: This signal is used to tune the device’s output impedance and ODT. RZQ
needs to be 240Ω, where RZQ is a resistor from this signal to ground.
QKx, QKx#
Output
Output data clocks: QK and QK# are opposite-polarity output data clocks. They are free-running signals and during READ commands are edge-aligned with the DQs. For the x36 device,
QK0, QK0# align with DQ[8:0]; QK1, QK1# align with DQ[17:9]; QK2, QK2# align with DQ[26:18];
QK3, QK3# align with DQ[35:27]. For the x18 device, QK0, QK0# align with DQ[8:0]; QK1, QK1#
align with DQ[17:9].
QVLDx
Output
Data valid: The QVLD ball indicates that valid output data will be available on the subsequent
rising clock edge. There is a single QVLD ball for the x18 device and two, QVLD0 and QVLD1, for
the x36 device. QVLD0 aligns with DQ[17:0]; QVLD1 aligns with DQ[35:18].
MF
Input
Mirror function: The mirror function ball is a DC input used to create mirrored ballouts for simple dual-loaded clamshell mounting. If the ball is tied to VSS, the address and command balls are
in their true layout. If the ball is tied to VDDQ, they are in the complement location. MF must be
tied HIGH or LOW and cannot be left floating. MF is a CMOS input defined with DC HIGH ≥ 0.8 x
VDD and DC LOW ≤ 0.2 x VDDQ.
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576Mb: x18, x36 RLDRAM 3
Ball Assignments and Descriptions
Table 3: Ball Descriptions (Continued)
Symbol
Type
TDO
Output
Description
IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function
is not used.
VDD
Supply
Power supply: 1.35V nominal. See Table 7 (page 22) for range.
VDDQ
Supply
DQ power supply: 1.2V nominal. Isolated on the device for improved noise immunity. See Table 7 (page 22) for range.
VEXT
Supply
Power supply: 2.5V nominal. See Table 7 (page 22) for range.
VREF
Supply
Input reference voltage: VDDQ/2 nominal. Provides a reference voltage for the input buffers.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
NC
–
No connect: These balls are not connected to the DRAM.
NF
–
No function: These balls are connected to the DRAM, but provide no functionality.
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576Mb: x18, x36 RLDRAM 3
Package Dimensions
Package Dimensions
Figure 5: 168-Ball FBGA
Seating plane
A
168X Ø0.55
Dimensions apply
to solder balls postreflow on Ø0.40 NSMD
ball pads.
0.12 A
Ball A1 ID
Ball A1 ID
13 12
11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
13.5 ±0.1
E
F
G
12 CTR
H
J
K
L
M
1 TYP
N
1 TYP
1.1 ±0.1
12 CTR
0.325 MIN
13.5 ±0.1
Note:
1. All dimensions are in millimeters.
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Electrical Characteristics – IDD Specifications
Table 4: IDD Operating Conditions and Maximum Limits
Notes 1–6 apply to the entire table
Description Condition
Symbol
-093E
-093
-107E
-107
-125E
-125
Units
Notes
tCK
ISB1 (VDD) x18
125
125
125
125
125
125
mA
7
ISB1 (VDD) x36
125
125
125
125
125
125
= idle; All banks idle; No inputs
toggling
ISB1 (VEXT)
30
30
30
30
30
30
Clock active
standby current
CS# = 1; No commands; Bank address incremented and half address/data change once every four
clock cycles
ISB2 (VDD) x18
870
870
815
815
725
725
ISB2 (VDD) x36
895
895
835
835
740
740
ISB2 (VEXT)
30
30
30
30
30
30
Operational
current: BL2
BL = 2; Sequential bank access;
Bank transitions once every tRC;
Half address transitions once every
tRC; Read followed by write sequence; Continuous data during
WRITE commands
IDD1 (VDD) x18
1175
1115
1100
1045
940
915
IDD1 (VDD) x36
1185
1125
1110
1055
950
925
IDD1 (VEXT)
35
35
35
35
35
35
BL = 4; Sequential bank access;
Bank transitions once every tRC;
Half address transitions once every
tRC; Read followed by write sequence; Continuous data during
WRITE commands
IDD2 (VDD) x18
1205
1145
1130
1075
970
945
IDD2 (VDD) x36
1215
1155
1140
1080
980
950
IDD2 (VEXT)
35
35
35
35
35
35
BL = 8; Sequential bank access;
Bank transitions once every tRC;
Half address transitions once every
tRC; Read followed by write sequence; Continuous data during
WRITE commands
IDD3 (VDD) x18
1300
1220
1200
1130
1030
1000
IDD3 (VDD) x36
NA
NA
NA
NA
NA
NA
IDD3 (VEXT)
35
35
35
35
35
35
Sixteen bank cyclic refresh using
Bank Address Control AREF protocol; Command bus remains in refresh for all sixteen banks; DQs are
High-Z and at VDDQ/2; Addresses
are at VDDQ/2
IREF1 (VDD) x18
1550
1550
1400
1400
1230
1230
IREF1 (VDD) x36
1570
1570
1420
1420
1245
1245
IREF1 (VEXT)
80
80
75
75
70
70
Operational
current: BL4
Operational
current: BL8
Burst refresh
current
17
DRAFT 12/19/2011
mA
mA
mA
mA
mA
576Mb: x18, x36 RLDRAM 3
Electrical Characteristics – IDD Specifications
Standby
current
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01/17/2012
Table 4: IDD Operating Conditions and Maximum Limits (Continued)
Notes 1–6 apply to the entire table
Description Condition
Symbol
-093E
-093
-107E
-107
-125E
-125
Units
IREF2 (VDD) x18
855
855
800
800
710
710
mA
IREF2 (VDD) x36
875
875
815
815
725
725
IREF2 (VEXT)
30
30
30
30
30
30
1965
1965
1895
1895
1650
1650
2155
2155
1915
1915
1665
1665
130
130
115
115
105
105
Single bank refresh using Bank Address Control AREF protocol; Sequential bank access every 0.489μs;
DQs are High-Z and at VDDQ/2; Addresses are at VDDQ/2
Multibank refresh current:
4 bank refresh
Quad bank refresh using MultiIMBREF4 (VDD) x18
bank AREF protocol; BL=4; Cyclic
IMBREF4 (VDD) x36
bank access; Subject to tSAW and
IMBREF4 (VEXT)
tMMD specifications; DQs are HighZ and at VDDQ/2; Bank addresses
are at VDDQ/2
Operating
burst write
current : BL2
BL = 2; Cyclic bank access; Half of
address bits change every clock cycle; Continuous data; Measurement is taken during continuous
WRITE
IDD2W (VDD) x18
2110
2110
1910
1910
1665
1665
IDD2W (VDD) x36
2290
2290
2070
2070
1805
1805
IDD2W (VEXT)
80
80
75
75
70
70
Operating
burst write
current : BL4
BL = 4; Cyclic bank access; Half of
address bits change every two
clock cycles; Continuous data;
Measurement is taken during continuous WRITE
IDD4W (VDD) x18
1730
1730
1590
1590
1395
1395
IDD4W (VDD) x36
1815
1815
1665
1665
1460
1460
IDD4W (VEXT)
55
55
55
55
50
50
Operating
burst write
current :BL8
BL = 8; Cyclic bank access; Half of
address bits change every four
clock cycles; Continuous data;
Measurement is taken during continuous WRITE
IDD8W (VDD) x18
1475
1475
1335
1335
1190
1190
IDD8W (VDD) x36
NA
NA
NA
NA
NA
NA
IDD8W (VEXT)
45
45
40
40
40
40
Multibank
write current:
Dual bank
write
BL = 4; Cyclic bank access using Dual Bank WRITE; Half of address bits
change every two clock cycles; Continuous data; Measurement is taken during continuous WRITE
IDBWR (VDD) x18
2305
2305
2170
2170
1885
1885
IDBWR (VDD) x36
2400
2400
2250
2250
1960
1960
IDBWR (VEXT)
80
80
75
75
70
70
18
DRAFT 12/19/2011
mA
mA
mA
mA
mA
576Mb: x18, x36 RLDRAM 3
Electrical Characteristics – IDD Specifications
Distributed
refresh current
Notes
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Table 4: IDD Operating Conditions and Maximum Limits (Continued)
Notes 1–6 apply to the entire table
Description Condition
Symbol
-093E
-093
-107E
-107
-125E
-125
Units
mA
BL=4; Cyclic bank access using
Quad Bank WRITE; Half of address
bits change every two clock cycles;
Continuous data; Measurement is
taken during continuous WRITE;
Subject to tSAW specification
IQBWR (VDD) x18
2965
2965
2890
2890
2525
2525
IQBWR (VDD) x36
3195
3195
3000
3000
2615
2615
IQBWR (VEXT)
130
130
115
115
100
100
Operating
burst read
current
example
BL = 2; Cyclic bank access; Half of
address bits change every clock cycle; Continuous data; Measurement is taken during continuous
READ
IDD2R (VDD) x18
2250
2250
2045
2045
1785
1785
IDD2R (VDD) x36
2395
2395
2180
2180
1895
1895
IDD2R (VEXT)
80
80
75
75
70
70
Operating
burst read
current
example
BL = 4; Cyclic bank access; Half of
address bits change every two
clock cycles; Continuous data;
Measurement is taken during continuous READ
IDD4R (VDD) x18
1740
1740
1595
1595
1400
1400
IDD4R (VDD) x36
1835
1835
1685
1685
1475
1475
IDD4R (VEXT)
55
55
55
55
50
50
Operating
burst read
current
example
BL = 8; Cyclic bank access; Half of
address bits change every four
clock cycles; Continuous data;
Measurement is taken during continuous READ
IDD8R (VDD) x18
1450
1450
1315
1315
1175
1175
IDD8R (VDD) x36
NA
NA
NA
NA
NA
NA
IDD8R (VEXT)
45
45
40
40
40
40
19
DRAFT 12/19/2011
mA
mA
mA
576Mb: x18, x36 RLDRAM 3
Electrical Characteristics – IDD Specifications
Multibank
write current:
Quad bank
write
Notes
576Mb: x18, x36 RLDRAM 3
Electrical Characteristics – IDD Specifications
Notes:
1. IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ +95°C;
+1.28V ≤ VDD ≤ +1.42V,+1.14V ≤ VDDQ ≤ +1.26V,+2.38V ≤ VEXT ≤ +2.63V,VREF = VDDQ/2.
2. IDD mesurements use tCK (MIN), tRC (MIN), and minimum data latency (RL and WL).
3. Input slew rate is 1V/ns for single ended signals and 2V/ns for differential signals.
4. Definitions for IDD conditions:
• LOW is defined as VIN ≤ VIL(AC)MAX.
• HIGH is defined as VIN ≥ VIH(AC)MIN.
• Continuous data is defined as half the DQ signals changing between HIGH and LOW
every half clock cycle (twice per clock).
• Continuous address is defined as half the address signals changing between HIGH and
LOW every clock cycle (once per clock).
• Sequential bank access is defined as the bank address incrementing by one every tRC.
• Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2 this is every clock, for BL = 4 this is every other clock, and for
BL = 8 this is every fourth clock.
5. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions more than once per clock cycle.
6. IDD parameters are specified with ODT disabled.
7. Upon exiting standby current conditions, at least one NOP command must be issued
with stable clock prior to issuing any other valid command.
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576Mb: x18, x36 RLDRAM 3
Electrical Specifications – Absolute Ratings and I/O Capacitance
Electrical Specifications – Absolute Ratings and I/O Capacitance
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 5: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VDDQ
Voltage on VDDQ supply relative to VSS
–0.4
1.66
V
Voltage on any ball relative to VSS
–0.4
1.66
V
Voltage on VEXT supply relative to VSS
–0.4
2.8
V
VIN,VOUT
VEXT
Input/Output Capacitance
Table 6: Input/Output Capacitance
Notes 1-2 apply to entire table
RL3-2133
Capacitance Parameters
Symbol
Min
CK/CK#
CCK
ΔC: CK to CK#
CDCK
Single-ended I/O: DQ, DM
Input strobe: DK/DK#
Output strobe: QK/QK#, QVLD
RL3-1866
Max
Min
1.3
2.1
0
0.15
CIO
1.9
CIO
1.9
RL3-1600
Max
Min
Max
Units
1.3
2.1
0
0.15
1.3
2.2
pF
0
0.15
pF
2.9
1.9
3.0
2.0
3.1
pF
2.9
1.9
3.0
2.0
3.1
pF
Notes
3
CIO
1.9
2.9
1.9
3.0
2.0
3.1
pF
ΔC: DK to DK#
CDDK
0
0.15
0
0.15
0
0.15
pF
ΔC: QK to QK#
CDQK
0
0.15
0
0.15
0
0.15
pF
ΔC: DQ to QK or DQ to DK
CDIO
–0.5
0.3
–0.5
0.3
–0.5
0.3
pF
4
Inputs (CMD, ADDR)
ΔC: CMD_ADDR to CK
JTAG balls
RESET#, MF balls
Notes:
CI
1.25
2.25
1.25
2.25
1.25
2.25
pF
5
CDI_CMD_ADDR
–0.5
0.3
–0.5
0.3
–0.4
0.4
pF
6
CJTAG
1.5
4.5
1.5
4.5
1.5
4.5
pF
7
CI
–
3.0
–
3.0
–
3.0
pF
1. +1.28V ≤ VDD ≤ +1.42V, +1.14V ≤ VDDQ ≤ 1.26V, +2.38V ≤ VEXT ≤ +2.63V,VREF = VSS, f = 100
MHz, TC = 25°C, VOUT(DC) = 0.5 × VDDQ, VOUT (peak-to-peak) = 0.1V.
2. Capacitance is not tested on ZQ ball.
3. DM input is grouped with the I/O balls, because they are matched in loading.
4. CDIO = CIO(DQ) - 0.5 × (CIO [QK] + CIO [QK#]).
5. Includes CS#, REF#, WE#, A[19:0], and BA[3:0].
6. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 × (CCK [CK] + CCK [CK#]).
7. JTAG balls are tested at 50 MHz.
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576Mb: x18, x36 RLDRAM 3
AC and DC Operating Conditions
AC and DC Operating Conditions
Table 7: DC Electrical Characteristics and Operating Conditions
Note 1 applies to the entire table; Unless otherwise noted: 0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V
Description
Symbol
Min
Max
Units
Supply voltage
VEXT
2.38
2.63
V
Supply voltage
VDD
1.28
1.42
V
Isolated output buffer supply
VDDQ
1.14
1.26
V
Reference voltage
VREF
0.49 × VDDQ
0.51 × VDDQ
V
Input HIGH (logic 1) voltage
VIH(DC)
VREF + 0.10
VDDQ
V
Input LOW (logic 0) voltage
VIL(DC)
VSS
VREF - 0.10
V
ILI
–2
2
µA
IREF
–5
5
µA
Input leakage current: Any input 0V ≤ VIN ≤ VDD, VREF
ball 0V ≤ VIN ≤ 1.1V (All other balls not under test = 0V)
Reference voltage current
Notes:
Notes
2, 3
1. All voltages referenced to VSS (GND).
2. The nominal value of VREF is expected to be 0.5 × VDDQ of the transmitting device. VREF is
expected to track variations in VDDQ.
3. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2% of the DC value.
DC values are determined to be less than 20 MHz. Peak-to-peak AC noise on VREF should
not exceed ±2% of VREF(DC). Thus, from VDDQ/2, VREF is allowed ±2% VDDQ/2 for DC error
and an additional ±2% VDDQ/2 for AC noise. The measurement is to be taken at the
nearest VREF bypass capacitor.
Table 8: Input AC Logic Levels
Notes 1-3 apply to entire table; Unless otherwise noted: 0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V
Description
Symbol
Min
Max
Units
Input HIGH (logic 1) voltage
VIH(AC)
VREF + 0.15
–
V
Input LOW (logic 0) voltage
VIL(AC)
–
VREF - 0.15
V
Notes:
1. All voltages referenced to VSS (GND).
2. The receiver will effectively switch as a result of the signal crossing the AC input level,
and will remain in that state as long as the signal does not ring back above/below the
DC input LOW/HIGH level.
3. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is
900mV (peak-to-peak).
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576Mb: x18, x36 RLDRAM 3
AC and DC Operating Conditions
Figure 6: Single-Ended Input Signal
VIL and VIH levels with ringback
1.60V
VDDQ + 0.4V narrow
pulse width
1.20V
VDDQ
Minimum VIL and VIH levels
0.750V
0.70V
VIH(AC)
VIH(DC)
0.624V
0.612V
0.60V
0.588V
0.576V
0.50V
0.45V
0.750V
VIH(AC)
0.70V
VIH(DC)
0.624V
0.612V
0.60V
0.588V
0.576V
VIL(DC)
VIL(AC)
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
0.50V
VIL(DC)
0.450V
VIL(AC)
0.0V
–0.40V
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VSS
VSS - 0.4V narrow
pulse width
23
576Mb: x18, x36 RLDRAM 3
AC and DC Operating Conditions
AC Overshoot/Undershoot Specifications
Table 9: Control and Address Balls
Parameter
RL3-2133
RL3-1866
RL3-1600
Maximum peak amplitude allowed for overshoot area
0.4V
0.4V
0.4V
Maximum peak amplitude allowed for undershoot area
0.4V
0.4V
0.4V
Maximum overshoot area above VDDQ
0.25 Vns
0.28 Vns
0.33 Vns
Maximum undershoot area below VSS/VSSQ
0.25 Vns
0.28 Vns
0.33 Vns
RL3-2133
RL3-1866
RL3-1600
Maximum peak amplitude allowed for overshoot area
0.4V
0.4V
0.4V
Maximum peak amplitude allowed for undershoot area
0.4V
0.4V
0.4V
Maximum overshoot area above VDDQ
0.10 Vns
0.11 Vns
0.13 Vns
Maximum undershoot area below VSS/VSSQ
0.10 Vns
0.11 Vns
0.13 Vns
Table 10: Clock, Data, Strobe, and Mask Balls
Parameter
Figure 7: Overshoot
Volts (V)
Maximum amplitude
Overshoot area
VDDQ
Time (ns)
Figure 8: Undershoot
VSS/VSSQ
Volts (V)
Undershoot area
Maximum amplitude
Time (ns)
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AC and DC Operating Conditions
Table 11: Differential Input Operating Conditions (CK, CK# and DKx, DKx#)
Notes 1 and 2 apply to entire table
Parameter/Condition
Symbol
Min
Differential input voltage logic HIGH – slew
VIH,diff_slew
+200
n/a
mV
3
Differential input voltage logic LOW – slew
VIL,diff_slew
n/a
-200
mV
3
Differential input voltage logic HIGH
VIH,diff(AC)
2 × (VIH(AC) - VREF)
VDDQ
mV
4
Differential input voltage logic LOW
VIL,diff(AC)
VSSQ
2 × (VIL(AC) - VREF )
mV
5
Differential input crossing voltage relative to VDD/2
Max
Units
Notes
VIX
VREF(DC) - 150
VREF(DC) + 150
mV
6
Single-ended HIGH level
VSEH
VIH(AC)
VDDQ
mV
4
Single-ended LOW level
VSEL
VSSQ
VIL(AC)
mV
5
Notes:
1.
2.
3.
4.
CK/CK# and DKx/DKx# are referenced to VDDQ and VSSQ.
Differential input slew rate = 2 V/ns.
Defines slew rate reference points, relative to input crossing voltages.
Maximum limit is relative to single-ended signals; overshoot specifications are applicable.
5. Minimum limit is relative to single-ended signals; undershoot specifications are applicable.
6. The typical value of VIX is expected to be about 0.5 × VDDQ of the transmitting device
and VIX is expected to track variations in VDDQ. VIX indicates the voltage at which differential input signals must cross.
Figure 9: VIX for Differential Signals
VDDQ
VDDQ
CK#, DKx#
CK#, DKx#
X
VIX
VIX
VDDQ/2
X
X
VDDQ/2
VIX
X
CK, DKx
VSSQ
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VIX
CK, DKx
VSSQ
25
576Mb: x18, x36 RLDRAM 3
AC and DC Operating Conditions
Figure 10: Single-Ended Requirements for Differential Signals
VDDQ
VSEH,min
VDDQ/2
VSEH
CK or DKx
VSEL,max
VSEL
VSS
Figure 11: Definition of Differential AC Swing and tDVAC
tDVAC
VIH,diff(AC)min
VIH,diff_slew,min
CK - CK#
DKx - DKx#
0.0
VIL,diff_slew,max
VIL,diff(AC)max
half cycle
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tDVAC
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AC and DC Operating Conditions
Table 12: Allowed Time Before Ringback (tDVAC) for CK, CK#, DKx, and DKx#
Slew Rate (V/ns)
MIN tDVAC (ps) at |VIH/VIL,diff(AC)|
>4.0
175
4.0
170
3.0
167
2.0
163
1.9
162
1.6
161
1.4
159
1.2
155
1.0
150
<1.0
150
Slew Rate Definitions for Single-Ended Input Signals
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V REF and the first crossing of V IH(AC)min. Setup (tIS and tDS)
nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V REF and the first crossing of V IL(AC)max.
Hold (tIH and tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V IL(DC)max and the first crossing of V REF. Hold (tIH and tDH)
nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V IH(DC)min and the first crossing of V REF (see Figure 12 (page 28)).
Table 13: Single-Ended Input Slew Rate Definition
Input Slew Rates
(Linear Signals)
Measured
Input
Edge
From
To
Calculation
Setup
Rising
VREF
VIH(AC)min
[VIH(AC)min - VREF]/ΔTRS
Falling
VREF
VIL(AC)max
[VREF - VIL(AC)max]/ΔTFS
Rising
VIL(DC)max
VREF
[VREF - VIL(DC)max]/ΔTRH
Falling
VIH(DC)min
VREF
[VIH(DC)min - VREF]/ΔTFH
Hold
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AC and DC Operating Conditions
Figure 12: Nominal Slew Rate Definition for Single-Ended Input Signals
ΔTRS
Setup
Single-ended input voltage (DQ, CMD, ADDR)
VIH(AC)min
VIH(DC)min
VREF
VIL(DC)max
VIL(AC)max
ΔTFS
ΔTRH
Hold
Single-ended input voltage (DQ, CMD, ADDR)
VIH(AC)min
VIH(DC)min
VREF
VIL(DC)max
VIL(AC)max
ΔTFH
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AC and DC Operating Conditions
Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK# and DKx, DKx#) are defined and measured as shown in the following two tables. The nominal slew rate for a rising signal is
defined as the slew rate between V IL,diff,max and V IH,diff,min. The nominal slew rate for a
falling signal is defined as the slew rate between V IH,diff,min and V IL,diff,max.
Table 14: Differential Input Slew Rate Definition
Differential Input
Slew Rates
(Linear Signals)
Input
Edge
CK and DK
reference
Measured
From
To
Calculation
Rising
VIL,diff_slew,max
VIH,diff_slew,min
[VIH,diff_slew,min - VIL,diff_slew,max]/ΔTRdiff
Falling
VIH,diff_slew,min
VIL,diff_slew,max
[VIH,diff_slew,min - VIL,diff_slew,max]/ΔTFdiff
Figure 13: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx#
Differential input voltage (CK, CK#; DKx, DKx#)
ΔTRdiff
VIH,diff_slew,min
0
VIL,diff_slew,max
ΔTFdiff
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ODT Characteristics
ODT Characteristics
ODT effective resistance, RTT, is defined by MR1[4:2]. ODT is applied to the DQ, DM,
and DKx, DKx# balls. The individual pull-up and pull-down resistors (R TTPU and RTTPD)
are defined as follows:
RTTPU =(VDDQ - VOUT) / |IOUT|, under the condition that RTTPD is turned off
RTTPD = (VOUT) / |IOUT|, under the condition that RTTPU is turned off
Figure 14: ODT Levels and I-V Characteristics
Chip in termination mode
ODT
VDDQ
IPU
To
other
circuitry
such as
RCV, . . .
IOUT = IPD - IPU
RTTPU
DQ
IOUT
RTTPD
VOUT
IPD
VSSQ
Table 15: ODT DC Electrical Characteristics
Parameter/Condition
Symbol
RTT effective impedance from VIL(AC) to VIH(AC)
Deviation of VM with respect to VDDQ/2
Notes:
Min
RTT_EFF
Nom
Max
Units
ΔVm
-5
-
+5
Notes
1, 2
See Table 16 (page 31).
%
3
1. Tolerance limits are applicable after proper ZQ calibration has been performed at a stable temperature and voltage. Refer to ODT Sensitivity (page 32) if either the temperature or voltage changes after calibration.
2. Measurement definition for RTT: Apply VIH(AC) to ball under test and measure current
I[VIH(AC)], then apply VIL(AC) to ball under test and measure current I[VIL(AC)]:
RTT =
VIH(AC) - VIL(AC)
|I[VIH(AC)] - I[VIL(AC)]|
3. Measure voltage (VM) at the tested ball with no load:
ΔVM =
2 × VM
- 1 × 100
VDDQ
ODT Resistors
The on-die termination resistance is selected by MR1[4:2]. The following table provides
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576Mb: x18, x36 RLDRAM 3
ODT Characteristics
fication requirements; however, they can be used as design guidelines to indicate what
RTT is targeted to provide:
• RTT 120Ω is made up of RTT120(PD240) and RTT120(PU240).
• RTT 60Ω is made up of RTT60(PD120) and RTT60(PU120).
• RTT 40Ω is made up of RTT40(PD80) and RTT40(PU80).
Table 16: RTT Effective Impedances
RTT
Resistor
VOUT
Min
Nom
Max
Units
120Ω
RTT120(PD240)
0.2 x VDDQ
0.6
1.0
1.1
RZQ/1
0.5 x VDDQ
0.9
1.0
1.1
RZQ/1
0.8 x VDDQ
0.9
1.0
1.4
RZQ/1
RTT120(PU240)
120Ω
60Ω
RTT60(PD120)
RTT60(PU120)
60Ω
40Ω
RTT40(PD80)
RTT40(PU80)
40Ω
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0.2 x VDDQ
0.9
1.0
1.4
RZQ/1
0.5 x VDDQ
0.9
1.0
1.1
RZQ/1
0.8 x VDDQ
0.6
1.0
1.1
RZQ/1
VIL(AC) to
VIH(AC)
0.9
1.0
1.6
RZQ/2
0.2 x VDDQ
0.6
1.0
1.1
RZQ/2
0.5 x VDDQ
0.9
1.0
1.1
RZQ/2
0.8 x VDDQ
0.9
1.0
1.4
RZQ/2
0.2 x VDDQ
0.9
1.0
1.4
RZQ/2
0.5 x VDDQ
0.9
1.0
1.1
RZQ/2
0.8 x VDDQ
0.6
1.0
1.1
RZQ/2
VIL(AC) to
VIH(AC)
0.9
1.0
1.6
RZQ/4
0.2 x VDDQ
0.6
1.0
1.1
RZQ/3
0.5 x VDDQ
0.9
1.0
1.1
RZQ/3
0.8 x VDDQ
0.9
1.0
1.4
RZQ/3
0.2 x VDDQ
0.9
1.0
1.4
RZQ/3
0.5 x VDDQ
0.9
1.0
1.1
RZQ/3
0.8 x VDDQ
0.6
1.0
1.1
RZQ/3
VIL(AC) to
VIH(AC)
0.9
1.0
1.6
RZQ/6
31
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ODT Characteristics
ODT Sensitivity
If either temperature or voltage changes after I/O calibration, then the tolerance limits
listed in Table 15 (page 30) and Table 16 (page 31) can be expected to widen according
to Table 17 (page 32) and Table 18 (page 32).
Table 17: ODT Sensitivity Definition
Symbol
Min
Max
Units
RTT
0.9 - dRTTdT × |DT| - dRTTdV × |DV|
1.6 + dRTTdT × |DT| + dRTTdV × |
DV|
RZQ/(2,4,6)
Note:
1. DT = T - T(@ calibration), DV = VDDQ - VDDQ(@ calibration) or VDD - VDD(@ calibration).
Table 18: ODT Temperature and Voltage Sensitivity
Change
Min
Max
Units
dRTTdT
0
1.5
%/°C
dRTTdV
0
0.15
%/mV
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Output Driver Impedance
Output Driver Impedance
The output driver impedance is selected by MR1[1:0] during initialization. The selected
value is able to maintain the tight tolerances specified if proper ZQ calibration is performed.
Output specifications refer to the default output driver unless specifically stated otherwise. A functional representation of the output buffer is shown below. The output driver
impedance RON is defined by the value of the external reference resistor RZQ as follows:
• RON,x = RZQ/y (with RZQ = 240Ω ±1%; x = 40Ω or 60Ω with y = 6 or 4, respectively)
The individual pull-up and pull-down resistors (RON(PU) and RON(PD)) are defined as follows:
• RON(PU) = (VDDQ - V OUT)/|IOUT|, when RON(PD) is turned off
• RON(PD) = (VOUT)/|IOUT|, when RON(PU) is turned off
Figure 15: Output Driver
Chip in drive mode
Output Driver
VDDQ
IPU
To
other
circuitry
such as
RCV, . . .
RON(PU)
IOUT
RON(PD)
DQ
VOUT
IPD
VSSQ
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Output Driver Impedance
Table 19: Driver Pull-Up and Pull-Down Impedance Calculations
RON
Min
Nom
Max
Units
RZQ/6 = (240Ω ±1%)/6
39.6
40
40.4
Ω
59.4
60
60.6
Ω
Driver
VOUT
Min
Nom
Max
Units
40Ω pull-down
0.2 × VDDQ
24
40
44
Ω
0.5 × VDDQ
36
40
44
Ω
RZQ/4 = (240Ω ±1%)/4
40Ω pull-up
60Ω pull-down
60Ω pull-up
0.8 × VDDQ
36
40
56
Ω
0.2 × VDDQ
36
40
56
Ω
0.5 × VDDQ
36
40
44
Ω
0.8 × VDDQ
24
40
44
Ω
0.2 × VDDQ
36
60
66
Ω
0.5 × VDDQ
54
60
66
Ω
0.8 × VDDQ
54
60
84
Ω
0.2 × VDDQ
54
60
84
Ω
0.5 × VDDQ
54
60
66
Ω
0.8 × VDDQ
36
60
66
Ω
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Output Driver Impedance
Output Driver Sensitivity
If either the temperature or the voltage changes after ZQ calibration, then the tolerance
limits listed in Table 19 (page 34) can be expected to widen according to Table 20
(page 35) and Table 21 (page 35).
Table 20: Output Driver Sensitivity Definition
Symbol
Min
Max
Units
RON(PD) @ 0.2 × VDDQ
0.6 - dRONdTH × DT - dRONdVH × DV
1.1 + dRONdTH × DT + dRONdVH × DV
RZQ/(6, 4)
RON(PD) @ 0.5 × VDDQ
0.9 - dRONdTM × DT - dRONdVM × DV 1.1 + dRONdTM × DT + dRONdVM × DV
RZQ/(6, 4)
RON(PD) @ 0.8 × VDDQ
0.9 - dRONdTL × DT - dRONdVL × DV
1.4 + dRONdTL × DT + dRONdVL × D
RZQ/(6, 4)
RON(PU) @ 0.2 × VDDQ
0.9 - dRONdTH × DT - dRONdVH × DV
1.4 + dRONdTH × DT + dRONdVH × DV
RZQ/(6, 4)
RON(PU) @ 0.5 × VDDQ
0.9 - dRONdTM × DT - dRONdVM × DV 1.1 + dRONdTM × DT + dRONdVM × DV
RZQ/(6, 4)
RON(PU) @ 0.8 × VDDQ
0.6 - dRONdTL × DT - dRONdVL × DV
Note:
1.1 + dRONdTL × DT + dRONdVL × DV
RZQ/(6, 4)
1. DT = T - T(@ calibration), DV = VDDQ - VDDQ(@ calibration) or VDD - VDD(@ calibration).
Table 21: Output Driver Voltage and Temperature Sensitivity
Change
Min
Max
Unit
dRONdTM
0
1.5
%/°C
dRONdVM
0
0.15
%/mV
dRONdTL
0
1.5
%/°C
dRONdVL
0
0.15
%/mV
dRONdTH
0
1.5
%/°C
dRONdVH
0
0.15
%/mV
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Output Characteristics and Operating Conditions
Output Characteristics and Operating Conditions
Table 22: Single-Ended Output Driver Characteristics
Note 1 and 2 apply to entire table
Parameter/Condition
Symbol
Min
Max
Units
Notes
Output leakage current; DQ are disabled; Any output ball
0V ≤ VOUT ≤ VDDQ; ODT is disabled; All other balls not under
test = 0V
IOZ
–5
5
µA
Output slew rate: Single-ended; For rising and falling edges,
measures between VOL(AC) = VREF - 0.1 × VDDQ and VOH(AC) =
VREF + 0.1 × VDDQ
SRQSE
2.5
6
V/ns
4, 5
Single-ended DC high-level output voltage
VOH(DC)
0.8 × VDDQ
V
6
Single-ended DC mid-point level output voltage
VOM(DC)
0.5 × VDDQ
V
6
Single-ended DC low-level output voltage
VOL(DC)
0.2 × VDDQ
V
6
Single-ended AC high-level output voltage
VOH(AC)
VTT + 0.1 × VDDQ
V
7, 8, 9
Single-ended AC low-level output voltage
VOL(AC)
VTT - 0.1 × VDDQ
V
7, 8, 9
–10
%
3
Impedance delta between pull-up and pull-down for DQ
and QVLD
Test load for AC timing and output slew rates
Notes:
MMPUPD
10
Output to VTT (VDDQ/2) via 25Ω resistor
9
1. All voltages are referenced to VSS.
2. RZQ is 240Ω (±1%) and is applicable after proper ZQ calibration has been performed at
a stable temperature and voltage.
3. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RON(PU) and RON(PD) at 0.5 × VDDQ:
MMPUPD =
RonPU - RonPD
RonNOM
x 100
4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from
HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are
either all static or switching the opposite direction. For all other DQ signal switching
combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns.
5. See Table 24 (page 40) for output slew rate.
6. See the Driver Pull-Up and Pull-Down Impedance Calculations table for IV curve linearity.
Do not use AC test load.
7. VTT = VDDQ/2
8. See Figure 16 (page 38) for an example of a single-ended output signal.
9. See Figure 18 (page 39) for the test load configuration.
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Output Characteristics and Operating Conditions
Table 23: Differential Output Driver Characteristics
Notes 1 and 2 apply to entire table
Parameter/Condition
Symbol
Min
Max
Units
IOZ
–5
5
µA
Output slew rate: Differential; For rising and falling
edges, measures between VOL,diff(AC) = –0.2 × VDDQ and
VOH,diff(AC) = +0.2 × VDDQ
SRQdiff
5
12
V/ns
5
Output differential cross-point voltage
VOX(AC)
VREF - 150
VREF + 150
mV
6
Differential high-level output voltage
VOH,diff(AC)
V
6
Differential low-level output voltage
VOL,diff(AC)
V
6
%
3
Output leakage current; DQ are disabled; Any output
ball 0V ≤ VOUT ≤ VDDQ; ODT is disabled; All other balls not
under test = 0V
Delta resistance between pull-up and pull-down for
QK/QK#
Test load for AC timing and output slew rates
Notes:
MMPUPD
+0.2 × VDDQ
–0.2 × VDDQ
–10
10
Notes
Output to VTT (VDDQ/2) via 25Ω resistor
4
1. All voltages are referenced to VSS.
2. RZQ is 240Ω (±1%) and is applicable after proper ZQ calibration has been performed at
a stable temperature and voltage.
3. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RON(PU) and RON(PD) at 0.5 x VDDQ:
MMPUPD =
RonPU - RonPD
RonNOM
x 100
4. See Figure 18 (page 39) for the test load configuration.
5. See Table 25 (page 41) for the output slew rate.
6. See Figure 17 (page 39) for an example of a differential output signal.
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Output Characteristics and Operating Conditions
Figure 16: DQ Output Signal
MAX output
VOH(AC)
VOL(AC)
MIN output
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Output Characteristics and Operating Conditions
Figure 17: Differential Output Signal
MAX output
VOH,diff
X
X
VOX(AC)max
X
VOX(AC)min
X
VOL,diff
MIN output
Reference Output Load
The following figure represents the effective reference load of 25Ω used in defining the
relevant device AC timing parameters as well as the output slew rate measurements. It is
not intended to be a precise representation of a particular system environment or a depiction of the actual load presented by a production tester. System designers should use
IBIS or other simulation tools to correlate the timing reference load to a system environment.
Figure 18: Reference Output Load for AC Timing and Output Slew Rate
DUT
VREF
DQ
QKx
QKx#
QVLD
ZQ
VDDQ/2
RTT = 25Ω
VTT = VDDQ/2
Timing reference point
RZQ = 240Ω
VSS
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Slew Rate Definitions for Single-Ended Output Signals
Slew Rate Definitions for Single-Ended Output Signals
The single-ended output driver is summarized in the following table. With the reference
load for timing measurements, the output slew rate for falling and rising edges is defined and measured between V OL(AC) and V OH(AC) for single-ended signals.
Table 24: Single-Ended Output Slew Rate Definition
Single-Ended Output Slew Rates (Linear Signals)
Measured
Output
Edge
From
To
Calculation
DQ and QVLD
Rising
VOL(AC)
VOH(AC)
VOH(AC) - VOL(AC)
VOH(AC)
VOL(AC)
VOH(AC) - VOL(AC)
Falling
ΔTRSE
ΔTFSE
Figure 19: Nominal Slew Rate Definition for Single-Ended Output Signals
ΔTRSE
VOH(AC)
VTT
VOL(AC)
ΔTFSE
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Slew Rate Definitions for Differential Output Signals
Slew Rate Definitions for Differential Output Signals
The differential output driver is summarized in the following table. With the reference
load for timing measurements, the output slew rate for falling and rising edges is defined and measured between V OL(AC) and V OH(AC) for differential signals.
Table 25: Differential Output Slew Rate Definition
Differential Output Slew Rates (Linear Signals)
Measured
Output
Edge
From
To
Calculation
QKx, QKx#
Rising
VOL,diff(AC)
VOH,diff(AC)
VOH,diff(AC)max - VOL,diff(AC)
VOH,diff(AC)
VOL,diff(AC)
VOH,diff(AC) - VOL,diff(AC)
Falling
ΔTRdiff
ΔTFdiff
Figure 20: Nominal Differential Output Slew Rate Definition for QKx, QKx#
ΔTRdiff
VOH,diff(AC)
0
VOL,diff(AC)
ΔTFdiff
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576Mb: x18, x36 RLDRAM 3
Speed Bin Tables
Speed Bin Tables
Table 26: RL3 Speed Bins
-093E
Parameter
Symbol
RL = 3 ; WL = 4
tCK
-093
-107E
Max
Min
-107
Max
Min
125E
Max
Min
-125
Min
Max
Min
Max
Min
Max Units
(avg)
5
5
5
5
Reserved
Reserved
Reserved
Reserved
ns
RL = 4 ; WL = 5
tCK
(avg)
4
5
4
5
4
5
4
5
4
5
5
5
ns
RL = 5 ; WL = 6
tCK
(avg)
3
4.3
3
4.3
3.5
4.3
4
4.3
4
4.3
4
5
ns
RL = 6 ; WL = 7
tCK
(avg)
2.5
3.5
2.5
4
3
3.5
3
4.3
3
4.3
3.5
4.3
ns
RL = 7 ; WL = 8
tCK
(avg)
2.5
3
2.5
3
2.5
3
2.5
3
2.5
3
3
3.5
ns
RL = 8 ; WL = 9
tCK
(avg)
1.875
2.5
1.875
3
2
2.5
2
3
2
3
2.5
3
ns
RL = 9 ; WL = 10
tCK
(avg)
1.875
2
1.875
2
1.875
2
1.875
2
1.875
2
2.33
2.66
ns
RL = 10 ; WL =
11
tCK
(avg)
1.5
2
1.5
2
1.875
2
1.875
2
1.875
2
2
2.33
ns
RL = 11 ; WL =
12
tCK
(avg)
1.5
1.875
1.5
2
1.5
1.875
1.5
2
1.5
2
1.875
2.33
ns
RL = 12 ; WL =
13
tCK
(avg)
1.25
1.5
1.25
1.875
1.5
1.66
1.5
1.875
1.5
2
ns
RL = 13 ; WL =
14
tCK
(avg)
1.25
1.5
1.25
1.5
1.25
1.5
1.25
1.5
1.25
RL = 14 ; WL =
15
tCK
(avg)
1.07
1.25
1.07
1.5
1.25
1.33
1.25
RL = 15 ; WL =
16
tCK
(avg)
1.0
1.25
1.0
1.25
1.07
1.33
1.07
RL = 16 ; WL =
17
tCK
(avg)
0.935
1.25
0.935
1.25
Clock Timing
Reserved
1.875 1.875
1.5
1.5
1.875
ns
1.5
Reserved
1.4
1.66
ns
1.25
Reserved
1.33
1.66
ns
Reserved
Reserved
1.25
1.33
ns
10
10
12
-
ns
Row Cycle Timing
Row Cycle Time
tRC
Note:
8
-
10
-
8
-
-
-
1. The MIN tCK value for a given RL/WL parameter must be used to determine the tRC
mode register setting.
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576Mb: x18, x36 RLDRAM 3
AC Electrical Characteristics
AC Electrical Characteristics
Table 27: AC Electrical Characteristics
Notes 1–7 apply to entire table
RL3–2133
Parameter
Symbol
Min
Max
RL3–1866
Min
RL3–1600
Max
Min
Max
Units
Notes
488
8
488
ns
8
ns
9, 10
Clock Timing
Clock period average:
DLL disable mode
tCK(DLL_DIS
Clock period average: DLL enable mode
tCK(avg)
High pulse width average
tCH(avg)
0.47
0.53
0.47
0.53
0.47
0.53
CK
11
Low pulse width average
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
CK
11
Clock
period
jitter
DLL locked
tJIT(per)
–50
50
–60
60
–70
70
ps
12
DLL locking
tJIT(per),lck
–40
40
–50
50
–60
60
ps
12
)
8
488
See
tCK
8
values in the RL3 Speed Bins table.
Clock absolute period
tCK(abs)
Clock absolute high pulse
width
tCH(abs)
0.43
–
0.43
–
0.43
–
tCK(avg)
13
Clock absolute low pulse
width
tCL(abs)
0.43
–
0.43
–
0.43
–
tCK(avg)
14
Cycle-tocycle
jitter
Cumulative
error across
MIN = tCK(avg),min + tJIT(per),min; MAX =
tCK(avg),max + tJIT(per),max
ps
DLL locked
tJIT(cc)
100
120
140
ps
15
DLL locking
tJIT(cc),lck
80
100
120
ps
15
2 cycles
tERR(2per)
–74
74
–88
88
–103
103
ps
16
3 cycles
tERR(3per)
–87
87
–105
105
–122
122
ps
16
4 cycles
tERR(4per)
–97
97
–117
117
–136
136
ps
16
5 cycles
tERR(5per)
–105
105
–126
126
–147
147
ps
16
6 cycles
tERR(6per)
–111
111
–133
133
–155
155
ps
16
7 cycles
tERR(7per)
–116
116
–139
139
–163
163
ps
16
8 cycles
tERR(8per)
–121
121
–145
145
–169
169
ps
16
9 cycles
tERR(9per)
–125
125
–150
150
–175
175
ps
16
10 cycles
tERR(10per)
–128
128
–154
154
–180
180
ps
16
11 cycles
tERR(11per)
–132
132
–158
158
–184
184
ps
16
12 cycles
tERR(12per)
–134
134
–161
161
–188
188
ps
16
n = 13, 14 ... 49,
50 cycles
tERR(nper)
tJIT(per),min
ps
16
Base
(specification)
tDS(AC150)
tERR(nper),min
tERR(nper),max
= [1 + 0.68LN(n)] ×
= [1 + 0.68LN(n)] × tJIT(per),max
DQ Input Timing
Data setup
time to DK,
DK#
VREF
@ 1 V/ns
–30
–
–15
–
10
–
ps
17, 18
120
–
135
–
160
–
ps
18, 19
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AC Electrical Characteristics
Table 27: AC Electrical Characteristics (Continued)
Notes 1–7 apply to entire table
RL3–2133
Parameter
Data hold
time from
DK, DK#
Base
(specification)
RL3–1866
RL3–1600
Symbol
Min
Max
Min
Max
Min
Max
Units
Notes
tDH(DC100)
5
–
20
–
45
–
ps
17, 18
105
–
120
–
145
–
ps
280
–
320
–
360
–
ps
VREF
@ 1 V/ns
Minimum data pulse width
tDIPW
QK, QK# edge to output data
edge within byte group
tQKQ
–
75
–
85
–
100
ps
QK, QK# edge to any output
data edge within specific data
word grouping (only for x36)
tQKQ02,
–
125
–
135
–
150
ps
22
20
DQ Output Timing
x
tQKQ13
DQ output hold time from
QK, QK#
tQH
0.38
–
0.38
–
0.38
–
tCK(avg)
23
DQ Low-Z time from CK, CK#
tLZ
–360
180
–390
195
–450
225
ps
24, 26
DQ High-Z time from CK, CK#
tHZ
–
180
–
195
–
225
ps
24, 26
DK (rising), DK# (falling) edge
to/from CK (rising), CK# (falling) edge
tCKDK
–0.27
0.27
–0.27
0.27
–0.27
0.27
CK
29
DK, DK# differential input
HIGH width
tDKH
0.45
0.55
0.45
0.55
0.45
0.55
CK
DK, DK# differential input
LOW width
tDKL
0.45
0.55
0.45
0.55
0.45
0.55
CK
QK (rising), QK# (falling) edge
to CK (rising), CK# (falling)
edge
tCKQK
–135
135
–140
140
–160
160
ps
26
- 5%
tCK
+ 5%
tCK
- 5%
tCK
+ 5%
tCK
- 5%
tCK
+ 5%
tCK
QK (rising), QK# (falling) edge
to CK (rising), CK# (falling)
edge with DLL disabled
tCKQK
1
10
1
10
1
10
ns
27
Input and Output Strobe Timing
DLL_DIS
QK, QK# differential output
HIGH time
tQKH
0.4
–
0.4
–
0.4
–
CK
23
QK, QK# differential output
LOW time
tQKL
0.4
–
0.4
–
0.4
–
CK
23
tQKVLD
–
125
–
135
–
150
ps
25
QK (falling), QK# (rising) edge
to QVLD edge
Command and Address Timing
CTRL, CMD,
ADDR, setup to
CK,CK#
Base
(specification)
VREF
@ 1 V/ns
tIS(AC150)
85
–
120
–
170
–
ps
28, 30
235
–
270
–
320
–
ps
19, 30
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576Mb: x18, x36 RLDRAM 3
AC Electrical Characteristics
Table 27: AC Electrical Characteristics (Continued)
Notes 1–7 apply to entire table
RL3–2133
RL3–1866
RL3–1600
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Units
Notes
CTRL, CMD,
ADDR,
hold from
CK,CK#
tIH(DC100)
65
–
100
–
120
–
ps
28, 30
165
–
200
–
220
–
ps
19, 30
470
–
535
–
560
–
ps
20
ns
21
Base
(specification)
VREF
@ 1 V/ns
tIPW
Minimum CTRL, CMD, ADDR
pulse width
Row cycle time
tRC
See minimum tRC values in the RL3 Speed Bins table.
Refresh rate
tREF
64
–
Sixteen-bank access window
tSAW
8
–
8
–
8
–
ns
Multibank access delay
tMMD
2
–
2
–
2
–
CK
33
WRITE-to-READ to same address
tWTR
WL +
BL/2
–
WL +
BL/2
–
WL +
BL/2
–
ns
32
Mode register set cycle time
to any command
tMRSC
12
–
12
–
12
–
CK
READ training register minimum READ time
tRTRS
2
–
2
–
2
–
CK
READ training register burst
end to mode register set for
training register exit
tRTRE
1
–
1
–
1
–
CK
–
CK
64
–
64
–
ms
Calibration Timing
ZQCL: Long POWER-UP and
calibration RESET operation
time
Normal operation
ZQCS: Short calibration time
tZQinit
512
–
512
–
512
tZQoper
256
–
256
–
256
–
CK
tZQcs
64
–
64
–
64
–
CK
Initialization and Reset Timing
Begin power-supply ramp to
power supplies stable
tV
DDPR
–
200
–
200
–
200
ms
RESET# LOW to power supplies stable
tRPS
–
200
–
200
–
200
ms
RESET# LOW to I/O and RTT
High-Z
tIOz
–
20
–
20
–
20
ns
Notes:
31
1. Parameters are applicable with 0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V, +2.38V ≤ VEXT ≤
+2.63V, +1.14V ≤ VDDQ ≤ 1.26V.
2. All voltages are referenced to VSS.
3. The unit tCK(avg) represents the actual tCK(avg) of the input clock under operation. The
unit CK represents one clock cycle of the input clock, counting the actual clock edges.
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the
AC/DC trip points and CK,CK# and DKx, DKx# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
and 2 V/ns for differential inputs in the range between VIL(AC) and VIH(AC).
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AC Electrical Characteristics
5. All timings that use time-based values (ns, µs, ms) should use t CK(avg) to determine the
correct number of clocks. In the case of noninteger results, all minimum limits should be
rounded up to the nearest whole integer, and all maximum limits should be rounded
down to the nearest whole integer
.
6. The term “strobe” refers to the DK and DK# or QK and QK# differential crossing point
when DK and QK, respectively, is the rising edge. Clock, or CK, refers to the CK and CK#
differential crossing point when CK is the rising edge.
7. The output load defined in Figure 18 (page 39) is used for all AC timing and slew rates.
The actual test load may be different. The output signal voltage reference point is
VDDQ /2 for single-ended signals and the crossing point for differential signals.
8. When operating in DLL disable mode, ISSI does not warrant compliance with normal
mode timings or functionality.
9. The clock’s t CK(avg) is the average clock over any 200 consecutive clocks and
t CK(avg),min is the smallest clock rate allowed, with the exception of a deviation due to
clock jitter. Input clock jitter is allowed provided it does not exceed values specified and
must be of a random Gaussian distribution in nature.
10. Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of t CK(avg) as a long-term jitter component; however, the spread spectrum may not use a clock rate below t CK(avg),min.
11. The clock’s t CH(avg) and t CL(avg) are the average half-clock period over any 200 consecutive clocks and is the smallest clock half-period allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.
12. The period jitter, t JIT(per), is the maximum deviation in the clock period from the average or nominal clock. It is allowed in either the positive or negative direction.
13. t CH(abs) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge.
14. t CL(abs) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge.
15. The cycle-to-cyle jitter, t JIT(cc), is the amount the clock period can deviate from one cycle
to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.
16. The cumulative jitter error, t ERR(nper), where n is the number of clocks between 2 and
50, is the amount of clock time allowed to accumulate consecutively away from the
average clock over n number of clock cycles.
17. t DS(base) and t DH(base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns differential DK, DK# slew rate.
18. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DK, DK#) crossing.
19. The setup and hold times are listed converting the base specification values (to which
derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate
of 1 V/ns, are for reference only.
20. Pulse width of an input signal is defined as the width between the first crossing of
VREF(DC) and the consecutive crossing of VREF(DC)
.
21. Bits MR0[3:0] select the number of clock cycles required to satisfy the minimum t RC value. Minimum t RC value must be divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge that the subsequent command can
be issued to the bank.
22. t QKQ02 defines the skew between QK0 and DQ[26:18] and between QK2 and DQ[8:0].
t QKQ13 defines the skew between QK1 and DQ[35:27] and between QK3 and DQ[17:9].
23. When the device is operated with input clock jitter, this parameter needs to be derated
by the actual t JIT(per) (the larger of t JIT(per),min or t JIT(per),max of the input clock; output deratings are relative to the SDRAM input clock).
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AC Electrical Characteristics
24. Single-ended signal parameter.
25. For x36 device this specification references the skew between the falling edge of QK0
and QK1 to QVLD0 and the falling edge of QK2 and QK3 to QVLD1.
26. The DRAM output timing is aligned to the nominal or average clock. The following output parameters must be derated by the actual jitter error when input clock jitter is
present, even when within specification. This results in each parameter becoming larger.
The following parameters are required to be derated by subtracting tERR(10per),max:
tCKQK (MIN), and tLZ (MIN). The following parameters are required to be derated by
subtracting tERR(10per),min: tCKQK (MAX), tHZ (MAX), and tLZ (MAX).
27. The tDQSCKdll_dis parameter begins RL - 1 cycles after the READ command.
28. tIS(base) and tIH(base) values are for a single-ended 1 V/ns control/command/address
slew rate and 2 V/ns CK, CK# differential slew rate.
29. These parameters are measured from the input data strobe signal (DK/DK#) crossing to
its respective clock signal crossing (CK/CK#). The specification values are not affected by
the amount of clock jitter applied as they are relative to the clock signal crossing. These
parameters should be met whether or not clock jitter is present.
30. These parameters are measured from a command/address signal transition edge to its
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether or not clock jitter is present.
31. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in excessive current, depending on bus activity.
32. If tWTR is violated, the data just written will not be read out when a READ command is
issued to the same address. Whatever data was previously written to the address will be
output with the READ command.
33. This specification is defined as any bank command (READ, WRITE, AREF) to a multi-bank
command or a multi-bank command to any bank command. This specification only applies to quad bank WRITE, 3-bank AREF and 4-bank AREF commands. Dual bank WRITE,
2-bank AREF, and all single bank access commands are not bound by this specification.
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576Mb: x18, x36 RLDRAM 3
Temperature and Thermal Impedance Characteristics
Temperature and Thermal Impedance Characteristics
It is imperative that the device’s temperature specifications be maintained in order to
ensure that the junction temperature is in the proper operating range to meet data
sheet specifications. An important way to maintain the proper junction temperature is
to use the device’s thermal impedances correctly. Thermal impedances are listed for the
available packages.
Incorrectly using thermal impedances can produce significant errors.
The device’s safe junction temperature range can be maintained when the TC specification is not exceeded. In applications where the device’s ambient temperature is too
high, use of forced air and/or heat sinks may be required in order to meet the case temperature specifications.
Table 28: Temperature Limits
Parameter
Storage temperature
Reliability junction temperature
Commercial
Symbol
Min
Max
Units
Notes
TSTG
-55
150
°C
1
TJ(REL)
-
110
°C
2
-
110
°C
2
Industrial
Operating junction temperature
Commercial
TJ(OP)
Industrial
Operating case temperature
Commercial
TC
Industrial
Notes:
0
100
°C
3
-40
100
°C
3
0
95
°C
4, 5
-40
95
°C
4, 5
1. MAX storage case temperature; TSTG is measured in the center of the package (see Figure 21 (page 49)). This case temperature limit is allowed to be exceeded briefly during
package reflow.
2. Temperatures greater than 110°C may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at or above this is not implied.
Exposure to absolute maximum rating conditions for extended periods may adversely
affect the reliability of the part.
3. Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow.
4. MAX operating case temperature; TC is measured in the center of the package (see Figure 21 (page 49)).
5. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
Table 29: Thermal Impedance
θ JA (°C/W)
Airflow = 0m/s
θ JA (°C/W)
Airflow = 1m/s
θ JA (°C/W)
Airflow = 2m/s
θ JB (°C/W)
θ JC (°C/W)
2-layer
39.3
28.8
25.2
16.3
2.0
4-layer
22.0
17.2
15.9
10.3
Package Substrate
FBGA
Note:
1. Thermal impedance data is based on a number of samples from multiple lots, and
should be viewed as a typical number.
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Temperature and Thermal Impedance Characteristics
Figure 21: Example Temperature Test Point Location
Test point
13.5mm
6.75mm
6.75mm
13.5mm
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576Mb: x18, x36 RLDRAM 3
Command and Address Setup, Hold, and Derating
Command and Address Setup, Hold, and Derating
The total tIS (setup time) and tIH (hold time) required is calculated by adding the data
sheet tIS (base) and tIH (base) values (see Table 30 (page 50); values come from Table 27 (page 43)) to the ΔtIS and ΔtIH derating values (see Table 31 (page 51)), respectively. Example: tIS (total setup time) = tIS (base) + ΔtIS. For a valid transition, the input
signal must remain above/below V IH(AC)/VIL(AC) for some time tVAC (see Table 32
(page 51)).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V IH(AC)/VIL(AC) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach V IH(AC)/
VIL(AC). For slew rates which fall between the values listed in Table 31 (page 51) and
Table 32 (page 51) for Valid Transition, the derating values may be obtained by linear
interpolation.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup (tIS) nominal slew rate
for a falling signal is defined as the slew rate between the last crossing of V REF(DC) and
the first crossing of V IL(AC)max. If the actual signal is always earlier than the nominal slew
rate line between the shaded V REF(DC)-to-AC region, use the nominal slew rate for derating value (see Figure 22 (page 52)). If the actual signal is later than the nominal slew
rate line anywhere between the shaded V REF(DC)-to-AC region, the slew rate of a tangent
line to the actual signal from the AC level to the DC level is used for derating value (see
Figure 24 (page 54)).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tIH) nominal slew rate
for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min and
the first crossing of V REF(DC). If the actual signal is always later than the nominal slew
rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for derating value (see Figure 23 (page 53)). If the actual signal is earlier than the nominal slew
rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a tangent
line to the actual signal from the DC level to the V REF(DC) level is used for derating value
(see Figure 25 (page 55)).
Table 30: Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based
Symbol
RL3-2133
RL3-1866
RL3-1600
Units
Reference
tIS(base),AC150
85
120
170
ps
VIH(AC)/VIL(AC)
tIH(base),DC100
65
100
120
ps
VIH(DC)/VIL(DC)
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Command and Address Setup, Hold, and Derating
Table 31: Derating Values for tIS/tIH – AC150/DC100-Based
ΔtIS, ΔtIH Derating (ps) - AC/DC-Based AC 150 Threshold: VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV
CK, CK# Differential Slew Rate
CMD/ADDR
Slew Rate
(V/ns)
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
2.0
75
50
75
50
75
50
83
58
91
66
99
74
107
84
115
100
1.5
50
34
50
34
50
34
58
42
66
50
74
58
82
68
90
84
1.0
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
0
–4
0
–4
0
–4
8
4
16
12
24
20
32
30
40
46
0.8
0
–10
0
–10
0
–10
8
–2
16
6
24
14
32
24
40
40
0.7
0
–16
0
–16
0
–16
8
–8
16
0
24
8
32
18
40
34
0.6
–1
–26
–1
–26
–1
–26
7
–18
15
–10
23
–2
31
8
39
24
0.5
–10
–40
–10
–40
–10
–40
–2
–32
6
–24
14
–16
22
–6
30
10
0.4
–25
–0
–25
–60
–25
–60
–17
–52
–9
–44
–1
–36
7
–26
15
–10
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
Table 32: Minimum Required Time tVAC Above VIH(AC) (or Below VIL(AC)) for Valid Transition
Slew Rate (V/ns)
tVAC
(ps)
>2.0
175
2.0
170
1.5
167
1.0
163
0.9
162
0.8
161
0.7
159
0.6
155
0.5
150
<0.5
150
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Command and Address Setup, Hold, and Derating
Figure 22: Nominal Slew Rate and tVAC for tIS (Command and Address - Clock)
tIS
tIS
tIH
tIH
CK
CK#
DK#
DK
VDDQ
tVAC
VIH(AC)min
VREF to AC
region
VIH(DC)min
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC)max
VREF to AC
region
VIL(AC)max
tVAC
VSS
DTR
DTF
Setup slew rate
falling signal =
Note:
VREF(DC) - VIL(AC)max
DTF
Setup slew rate
=
rising signal
VIH(AC)min - VREF(DC)
DTR
1. Both the clock and the data strobe are drawn on different time scales.
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Command and Address Setup, Hold, and Derating
Figure 23: Nominal Slew Rate for tIH (Command and Address - Clock)
tIS
tIS
tIH
tIH
CK
CK#
DK#
DK
VDDQ
VIH(AC)min
VIH(DC)min
Nominal
slew rate
DC to VREF
region
VREF(DC)
DC to VREF
region
Nominal
slew rate
VIL(DC)max
VIL(AC)max
VSS
DTR
Hold slew rate
rising signal =
Note:
VREF(DC) - VIL(DC)max
DTR
Hold slew rate
falling signal =
DTF
VIH(DC)min - VREF(DC)
DTF
1. Both the clock and the data strobe are drawn on different time scales.
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Command and Address Setup, Hold, and Derating
Figure 24: Tangent Line for tIS (Command and Address - Clock)
tIS
tIS
tIH
tIH
CK
CK#
DK#
DK
VDDQ
tVAC
Nominal
line
VIH(AC)min
VREF to AC
region
VIH(DC)min
Tangent
line
VREF(DC)
Tangent
line
VIL(DC)max
VREF to AC
region
VIL(AC)max
Nominal
line
tVAC
DTR
VSS
DTF
Setup slew rate
rising signal =
Setup slew rate
falling signal =
Note:
Tangent line [V IH(DC)min - VREF(DC)]
DTR
Tangent line[ V REF(DC) - VIL(AC)max]
DTF
1. Both the clock and the data strobe are drawn on different time scales.
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Command and Address Setup, Hold, and Derating
Figure 25: Tangent Line for tIH (Command and Address - Clock)
tIS
tIH
tIS
tIH
CK
CK#
DK#
DK
VDDQ
VIH(AC)min
Nominal
line
VIH(DC)min
DC to VREF
region
Tangen t
line
VREF(DC)
DC to VREF
region
Tangen t
line
Nominal
line
VIL(DC)max
VIL(AC)max
VSS
DTF
DTR
Hold slew rate
rising signal =
Hold slew rate
falling signal =
Note:
Tangent line [V REF(DC) - VIL(DC)max]
DTR
Tangent line [V IH(DC)min - VREF(DC)]
DTF
1. Both the clock and the data strobe are drawn on different time scales.
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Data Setup, Hold, and Derating
Data Setup, Hold, and Derating
The total tDS (setup time) and tDH (hold time) required is calculated by adding the data
sheet tDS (base) and tDH (base) values (see the table below; values come from Table 27
(page 43)) to the ΔtDS and ΔtDH derating values (see Table 34 (page 57)), respectively.
Example: tDS (total setup time) = tDS (base) + ΔtDS. For a valid transition, the input signal has to remain above/below V IH(AC)/VIL(AC) for some time tVAC (see Table 35
(page 57)).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V IH(AC)/VIL(AC)) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach V IH/
VIL(AC). For slew rates which fall between the values listed in Table 34 (page 57) and
Table 35 (page 57), the derating values may obtained by linear interpolation.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup (tDS) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of V REF(DC)
and the first crossing of V IL(AC)max. If the actual signal is always earlier than the nominal
slew rate line between the shaded V REF(DC)-to-AC region, use the nominal slew rate for
derating value (see Figure 26 (page 58)). If the actual signal is later than the nominal
slew rate line anywhere between the shaded V REF(DC)-to-AC region, the slew rate of a
tangent line to the actual signal from the AC level to the DC level is used for derating
value (see Figure 28 (page 60)).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tDH) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min
and the first crossing of V REF(DC). If the actual signal is always later than the nominal
slew rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for
derating value (see Figure 27 (page 59)). If the actual signal is earlier than the nominal
slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a
tangent line to the actual signal from the DC-to-VREF(DC) region is used for derating value (see Figure 29 (page 61)).
Table 33: Data Setup and Hold Values at 1 V/ns (DKx, DKx# at 2V/ns) – AC/DC-Based
Symbol
RL3-2133
RL3-1866
RL3-1600
Units
Reference
tDS(base),AC150
–30
-15
10
ps
VIH(AC)/VIL(AC)
tDH(base),DC100
5
20
45
ps
VIH(DC)/VIL(DC)
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Data Setup, Hold, and Derating
Table 34: Derating Values for tDS/tDH – AC150/DC100-Based
Empty cells indicate slew rate combinations not supported
ΔtDS, ΔtDH Derating (ps) - AC/DC-Based
DKx, DKx# Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
DQ Slew
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Rate (V/ns) Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS ΔtDH
2.0
75
50
75
50
75
50
1.5
50
34
50
34
50
34
58
42
1.0
0
0
0
0
0
0
8
8
16
16
0
–4
0
–4
8
4
16
12
24
20
0
–10
8
–2
16
6
24
14
32
24
8
–8
16
0
24
8
32
18
40
34
15
–10
23
–2
31
8
39
24
14
–16
22
–6
30
10
7
–26
15
–10
0.9
0.8
0.7
0.6
0.5
0.4
Table 35: Minimum Required Time tVAC Above VIH(AC) (or Below VIL(AC)) for Valid Transition
Slew Rate (V/ns)
tVAC
(ps)
>2.0
175
2.0
170
1.5
167
1.0
163
0.9
162
0.8
161
0.7
159
0.6
155
0.5
150
<0.5
150
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Data Setup, Hold, and Derating
Figure 26: Nominal Slew Rate and tVAC for tDS (DQ - Strobe)
CK
CK#
DK#
DK
tDH
tDS
tDS
tDH
VDDQ
tVAC
VIH(AC)min
VREF to AC
region
VIH(DC)min
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC)max
VREF to AC
region
VIL(AC)max
tVAC
VSS
DTF
Setup slew rate
=
falling signal
Note:
DTR
VREF(DC) - VIL(AC)max
DTF
Setup slew rate
=
rising signal
VIH(AC)min - VREF(DC)
DTR
1. Both the clock and the strobe are drawn on different time scales.
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Data Setup, Hold, and Derating
Figure 27: Nominal Slew Rate for tDH (DQ - Strobe)
CK
CK#
DK#
DK
tDS
tDH
tDS
tDH
VDDQ
VIH(AC)min
VIH(DC)min
Nominal
slew rate
DC to VREF
region
VREF(DC)
Nominal
slew rate
DC to VREF
region
VIL(DC)max
VIL(AC)max
VSS
DTR
Hold slew rate
=
rising signal
Note:
VREF(DC) - VIL(DC)max
DTR
Hold slew rate
falling signal =
DTF
VIH(DC)min - VREF(DC)
DTF
1. Both the clock and the strobe are drawn on different time scales.
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Data Setup, Hold, and Derating
Figure 28: Tangent Line for tDS (DQ - Strobe)
CK
CK#
DK#
DK
tDS
tDH
tDS
tDH
VDDQ
Nominal
line
tVAC
VIH(AC)min
VREF to AC
region
VIH(DC)min
Tangent
line
VREF(DC)
Tangent
line
VIL(DC)max
VREF to AC
region
VIL(AC)max
Nominal
line
DTF
Note:
DTR
tVAC
VSS
Setup slew rate
rising signal =
Tangent line [V IH(AC)min - VREF(DC)]
Setup slew rate
falling signal =
Tangent line [V REF(DC) - VIL(AC)max ]
DTR
DTF
1. Both the clock and the strobe are drawn on different time scales.
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Data Setup, Hold, and Derating
Figure 29: Tangent Line for tDH (DQ - Strobe)
CK
CK#
DK#
DK
tDS
tDH
tDS
tDH
VDDQ
VIH(AC)min
Nominal
line
VIH(DC)min
DC to VREF
region
Tangent
line
VREF(DC)
DC to VREF
region
Tangent
line
Nominal
line
VIL(DC)max
VIL(AC)max
VSS
DTR
Note:
DTF
Hold slew rate
rising signal =
Tangent line [V REF(DC) - VIL(DC)max]
Hold slew rate
falling signal =
Tangent line [V IH(DC)min - VREF(DC)]
DTR
DTF
1. Both the clock and the strobe are drawn on different time scales.
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Commands
Commands
The following table provides descriptions of the valid commands of the RLDRAM 3 device. All command and address inputs must meet setup and hold times with respect to
the rising edge of CK.
Table 36: Command Descriptions
Command
Description
NOP
The NOP command prevents new commands from being executed by the DRAM.
Operations already in progress are not affected by NOP commands. Output values depend on command history.
MRS
Mode registers MR0, MR1, and MR2 are used to define various modes of programmable operations of
the DRAM. A mode register is programmed via the MODE REGISTER SET (MRS) command during initialization and retains the stored information until it is reprogrammed, RESET# goes LOW, or until the
device loses power. The MRS command can be issued only when all banks are idle, and no bursts are
in progress.
READ
The READ command is used to initiate a burst read access to a bank. The BA[3:0] inputs select a bank,
and the address provided on inputs A[19:0] select a specific location within a bank.
WRITE
The WRITE command is used to initiate a burst write access to a bank (or banks). MRS bits MR2[4:3]
select single, dual, or quad bank WRITE protocol. The BA[x:0] inputs select the bank(s) (x = 3, 2, or 1
for single, dual, or quad bank WRITE, respectively). The address provided on inputs A[19:0] select a
specific location within the bank. Input data appearing on the DQ is written to the memory array
subject to the DM input logic level appearing coincident with the data. If the DM signal is registered
LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored (that is, this part of the data word will not be written).
AREF
The AREF command is used during normal operation of the RLDRAM 3 to refresh the memory content of a bank. There are two methods by which the RLDRAM 3 can be refreshed, both of which are
selected within the mode register. The first method, bank address-controlled AREF, is identical to the
method used in RLDRAM2. The second method, multibank AREF, enables refreshing of up to four
banks simultaneously. More info is available in the Auto Refresh section. For both methods, the command is nonpersistent, so it must be issued each time a refresh is required.
Table 37: Command Table
Note 1 applies to the entire table
Operation
Code
CS#
WE#
REF#
A[19:0]
BA[3:0]
Notes
NOP
NOP
H
X
X
X
X
MRS
MRS
L
L
L
OPCODE
OPCODE
READ
READ
L
H
H
A
BA
2
WRITE
WRITE
L
L
H
A
BA
2
AREF
L
H
L
A
BA
3
AUTO REFRESH
Notes:
1. X = “Don’t Care;” H = logic HIGH; L = logic LOW; A = valid address; BA = valid bank address; OPCODE = mode register bits
2. Address width varies with burst length and configuration; see the Address Widths of
Different Burst Lengths table for more information.
3. Bank address signals (BA) are used only during bank address-controlled AREF; Address
signals (A) are used only during multibank AREF.
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MODE REGISTER SET (MRS) Command
MODE REGISTER SET (MRS) Command
The mode registers, MR0, MR1, and MR2, store the data for controlling the operating
modes of the memory. The MODE REGISTER SET (MRS) command programs the
RLDRAM 3 operating modes and I/O options. During an MRS command, the address
inputs are sampled and stored in the mode registers. The BA[1:0] signals select between
mode registers 0–2 (MR0–MR2). After the MRS command is issued, each mode register
retains the stored information until it is reprogrammed, until RESET# goes LOW, or until the device loses power.
After issuing a valid MRS command, tMRSC must be met before any command can be
issued to the RLDRAM 3. The MRS command can be issued only when all banks are
idle, and no bursts are in progress.
Figure 30: MRS Command Protocol
CK#
CK
CS#
WE#
REF#
Address
OPCODE
Bank
Address
OPCODE
Don’t Care
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Mode Register 0 (MR0)
Mode Register 0 (MR0)
Figure 31: MR0 Definition for Non-Multiplexed Address Mode
BA3 BA2 BA1 BA0 A17 ... A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
21 20 19 18
01 01 MRS
9 8 7 6 5 4
AM DLL Data Latency
17-10
Reserved
3
2
1
0
Address Bus
Mode Register (Mx)
tRC_MRS
M7 M6 M5 M4 Data Latency (RL & WL)
M19 M18
0
0
Mode Register Definition
M8
DLL Enable
0
Enable
1
Disable
Mode Register 0 (MR0)
0
1
Mode Register 1 (MR1)
1
0
Mode Register 2 (MR2)
1
1
Reserved
Notes:
M9
Address MUX
0
Non-multiplexed
1
Multiplexed
0
0
0
0
RL = 3 ; WL = 4
0
0
0
1
RL = 4 ; WL = 5
0
0
1
0
RL = 5 ; WL = 6
0
0
0
0
22,3
0
0
1
1
RL = 6 ; WL = 7
0
0
0
1
32
0
1
0
0
RL = 7 ; WL = 8
0
0
1
0
42
0
1
0
1
RL = 8 ; WL = 9
0
0
1
1
5
0
1
1
0
RL = 9 ; WL = 10
0
1
0
0
6
0
1
1
0
1
0
1
0
RL = 10 ; WL = 11
RL = 11 ; WL = 12
0
1
0
1
7
1
0
0
1
0
1
1
0
8
RL = 12 ; WL = 13
1
0
1
0
RL = 13 ; WL = 14
0
1
1
0
1
0
1
0
1
0
1
1
10
RL = 14 ; WL = 15
1
0
0
1
1
1
0
0
RL = 15 ; WL = 16
1
0
1
0
11
12
1
1
0
1
RL = 16 ; WL = 17
1
0
1
1
Reserved
1
1
1
0
Reserved
1
1
0
0
Reserved
1
1
1
1
Reserved
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
M3 M2 M1 M0
t RC_MRS
9
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
2. BL8 not allowed.
3. BL4 not allowed.
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Mode Register 0 (MR0)
tRC
Bits MR0[3:0] select the number of clock cycles required to satisfy the tRC specifications.
After a READ, WRITE, or AREF command is issued to a bank, a subsequent READ,
WRITE, or AREF cannot be issued to the same bank until tRC has been satisfied. The
correct value (tRC_MRS) to program into MR0[3:0] is shown in the table below.
Table 38: tRC_MRS MR0[3:0] values
Parameter
-093E
-093
RL=3; WL=4
tRC_MRS
2
2
-107E
-107
-125E
-125
RL=4; WL=5
tRC_MRS
2
3
2
3
3
3
RL=5; WL=6
tRC_MRS
3
4
3
3
3
3
RL=6; WL=7
tRC_MRS
4
4
3
4
4
4
RL=7; WL=8
tRC_MRS
4
4
4
4
4
4
RL=8; WL=9
tRC_MRS
5
6
4
5
5
5
RL=9; WL=10
tRC_MRS
5
6
5
6
6
6
RL=10; WL=11
tRC_MRS
6
7
5
6
6
6
RL=11; WL=12
tRC_MRS
6
7
6
7
7
7
RL=12; WL=13
tRC_MRS
7
8
6
7
7
7
RL=13; WL=14
tRC_MRS
7
8
7
8
8
8
RL=14; WL=15
tRC_MRS
8
10
7
8
Reserved
9
RL=15; WL=16
tRC_MRS
8
10
8
10
Reserved
10
RL=16; WL=17
tRC_MRS
9
11
Reserved Reserved Reserved
10
Reserved Reserved Reserved Reserved
Data Latency
The data latency register uses MR0[7:4] to set both the READ and WRITE latency (RL
and WL). The valid operating frequencies for each data latency register setting can be
found in Table 27 (page 43).
DLL Enable/Disable
Through the programming of MR0[8], the DLL can be enabled or disabled.
The DLL must be enabled for normal operation. The DLL must be enabled during the
initialization routine and upon returning to normal operation after having been disabled for the purpose of debugging or evaluation. To operate the RLDRAM with the DLL
disabled, the tRC MRS setting must equal the read latency (RL) setting. Enabling the
DLL should always be followed by resetting the DLL using the appropriate MR1 command.
Address Multiplexing
Although the RLDRAM has the ability to operate similar to an SRAM interface by accepting the entire address in one clock (non-multiplexed, or broadside addressing),
MR0[9] can be set to 1 so that it functions with multiplexed addressing, similar to a traditional DRAM. In multiplexed address mode, the address is provided to the RLDRAM
in two parts that are latched into the memory with two consecutive rising edges of CK.
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576Mb: x18, x36 RLDRAM 3
Mode Register 0 (MR0)
When in multiplexed address mode, only 11 address balls are required to control the
RLDRAM, as opposed to 20 address balls when in non-multiplexed address mode. The
data bus efficiency in continuous burst mode is only affected when using the BL = 2 setting because the device requires two clocks to read and write data. During multiplexed
mode, the bank addresses as well as WRITE and READ commands are issued during the
first address part, Ax. The Address Mapping in Multiplexed Address Mode table shows
the addresses needed for both the first and second rising clock edges (Ax and Ay, respectively).
After MR0[9] is set HIGH, READ, WRITE, and MRS commands follow the format described in the Command Description in Multiplexed Address Mode figure. Refer to Multiplexed Address Mode for further information on operation with multiplexed addressing.
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576Mb: x18, x36 RLDRAM 3
Mode Register 1 (MR1)
Mode Register 1 (MR1)
Figure 32: MR1 Definition for Non-Multiplexed Address Mode
BA3 BA2 BA1 BA0 A17 ... A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
21 20 19 18 17-11
01 MRS Reserved
01
M19 M18
Mode Register Definition
10 9 8 7 6 5
BL Ref ZQe ZQ DLL
4 3
ODT
M5 DLL Reset
M10 M9 Burst Length
2
1
0
Mode Register (Mx)
Drive
M4 M3 M2
ODT
M1 M0 Output Drive
0
0
2
0
No
0
0
0
Off
0
0
RZQ/6 (40W)
Mode Register 1 (MR1)
0
1
4
1
Yes
0
0
1
RZQ/6 (40W)
0
1
RZQ/4 (60W)
0
Mode Register 2 (MR2)
1
0
8
0
1
0
RZQ/4 (60W)
1
0
Reserved
1
Reserved
1
Reserved
RZQ/2 (120W)
1
1
Reserved
0
0
Mode Register 0 (MR0)
0
1
1
1
Notes:
1
M6 ZQ Calibration Selection
0
1
1
0
Short ZQ Calibration
1
0
0
Reserved
1
Long ZQ Calibration
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M8
AREF P rotocol
M7
0
Bank Address Control
0
Disabled - Default
1
Multibank
1
Enable
ZQ Calibration Enable
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
2. BL8 not available in x36.
Output Drive Impedance
The RLDRAM 3 uses programmable impedance output buffers, which enable the user
to match the driver impedance to the system. MR1[0] and MR1[1] are used to select 40Ω
or 60Ω output impedance, but the device powers up with an output impedance of 40Ω.
The drivers have symmetrical output impedance. To calibrate the impedance a 240Ω
±1% external precision resistor (RZQ) is connected between the ZQ ball and V SSQ.
The output impedance is calibrated during initialization through the ZQCL mode register setting. Subsequent periodic calibrations (ZQCS) may be performed to compensate
for shifts in output impedance due to changes in temperature and voltage. More detailed information on calibration can be found in the ZQ Calibration section.
DQ On-Die Termination (ODT)
MR1[4:2] are used to select the value of the on-die termination (ODT) for the DQ, DKx
and DM balls. When enabled, ODT terminates these balls to V DDQ/2. The RLDRAM 3
device supports 40Ω, 60Ω, or 120Ω ODT. The ODT function is dynamically switched off
when a DQ begins to drive after a READ command has been issued. Similarly, ODT is
designed to switch on at the DQs after the RLDRAM has issued the last piece of data.
The DM and DKx balls are always terminated after ODT is enabled.
DLL Reset
Programming MR1[5] to 1 activates the DLL RESET function. MR1[5] is self-clearing,
meaning it returns to a value of 0 after the DLL RESET function has been initiated.
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576Mb: x18, x36 RLDRAM 3
Mode Register 1 (MR1)
Whenever the DLL RESET function is initiated, CK/CK# must be held stable for 512
clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization
to occur may cause output timing specifications, such as tCKQK, to be invalid .
ZQ Calibration
The ZQ CALIBRATION mode register command is used to calibrate the DRAM output
drivers (RON) and ODT values (RTT) over process, voltage, and temperature, provided a
dedicated 240Ω (±1%) external resistor is connected from the DRAM’s RZQ ball to V SSQ.
Bit MR1[6] selects between ZQ calibration long (ZQCL) and ZQ calibration short
(ZQCS), each of which are described in detail below. When bit MR1[7] is set HIGH, it
enables the calibration sequence. Upon completion of the ZQ calibration sequence,
MR1[7] automatically resets LOW.
The RLDRAM 3 needs a longer time to calibrate RON and ODT at power-up initialization
and a relatively shorter time to perform periodic calibrations. An example of ZQ calibration timing is shown below.
All banks must have tRC met before ZQCL or ZQCS mode register settings can be issued
to the DRAM. No other activities (other than loading another ZQCL or ZQCS mode register setting may be issued to another DRAM) can be performed on the DRAM channel
by the controller for the duration of tZQinit or tZQoper. The quiet time on the DRAM
channel helps accurately calibrate RON and ODT. After DRAM calibration is achieved,
the DRAM will disable the ZQ ball’s current consumption path to reduce power.
ZQ CALIBRATION mode register settings can be loaded in parallel to DLL reset and
locking time.
In systems that share the ZQ resistor between devices, the controller must not allow
overlap of tZQinit, tZQoper, or tZQcs between devices.
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576Mb: x18, x36 RLDRAM 3
Mode Register 1 (MR1)
Figure 33: ZQ Calibration Timing (ZQCL and ZQCS)
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
Command
MRS
NOP
NOP
NOP
Valid
Valid
MRS
NOP
NOP
NOP
Valid
Address
ZQCL
Valid
Valid
ZQCS
CK#
CK
DQ
Valid
Activities
Activities
Activities
Activities
QK#
QK
QVLD
tZQinit or tZQoper
tZQCS
Indicates a break in
time scale
Don’t Care
or Unknown
1. All devices connected to the DQ bus should be held High-Z during calibration.
2. The state of QK and QK# are unknown during ZQ calibration.
3. tMRSC after loading the MR1 settings, QVLD output drive strength will be at the value
selected or lower until ZQ calibration is complete.
Notes:
ZQ Calibration Long
The ZQ calibration long (ZQCL) mode register setting is used to perform the initial calibration during a power-up initialization and reset sequence. It may be loaded at any
time by the controller depending on the system environment. ZQCL triggers the calibration engine inside the DRAM. After calibration is achieved, the calibrated values are
transferred from the calibration engine to the DRAM I/O, which are reflected as updated RON and ODT values.
The DRAM is allowed a timing window defined by either tZQinit or tZQoper to perform
the full calibration and transfer of values. When ZQCL is issued during the initialization
sequence, the timing parameter tZQinit must be satisfied. When initialization is complete, subsequent loading of the ZQCL mode register setting requires the timing parameter tZQoper to be satisfied.
ZQ Calibration Short
The ZQ calibration short (ZQCS) mode register setting is used to perform periodic calibrations to account for small voltage and temperature variations. The shorter timing
window is provided to perform the reduced calibration and transfer of values as defined
by timing parameter tZQCS. ZQCS can effectively correct a minimum of 0.5% RON and
RTT impedance error within 64 clock cycles, assuming the maximum sensitivities specified in the ODT Temperature and Voltage Sensitivity and the Output Driver Voltage and
Temperature Sensitivity tables.
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576Mb: x18, x36 RLDRAM 3
Mode Register 1 (MR1)
AUTO REFRESH Protocol
The AUTO REFRESH (AREF) protocol is selected with bit MR1[8]. There are two ways in
which AREF commands can be issued to the RLDRAM. Depending upon how bit
MR1[8] is programmed, the memory controller can issue either bank address-controlled or multibank AREF commands. Bank address-controlled AREF uses the BA[3:0] inputs to refresh a single bank per command. Multibank AREF is enabled by setting bit
MR1[8] HIGH during an MRS command. This refresh protocol enables the simultaneous refreshing of a row in up to four banks. In this method, the address pins A[15:0] represent banks 0–15, respectively. More information on both AREF protocols can be found
in AUTO REFRESH Command (page 77).
Burst Length (BL)
Burst length is defined by MR1[9] and MR1[10]. Read and write accesses to the
RLDRAM are burst-oriented, with the burst length being programmable to 2, 4, or 8.
Figure 34 (page 71) shows the different burst lengths with respect to a READ command. Changes in the burst length affect the width of the address bus (see the following
table for details).
The data written by the prior burst length is not guaranteed to be accurate when the
burst length of the device is changed.
Table 39: Address Widths of Different Burst Lengths
Configuration
Burst Length
x18
x36
2
A[19:0]
A[18:0]
4
A[18:0]
A[17:0]
8
A[17:0]
NA
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576Mb: x18, x36 RLDRAM 3
Mode Register 1 (MR1)
Figure 34: Read Burst Lengths
CK#
T0
T1
T2
T3
T4
T4n
READ
NOP
NOP
NOP
NOP
T5
T5n
T6
T6n
T7
T7n
CK
Command
Address
NOP
NOP
NOP
NOP
Bank a,
Col n
RL = 4
QK#
BL = 2
QK
QVLD
DO
an
DQ
QK#
BL = 4
QK
QVLD
DO
an
DQ
QK#
BL = 8
QK
QVLD
DO
an
DQ
Transitioning Data
Note:
Don’t Care
1. DO an = data-out from bank a and address an.
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576Mb: x18, x36 RLDRAM 3
Mode Register 2 (MR2)
Mode Register 2 (MR2)
Figure 35: MR2 Definition for Non-Multiplexed Address Mode
BA3 BA2 BA1 BA0 A17 ... A4 A3 A2 A1 A0 Address Bus
21 20 19 18
4 3 2
17-5
01 01 MRS Reserved WRITE En
M19 M18
1 0
RTR
Mode Register (Mx)
Mode Register Definition
0
0
Mode Register 0 (MR0)
0
1
Mode Register 1 (MR1)
1
0
Mode Register 2 (MR2)
1
1
Reserved
M1 M0
M4 M3
Note:
WRITE Protocol
READ Training Register
0
0
0-1-0-1 on all DQs
0
1
Even DQs: 0-1-0-1 ; Odd DQs: 1-0-1-0
1
0
Reserved
1
1
Reserved
0
0
Single Bank
0
1
Dual Bank
1
0
Quad Bank
0
Normal RLDRAM Operation
1
1
Reserved
1
READ Training Enabled
M2 READ Training Register Enable
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
READ Training Register (RTR)
The READ training register (RTR) is controlled through MR2[2:0]. It is used to output a
predefined bit sequence on the output balls to aid in system timing calibration. MR2[2]
is the master bit that enables or disables access to the READ training register, and
MR2[1:0] determine which predefined pattern for system calibration is selected. If
MR2[2] is set to 0, the RTR is disabled, and the DRAM operates in normal mode. When
MR2[2] is set to 1, the DRAM no longer outputs normal read data, but a predefined pattern that is defined by MR2[1:0].
Prior to enabling the RTR, all banks must be in the idle state (tRC met). When the RTR is
enabled, all subsequent READ commands will output four bits of a predefined sequence from the RTR on all DQs. The READ latency during RTR is defined with the Data
Latency bits in MR0. To loop on the predefined pattern when the RTR is enabled, successive READ commands must be issued and satisfy tRTRS. Address balls A[19:0] are
considered "Don't Care" during RTR READ commands. Bank address bits BA[3:0] must
access Bank 0 with each RTR READ command. tRC does not need to be met in between
RTR READ commands to Bank 0. When the RTR is enabled, only READ commands are
allowed. When the last RTR READ burst has completed and tRTRE has been satisfied, an
MRS command can be issued to exit the RTR. Standard RLDRAM 3 operation may then
start after tMRSC has been met. The RESET function is supported when the RTR is enabled.
If MR2[1:0] is set to 00 a 0-1-0-1 pattern will be output on all DQs with each RTR READ
command. If MR2[1:0] is set to 01, a 0-1-0-1 pattern will output on all even DQs and the
opposite pattern, a 1-0-1-0, will output on all odd DQs with each RTR READ command.
Note: Enabling RTR may corrupt previously written data.
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Figure 36: READ Training Function - Back-to-Back Readout
CK#
T0
CK
Command
Address
Bank
DM
QK#
QK
DK#
DK
((
))
((
))
T1
T2
T3
T4
T5
READ
NOP
READ
NOP
READ
T6
T7
T8
T9
READ
NOP
READ
NOP
( T10
(
))
((
))
T12
NOP
MRS
MRS
((
))
((
))
MR2[17:0]
((
))
((
))
((
))
((
))
MR2[17:0]
MR2[21:18]
((
))
((
))
((
))
((
))
MR2[21:18]
BANK 0
BANK 0
NOP
BANK 0
BANK 0
BANK 0
((
))
((
))
T11
NOP
((
))
((
))
((
))
((
))
T13
VALID
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
RL
tMRSC
QVLD
DQ
tRTRS
tRTRS
tRTRS
tRTRS
tRTRE
((
))
((
))
((
))
((
))
Transitioning Data
Note:
tMRSC
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Don’t Care
((
) ) Indicates a break
((
) ) in time scale
1. RL = READ latency defined with data latency MR0 setting.
576Mb: x18, x36 RLDRAM 3
Mode Register 2 (MR2)
73
DRAFT 12/19/2011
576Mb: x18, x36 RLDRAM 3
WRITE Command
WRITE Protocol
Single or multibank WRITE operation is programmed with bits MR2[4:3]. The purpose
of multibank WRITE operation is to reduce the effective tRC during READ commands.
When dual- or quad-bank WRITE protocol is selected, identical data is written to two or
four banks, respectively. With the same data stored in multiple banks on the RLDRAM,
the memory controller can select the appropriate bank to READ the data from and minimize tRC delay. Detailed information on the multibank WRITE protocol can be found
in Multibank WRITE (page 75).
WRITE Command
Write accesses are initiated with a WRITE command. The address needs to be provided
concurrent with the WRITE command.
During WRITE commands, data will be registered at both edges of DK, according to the
programmed burst length (BL). The RLDRAM operates with a WRITE latency (WL) determined by the data latency bits within MR0. The first valid data is registered at the first
rising DK edge WL cycles after the WRITE command.
Any WRITE burst may be followed by a subsequent READ command (assuming tRC is
met). Depending on the amount of input timing skew, an additional NOP command
might be necessary between WRITE and READ commands to avoid external data bus
contention (see Figure 44 (page 83)).
Setup and hold times for incoming DQ relative to the DK edges are specified as tDS and
tDH. The input data is masked if the corresponding DM signal is HIGH.
Figure 37: WRITE Command
CK#
CK
CS#
WE#
REF#
Address
A
Bank
Address
BA
Don’t Care
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READ Command
Multibank WRITE
All the information provided above in the WRITE section is applicable to a multibank
WRITE operation as well. Either two or four banks can be simultaneously written to
when the appropriate MR2[4:3] mode register bits are selected.
If a dual-bank WRITE has been selected through the mode register, both banks x and x
+8 will be written to simultaneously with identical data provided during the WRITE
command. For example, when a dual-bank WRITE has been loaded and the bank address for Bank 1 has been provided during the WRITE command, Bank 9 will also be
written to at the same time. When a dual-bank WRITE command is issued, only bank
address bits BA[2:0] are valid and BA3 is considered a “Don’t Care.”
The same methodology is used if the quad-bank WRITE has been selected through the
mode register. Under these conditions, when a WRITE command is issued to Bank x,
the data provided on the DQs will be issued to banks x, x+4, x+8, and x+12. When a
quad-bank WRITE command is issued, only bank address bits BA[1:0] are valid and
BA[3:2] are considered “Don’t Care.”
The timing parameter tSAW must be adhered to when operating with multibank WRITE
commands. This parameter limits the number of active banks at 16 within an 8ns window. The tMMD specification must also be followed if the quad-bank WRITE is being
used. This specification requires two clock cycles between any bank command (READ,
WRITE, or AREF) to a quad-bank WRITE or a quad-bank WRITE to any bank command.
The data bus efficiency is not compromised if BL4 or BL8 is being utilized.
READ Command
Read accesses are initiated with a READ command (see the figure below). Addresses are
provided with the READ command.
During READ bursts, the memory device drives the read data so it is edge-aligned with
the QK signals. After a programmable READ latency, data is available at the outputs.
One half clock cycle prior to valid data on the read bus, the data valid signal(s), QVLD,
transitions from LOW to HIGH. QVLD is also edge-aligned with the QK signals.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQx is the
skew between a QK pair and the last valid data edge generated at the DQ signals in the
associated byte group, such as DQ[7:0] and QK0. tQKQx is derived at each QK clock edge
and is not cumulative over time. For the x36 device, the tQKQ02 and tQKQ13 specifications define the relationship between the DQs and QK signals within specific data word
groupings. tQKQ02 defines the skew between QK0 and DQ[26:18] and between QK2 and
DQ[8:0]. tQKQ13 defines the skew between QK1 and DQ[35:17] and between QK3 and
DQ[17:9].
After completion of a burst, assuming no other commands have been initiated, output
data (DQ) will go High-Z. The QVLD signal transitions LOW on the last bit of the READ
burst. The QK clocks are free-running and will continue to cycle after the read burst is
complete. Back-to-back READ commands are possible, producing a continuous flow of
output data.
Any READ burst may be followed by a subsequent WRITE command. Some systems
having long line lengths or severe skews may need an additional idle cycle inserted between READ and WRITE commands to prevent data bus contention.
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576Mb: x18, x36 RLDRAM 3
READ Command
Figure 38: READ Command
CK#
CK
CS#
WE#
REF#
Address
A
Bank
Address
BA
Don’t Care
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576Mb: x18, x36 RLDRAM 3
AUTO REFRESH Command
AUTO REFRESH Command
The RLDRAM 3 device uses two unique AUTO REFRESH (AREF) command protocols,
bank address-controlled AREF and multibank AREF. The desired protocol is selected by
setting MR1[8] LOW (for bank address-controlled AREF) or HIGH (for multibank AREF)
during an MRS command. Bank address-controlled AREF is identical to the method
used in RLDRAM2 devices, whereby banks are refreshed independently. The value on
bank addresses BA[3:0], issued concurrently with the AREF command, define which
bank is to be refreshed. The array address is generated by an internal refresh counter,
effectively making each address bit a "Don't Care" during the AREF command. The delay between the AREF command and a subsequent command to the same bank must be
at least tRC.
Figure 39: Bank Address-Controlled AUTO REFRESH Command
CK#
CK
CS#
WE#
REF#
Address
Bank
Address
BA[3:0]
Don’t Care
The multibank AREF protocol, enabled by setting bit MR1[8] HIGH during an MRS
command, enables the simultaneous refresh of a row in up to four banks. In this method, address balls A[15:0] represent banks [15:0], respectively. The row addresses are generated by an internal refresh counter for each bank; therefore, the purpose of the address balls during an AREF command is only to identify the banks to be refreshed. The
bank address balls BA[3:0] are considered "Don't Care" during a multibank AREF command.
A multibank AUTO REFRESH is performed for a given bank when its corresponding address ball is asserted HIGH during an AREF command. Any combination of up to four
address balls can be asserted HIGH during the rising clock edge of an AREF command
to simultaneously refresh a row in each corresponding bank. The delay between an
AREF command and subsequent commands to the banks refreshed must be at least
tRC. Adherence to tSAW must be followed when simultaneously refreshing multiple
banks. If refreshing three or four banks with the multibank AREF command, tMMD
must be followed. This specification requires two clock cycles between any bank command (READ, WRITE, AREF) to the multibank AREF or the multibank AREF to any bank
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576Mb: x18, x36 RLDRAM 3
AUTO REFRESH Command
command. Note that refreshing one or two banks with the multibank AREF command is
not subject to the tMMD specification.
The entire device must be refreshed every 64ms (tREF). The RLDRAM device requires
128K cycles at an average periodic interval of 0.489µs MAX (64ms/[8K rows x 16 banks]).
Figure 40: Multibank AUTO REFRESH Command
CK#
CK
CS#
WE#
REF#
Address
A[15:0]
Bank
Address
Don’t Care
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576Mb: x18, x36 RLDRAM 3
INITIALIZATION Operation
INITIALIZATION Operation
The RLDRAM 3 device must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operations or
permanent damage to the device.
The following sequence is used for power-up:
1. Apply power (VEXT, V DD, V DDQ). Apply V DD and V EXT before, or at the same time as,
VDDQ. V DD must not exceed V EXT during power supply ramp. V EXT, V DD, V DDQ must
all ramp to their respective minimum DC levels within 200ms.
2. Ensure that RESET# is below 0.2 × V DDQ during power ramp to ensure the outputs
remain disabled (High-Z) and ODT is off (RTT is also High-Z). DQs, and QK signals
will remain High-Z until MR0 command. All other inputs may be undefined during the power ramp.
3. After the power is stable, RESET# must be LOW for at least 200µs to begin the initialization process.
4. After 100 or more stable input clock cycles with NOP commands, bring RESET#
HIGH.
5. After RESET# goes HIGH, a stable clock must be applied in conjunction with NOP
commands for 10,000 cycles.
6. Load desired settings into MR0.
7. tMRSC after loading the MR0 settings, load operating parameters in MR1, including DLL Reset and Long ZQ Calibration.
8. After the DLL is reset and Long ZQ Calibration is enabled, the input clock must be
stable for 512 clock cycles while NOPs are issued.
9. Load desired settings into MR2. If using the RTR, follow the procedure outlined in
the READ Training Function – Back-to-Back Readout figure prior to entering normal operation.
10. The RLDRAM 3 is ready for normal operation.
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576Mb: x18, x36 RLDRAM 3
INITIALIZATION Operation
Figure 41: Power-Up/Initialization Sequence
T (MAX) = 200ms
VDD
See power-up
conditions
in the
initialization
sequence text
VDDQ
VEXT
VREF
Power-up
ramp
Stable and
valid clock
tCK
CK#
CK
tCH
100 cycles
tIOZ
tCL
= 20ns
RESET#
tDK
DK#
DK
tDKH
NOP
Command
NOP
NOP
tDKL
MRS
MRS
MR0
MR1
MRS
Valid
DM
Address
MR2
Valid
QK#
QK
QVLD1
DQ
RTT
T = 200µs (MIN)
10,000 CK cycles (MIN)
All voltage
supplies valid
and stable
Notes:
tMRSC
512 clock cycles
for DLL Reset &
ZQ Calibration
READ Training
register specs
apply
Indicates a break in
time scale
Normal
operation
Don’t Care
or Unknown
1. QVLD output drive status during power-up and initialization:
a. QVLD remains High-Z until 20ns after power supplies are stable and TCK or CK
have cycled 4 times.
b. QVLD will then drive LOW with 40Ω or lower until the output drive value selected
in MR1 is enabled.
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576Mb: x18, x36 RLDRAM 3
INITIALIZATION Operation
c. tMRSC after loading the MR1 settings, QVLD output drive strength will be at the
value selected or lower until ZQ calibration is complete.
d. QVLD will meet the output drive strength specifications upon completion of the
ZQ calibration timing.
2. After MR2 has been issued, Rtt is either High-Z or enabled to the ODT value selected in
MR1.
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576Mb: x18, x36 RLDRAM 3
WRITE Operation
WRITE Operation
Figure 42: WRITE Burst
T0
T1
T2
T3
T4
T5
Command
WRITE
NOP
NOP
NOP
NOP
NOP
Address
Bank a,
Add n
CK#
T5n
T6
T6n
T7
CK
t CKDKnom
NOP
NOP
WL = 5
DK#
DK
DI
an
DQ
DM
t CKDKmin
WL - tCKDK
DK#
DK
DI
an
DQ
DM
t CKDKmax
WL + tCKDK
DK#
DK
DI
an
DQ
DM
Transitioning Data
Note:
Don’t Care
1. DI an = data-in for bank a and address n.
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WRITE Operation
Figure 43: Consecutive WRITE Bursts
CK#
T0
T1
T2
T3
WRITE
NOP
WRITE
NOP
T4
T5
T5n
T6
T6n
T7
T7n
T8
T8n
T9
CK
Command
Address
Bank a,
Add n
WRITE
NOP
NOP
NOP
NOP
NOP
Bank a,
Add n
Bank b,
Add n
DK#
DK
tRC
WL
WL
DI
an
DQ
DI
bn
DI
an
DM
Transitioning Data
Indicates a break
in time scale
Note:
Don’t Care
1. DI an (or bn or cn) = data-in for bank a (or b or c) and address n.
Figure 44: WRITE-to-READ
T0
T1
T2
T3
T4
T5
Command
WRITE
NOP
READ
NOP
NOP
NOP
Address
Bank a,
Add n
CK#
T5n
T6
T6n
T7
CK
NOP
NOP
Bank b,
Add n
WL = 5
RL = 4
QK#
QK
DK#
DK
QVLD
DI
an
DQ
DO
bn
DM
Don’t Care
Notes:
Transitioning Data
1. DI an = data-in for bank a and address n.
2. DO bn = data-out from bank b and address n.
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WRITE Operation
Figure 45: WRITE - DM Operation
CK#
T0
T1
T2
T3
T4
NOP
NOP
T5
T6
T6n
NOP
NOP
T7
T7n
T8
CK
tCK
Command
Address
NOP
WRITE
tCH
tCL
NOP
NOP
NOP
Bank a,
Add n
DK#
DK
tDKL
WL = 5
tDKH
DI
an
DQ
DM
tDS
tDH
Transitioning Data
Note:
Don’t Care
1. DI an = data-in for bank a and address n.
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WRITE Operation
Figure 46: Consecutive Quad Bank WRITE Bursts
T0
T1
T2
Quad-Bank
WRITE
NOP
Quad-Bank
WRITE
CK#
T3
T4
T5
NOP
NOP
NOP
T6
T5n
T6n
T7
T7n
CK
Command
NOP
Bank b,
Add n
Bank a,
Add n
Address
NOP
tMMD = 2
WL = 5
DK#
DK
DI
an
DQ
DI
bn
DM
Transitioning Data
Notes:
Don’t Care
1. DI an = data-in for bank a, a+4, a+8, and a+12 and address n.
2. DI bn = data-in for bank b, b+4, b+8, and b+12 and address n.
Figure 47: Interleaved READ and Quad Bank WRITE Bursts
CK#
T0
T1
T2
READ
NOP
Quad-Bank
WRITE
T3
T4
T5
T5n
NOP
READ
NOP
T6
T6n
T7
T8
NOP
NOP
T8n
T9
T9n
CK
Command
Address
Bank a,
Add n
Bank b,
Add n
tMMD = 2
Bank c,
Add n
tMMD = 2
Quad-Bank
WRITE
NOP
Bank d,
Add n
tMMD = 2
RL = 5
WL = 6
QK#
QK
DK#
DK
QVLD
DO
an
DQ
DI
bn
DM
Transitioning Data
Notes:
Don’t Care
1. DO an = data-out for bank a and address n.
2. DI bn = data-in for bank b, b+4, b+8, and b+12 and address n.
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READ Operation
READ Operation
Figure 48: Basic READ Burst
CK#
T1
T0
T2
T3
T4
T5
NOP
NOP
T5n
T6
T6n
T7
CK
tCK
Command
Address
READ
NOP
tCH
tCL
NOP
READ
Bank a
Add n
NOP
NOP
Bank a
Add n
RL = 4
tRC
=4
DM
tCKQKmin
tCKQKmin
QK#
QK
tQK
tQKH
tQKVLD
tQKL
tQKVLD
QVLD
DO
an
DQ
tCKQKmax
tCKQKmax
QK
QK#
tQK
tQKH
tQKL
QVLD
DO
an
DQ
Transitioning Data
Note:
Don’t Care
1. DO an = data-out from bank a and address an.
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READ Operation
Figure 49: Consecutive READ Bursts (BL = 2)
T5n
T6n
T0
T1
T2
T3
T4
Command
READ
READ
READ
READ
READ
READ
READ
Address
Bank a
Add n
Bank b
Add n
Bank c
Add n
Bank d
Add n
Bank e
Add n
Bank f
Add n
Bank g
Add n
CK#
T4n
T5
T6
CK
RL = 4
QVLD
QK#
QK
DO
an
DQ
DO
bn
DO
cn
Transitioning Data
Note:
Don’t Care
1. DO an (or bn, cn) = data-out from bank a (or bank b, c) and address n.
Figure 50: Consecutive READ Bursts (BL = 4)
T0
T1
T2
T3
T4
Command
READ
NOP
READ
NOP
READ
Address
Bank a
Add n
CK#
T4n
T5
T5n
T6n
T6
CK
Bank b
Add n
NOP
Bank c
Add n
READ
Bank d
Add n
RL = 4
QVLD
QK#
QK
DO
an
DQ
Transitioning Data
Note:
DO
bn
Don’t Care
1. DO an (or bn) = data-out from bank a (or bank b) and address n.
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READ Operation
Figure 51: READ-to-WRITE
T0
T1
T2
T3
T4
T5
T6
T7
T8
Command
READ
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
Bank a,
Add n
CK#
CK
Bank b,
Add n
DM
QK#
QK
DK#
DK
RL = 4
WL = 5
QVLD
DO
an
DQ
DI
bn
Transitioning Data
Notes:
Don’t Care
1. DO an = data-out from bank a and address n.
2. DI bn = data-in for bank b and address n.
Figure 52: Read Data Valid Window
CK#
T0
T1
T2
READ
NOP
NOP
T3
T4
T5
T6
T7
T8
T9
T10
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
RL = 5
Address
Bank,
Addr n
QVLD
tQKQx,max
tQKQx,max
tHZmax
tLZmin
QKx, QKx#
tQH
DO
n
DQ (last data valid)2
DO
n
DQ (first data no longer valid)2
All DQ collectively2
tQH
DO
DO
DO
DO
DO
DO
DO
n+1
n+2
n+3
n+4
n+5
n+6
n+7
DO
DO
DO
DO
DO
DO
DO
n+1
n+2
n+3
n+4
n+5
n+6
n+7
DO
n
Data valid
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
Data valid
Transitioning Data
Notes:
Don’t Care
DO n = data-out from bank a and address n.
Represents DQs associated with a specific QK, QK# pair.
Output timings are referenced to VDDQ/2 and DLL on and locked.
tQKQx defines the skew between the QK0, QK0# pair to its respective DQs. tQKQx does
not define the skew between QK and CK.
5. Early data transitions may not always happen at the same DQ. Data transitions of a DQ
can vary (either early or late) within a burst.
1.
2.
3.
4.
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AUTO REFRESH Operation
AUTO REFRESH Operation
Figure 53: Bank Address-Controlled AUTO REFRESH Cycle
T0
CK#
CK
T1
((
))
tCK
AREFx
Command
AREFy
Address
Bank
BAx
BAy
((
))
T2
T3
tCH
tCL
ACx
ACy
((
))
((
))
((
))
((
))
DK, DK#
DQ
DM
tRC
((
))
Indicates a break
in time scale
Notes:
Don’t’ Care
1. AREFx (or AREFy)= AUTO REFRESH command to bank x (or bank y).
2. ACx = any command to bank x; ACy = any command to bank y.
3. BAx = bank address to bank x; BAy = bank address to bank y.
Figure 54: Multibank AUTO REFRESH Cycle
CK#
T0
T1
T2
T3
T4
T5
T6
T7
CK
Command
Address
AREF
AREF
AREF
AC
Bank
0,4,8,12
Bank
1,5,9,13
Bank
2, 3
Bank
0
tMMD
tMMD
Bank
DK, DK#
DQ
DM
tRC
Indicates a break
in time scale
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Don’t Care
89
576Mb: x18, x36 RLDRAM 3
AUTO REFRESH Operation
Figure 55: READ Burst with ODT
CK#
T0
T1
T2
T3
T4
T4n
READ
NOP
NOP
NOP
NOP
T5
T5n
T6
T6n
T7
T7n
CK
Command
Address
NOP
NOP
NOP
NOP
Bank a,
Col n
RL = 4
QK#
BL = 2
QK
QVLD
DO
an
DQ
ODT
ODT on
ODT off
ODT on
QK#
BL = 4
QK
QVLD
DO
an
DQ
ODT
ODT on
ODT off
ODT on
QK#
BL = 8
QK
QVLD
DO
an
DQ
ODT
ODT on
Transitioning Data
Note:
on
ODT off
Don’t Care
1. DO an = data out from bank a and address n.
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AUTO REFRESH Operation
Figure 56: READ-NOP-READ with ODT
CK#
T0
T1
T2
T3
T4
T4n
READ
NOP
READ
NOP
NOP
T5
T6
T6n
NOP
NOP
T7
CK
Command
Address
Bank a,
Col n
NOP
NOP
Bank b,
Col n
RL = 4
QK#
QK
QVLD
DO
an
DQ
ODT
ODT on
ODT off
DO
bn
ODT on
ODT off
Transitioning Data
Note:
ODT on
Don’t Care
1. DO an (or bn) = data-out from bank a (or bank b) and address n.
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Multiplexed Address Mode
Multiplexed Address Mode
Figure 57: Command Description in Multiplexed Address Mode
READ
WRITE
MRS
AREF
CK#
CK
CS#
WE#
REF#
Address
Ax
Bank
Address
BA
Ay
Ax
BA
Ay
Ax
BA
Ay
Ax1
Ay1
BA2
Don’t Care
Notes:
1. Addresses valid only during a multibank AUTO REFRESH command.
2. Bank addresses valid only during a bank address-controlled AUTO REFRESH command.
3. The minimum setup and hold times of the two address parts are defined as tIS and tIH.
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Multiplexed Address Mode
Figure 58: Power-Up/Initialization Sequence in Multiplexed Address Mode
T (MAX) = 200ms
VDD
VDDQ
VEXT
See power-up
conditions
in the
initialization
sequence text
VREF
Power-up
ramp
Stable and
valid clock
tCK
CK#
CK
tCL
tCH
100 cycles
tIOZ
= 20ns
RESET#
tDK
DK#
DK
tDKH
Command
NOP
NOP
NOP
tDKL
MRS
MRS
MR01
MR02 (Ax)
NOP
MRS
NOP
MRS
MR1 (Ax)
MR1 (Ay)
MR2 (Ax)
NOP
Valid
DM
Address
MR0 (Ay)
MR2 (Ay)
Valid
QK#
QK
QVLD5
DQ
RTT High-Z
T = 200µs (MIN)
10,000 CK cycles (MIN)
All voltage
supplies valid
and stable
tMRSC
tMRSC
512 clock cycles
for DLL Reset &
ZQ Calibration
Indicates a break
in time scale
Notes:
Normal
READ Training operation
register specs
apply
Don’t Care
or Unknown
1. Set address bit MR0[9] HIGH. This enables the device to enter multiplexed address mode
when in non-multiplexed mode operation. Multiplexed address mode can also be entered at a later time by issuing an MRS command with MR0[9] HIGH. After address bit
MR0[9] is set HIGH, tMRSC must be satisfied before the two-cycle multiplexed mode MRS
command is issued.
2. Address MR0[9] must be set HIGH. This and the following step set the desired MR0 setting after the RLDRAM device is in multiplexed address mode.
3. MR1 (Ax), MR1 (Ay), MR2 (Ax), and MR2 (Ay) represent MR1 and MR2 settings in multiplexed address mode.
4. The above sequence must be followed in order to power up the RLDRAM device in the
multiplexed address mode.
5. See QVLD output drive strength status during power up and initialization in non-multiplexed initialization operation section.
6. After MR2 has been issued, RTT is either High-Z or enabled to the ODT value selected in
MR1.
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Multiplexed Address Mode
Figure 59: MR0 Definition for Multiplexed Address Mode
A5 A4 A3
Ax A18.......A10 A9 A8
A0
Ay A18.......A10
A9 A8
A4 A3
Address Bus
BA3 BA2 BA1 BA0
21 20 19 18
01 01 MRS
9 8 7 6 5 4
AM DLL Data Latency
17-10
Reserved
3
2
1
0
Mode Register (Mx)
tRC_MRS
M7 M6 M5 M4 Data Latency (RL & WL)
M19 M18
0
0
Mode Register Definition
M8
DLL Enable
0
Enable
1
Disable
Mode Register 0 (MR0)
0
1
Mode Register 1 (MR1)
1
0
Mode Register 2 (MR2)
1
1
Reserved
Notes:
M9
Address MUX
0
Non-multiplexed
1
Multiplexed
0
0
0
0
RL = 3 ; WL = 4
0
0
0
1
RL = 4 ; WL = 5
0
0
1
0
RL = 5 ; WL = 6
0
0
0
0
22,3
0
0
1
1
RL = 6 ; WL = 7
0
0
0
1
32
0
1
0
0
RL = 7 ; WL = 8
0
0
1
0
42
0
1
0
1
RL = 8 ; WL = 9
0
0
1
1
5
0
1
1
0
RL = 9 ; WL = 10
0
1
0
0
6
0
1
1
0
1
0
1
0
RL = 10 ; WL = 11
RL = 11 ; WL = 12
0
1
0
1
7
1
0
0
1
0
1
1
0
8
RL = 12 ; WL = 13
1
0
1
0
RL = 13 ; WL = 14
0
1
1
0
1
0
1
0
1
0
1
1
10
RL = 14 ; WL = 15
1
0
0
1
1
1
0
0
RL = 15 ; WL = 16
1
0
1
0
11
12
1
1
0
1
RL = 16 ; WL = 17
1
0
1
1
Reserved
1
1
1
0
Reserved
1
1
0
0
Reserved
1
1
1
1
Reserved
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
M3 M2 M1 M0
t RC_MRS
9
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
2. BL8 not allowed.
3. BL4 not allowed.
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Multiplexed Address Mode
Figure 60: MR1 Definition for Multiplexed Address Mode
Ax A18.......A13
Ay A18.......A13
A10 A9 A8
A5 A4 A3
A0
A4 A3
A9 A8
Address Bus
BA3 BA2 BA1 BA0
21 20 19 18 17-11
MRS Reserved
01 01
M19 M18
Mode Register Definition
0
Mode Register 0 (MR0)
0
1
Mode Register 1 (MR1)
0
1
0
Mode Register 2 (MR2)
1
1
1
Reserved
1
0
4 3
ODT
M5 DLL Reset
M10 M9 Burst Length
0
Notes:
10 9 8 7 6 5
BL2 Ref ZQe ZQ DLL
2
1
0
Mode Register (Mx)
Drive
M4 M3 M2
ODT
M1 M0 Output Drive
2
0
No
0
0
0
Off
0
0
RZQ/6 (40W)
1
4
1
Yes
0
0
1
RZQ/6 (40W)
0
1
RZQ/4 (60W)
0
8
0
1
0
RZQ/4 (60W)
1
0
Reserved
1
Reserved
M6 ZQ Calibration Selection
0
1
1
RZQ/2 (120W)
1
1
Reserved
0
Short ZQ Calibration
1
0
0
Reserved
1
Long ZQ Calibration
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
0
M8
AREF Protocol
M7
0
Bank Address Control
0
Disabled - Default
1
Multibank
1
Enable
ZQ Calibration Enable
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
2. BL8 not available in x36.
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Multiplexed Address Mode
Figure 61: MR2 Definition for Multiplexed Address Mode
A0
Ax A18.......A5 A4 A3
Ay A18.......A5
A4 A3
BA3 BA2 BA1 BA0
21 20 19 18
17-5
4 3 2
01 01 MRS Reserved WRITE En
M19 M18
1 0
RTR
Address Bus
Mode Register (Mx)
Mode Register Definition
0
0
Mode Register 0 (MR0)
0
1
Mode Register 1 (MR1)
1
0
Mode Register 2 (MR2)
0
0
0-1-0-1 on all DQs
1
1
Reserved
0
1
Even DQs: 0-1-0-1 ; Odd DQs: 1-0-1-0
1
0
Reserved
1
1
Reserved
M4 M3
Note:
READ Training Register
M1 M0
WRITE Protocol
0
0
Single Bank
0
1
Dual Bank
1
0
Quad Bank
1
1
Reserved
M2 READ Training Register Enable
0
Normal RLDRAM Operation
1
READ Training Enabled
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
Table 40: Address Mapping in Multiplexed Address Mode
Address
Data
Width
Burst
Length
Ball
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
x36
2
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
X
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
X
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
4
x18
2
4
8
Note:
1. X = “Don’t Care”
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Multiplexed Address Mode
Data Latency in Multiplexed Address Mode
When in multiplexed address mode, data latency (READ and WRITE) begins when the
Ay part of the address is issued with any READ or WRITE command. tRC is measured
from the clock edge in which the command and Ax part of the address is issued in both
multiplexed and non-multiplexed address mode.
REFRESH Command in Multiplexed Address Mode
Similar to other commands when in multiplexed address mode, both modes of AREF
(single and multibank) are executed on the rising clock edge, following the one on
which the command is issued. However, when in bank address-controlled AREF, as only
the bank address is required, the next command can be applied on the following clock.
When using multibank AREF, the bank addresses are mapped across Ax and Ay so a subsequent command cannot be issued until two clock cycles later.
Figure 62: Bank Address-Controlled AUTO REFRESH Operation with Multiplexed Addressing
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Command
AC1
NOP
AREF
AREF
AREF
AREF
AREF
AREF
AREF
AREF
Address
Ax
Ay
CK#
T10
T11
CK
Bank
AC1
Ay
Ax
Bank n
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank n
Don’t Care
Note:
1. Any command subject to tRC specification.
Figure 63: Multibank AUTO REFRESH Operation with Multiplexed Addressing
CK#
T0
T1
T2
T3
AREF1
NOP
AREF1
NOP
Ax
Ay
Ax
Ay
T4
T5
T6
T7
AREF1
NOP
AC2
NOP
Ax
Ay
Ax
Ay
CK
Command
Address
Bank
Bank n
Don’t Care
Notes:
1. Usage of multibank AREF subject to tSAW and tMMD specifications.
2. Any command subject to tRC specification.
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Multiplexed Address Mode
Figure 64: Consecutive WRITE Bursts with Multiplexed Addressing
CK#
T0
T1
T2
T3
T4
WRITE
NOP
WRITE
NOP
Ax
Ay
Ax
Ay
T5
T6
WRITE
NOP
NOP
Ax
Ay
T6n
T7
T7n
T8
T8n
T9
CK
Command
Address
Bank
Bank a
Bank b
NOP
NOP
NOP
Bank a
DK#
DK
tRC
WL
DI
a
DQ
DI
b
DM
Indicates a break
in time scale
Note:
Transitioning Data
Don’t Care
1. DI a = data-in for bank a; DI b = data-in for bank b.
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Multiplexed Address Mode
Figure 65: WRITE-to-READ with Multiplexed Addressing
T0
T1
T2
T3
T4
T5
T6
WRITE
NOP
READ
NOP
NOP
NOP
NOP
Ax
Ay
Ax
Ay
CK#
T6n
T7
T7n
T8
T8n
CK
Command
Address
NOP
NOP
WL
Bank
Bank a
Bank b
RL
QK#
QK
DK#
DK
QVLD
DI
a
DQ
DO
b
DM
Indicates a break
in time scale
Note:
Transitioning Data
Don’t Care
1. DI a = data-in for bank a; DI b = data-in for bank b.
Figure 66: Consecutive READ Bursts with Multiplexed Addressing
CK#
T0
T1
T2
T3
T4
T5
T5n
T6
T6n
READ
NOP
READ
NOP
READ
NOP
READ
Ax
Ay
Ax
Ay
Ax
Ay
Ax
CK
Command
Address
Bank
Bank a
Bank b
Bank c
Bank d
RL
QVLD
QK#
QK
DO
a
DQ
Indicates a break
in time scale
Note:
Transitioning Data
Don’t Care
1. DO a = data-out for bank a.
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Multiplexed Address Mode
Figure 67: READ-to-WRITE with Multiplexed Addressing
CK#
T0
T1
T2
T3
T4
T5
T6
READ
NOP
WRITE
NOP
NOP
NOP
NOP
Ax
Ay
Ax
Ay
T6n
T7
T7n
T8
T9
NOP
NOP
NOP
T9n
CK
Command
Address
Bank
Bank a
NOP
Bank b
DM
QK#
QK
DK#
DK
RL
WL
QVLD
DO
an
DQ
Indicates a break
in time scale
Note:
DI
bn
Transitioning Data
Don’t Care
1. DO a = data-out for bank a; DI b = data-in for bank b.
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Mirror Function
Mirror Function
The mirror function ball (MF) is a DC input used to create mirrored ballouts for simple
dual-loaded clamshell mounting. If the MF ball is tied LOW, the address and command
balls are in their true layout. If the MF ball is tied HIGH, the address and command balls
are mirrored around the central y-axis (column 7). The following table shows the ball
assignments when the MF ball is tied HIGH for a x18 device. Compare that table to Table 1 (page 12) to see how the address and command balls are mirrored. The same balls
are mirrored on the x36 device.
Table 41: 32 Meg x 18 Ball Assignments with MF Ball Tied HIGH
1
A
2
3
4
5
6
7
8
9
10
11
12
13
VSS
VDD
NF
VDDQ
NF
VREF
DQ7
VDDQ
DQ8
VDD
VSS
RESET#
B
VEXT
VSS
NF
VSSQ
NF
VDDQ
DM0
VDDQ
DQ5
VSSQ
DQ6
VSS
VEXT
C
VDD
NF
VDDQ
NF
VSSQ
NF
DK0#
DQ2
VSSQ
DQ3
VDDQ
DQ4
VDD
D
A13
VSSQ
NF
VDDQ
NF
VSSQ
DK0
VSSQ
QK0
VDDQ
DQ0
VSSQ
A11
E
VSS
CS#
VSSQ
NF
VDDQ
NF
MF
QK0#
VDDQ
DQ1
VSSQ
A0
VSS
A7
VSS
F
A9
A5
VDD
A4
A3
REF#
ZQ
WE#
A1
A2
VDD
NC1
G
VSS
A18
A8
VSS
BA0
VSS
CK#
VSS
BA1
VSS
A6
A15
H
A10
VDD
A12
A17
VDD
BA2
CK
BA3
VDD
A16
A14
VDD
A19
J
VDDQ
NF
VSSQ
NF
VDDQ
NF
VSS
QK1#
VDDQ
DQ9
VSSQ
QVLD
VDDQ
K
NF
VSSQ
NF
VDDQ
NF
VSSQ
DK1
VSSQ
QK1
VDDQ
DQ10
VSSQ
DQ11
L
VDD
NF
VDDQ
NF
VSSQ
NF
DK1#
DQ12
VSSQ
DQ13
VDDQ
DQ14
VDD
M
VEXT
VSS
NF
VSSQ
NF
VDDQ
DM1
VDDQ
DQ15
VSSQ
DQ16
VSS
VEXT
N
VSS
TCK
VDD
TDO
VDDQ
NF
VREF
DQ17
VDDQ
TDI
VDD
TMS
VSS
RESET Operation
The RESET signal (RESET#) is an asynchronous signal that triggers any time it drops
LOW. There are no restrictions for when it can go LOW. After RESET# goes LOW, it must
remain LOW for 100ns. During this time, the outputs are disabled, ODT (RTT) turns off
(High-Z), and the DRAM resets itself. Prior to RESET# going HIGH, at least 100 stable CK
cycles with NOP commands must be given to the RLDRAM. After RESET# goes HIGH,
the DRAM must be reinitialized as though a normal power-up was executed. All refresh
counters on the DRAM are reset, and data stored in the DRAM is assumed unknown after RESET# has gone LOW.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The RLDRAM 3 device incorporates a serial boundary-scan test access port (TAP) for
the purpose of testing the connectivity of the device after it has been mounted on a
printed circuit board (PCB). As the complexity of PCB high-density surface mounting
techniques increases, the boundary-scan architecture is a valuable resource for interconnectivity debug. This port operates in accordance with IEEE Standard 1149.1-2001
(JTAG) with the exception of the ZQ pin. To ensure proper boundary-scan testing of the
ZQ pin, MR1[7] needs to be set to 0 until the JTAG testing of the pin is complete. Note
that upon power up, the default state of the MRS bit M1[7] is low.
The JTAG test access port utilizes the TAP controller on the device, from which the instruction register, boundary-scan register, bypass register, and ID register can be selected. Each of these functions of the TAP controller is described in detail below.
Disabling the JTAG Feature
It is possible to operate an RLDRAM 3 device without using the JTAG feature. To disable
the TAP controller, TCK must be tied LOW (V SS) to prevent clocking of the device. TDI
and TMS are internally pulled up and may be unconnected. They may alternately be
connected to V DDQ through a pull-up resistor. TDO should be left unconnected. Upon
power-up, the device will come up in a reset state, which will not interfere with the operation of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising
edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the
rising edge of TCK.
All the states in Figure 68 (page 104) are entered through the serial input of the TMS
ball. A 0 in the diagram represents a LOW on the TMS ball during the rising edge of TCK,
while a 1 represents a HIGH on TMS.
Test Data-In (TDI)
The TDI ball is used to serially input test instructions and data into the registers and can
be connected to the input of any of the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure 68 (page 104). TDI is connected to
the most significant bit (MSB) of any register (see Figure 69 (page 104)).
Test Data-Out (TDO)
The TDO output ball is used to serially clock test instructions and data out from the registers. The TDO output driver is only active during the Shift-IR and Shift-DR TAP controller states. In all other states, the TDO ball is in a High-Z state. The output changes on
the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register (see Figure 69 (page 104)).
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IEEE 1149.1 Serial Boundary Scan (JTAG)
TAP Controller
The TAP controller is a finite state machine that uses the state of the TMS ball at the
rising edge of TCK to navigate through its various modes of operation (see Figure 68
(page 104)). Each state is described in detail below.
Test-Logic-Reset
The test-logic-reset controller state is entered when TMS is held HIGH for at least five
consecutive rising edges of TCK. As long as TMS remains HIGH, the TAP controller will
remain in the test-logic-reset state. The test logic is inactive during this state.
Run-Test/Idle
The run-test/idle is a controller state in between scan operations. This state can be
maintained by holding TMS LOW. From there, either the data register scan, or subsequently, the instruction register scan, can be selected.
Select-DR-Scan
Select-DR-scan is a temporary controller state. All test data registers retain their previous state while here.
Capture-DR
The capture-DR state is where the data is parallel-loaded into the test data registers. If
the boundary-scan register is the currently selected register, then the data currently on
the balls is latched into the test data registers.
Shift-DR
Data is shifted serially through the data register while in this state. As new data is input
through the TDI ball, data is shifted out of the TDO ball.
Exit1-DR, Pause-DR, and Exit2-DR
The purpose of exit1-DR is used to provide a path to return back to the run-test/idle
state (through the update-DR state). The pause-DR state is entered when the shifting of
data through the test registers needs to be suspended. When shifting is to reconvene,
the controller enters the exit2-DR state and then can re-enter the shift-DR state.
Update-DR
When the EXTEST instruction is selected, there are latched parallel outputs of the boundary-scan shift register that only change state during the update-DR controller state.
Instruction Register States
The instruction register states of the TAP controller are similar to the data register
states. The desired instruction is serially shifted into the instruction register during the
shift-IR state and is loaded during the update-IR state.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
Figure 68: TAP Controller State Diagram
1
Test-logic
reset
0
Run-test/
Idle
0
1
1
Select
DR-scan
Select
IR-scan
0
1
0
1
Capture-DR
Capture-IR
0
0
Shift-DR
Shift-IR
0
1
1
Exit1-IR
0
1
0
Pause-DR
Pause-IR
0
1
0
1
Exit2-DR
0
Exit2-IR
1
1
Update-DR
1
0
1
Exit1-DR
0
1
Update-IR
1
0
0
Figure 69: TAP Controller Functional Block Diagram
0
Bypass register
7 6 5 4 3 2 1 0
TDI
Instruction register
Selection
circuitry
31 30 29 .
.
. 2 1 0
Selection
circuitry
TDO
Identification register
x1 . . . . . 2 1 0
Boundry scan register
TCK
TMS
Note:
TAP controller
1. x = 121 for all configurations.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
Performing a TAP RESET
A reset is performed by forcing TMS HIGH (V DDQ) for five rising edges of tCK. This RESET does not affect the operation of the device and may be performed while the device
is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
If JTAG inputs cannot be guaranteed to be stable during power-up it is recommended
that TMS be held HIGH for at least 5 consecutive TCK cycles prior to boundary scan
testing.
TAP Registers
Registers are connected between the TDI and TDO balls and allow data to be scanned
into and out of the RLDRAM 3 device test circuitry. Only one register can be selected at
a time through the instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is
loaded during the update-IR state of the TAP controller. Upon power-up, the instruction
register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the capture-IR state, the two LSBs are loaded with a binary 01 pattern to allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous
to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This enables data to be shifted through the device with
minimal delay. The bypass register is set LOW (V SS) when the BYPASS instruction is executed.
Boundary-Scan Register
The boundary-scan register is connected to all the input and bidirectional balls on the
device. Several balls are also included in the scan register to reserved balls. The device
has a 121-bit register.
The boundary-scan register is loaded with the contents of the RAM I/O ring when the
TAP controller is in the capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the shift-DR state.
The order in which the bits are connected is shown in Table 48 (page 110). Each bit corresponds to one of the balls on the RLDRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR
state when the IDCODE command is loaded in the instruction register. The IDCODE is
hardwired into the RLDRAM 3 and can be shifted out when the TAP controller is in the
shift-DR state. The ID register has a vendor code and other information described in
Table 45 (page 109).
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IEEE 1149.1 Serial Boundary Scan (JTAG)
TAP Instruction Set
Overview
There are 28 different instructions possible with the 8-bit instruction register. All combinations used are listed in Table 47 (page 110). These six instructions are described in
detail below. The remaining instructions are reserved and should not be used.
The TAP controller used in this RLDRAM 3 device is fully compliant to the IEEE 1149.1
convention.
Instructions are loaded into the TAP controller during the shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are
shifted through the instruction register through the TDI and TDO balls. To execute the
instruction after it is shifted in, the TAP controller needs to be moved into the update-IR
state.
EXTEST
The EXTEST instruction enables circuitry external to the component package to be tested. Boundary-scan register cells at output balls are used to apply a test vector, while
those at input balls capture test results. Typically, the first test vector to be applied using
the EXTEST instruction will be shifted into the boundary-scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output driver is
turned on, and the PRELOAD data is driven onto the output balls.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls
and enables the IDCODE to be shifted out of the device when the TAP controller enters
the shift-DR state. The IDCODE instruction is loaded into the instruction register upon
power-up or whenever the TAP controller is given a test logic reset state.
High-Z
The High-Z instruction causes the bypass register to be connected between the TDI and
TDO. This places all RLDRAM outputs into a High-Z state.
CLAMP
When the CLAMP instruction is loaded into the instruction register, the data driven by
the output balls are determined from the values held in the boundary-scan register.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the
TAP controller is in the capture-DR state, allows a snapshot to be taken of the states of
the component's input and output signals without interfering with the normal operation of the assembled board. The snapshot is taken on the rising edge of TCK and is captured in the boundry-scan register. The data can then be viewed by shifting through the
component's TDO output.
The user must be aware that the TAP controller clock can only operate at a frequency up
to 50 MHz, while the RLDRAM 3 clock operates significantly faster. Because there is a
large difference between the clock frequencies, it is possible that during the capture-DR
state, an input or output will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm the device, but there is
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IEEE 1149.1 Serial Boundary Scan (JTAG)
no guarantee as to the value that will be captured. Repeatable results may not be possible.
To ensure that the boundary-scan register will capture the correct value of a signal, the
RLDRAM signal must be stabilized long enough to meet the TAP controller’s capture
setup plus hold time (tCS plus tCH). The RLDRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/
PRELOAD instruction. If this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK# captured in the boundary-scan register.
After the data is captured, it is possible to shift out the data by putting the TAP into the
shift-DR state. This places the boundary-scan register between the TDI and TDO balls.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed
in a shift-DR state, the bypass register is placed between TDI and TDO. The advantage
of the BYPASS instruction is that it shortens the boundary-scan path when multiple devices are connected together on a board.
Reserved for Future Use
The remaining instructions are not implemented but are reserved for future use. Do not
use these instructions.
Figure 70: JTAG Operation - Loading Instruction Code and Shifting Out Data
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
((
))
((
))
TCK
TMS
((
))
((
))
TDI
((
))
((
))
TAP
Controller
State
Test-LogicReset
Run-Test
Idle
Select-DRSCAN
Select-IRSCAN
Capture-IR
((
Shift ( )( ) IR
Shift-IR
Exit 1-IR
Pause-IR
Pause-IR
))
((
))
((
))
TDO
8-bit instruction
code
T10
T11
T12
T13
T14
T15
T16
TCK
T18
T19
((
))
((
))
TMS
((
))
((
))
TDI
TAP
Controller
State
T17
((
))
((
))
Exit 2-IR
Update-IR
Select-DRScan
Capture-DR
TDO
Shift-DR
Shift
((
))
((
))
DR
Exit1-DR
Update-DR
Run-Test
Idle
Run-Test
Idle
((
))
((
))
n-bit register
between
TDI and TDO
Transitioning Data
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Don’t Care
107
576Mb: x18, x36 RLDRAM 3
IEEE 1149.1 Serial Boundary Scan (JTAG)
Figure 71: TAP Timing
T2
T1
T3
T4
T6
T5
Test clock
(TCK)
tTHTL
tTLTH
tTHTH
tMVTH tTHMX
Test mode select
(TMS)
tDVTH tTHDX
Test data-in
(TDI)
tTLOV
tTLOX
Test data-out
(TDO)
Undefined
Don’t Care
Table 42: TAP Input AC Logic Levels
0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V, unless otherwise noted
Description
Symbol
Min
Max
Units
Input HIGH (logic 1) voltage
VIH
VREF + 0.225
-
V
Input LOW (logic 0) voltage
VIL
-
VREF - 0.225
V
Note:
1. All voltages referenced to VSS (GND).
Table 43: TAP AC Electrical Characteristics
0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V
Description
Symbol
Min
Max
Units
Clock cycle time
tTHTH
20
Clock frequency
fTF
50
MHz
Clock HIGH time
tTHTL
10
ns
Clock LOW time
tTLTH
10
ns
TCK LOW to TDO unknown
tTLOX
0
ns
TCK LOW to TDO valid
tTLOV
TDI valid to TCK HIGH
tDVTH
5
ns
TCK HIGH to TDI invalid
tTHDX
5
ns
tMVTH
5
ns
Clock
ns
TDI/TDO times
10
ns
Setup times
TMS setup
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IEEE 1149.1 Serial Boundary Scan (JTAG)
Table 43: TAP AC Electrical Characteristics (Continued)
0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V
Description
Symbol
Min
tCS
5
ns
tTHMX
5
ns
tCH
5
ns
Capture setup
Max
Units
Hold times
TMS hold
Capture hold
Note:
1. tCS and tCH refer to the setup and hold time requirements of latching data from the
boundary-scan register.
Table 44: TAP DC Electrical Characteristics and Operating Conditions
0°C ≤ TC ≤ +95°C; +1.28V ≤ VDD ≤ +1.42V, unless otherwise noted
Description
Condition
Symbol
Min
Max
Units
Notes
Input HIGH (logic 1) voltage
VIH
VREF + 0.15
VDDQ
V
1, 2
Input LOW (logic 0) voltage
VIL
VSSQ
VREF - 0.15
V
1, 2
0V ≤ VIN ≤ VDD
ILI
-5.0
5.0
µA
Output disabled, 0V ≤
VIN ≤ VDDQ
ILO
-5.0
5.0
µA
Input leakage current
Output leakage current
Output low voltage
IOLC = 100µA
VOL1
0.2
V
1
Output low voltage
IOLT = 2mA
VOL2
0.4
V
1
Output high voltage
|IOHC| = 100µA
VOH1
VDDQ - 0.2
V
1
|IOHT| = 2mA
VOH2
VDDQ - 0.4
V
1
OUTPUT HIGH VOLTAGE
Notes:
1. All voltages referenced to VSS (GND).
2. See AC Overshoot/Undershoot Specifications section for overshoot and undershoot limits.
Table 45: Identification Register Definitions
Instruction Field
Revision number (31:28)
All Devices
abcd
Description
ab = 00 for Die Revision A
cd = 00 for x18, 01 for x36
Device ID (27:12)
00jkidef10100111 def = 000 for 576Mb, 001 for 1Gb Double Die Package, 010 for
1Gb Monolithic
i = 0 for common I/O
jk = 10 for RLDRAM 3
ISSI JEDEC ID code (11:1)
ID register presence indicator (0)
000 1101 0101
1
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Enables unique identification of RLDRAM vendor
Indicates the presence of an ID register
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IEEE 1149.1 Serial Boundary Scan (JTAG)
Table 46: Scan Register Sizes
Register Name
Bit Size
Instruction
8
Bypass
1
ID
32
Boundary scan
121
Table 47: Instruction Codes
Instruction
Code
Description
Extest
0000 0000
Captures I/O ring contents; Places the boundary-scan register between TDI and TDO;
This operation does not affect RLDRAM 3 operations.
ID code
0010 0001
Loads the ID register with the vendor ID code and places the register between TDI
and TDO; This operation does not affect RLDRAM 3 operations.
Sample/preload
0000 0101
Captures I/O ring contents; Places the boundary-scan register between TDI and TDO.
Clamp
0000 0111
Selects the bypass register to be connected between TDI and TDO; Data driven by
output balls are determined from values held in the boundary-scan register.
High-Z
0000 0011
Selects the bypass register to be connected between TDI and TDO; All outputs are
forced into High-Z.
Bypass
1111 1111
Places the bypass register between TDI and TDO; This operation does not affect
RLDRAM operations.
Table 48: Boundary Scan (Exit)
Bit#
Ball
Bit#
Ball
Bit#
Ball
1
N8
42
L7
83
M3
2
N8
43
K7
84
M3
3
M11
44
H1
85
M5
4
M11
45
H4
86
M5
5
M9
46
G2
87
L2
6
M9
47
G3
88
L2
7
L12
48
F1
89
L4
8
L12
49
F5
90
L4
9
L10
50
F4
91
L6
10
L10
51
F2
92
L6
11
L8
52
D1
93
K1
12
L8
53
F7
94
K1
13
K13
54
D7
95
K3
14
K13
55
C7
96
K3
15
K11
56
A13
97
J4
16
K11
57
B7
98
J4
Integrated Silicon Solution, Inc. — www.issi.com
01/17/2012
110
576Mb: x18, x36 RLDRAM 3
IEEE 1149.1 Serial Boundary Scan (JTAG)
Table 48: Boundary Scan (Exit) (Continued)
Bit#
Ball
Bit#
Ball
Bit#
Ball
17
J10
58
E7
99
J6
18
J10
59
D13
100
K5
19
J8
60
F12
101
J2
20
K9
61
F10
102
A4
21
J12
62
F9
103
A4
22
A10
63
E2
104
A6
23
A10
64
E12
105
A6
24
A8
65
F6
106
B3
25
A8
66
F8
107
B3
26
B11
67
G7
108
B5
27
B11
68
H7
109
B5
28
B9
69
G5
110
C2
29
B9
70
G9
111
C2
30
C12
71
H6
112
C4
31
C12
72
H8
113
C4
32
C10
73
F13
114
C6
33
C10
74
G11
115
C6
34
C8
75
G12
116
E4
35
C8
76
H10
117
E4
36
E10
77
H3
118
D3
37
E10
78
H11
119
D3
38
D11
79
H13
120
E6
39
D11
80
M7
121
D5
40
E8
81
N6
-
-
41
D9
82
N6
-
-
Integrated Silicon Solution, Inc. — www.issi.com
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576Mb: x18, x36 RLDRAM3
Ordering Information
Table 49: Ordering Information
Commercial Range: TC = 0° to +95°C
Frequency
Speed (tCK)
tRC(min)
8ns
1066 MHz
0.93ns
10ns
8ns
933 MHz
1.07ns
10ns
10ns
800 MHz
1.25ns
12ns
Order Part No.
Organization
Package
IS49RL18320-093EBL
32M x 18
168 FBGA, Lead-free
IS49RL36160-093EBL
16M x 36
168 FBGA, Lead-free
IS49RL18320-093BL
32M x 18
168 FBGA, Lead-free
IS49RL36160-093BL
16M x 36
168 FBGA, Lead-free
IS49RL18320-107EBL
32M x 18
168 FBGA, Lead-free
IS49RL36160-107EBL
16M x 36
168 FBGA, Lead-free
IS49RL18320-107BL
32M x 18
168 FBGA, Lead-free
IS49RL36160-107BL
16M x 36
168 FBGA, Lead-free
IS49RL18320-125EBL
32M x 18
168 FBGA, Lead-free
IS49RL36160-125EBL
16M x 36
168 FBGA, Lead-free
IS49RL18320-125BL
32M x 18
168 FBGA, Lead-free
IS49RL36160-125BL
16M x 36
168 FBGA, Lead-free
Order Part No.
Organization
Package
IS49RL18320-093EBLI
32M x 18
168 FBGA, Lead-free
IS49RL36160-093EBLI
16M x 36
168 FBGA, Lead-free
IS49RL18320-093BLI
32M x 18
168 FBGA, Lead-free
IS49RL36160-093BLI
16M x 36
168 FBGA, Lead-free
IS49RL18320-107EBLI
32M x 18
168 FBGA, Lead-free
Industrial Range: TC = -40° to +95°C
Frequency
Speed (tCK)
tRC(min)
8ns
1066 MHz
0.93ns
10ns
8ns
933 MHz
1.07ns
10ns
10ns
800 MHz
1.25ns
12ns
IS49RL36160-107EBLI
16M x 36
168 FBGA, Lead-free
IS49RL18320-107BLI
32M x 18
168 FBGA, Lead-free
IS49RL36160-107BLI
16M x 36
168 FBGA, Lead-free
IS49RL18320-125EBLI
32M x 18
168 FBGA, Lead-free
IS49RL36160-125EBLI
16M x 36
168 FBGA, Lead-free
IS49RL18320-125BLI
32M x 18
168 FBGA, Lead-free
IS49RL36160-125BLI
16M x 36
168 FBGA, Lead-free
Integrated Silicon Solution, Inc. — www.issi.com
01/17/2012
112
576Mb: x18, x36 RLDRAM 3
Revision History
Revision History
Rev. B, Advance – 10/11
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changed tQKQx,min to tQKQx,max in figure 52 read data valid window
Added Vext information to Note 1 of Input/Output Capacitance table
Added Table 38 tRC_MRS values
Updated tIS/tIH(base) values on page 50 to 85,120,170 & 65,100, 120
Corrected error in High-Z description. replaced "boundry-scan" with "bypass"
Added verbage in SAMPLE/PRELOAD description, specifying which edge of TCK is
used to capture the states of the pins.
Changed JTAG boundary scan order. Now L7=bit 42, K7=bit 43, J6=bit 99, K5=bit 100
Updated Figure 70 "JTAG Operation" to match actual operation of the device.
Changed QKx, QKx# to DKx, DKx# in table 33 & 34 Derating values for tDS/tDH.
Changed Cjtag min from 2.0 to 1.5.
Corrected typo in X36 functional block diagram. Changed DQ1/DK1# to DK1/DK1#.
Added RESET# and MF pin Ci Max spec into Input/Output Capacitance table 6.
Listed QVLD with the QK/QK# signals in Table 6.
Changed tDS Base value from 15 to -15 in Table 33.
Corrected errors in VSEH min, VSEL max and VILdiff(AC) max definitions.
Updated Speed bin table 26 to fill in tCK gaps by adjusting tCKmin values for -107E,
RL=5, -125, RL=6,9,14,15.
Updated table 38 tRC_MRS values to reflect the speed bin table changes
Changed the Cimax (CMD, ADDR) spec from 2.1 to 2.25
Changed the Cjtag max from 5.3 to 4.5
Added X18 & X36 IDD values.
updated tCKQK AC timing specifications.
Added in the thermal impedance values
Rev. A, Advance – 6/11
• Initial release
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01/17/2012
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