HT49RV5/HT49CV5 A/D With VFD Type 8-Bit MCU Technical Document · Tools Information · FAQs · Application Note - HA0077E HT49CVX Remote Control Receiver SWIP Design Note - HA0078E HT49CVX Display SWIP Design Note Features · Operating voltage: · 8-bit prescaler for RTC fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V · Watchdog Timer · Buzzer output · 20 bidirectional I/O lines (PA, PB, PC, PD) · On-chip crystal, RC and 32768Hz crystal oscillator · Two external interrupt inputs · HALT function and wake-up feature reduce power · Two 16-bit programmable timer/event counters with consumption PFD (programmable frequency divider) function · 8-level subroutine nesting · One 8-bit Remote Control Timer (RMT), pin-shared · 4-channel 8-bit resolution A/D converter with PC7 · 2-channel 8-bit PWM output shared with 2 I/O lines · Single channel serial interface · Low voltage reset function · VFD driver with 11´11 segments · Bit manipulation instruction (16-segment & 4-grid to 11-segment & 11-grid) · 16-bit table read instruction · 4K´16 program memory · Up to 0.5ms instruction cycle with 8MHz system clock · 192´8 data memory RAM · 63 powerful instructions · Supports PFD for sound generation · All instructions in 1 or 2 machine cycles · Real Time Clock (RTC) · 56-pin SSOP package General Description driver they are suitable for use in products which require a front panel for their operation such as DVDs, VCDs, Mini-component audio systems, cassette decks, tuners, CD players, other home appliances, etc. The HT49RV5/HT49CV5 are 8-bit high performance single chip MCUs. Their single cycle instruction and 2-stage pipeline architecture make them suitable for high speed applications. As the devices include an VFD Rev. 1.20 1 April 14, 2006 HT49RV5/HT49CV5 Block Diagram In te rru p t C ir c u it M T M R 1 C T M R 1 P F D 1 IN T C M M P U U fS X U M S T A T U S A L U fS U Y S R T C X P D P D P D P D P D P O R T D P D S h ifte r /4 O S C 3 O S C O S C 4 0 / 4 / 5 / 6 / 7 / P W IN IN T M T M M 0 ~ P D 1 /P W T 0 T 1 R 0 R 1 M 1 4 -C h a n n e l A /D C o n v e rte r P B C B P S /4 X P W M P D C T im in g G e n e r a tio n Y S 3 2 7 6 8 H z W D T O S C M U X In s tr u c tio n D e c o d e r Y S P D 6 /T M R 0 D a ta M e m o ry X fS P D 7 /T M R 1 M W D T O S O S V D V S R E X R T C In s tr u c tio n R e g is te r O S C 2 O S C 4 U P F D 0 S ta c k P ro g ra m C o u n te r P ro g ra m R O M P r e s c a le r M T M R 0 C T M R 0 A C C D C 1 C 3 V F D M e m o ry P A C E N /D IS H A L T S E G 1 1 /G r id 1 0 ~ S E G 1 5 /G r id 6 P A 0 P A 1 P A 2 P A 3 P A 4 P O R T A P A V F D D r iv e r G r id 0 ~ G r id 5 P B 0 /A N 0 ~ P B 3 /A N 3 P B S V E E P O R T B /B Z /B Z /P F D ~ P A 7 L V R S E G 0 ~ S E G 1 0 P C C P O R T C P C 6 P C 7 /R M T P C S D I S D O S C K S e r ia l In te r fa c e S C S M U X fS fR 8 - b it R e m o te C o n tr o l T im e r Rev. 1.20 2 Y S /4 T C O S C R M T April 14, 2006 HT49RV5/HT49CV5 Pin Assignment O S C 2 1 5 6 V D D O S C 1 2 5 5 O S C 3 O S C 4 R E S 3 5 4 P A 0 /B Z 4 5 3 S D I P A 1 /B Z 5 5 2 S D O P A 2 6 5 1 S C K P A 3 /P F D 7 5 0 S C S P A 4 8 4 9 G R ID 0 P A 5 9 4 8 G R ID 1 P A 6 1 0 4 7 G R ID 2 P A 7 1 1 4 6 G R ID 3 P B 0 /A N 0 1 2 4 5 G R ID 4 P B 1 /A N 1 1 3 4 4 G R ID 5 P B 2 /A N 2 1 4 4 3 V D D P B 3 /A N 3 1 5 4 2 V E E V S S 1 6 4 1 S E G 1 5 /G R ID 6 P D 0 /P W M 0 1 7 4 0 S E G 1 4 /G R ID 7 P D 1 /P W M 1 1 8 3 9 S E G 1 3 /G R ID 8 P D 4 /IN T 0 1 9 3 8 S E G 1 2 /G R ID 9 P D 5 /IN T 1 2 0 3 7 S E G 1 1 /G R ID 1 0 P D 6 /T M R 0 2 1 3 6 S E G 1 0 P D 7 /T M R 1 2 2 3 5 S E G 9 V S S 2 3 3 4 S E G 8 P C 6 2 4 3 3 S E G 7 P C 7 /R M T 2 5 3 2 S E G 6 S E G 0 2 6 3 1 S E G 5 S E G 1 2 7 3 0 S E G 4 S E G 2 2 8 2 9 S E G 3 H T 4 9 R V 5 /H T 4 9 C V 5 5 6 S S O P -A Note: Each VDD (VSS) pins must be connected to the power (ground) of the system. Pin Description Pin Name PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7 PB0/AN0~ PB3/AN3 PC6 PC7/RMT Rev. 1.20 I/O Options Description I/O Wake-up Pull-high Buzzer PFD Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by configuration option. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option). Pins PA0, PA1 and PA3 are pin-shared with BZ, BZ and PFD, respectively. Pull-high Bidirectional 4-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high option: bit option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and pull-high resistor are disabled automatically. I/O I/O Pull-high Bidirectional 2-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high option: bit option). RMT with wake-up function (both rising and falling edge) and Schmitt trigger input with or without a pull-high resistor (determined by pull-high option). Note:The RMT is pin-shared with PC7. When PC7/RMT pin uses as the input mode of RMT function , suggesting the user to set PC7 as input mode for safety. And so that I/O function of PC7 will not influence the RMT input function. 3 April 14, 2006 HT49RV5/HT49CV5 Pin Name PD0/PWM0 PD1/PWM1 I/O I/O Options Description Pull-high PWM Bidirectional 2-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: bit option). PD0~PD1 are pin-shared with PWM0~PWM1 (dependent on Mask options). Bidirectional 4-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: bit option). Pins PD4~PD7 are pin-shared with INT0, INT1, TMR0 & TMR1, respectively (determined by software control). PD4/INT0 PD5/INT1 PD6/TMR0 PD7/TMR1 I/O Pull-high VSS ¾ ¾ Negative power supply, ground VEE ¾ ¾ VFD Negative power supply SEG0~SEG10 O ¾ High voltage segment output for VFD panel. SEG11/Grid10~ SEG15/Grid6 O ¾ High voltage output for VFD panel. These pins are selectable for segment or grid output. Grid0~Grid5 O ¾ High voltage grid output for VFD panel. SDI I ¾ Serial interface serial data input SDO O ¾ Serial interface serial data output SCK I/O ¾ Serial interface serial clock input/output (initial ²input²). SCS I/O ¾ Serial interface chip select pin, output for master mode, input for slave mode. OSC4 OSC3 O I VDD ¾ ¾ OSC2 OSC1 O I Crystal or RC RES I ¾ Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz RTC or crystal oscillator for timing purposes or to a system clock source (depending System Clock on the options). No built-in capacitor. Positive power supply OSC1 and OSC2 are connected to an RC network or a crystal (by options) for the internal system clock. For RC operation, OSC2 is an output pin for 1/4 system clock. The system clock may come from the RTC oscillator. If the system clock comes from RTCOSC, these two pins can be left floating. Schmitt trigger reset input, active low Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°C to 125°C Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.20 4 April 14, 2006 HT49RV5/HT49CV5 D.C. Characteristics Symbol Parameter VDD Operating Voltage VEE VFD Supply Voltage IDD1 Operating Current (Crystal OSC) IDD2 Operating Current (RC OSC) IDD3 Operating Current (fSYS=32768Hz) Ta=25°C Test Conditions VDD Conditions Min. Typ. Max. Unit ¾ fSYS=4MHz 2.2 ¾ 5.5 V ¾ fSYS=8MHz 3.3 ¾ 5.5 V ¾ 0 ¾ VDD-30 V No load, ADC off, VFD off, fSYS=4MHz ¾ 2.0 3.0 mA ¾ 5.0 8.0 mA No load, ADC off, VFD off, fSYS=4MHz ¾ 1.8 2.7 mA ¾ 4.6 7.5 mA ¾ 1.2 2 mA ¾ 3V 5V 3V 5V 3V 5V 3V IDD4 Operating Current (Crystal OSC) ISTB1 Standby Current (*fS=T1) ISTB2 Standby Current (*fS=32768Hz OSC) 3V VIL1 Input Low Voltage for I/O Ports, TMR and INT 3V VIH1 Input High Voltage for I/O Ports, TMR and INT 3V VIL2 Input Low Voltage (RES) VIH2 Input High Voltage (RES) IOL I/O Port Sink Current 5V 3V 5V 5V No load, ADC off, VFD off ¾ 4 7 mA No load, ADC off, VFD on, fSYS=4MHz ¾ 3.5 4.5 mA ¾ 7.5 12 mA No load, system HALT VFD off at HALT ¾ ¾ 1 mA ¾ ¾ 2 mA No load, system HALT VFD off at HALT ¾ 4 10 mA ¾ 14 20 mA ¾ 0 ¾ 0.2VDD V ¾ 0.8VDD ¾ VDD V ¾ 0 ¾ 0.4VDD V ¾ 0.9VDD ¾ VDD V 6 12 ¾ mA 10 25 ¾ mA -2 -4 ¾ mA -5 -8 ¾ mA 5V 5V 3V 5V 3V 5V 3V 5V 3V VOL=0.1VDD VOH=0.9VDD IOH1 I/O Port Source Current IOH2 Grid Source Current 5V VOH=VDD-2V -15 ¾ ¾ mA IOH3 Segment Source Current 5V VOH=VDD-2V -3 ¾ ¾ mA RPH Pull-high Resistance of I/O Ports and INT0, INT1 3V ¾ 20 60 100 kW 5V ¾ 10 30 50 kW RPL VFD Driver Output Pull-low Resistor 5V ¾ 50 100 150 kW VLVR Low Voltage Reset Voltage ¾ 2.7 3.0 3.3 V VAD A/D Input Voltage ¾ 0 ¾ VDD V ¾ ¾ ±0.5 ±1 LSB ¾ 1 2 mA ¾ 2 4 mA EAD A/D Conversion Error IADC Additional Power Consumption if A/D Converter is Used Note: 5V LVR enabled ¾ 3V 5V 3V 5V No load ²*fS² Refer to WDT clock option Rev. 1.20 5 April 14, 2006 HT49RV5/HT49CV5 A.C. Characteristics Ta=25°C Test Conditions Symbol Parameter fSYS1 System Clock Typ. Max. Unit ¾ 2.2V~5.5V 400 ¾ 4000 kHz ¾ 3.3V~5.5V 400 ¾ 8000 kHz 2.2V~5.5V ¾ 32768 ¾ Hz ¾ 32768 ¾ Hz fSYS2 System Clock (32768Hz Crystal OSC) ¾ fRTCOSC RTC Frequency ¾ fTIMER Timer I/P Frequency (TMR0/TMR1) tWDTOSC Watchdog Oscillator Period Min. Conditions VDD ¾ ¾ 2.2V~5.5V 0 ¾ 4000 kHz ¾ 3.3V~5.5V 0 ¾ 8000 kHz 3V ¾ 45 90 180 ms 5V ¾ 32 65 130 ms tRES External Reset Low Pulse Width ¾ ¾ 1 ¾ ¾ ms tSST System Start-up Timer Period ¾ Power-up or wake-up from HALT ¾ 1024 ¾ tSYS tINT Interrupt Pulse Width ¾ ¾ 1 ¾ ¾ ms tAD A/D Clock Period ¾ ¾ 1 ¾ ¾ ms tADC A/D Conversion Time ¾ ¾ ¾ 76 ¾ tAD tADCS A/D Sampling Time ¾ ¾ ¾ 32 ¾ tAD Note: tSYS= 1/fSYS Rev. 1.20 6 April 14, 2006 HT49RV5/HT49CV5 Functional Description Execution Flow executed and its contents specify a maximum of 4096 addresses. The system clock is derived from either a crystal or an RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme ensures that instructions are effectively executed in one cycle. Exceptions to this are instructions that change the contents of the program counter, such as subroutine calls or jumps, in which case, two cycles are required to complete the instruction. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, etc., the microcontroller manages program control by loading the address corresponding to each instruction. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the current instruction execution, is discarded and a dummy cycle replaces it while the proper instruction is obtained. Otherwise proceed with the next instruction. Program Counter - PC The 12-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are S y s te m O S C 2 (R C C lo c k T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 o n ly ) P C P C P C + 1 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) P C + 2 F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Program Counter Mode *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 Initial Reset 0 0 0 0 0 0 0 0 0 0 0 0 External Interrupt 0 0 0 0 0 0 0 0 0 0 1 0 0 External Interrupt 1 0 0 0 0 0 0 0 0 1 0 0 0 Timer/Event Counter 0 Overflow 0 0 0 0 0 0 0 0 1 1 0 0 Timer/Event Counter 1 Overflow 0 0 0 0 0 0 0 1 0 0 0 0 Serial Interface Interrupt 0 0 0 0 0 0 0 1 0 1 0 0 Multi-function Interrupt 0 0 0 0 0 0 0 1 1 0 0 0 Skip Program Counter+2 Loading PCL *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 1.20 S11~S0: Stack register bits @7~@0: PCL bits 7 April 14, 2006 HT49RV5/HT49CV5 The lower byte of the program counter (PCL) is available for program control and is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. · Location 008H When a control transfer takes place, an additional dummy cycle is required. · Location 00CH This area is reserved for the external interrupt service program. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program will jump to this location and begin execution. This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution. Program Memory - EPROM The program memory (EPROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 4096´16 bits format. The program counter is composed of 12 bits, so it can directly access the whole program memory without changing banks. · Location 010H This area is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution. Certain locations in the ROM are reserved for special usage: · Location 014H · Location 000H This area is reserved for the Serial Interface interrupt service program. If 8 bits of data have been received or transmitted successfully from the serial interface, and the interrupt is enabled, and the stack is not full, the program will jump to this location and begin execution. This area is reserved for use by the chip reset for program initialization. After a chip reset is initiated, the program will jump to this location and begin execution. · Location 004H This area is reserved for the external interrupt service program. If the INT0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program will jump to this location and begin execution. 0 0 0 H E x te r n a l In te r r u p t 0 S u b r o u tin e 0 0 8 H 0 1 0 H This area is reserved for the multi-function interrupt. If a real time clock interrupt occurs, or if a rising edge is detected from the RMT input pin, or if a falling edge is detected from the RMT input pin, or if the RMT overflow and the related interrupts are enabled, and the stack is not full, the program will jump to this location and begin execution. D e v ic e In itia liz a tio n P r o g r a m 0 0 4 H 0 0 C H · Location 018H E x te r n a l In te r r u p t 1 S u b r o u tin e · Table location T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e 0 1 4 H S e r ia l In te r fa c e In te r r u p t 0 1 8 H Any location within the program memory can be used as a look-up table where programmers can store fixed data. The instructions ²TABRDC [m]² (the current page, 1 page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are all transferred to the lower portion of TBLH. The TBLH is a read only register and the table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in the TBLP. All table re- P ro g ra m R O M M u lti- fu n c tio n In te r r u p t n 0 0 H L o o k - u p T a b le ( 2 5 6 W o r d s ) n F F H L o o k - u p T a b le ( 2 5 6 W o r d s ) F F F H 1 6 b its N o te : n ra n g e s fro m 0 to F Program Memory Table Location Instruction(s) *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits Rev. 1.20 P11~P8: Current program counter bits 8 April 14, 2006 HT49RV5/HT49CV5 0 0 H lated instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon user¢s requirements. Stack Register - STACK The stack register is a special part of the memory used to save the contents of the Program Counter. The stack is organized into 8 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At the start of a subroutine call or an interrupt acknowledgment, the contents of the Program Counter is pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the Program Counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a ²CALL² is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent 8 return addresses are stored). In d ir e c t A d d r e s s in g R e g is te r 0 0 1 H M P 0 0 2 H In d ir e c t A d d r e s s in g R e g is te r 1 0 3 H M P 1 0 4 H B P 0 5 H A C C 0 6 H P C L 0 7 H T B L P 0 8 H T B L H 0 9 H R T C C 0 A H S T A T U S 0 B H IN T C 0 0 C H T M R 0 H 0 D H T M R 0 L 0 E H T M R 0 C 0 F H T M R 1 H 1 0 H T M R 1 L 1 1 H T M R 1 C 1 2 H P A 1 3 H P A C 1 4 H P B 1 5 H P B C 1 6 H P C 1 7 H P C C 1 8 H P D 1 9 H P D C 1 A H P W M 0 1 B H P W M 1 S p e c ia l P u r p o s e D a ta M e m o ry 1 C H 1 D H Data Memory - RAM 1 E H The data memory (RAM) has a capacity of 231´8 bits, and is divided into two functional groups, namely; special function registers (39´8 bit) and general purpose data memory (RAM bank contains 192´8 bits) most of which are readable/writeable, but some are read only. The special function registers are overlapped in any banks. S B C R 2 0 H S B D R 2 1 H R M T C 2 2 H R M T 0 2 3 H R M T 1 2 4 H The special function registers consist of an Indirect addressing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an Accumulator (ACC;05H), a Program counter lower-order byte register (PCL;06H), a Table pointer (TBLP;07H), a Table higher-order byte register (TBLH;08H), a Real time clock control register (RTCC;09H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), a Timer/Event Counter 0 (TMR0H:0CH; TMR0L:0DH), a Timer/Event Counter 0 control register (TMR0C;0EH), a Timer/Event Counter 1 (TMR1H:0FH;TMR1L:10H), a Timer/Event Counter 1 control register (TMR1C; 11H), Interrupt control register 1 (INTC1;1EH), Serial Bus control register (SBCR;1FH), Serial Bus data register (SBDR; 20H), Remote timer control register (RMTC;21H), Remote control capture register 0 (RMT0;22H), Remote control Rev. 1.20 IN T C 1 1 F H 2 5 H A D R 2 6 H A D C R 2 7 H A C S R 2 8 H V F D C 2 9 H M F IS 3 0 H 3 F H 4 0 H F F H G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s ) : U n u s e d R e a d a s "0 0 " RAM Mapping capture register 1 (RMT1;23H), Multi-function interrupt status register (MFIS;29H), PWM data register (PWM0;1AH, PWM1;1BH), the A/D result register (ADR;25H), the A/D control register (ADCR;26H), the A/D clock setting register (ACSR;27H), VFD control register (VFDC; 28H), I/O registers (PA;12H, PB;14H, PC;16H, PD;18H) and I/O control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H). 9 April 14, 2006 HT49RV5/HT49CV5 Arithmetic and Logic Unit - ALU The remaining space before 40H is reserved for future expanded usage and reading these locations will return the result ²00H². The space before 40H overlaps in each bank. The general-purpose data memory, addressed from 40H to FFH (Bank0; BP=0), is used for data and control information under instruction commands. This circuit performs 8-bit arithmetic and logic operations and provides the following functions: · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Logic operations (AND, OR, XOR, CPL) · Rotation (RL, RR, RLC, RRC) · Increment and Decrement (INC, DEC) All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through memory pointer registers (MP0;01H/MP1;03H). · Branch decision (SZ, SNZ, SIZ, SDZ etc.) The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS The status register (0AH) is 8 bits wide and contains a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1(03H), respectively. Reading location 00H or 02H indirectly returns the result 00H. Writing indirectly leads to no operation. Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing a ²HALT² instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory, while MP1 can be applied to data memory and VFD display memory. On entering an interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. Accumulator - ACC The accumulator (ACC) is closely related with operations carried out by the ALU. It is mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Bit No. Label Function 0 C C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction. 1 AC AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise AC is cleared. 2 Z 3 OV OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared. 4 PDF PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction. 5 TO TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. 6~7 ¾ Unused bit, read as ²0² Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared. Status (0AH) Register Rev. 1.20 10 April 14, 2006 HT49RV5/HT49CV5 data from a serial interface. After the interrupt is enabled, and the stack is not full, and the TRF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (TRF) is reset and the EMI bit is cleared to disable further maskable interrupts. Interrupts The HT49RV5/HT49CV5 provides two external interrupts, two internal timer/event counter interrupts, three remote control timer interrupts, an internal real time clock interrupt and serial interface interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. The multi-function interrupt is initialized by setting the interrupt request flag (MFF; bit 6 of INTC1), which is caused by a regular real time clock signal, or caused by a rising edge of RMT, or caused by a falling edge of RMT, or caused by an RMT overflow. After the interrupt is enabled, and the stack is not full, and the MFF bit is set, a subroutine call to location 18H occurs. The related interrupt request flag (MFF) is reset and the EMI bit is cleared to disable further maskable interrupts. Once an interrupt subroutine is serviced, all other interrupts are blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If another interrupt requires servicing while the program is in the interrupt service routine, the programmer should set the EMI bit and the corresponding bit of the INTC0 or INTC1 to allow interrupt nesting. Once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full. During the execution of an interrupt subroutine, other maskable interrupt acknowledgments are all held until the ²RETI² instruction is executed or the EMI bit and the related interrupt control bit are both set to 1 (if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. All these interrupts can support a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the Program Counter onto the stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the Program Counter is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. Interrupt Source External interrupts are triggered by an edge transition of INT0 or INT1 (configuration option: high to low, low to high, low to high or high to low), and the related interrupt request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other maskable interrupts. Vector External interrupt 0 1 04H External interrupt 1 2 08H Timer/Event Counter 0 overflow 3 0CH Timer/Event Counter 1 overflow 4 10H Serial Interface interrupt 5 14H Multi-function interrupt 6 18H The RMT overflow interrupt flag (RMTVF; bit 0 of MFIS), real time clock interrupt flag (RTF; bit 1 of MFIS), the RMT rising edge interrupt flag (RMT0F; bit 2 of MFIS) and the RMT falling edge interrupt flag (RMT1F; bit 3 of MFIS) indicate that a related interrupt has occurred. After reading these flags, these flags will not be cleared automatically, they should be cleared by the user. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 6 of INTC0), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is cleared to disable other maskable interrupts. Timer/Event Counter 1 is operated in the same manner but its related interrupt request flag is T1F (bit 4 of INTC1) and its subroutine call location is 10H. The serial interface interrupt is indicated by the interrupt flag (TRF; bit 5 of INTC1), that is caused by receiving or transferring a complete 8-bit data transfer between the HT49RV5/ HT49CV5 and an external device. After the interrupt is enabled (by setting ESBI; bit 1 of INTC1), and the stack is not full, a subroutine call to location 14H occurs. TRF is set by SIO and should be cleared by users. The Serial Interface interrupt is initialized by setting the interrupt request flag (TRF; bit 5 of INTC1), which is caused by completely receiving or transferring 8 bits of Rev. 1.20 Priority The Timer/Event Counter 0 interrupt request flag (T0F), external interrupt 1 request flag (EIF1), external interrupt 0 request flag (EIF0), enable Timer/Event Counter0 11 April 14, 2006 HT49RV5/HT49CV5 Bit No. Label 0 EMI Control the master (global) interrupt (1=enabled; 0=disabled) Function 1 EEI0 Control the external interrupt 0 (1=enabled; 0=disabled) 2 EEI1 Control the external interrupt 1 (1=enabled; 0=disabled) 3 ET0I Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) 4 EIF0 External interrupt 0 request flag (1=active; 0=inactive) 5 EIF1 External interrupt 1 request flag (1=active; 0=inactive) 6 T0F Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) 7 ¾ For test mode used only. Must be written as ²0²; otherwise may result in unpredictable operation. INTC0 (0BH) Register Bit No. Label 0 ET1I Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) Function 1 ESBI Control the serial interface interrupt (1=enabled; 0=disabled) 2 EMFI 3, 7 ¾ Control the real multi-function interrupt (1=enabled; 0=disabled) Unused bit, read as ²0² 4 T1F Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) 5 TRF Serial bus data transferred or data received interrupt request flag (1=active; 0=inactive) 6 MFF Multi-function interrupt request flag (1=active; 0=inactive) INTC1 (1EH) Register Bit No. Label 0 ¾ 1 ERMT0 2 ERMT1 Controls the remote control timer falling edge interrupt (1=enable; 0=disable) 3 ERMTV Controls the remote control timer overflow interrupt (1=enable; 0=disable) 4 RME 5 RMCS Selects the remote control timer clock source fX (1=fSYS; 0=fSYS/4) RMS0 RMS1 Selects the remote control timer clock 00=fX/25 01= fX/26 10= fX/27 11= fX/28 6 7 Function Unused bit, read as ²0² Controls the remote control timer rising edge interrupt (1=enable; 0=disable) Controls the remote control timer (1=enable; 0=disable) 1=enable & start counting; 0= disable & clear counter to 0 RMTC (21H) Register Bit No. Label Function Remote control timer overflow interrupt flag (1=indicates that an overflow has occurred; 0=indicates that an overflow has not occurred) 0 RMTVF 1 RTF 2 RMT0F Remote control timer rising edge interrupt flag (1=indicates that a rising edge interrupt has occurred; 0=indicates that a rising edge interrupt has not occurred) 3 RMT1F Remote control timer falling edge interrupt flag (1=indicates that a falling edge interrupt has occurred; 0=indicates that a falling edge interrupt has not occurred) 4 ERTI 5~7 ¾ Real time clock interrupt flag (1=indicates that an RTC interrupt has occurred; 0=indicates that an RTC interrupt has not occurred) Controls the real time clock interrupt (1=enable; 0=disable) Unused bit, read as ²0² MFIS (29H) Register Rev. 1.20 12 April 14, 2006 HT49RV5/HT49CV5 interrupt bit (ET0I), enable external interrupt 1 bit (EEI1), enable external interrupt 0 bit (EEI0), and enable master interrupt bit (EMI) constitute the Interrupt Control register 0 (INTC0) which is located at 0BH in the RAM. signal is used for the system clock. The HALT mode stops the system oscillator (RC and crystal oscillator only) and ignores external signals so as to conserve power. The 32768Hz crystal oscillator still runs in the HALT mode. If the 32768Hz crystal oscillator is selected as the system oscillator, the system oscillator is not stopped but the instruction execution is stopped. Since the 32768Hz oscillator is also designed for timing purposes, the internal timing (RTC, WDT) operation still runs even if the system enters the HALT mode. The multi-function interrupt request flag (MFF), serial interface interrupt request flag (TRF), Timer/Event Counter 1 interrupt request flag (T1F), enable multi-function interrupt (EMFI), enable serial interface interrupt bit (ESBI), and enable Timer/Event Counter 1 interrupt bit (ET1I), constitute the Interrupt Control register 1 (INTC1) which is located at 1EH in the RAM. Of the three oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 56kW to 1.5MW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore not suitable for timing sensitive operations where accurate oscillator frequency is desired. The enable Remote control timer rising edge interrupt (ERMT0), enable Remote control timer falling edge interrupt (ERMT1), enable Remote control timer overflow interrupt (ERMTV), enable Remote control timer start counting (RME), select the Remote control timer clock source (RMCS), and select the Remote control timer clock (RMS0, RMS1) constitute the Remote Timer control Register (RMTC) which is located at 21H in the RAM. E M I , EE I 0, E E I 1, E T0I , E T1I , S B E N , E RT I , EMFI,ERMT0 and ERMT1 are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (MFF, TRF, T0F, T1F, EIF1, EIF0) are all set, they remain in the INTC0~INTC1 respectively until the interrupts are serviced or cleared by a software instruction. On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors on OSC1 and OSC2 are required. There is another oscillator circuit designed for the real time clock. In this case, only a 32768Hz crystal oscillator can be applied. The crystal should be connected between OSC3 and OSC4. It is recommended that a program should not use the ²CALL subroutine² within the interrupt subroutine. This is because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. During that period, if only one stack is left, and enabling the interrupt is not well controlled, operation of the ²CALL² in the interrupt subroutine may damage the original control sequence. The RTC oscillator circuit can be controlled to start-up quickly by setting the ²QOSC² bit (bit 4 of RTCC). It is recommended to turn on the quick start-up function during power-on, and then turn it off after 2 seconds. The WDT oscillator is a free running on-chip RC oscillator and no external components are required. Although the system enters the power down mode, the system clock stops and the WDT oscillator still works with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by options so as to conserve power. Oscillator Configuration The HT49RV5/HT49CV5 provides three oscillator circuits for system clocks, i.e., RC oscillator, crystal oscillator and 32768Hz crystal oscillator, determined by options. No matter what type of oscillator is selected, the O S C 3 O S C 1 O S C 4 O S C 2 3 2 7 6 8 H z C r y s ta l/R T C O s c illa to r O S C 1 fS Y S /4 C r y s ta l O s c illa to r O S C 2 R C O s c illa to r System Oscillator Note: 32768Hz crystal enable condition: For WDT clock source or for system clock source. The external resistor and capacitor components connected to the 32768Hz crystal are not necessary to provide oscillation. For applications where precise RTC frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. Rev. 1.20 13 April 14, 2006 HT49RV5/HT49CV5 Watchdog Timer - WDT Multi-function Timer The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by options. But if the WDT is disabled, all executions related to the WDT lead to no operation. The HT49RV5/HT49CV5 provides a multi-function timer for the and RTC but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from the RTC OSC or the instruction clock (i.e., system clock divided by 4). The multi-function timer also provides a selectable frequency signal (ranging from fS/20 to fS/27) for the VFD driver circuits, and a selectable frequency signal (ranging from fS/21 to fS/28) for the buzzer output by options. It is recommended to select a frequency as close as possible to 32kHz for the VFD driver circuits to obtain good display clarity. Once an internal WDT oscillator (RC oscillator with a period of 65ms at 5V) is selected, it is divided by 212~215 (by configuration option to get the WDT time-out period). The minimum WDT time-out period is 300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selecting the WDT configuration option, longer time-out periods can be realized. If the WDT time-out is selected, 215, the maximum time-out period is divided by 215~216 which is 2.3s~4.7s. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operates in the same manner except that in the halt state the WDT may stop counting and lose its protecting purposes. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended since the HALT will stop the system clock. fS R O M C lo c k /4 R T C O S C 3 2 7 6 8 H z C o n fig u r a tio n O p tio n C o d e O p tio n V F D D r iv e r ( fS /2 0 ~ fS /2 7 ) B u z z e r (fS /2 1~ fS /2 8) Real Time Clock - RTC The real time clock (RTC) is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by software programming. Writing data to RT2, RT1 and RT0 (bits 2, 1, 0 of RTCC; 09H) yields various time-out periods. If the RTC time-out occurs and the interrupt is enabled, the related interrupt request flag (RTF; bit 1 of MFIS) is set and the multi-function interrupt request flag (MFF; bit 6 of INTC1) is set. If the interrupt (EMFI) is enabled, and the stack is not full, a subroutine call to location 18H occurs. The WDT overflow under normal operation initializes a ²chip reset² and sets the status bit ²TO². In the HALT mode, the overflow initializes a ²warm reset², and only the Program Counter and SP are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to RES), software instruction, and a ²HALT² instruction. There are two types of software instructions; ²CLR WDT² and the other set - ²CLR WDT1² and ²CLR WDT2². Of these two types of instruction, only one type of instruction can be active at a time depending on the options - ²CLR WDT² times selection option. If the ²CLR WDT² is selected (i.e., CLR WDT times is equal to one), any execution of the ²CLR WDT² instruction clears the WDT. In the case where the two ²CLR WDT1² and ²CLR WDT2² instructions are chosen (i.e., CLR WDT times is equal to two), these two instructions have to be executed to clear the WDT, otherwise, the WDT may reset the chip due to time-out. S y s te m D iv id e r RT2 RT1 RT0 RTC Clock Divided Factor 0 0 0 2 8* 0 0 1 2 9* 0 1 0 210* 0 1 1 211* 1 0 0 212 1 0 1 213 1 1 0 214 1 1 1 215 Note: * not recommended to be used fS C o n fig u r a tio n O p tio n fW fW D T D T /2 D iv id e r W D T 1 2 k H z O S C 8 W D T P r e s c a le r M a s k O p tio n W D T C le a r C K T R C K T R T im e - o u t fW D T /2 15~ fW D T /2 14~ fW D T /2 13~ fW D T /2 12~ R e s e t fW D T /2 1 fW D T /2 1 fW D T /2 1 fW D T /2 1 6 5 4 3 Watchdog Timer Rev. 1.20 14 April 14, 2006 HT49RV5/HT49CV5 fS D iv id e r P r e s c a le r R T 2 R T 1 R T 0 8 to 1 M u x . fS /2 8~ fS /2 15 R T C In te rru p t Real Time Clock The RTCC register descriptions are listed below. Bit No. Label Read/ Write Reset Function 0~2 RT0~RT2 R/W 1 8 to 1 multiplexer control inputs to select the real clock prescaler output 3, 5~7 ¾ ¾ ¾ Unused bit, read as ²0² 4 QOSC R/W 0 32768Hz OSC quick start-up oscillator 0/1: quick/slow start RTCC (09H) Register Power Down Operation - HALT interrupt is enabled and the stack is not full, the regular interrupt response takes place. The HALT mode is initialized by the ²HALT² instruction and results in the following. If an interrupt request flag is set to ²1² before entering the ²HALT² mode, the wake-up function of the related interrupt will be disabled. · The system oscillator turns off but the WDT oscillator keeps running (if the WDT oscillator or the real time clock is selected). If a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. However, if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. · The contents of the on-chip RAM and of the registers remain unchanged. · The WDT is cleared and starts recounting (if the WDT clock source is from the WDT oscillator or the real time clock oscillator). · All I/O ports maintain their original status. · The PDF flag is set but the TO flag is cleared. · The VFD driver keeps running (if the RTC OSC is se- To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT mode. lected). The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A, an external rising/falling edge on the RMT pin, or a WDT overflow. An external reset will initialize a chip reset and a WDT overflow will initialize a ²warm reset². After examining the TO and PDF flags, the source of the reset can be determined. The PDF flag is cleared by a system power-up or by executing the ²CLR WDT² instruction, and is set by executing the ²HALT² instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and SP, the other flags remain in their original status. Reset There are three ways in which a microcontroller reset can occur, through events occurring both internally and externally: · RES is reset during normal operation · RES is reset during HALT · WDT time-out is reset during normal operation The WDT time-out reset during HALT is a little different from other kinds of reset. Most of the conditions remain unchanged except that the program counter and stack pointer will be cleared to 0 and the TO flag will be set to 1. Most registers are reset to the ²initial condition² once the reset conditions are met. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by options. Awakening from an I/O port stimulus, the program will resume execution at the next instruction. If the system is woken up via an interrupt, two possibilities may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. But if the Rev. 1.20 The different types of resets described affect the reset flags in different ways. These flags, the PDF and TO flags, are located in the status register and are controlled by various microcontroller operations such as the HALT function or Watchdog Timer. 15 April 14, 2006 HT49RV5/HT49CV5 V The reset flags are shown in the table: TO PDF 0 0 RES reset during power-up u u RES reset during normal operation 0 1 RES Wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT Wake-up HALT D D 0 .0 1 m F * RESET Conditions 1 0 0 k W R E S 1 0 k W 0 .1 m F * Reset Circuit Note: ²u² stands for unchanged Note: To ensure that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system awakes from the HALT state or during power-on. V D D An extra SST delay is added during the power-on period, and any wake-up from HALT may enable only the SST delay. R E S 000H Interrupt Disabled Prescaler, Divider Cleared WDT Clear. After master reset, WDT begins counting tS S T S S T T im e - o u t The functional unit chip reset status is shown below. Program Counter ²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. C h ip R e s e t Reset Timing Chart H A L T W D T W a rm W D T T im e - o u t R e s e t E x te rn a l R E S Timer/Event Counter Off Input/Output Ports Input mode Stack Pointer Points to the top of the stack R e s e t C o ld R e s e t S S T 1 0 - b it R ip p le C o u n te r O S C 1 P o w e r - o n D e te c tio n Reset Configuration The register states are summarized below: Register Reset (Power-on) WDT Time-out RES Reset (Normal Operation) (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* TMR0H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR0L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR0C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu TMR1H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR1L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR1C 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- Program Counter 0000H 0000H 0000H 0000H 0000H MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu BP --0- -000 --0- -000 --0- -000 --0- -000 --u- -uuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu Rev. 1.20 16 April 14, 2006 HT49RV5/HT49CV5 Register INTC0 Reset (Power-on) WDT Time-out RES Reset (Normal Operation) (Normal Operation) -000 0000 -000 0000 -000 0000 RES Reset (HALT) WDT Time-out (HALT)* -000 0000 -uuu uuuu INTC1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu RMTC 0000 000- 0000 000- 0000 000- 0000 000- uuuu uuu- MFIS ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu RTCC ---0 -111 ---0 -111 ---0 -111 ---0 -111 ---u -uuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu PBC ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu PC 11-- ---- 11-- ---- 11-- ---- 11-- ---- uu-- ---- PCC 11-- ---- 11-- ---- 11-- ---- 11-- ---- uu-- ---- PD 1111 --11 1111 --11 1111 --11 1111 --11 uuuu --uu PDC 1111 --11 1111 --11 1111 --11 1111 --11 uuuu --uu PWM0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PWM1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SBCR 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu SBDR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu RMT0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu RMT1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ADR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADCR 01-0 0-00 01-0 0-00 01-0 0-00 01-0 0-00 uu-u u-uu ACSR 1--- --00 1--- --00 1--- --00 ---- --00 u--- --uu VFDC 0000 -111 0000 -111 0000 -111 0000 -111 0000 -111 Note: ²*² stands for ²warm reset² ²u² stands for ²unchanged² ²x² stands for ²unknown² Timer/Event Counter and the contents of the lower-order byte buffer to TMR0H (TMR1H) and TMR0L (TMR1L) registers, respectively. The Timer/Event Counter 1/0 preload register is changed by each writing TMR0H (TMR1H) operations. Reading TMR0H (TMR1H) will latch the contents of TMR0H (TMR1H) and TMR0L (TMR1L) counters to the destination and the lower-order byte buffer, respectively. Reading the TMR0L (TMR1L) will read the contents of the lower-order byte buffer. The TMR0C (TMR1C) is the Timer/Event Counter 0 (1) control register, which defines the operating mode, counting enable or disable and an active edge. Two timer/event counters (TMR0,TMR1) are implemented in the microcontroller. The Timer/Event Counter 0 contains a 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS. The Timer/Event Counter 1 contains a 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS/4 or 32768Hz selected by option. The external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. The TM0 and TM1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0, TMR1), and the counting is based on the internal selected clock source. There are six registers related to the Timer/Event Counter 0 and Timer/Event Counter 1; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH) and the Timer/Event Counter 1, TMR1H (0FH), TMR1L (10H), and TMR1C (11H). Writing TMR0L (TMR1L) will only place the written data to an internal lower-order byte buffer (8-bit) and writing TMR0H (TMR1H) will transfer the specified data Rev. 1.20 17 April 14, 2006 HT49RV5/HT49CV5 The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the TON bit is set. The cycle measurement will continue as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., the event and timer modes. In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFFFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F; bit 6 of INTC0, T1F; bit 4 of INTC1). In the pulse width measurement mode with the values of the TON and TE bits equal to 1, after the TMR0 (TMR1) has received a transient from low to high (or high to low if the TE bit is ²0²), it will start counting until the TMR0 (TMR1) returns to the original level and resets the TON. Bit No. 0~2 Label 3 T0E 4 T0ON 5 ¾ 6 7 Function Defines the prescaler stages. T0PSC2, T0PSC1, T0PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 T0PSC0~ 010: fINT=fSYS/4 T0PSC2 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 T0M0 T0M1 Defines the TMR0 active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T0M1,T0M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0=disable; 1=enable) Unused bit, read as ²0² Defines the operating mode (T0M1, T0M0) 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR0C (0EH) Register Bit No. Label 0~2 ¾ 3 T1E 4 T1ON 5 T1S 6 7 T1M0 T1M1 Function Unused bit, read as ²0² Defines the TMR1 active edge of the timer/event counter: In Event Counter Mode (T1M1,T1M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0= disable; 1= enable) Defines the TMR1 internal clock source (0=fSYS/4; 1=32768Hz) Defines the operating mode (T1M1, T1M0) 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR1C (11H) Register Rev. 1.20 18 April 14, 2006 HT49RV5/HT49CV5 When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1 register first, before turning on the related timer/event counter, for proper operation since the initial value of the TMR0/TMR1 is unknown. Due to the timer/event counter scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event counter function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. To enable the counting operation, the Timer on bit (TON; bit 4 of TMR0C or TMR1C) should be set to 1. In the pulse width measurement mode, TON is automatically cleared after the measurement cycle is completed. But in the other two modes, TON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider) output at PA3 by options. Only one PFD (PFD0 or PFD1) can be applied to PA3 by options. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. When the PFD function is selected, executing ²SET [PA].3² instruction will enable the PFD output and executing ²CLR [PA].3² instruction will disable the PFD output. Bits 2~0 of the TMR0C can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. The definitions are as shown. The overflow signal of the timer/event counter can be used to generate the PFD signal. The timer prescaler is also used as the PWM counter. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. P W M (6 + 2 ) o r (7 + 1 ) C o m p a re fS T o P D 0 /P D 1 8 - s ta g e P r e s c a le r Y S f IN 8 -1 M U X T 0 P S C 2 ~ T 0 P S C 0 D a ta B u s T T 0 M 1 T 0 M 0 T M R 0 R e lo a d 1 6 - b it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r T 0 E T 0 M 1 T 0 M 0 T 0 O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l O v e r flo w to In te rru p t 1 6 - b it T im e r /E v e n t C o u n te r (T M R 0 H /T M R 0 L ) T Q P F D 0 P A 3 D a ta C T R L Timer/Event Counter 0 fS Y S /4 3 2 7 6 8 H z T 1 S M U f IN D a ta B u s T X T 1 M 1 T 1 M 0 T M R 1 1 6 - b it T im e r /E v e n t C o u n te r R e lo a d P r e lo a d R e g is te r T 1 E T 1 M 1 T 1 M 0 T 1 O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l O v e r flo w to In te rru p t 1 6 - b it T im e r /E v e n t C o u n te r (T M R 1 H /T M R 1 L ) T Q P F D 1 P A 3 D a ta C T R L Timer/Event Counter 1 Rev. 1.20 19 April 14, 2006 HT49RV5/HT49CV5 Remote Control Timer - RMT The RMT pin with rising/falling edge wake-up function, 8-bit timer counter will be cleared during a chip reset. The HT49RV5/HT49CV5 provides an 8-bit remote control timer that has a pulse width measurement function. Pulse width is measured from a difference in count value when the valid edge (RMT pin) has been detected while the timer operates in the running mode. And the RMT clock starts to count after the rising/falling edge trigger. In te rru p t (R M T 0 F ) N o is e R e je c tio n R is in g E d g e D e te c tio n R M T fS fS Y S Y S /4 M U fX X R M C S L a tc h R e m o te C o n tr o l T im e r C a p tu r e R e g is te r R M T 0 (2 2 H ) fX /2 5~ fX /2 8 P r e - s c a le r O v e r flo w 4 -1 M U X R M S 1 R M S 0 (R M T V F ) 8 - b it T im e r C o u n te r C le a r R M E N o is e R e je c tio n F a llin g E d g e D e te c tio n L a tc h R e m o te C o n tr o l T im e r C a p tu r e R e g is te r R M T 1 (2 3 H ) In te rru p t (R M T 1 F ) Remote Control Timer Bit No. Label 0 ¾ 1 ERMT0 Function Unused bit, read as ²0² Controls the remote control timer rising edge interrupt (1=enable; 0=disable) 2 ERMT1 Controls the remote control timer falling edge interrupt (1=enable; 0=disable) 3 ERMTV Controls the remote control timer overflow interrupt (1=enable; 0=disable) 4 RME 5 RMCS Selects the remote control timer clock source fX (1=fSYS; 0=fSYS/4) RMS0 RMS1 Selects the remote control timer clock 00=fX/25 01= fX/26 10= fX/27 11= fX/28 6~7 Controls the remote control timer (1=enable & start count; 0=disable & clear counter) RMTC (21H) Register Bit No. Label Function 0 RMTVF 1 RTF 2 RMT0F Remote control timer rising edge interrupt flag (1=indicates that a rising edge interrupt has occurred; 0=indicates that a rising edge interrupt has not occurred) 3 RMT1F Remote control timer falling edge interrupt flag (1=indicates that a falling edge interrupt has occurred; 0=indicates that a falling edge interrupt has not occurred) 4 ERTI 5~7 ¾ Remote control timer overflow interrupt flag (1=indicates that an overflow has occurred; 0=indicates that an overflow has not occurred) Real time clock interrupt flag (1=indicates that an RTC interrupt has occurred; 0=indicates that an RTC interrupt has not occurred) Controls the real time clock interrupt (1=enable; 0=disable) Unused bit, read as ²0² MFIS (29H) Register Rev. 1.20 20 April 14, 2006 HT49RV5/HT49CV5 Serial Interface The Serial Interface function has four basic signals included. They are the SDI (serial data input), SDO (serial data output), SCK (serial clock) and SCS (slave select pin). Two registers (SBCR & SBDR) unique to the serial interface provide control, status and data storage. S B E N = 1 , C S E N = 0 ( if p u ll- h ig h e d ) S C S S B E N = C S E N = 1 S C K S D I S D O D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 SIO Timing (SIOCLK Configuration is Falling Edge) S B E N = 1 , C S E N = 0 ( if p u ll- h ig h e d ) S C S S B E N = C S E N = 1 S C K S D I S D O D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 SIO Timing (SIOCLK Configuration is Rising Edge) Bit No. Label 0 ¾ 1 WCOL 2 CSEN 3 MLS 4 SBEN 5, 6 M0, M1 7 CKS Function Unused bit, read as ²0² This bit shows the situation of the buffer SBDR 1: enable (set by SIO) writing to SBDR 0: disable (cleared by user) reading from SBDR Serial bus selection signal Shift first control bit (1: MSB; 0: LSB) Serial bus selection (1: enable; 0: disable) Master/slave mode selection: M1, M0= 00: master mode, baud rate=fSIO 01: master mode, baud rate=fSIO/4 10: master mode, baud rate=fSIO/16 11: slave mode Clock source selection (0: fSYS/4; 1: fRTCOSC) SBCR (1FH) Register · SBCR: Serial bus control register ¨ ¨ ¨ Bit 7 (CKS): clock source selection: fSIO=fSYS/4 or fRTCOSC Master mode: write data to SBDR (TXRX buffer) ® start transmission/reception automatically M1, M0: Master mode: when data has been transferred ® set TRF 00: master mode, baud rate=fSIO 01: master mode, baud rate=fSIO/4 Slave mode: when a SCK (and SCS dependent on CSEN) is received, data in TXRX buffer is shifted-out and data on SDI is shifted-in 10: master mode, baud rate=fSIO/16 11: slave mode Rev. 1.20 Enable: (SCS dependent on CSEN bit) Disable ® enable: SCK, SDI, SDO, SCS=0 and waiting for writing data to SBDR (TXRX buffer) Bit 6 (M1), Bit 5 (M0): master/slave mode & baud rate selection - Bit 4 (SBEN): serial bus enable/disable (1/0) - 21 April 14, 2006 HT49RV5/HT49CV5 - Disable: SCK, SDI, SCS floating, SDO output high ¨ Bit 3 (MLS): MSB or LSB (1/0) shift first control bit ¨ Bit 2 (CSEN): serial bus selection signal enable/disable (SCS), when CSEN=0, SCS is floating ¨ ¨ Clock Polarity=Rising Edge or Falling Edge (Configuration Option) · Serial interface operation ¨ Master mode operation Step1: Select CKS and select M1, M0 = 00, 01, 10 Bit 1 (WCOL): this bit is set to 1 if data is written to SBDR (TXRX buffer) when data is transferred ® writing will be ignored if data is written to SBDR (TXRX buffer) when data is transferred Step2: Select CSEN, MLS (the same as the slave) Step3: Set SBEN Step4: Writing data to SBDR Bit 0 (TRF): data transferred or data received ® used to generate interrupt Note: data receiving is still working when the MCU enters the HALT mode - data is stored in TXRX buffer - output SCK and SCS signals - go to step 5 Note: SIO internal operation: * data stored in TXRX buffer, and SDI data is shifted into TXRX buffer * data transferred, data in TXRX buffer is latched into SBDR · SBDR: Serial bus data register ¨ Data written to SBDR ® write data to TXRX buffer only ¨ Data read from SBDR ® read from SBDR only ¨ Step5: Check WCOL Operating Mode description - Master transmitter: clock sending and data I/O started by writing SBDR - WCOL= 1, clear WCOL and go to step 4 - WCOL= 0, go to step 6 Step6: Check TRFor waiting for serial bus interrupt - Master clock sending started by writing SBDR Step7: Read data from SBDR - Slave transmitter: data I/O started by clock received Step8: Clear TRF - Slave receiver: data I/O started by clock received Step9: Go to step 4 D a ta B u s S B D R ( R e c e iv e d D a ta R e g is te r ) M D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 U S D O X M L S A N D , S ta rt E N S C K A N D , S ta rt C lo c k P o la r ity S B E N M U X C 0 C 1 X S D I C 2 T D R F W C O L F la g In te r n a l B u s y F la g W r ite S B D R S B E N A N D , S ta rt E N C S E N U A N D M a s te r o r S la v e S D O S B E N M In te r n a l B a u d R a te C lo c k B u ffe r S B E N W r ite S B D R E n a b le /D is a b le W r ite S B D R S C S M a s te r o r S la v e SIO Block Diagram Rev. 1.20 22 April 14, 2006 HT49RV5/HT49CV5 ¨ Slave mode operation Some instructions first input data and then follow the output operations. For example, ²SET [m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Step1: CKS don¢t care and select M1, M0 =11 Step2: Select CSEN, MLS (the same as the master) Step3: Set SBEN Step4: Writing data to SBDR - data is stored in the TXRX buffer - waiting for master clock signal (and SCS): SCK - go to step 5 Each line of port A has the capability of waking-up the device. Note: SIO internal operation: * SCK (SCS) received * output data in TXRX buffer and SDI data is shifted into TXRX buffer * data transferred, data in TXRX buffer is latched into SBDR Each I/O port has a pull-high option. Once the pull-high option is selected, the I/O port has a pull-high resistor, otherwise, there¢s none. Take note that a non-pull-high I/O port operating in input mode will cause a floating state. The PA3 pin is pin-shared with the PFD signal. If the PFD option is selected, the output signal in the output mode of PA3 will be the PFD signal generated by the timer/event counter overflow signal. The input mode always retains its original functions. Once the PFD option is selected, the PFD output signal is controlled by the PA3 data register only. Writing a ²1² to PA3 data register will enable the PFD output function and writing a ²0² will force the PA3 pin to remain at ²0². The I/O functions of PA3 are shown below. Step5: Check WCOL - WCOL=1, clear WCOL, go to step 4 - WCOL=0, go to step 6 Step6: Check TRFor waiting for serial bus interrupt Step7: Read data from SBDR Step8: Clear TRF Step9: Go to step 4 Input/Output Ports There are 20 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC and PD, which are mapped to the data memory of [12H], [14H], [16H] and [18H], respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H, 16H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O I/P Mode (Normal) PA3 Note: I/P (PFD) O/P (PFD) Logical Output Logical Input PFD (Timer on) The PFD frequency is the timer/event counter overflow frequency divided by 2. The descriptions of PFD control signal and PFD output frequency are listed in the following table. Timer PA3 Data PA3 Pad Timer Preload Register State Value Each I/O line has its own control register (PAC, PBC, PCC, PDC) to control the input/output configuration. With this control register, CMOS output or Schmitt Trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write a ²1². The input source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the in t e rn a l b u s . Th e l at t er i s p o s s i bl e i n t h e ²read-modify-write² instruction. PFD Frequency OFF X 0 0 X OFF X 1 U X ON N 0 0 X ON N 1 PFD fTMR/[2´(M-N)] Note: For an output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H and 19H. ²X² stands for unused ²U² stands for unknown ²M² is ²65536² for PFD0 or PFD1 ²N² is preload value for timer/event counter ²fTMR² is input clock frequency for timer/event counter The PA0 and PA1 pins are pin-shared with the BZ and BZ signal, respectively. If the BZ/BZ option is selected, the output signal in the output mode of PA0/PA1 will be the buzzer signal generated by the multi-function timer. The input mode always remains in its original function. Once the BZ/BZ option is selected, the buzzer output signal are controlled by the PA0/PA1 data register only. After a chip reset, these input/output lines remain at high levels or floating state (depending on pull-high options). Each bit of these input/output latches can be set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H, 16H or 18H) instructions. Rev. 1.20 Logical Input O/P (Normal) 23 April 14, 2006 HT49RV5/HT49CV5 V C o n tr o l B it Q D D a ta B u s W r ite C o n tr o l R e g is te r P u ll- h ig h P A P A P A P A P A P B P C P C P D P D P D P D P D P D Q C K S C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it Q D W r ite D a ta R e g is te r C K S Q M P A 0 /P A 1 /P A 3 /P D 0 /P D 1 B Z /B Z /P F D /P W M 0 /P W M 1 M R e a d D a ta R e g is te r U 0 fo 1 fo 0 fo 1 fo r P r P r P r P D 4 D 5 D 6 D 7 o n o n o n o n U 0 /B Z 1 /B Z 2 3 /P 4 ~ P 0 /A 6 7 /R 0 /P 1 /P 4 /IN 5 /IN 6 /T 7 /T F D A 7 N 0 ~ P B 3 /A N 3 M T W M W M T 0 T 1 M R M R 1 1 0 0 X P F D E N (P A 3 ) X S y s te m W a k e -u p ( P A o n ly ) IN T IN T T M R T M R D D O P 0 ~ O P 7 ly ly ly ly Input/Output Ports The I/O function of PA0/PA1 are shown below. PA0 I/O It is recommended that unused or not bonded out I/O lines should be set as output pins by software instructions to avoid consuming power under input floating state. I I O O O O O O O O PA1 I/O I O I PA0 Mode X X C B B C B B B B PA1 Mode X C X X X C C C B B PWM PA0 Data X X D 0 PA1 Data X D X X X D1 D D X X PA0 Pad Status I I D 0 B D0 0 0 B PA1 Pad Status I D I I D1 D D 0 B The microcontroller provides a 2 channel and (6+2)/(7+1) (dependent on options) bits PWM output shared with PD0/PD1. The PWM channels have their data registers denoted as PWM0 (1AH), PWM1 (1BH). The frequency source of the PWM counter comes from fSYS. The PWM registers are two 8-bit registers. The waveforms of PWM outputs are as shown. Once the PD0/PD1 are selected as the PWM outputs and the output function of PD0/PD1 are enabled (PDC.0/PDC.1 =²0²), writing ²1² to PD0/PD1 data register will enable the PWM output function and writing ²0² will force the PD0/PD1 to remain at ²0². Note: I I I O O O O O 1 D0 0 1 B 0 1 ²I² input; ²O² output ²D, D0, D1² Data ²B² buzzer option, BZ or BZ ²X² don¢t care ²C² CMOS output The PB0~PB3 can also be used as A/D converter inputs. The A/D function will be described later. There is a function shared with PD0/PD1. If the PWM function is enabled, the PWM0/PWM1 signal will appear on PD0/PD1 (if PD0/PD1 is operating in the output mode). Writing a ²1² to PD0~PD1 data register will enable the PWM output function and writing a ²0² will force the PD0~PD1 to remain at ²0². The I/O functions of PD0/PD1 are as shown. I/O I/P Mode (Normal) PD0 PD1 Rev. 1.20 Logical Input O/P (Normal) I/P (PWM) O/P (PWM) Logical Output Logical Input PWM0 PWM1 A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. The group 2 is denoted by AC which is the value of PWM.1~PWM.0. 24 April 14, 2006 HT49RV5/HT49CV5 In a (7+1) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. In a (6+2) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter AC (0~3) Duty Cycle i<AC DC + 1 64 Modulation cycle i (i=0~3) Parameter Duty Cycle i<AC DC + 1 128 i³AC DC 128 Modulation cycle i (i=0~1) DC 64 i³AC AC (0~1) A (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle0~modulation cycle 1). Each modulation cycle has 128 PWM input clock period. The modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. In a (7+1) bits PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.1. PWM Modulation Frequency PWM Cycle PWM Cycle Frequency Duty fSYS/64 for (6+2) bits mode fSYS/256 fSYS/128 for (7+1) bits mode [PWM]/256 The group 2 is denoted by AC which is the value of PWM.0. fS /2 Y S [P W M ] = 1 0 0 P W M 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 6 /6 4 [P W M ] = 1 0 1 P W M [P W M ] = 1 0 2 P W M [P W M ] = 1 0 3 P W M 2 6 /6 4 P W M m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0 Y S M o d u la tio n c y c le 1 P W M M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS M o d u la tio n c y c le 3 M o d u la tio n c y c le 0 Y S (6+2) PWM Mode fS Y S /2 [P W M ] = 1 0 0 P W M 5 0 /1 2 8 5 0 /1 2 8 5 0 /1 2 8 5 1 /1 2 8 5 0 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 2 /1 2 8 [P W M ] = 1 0 1 P W M [P W M ] = 1 0 2 P W M [P W M ] = 1 0 3 P W M 5 2 /1 2 8 P W M m o d u la tio n p e r io d : 1 2 8 /fS Y S M o d u la tio n c y c le 0 M o d u la tio n c y c le 1 P W M c y c le : 2 5 6 /fS M o d u la tio n c y c le 0 Y S (7+1) PWM Mode Rev. 1.20 25 April 14, 2006 HT49RV5/HT49CV5 converter circuit is powered-on. The EOCB bit (bit6 of the ADCR) is the end of A/D conversion flag. Check this bit to know when the A/D conversion is completed. A/D Converter The 4 channels and 8 bit resolution A/D converter are implemented in these microcontrollers. The reference voltage is VDD. The A/D converter contains 3 special registers which are; ADR (25H), ADCR (26H) and ACSR (27H). The ADR contain the A/D result register is read-only. After the A/D conversion is completed, the ADR should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If the user wishes to start an A/D conversion, they should define the PB configuration, select the converted analog channel, and give the START bit a rising edge and falling edge (0®1®0). At the end of the A/D conversion, the EOCB bit is cleared. The ACSR is the A/D clock setting register, which is used to select the A/D clock source. The START bit of the ADCR is used to begin the conversion of the A/D converter. Giving the START bit a rising edge and falling edge means that the A/D conversion has started. In order to ensure that the A/D conversion is completed, the START should remain at ²0² until the EOCB is cleared to ²0² (end of A/D conversion). Bit 7 of the ACSR is used for testing purposes only. It cannot be used by the user. The bit 1 and bit 0 of the ACSR are used to select the A/D clock sources. When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1² when the START bit is set from ²0² to ²1². Important Note for A/D initialisation: Special care must be taken to initialise the A/D converter each time the Port B A/D channel selection bits are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialisation is implemented by setting the START bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel selection bits are all cleared to zero then an A/D initialisation is not required. The A/D converter control register is used to control the A/D converter. Bits 1~0 of the ADCR are used to select an analog input channel. There¢s a total of four channels to select. The bit5~bit3 of the ADCR are used to set the PB0~PB3 configurations. PB can be an analog input or digital I/O line determined by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D Bit No. Label 0 1 ADCS0 ADCS1 Function Selects the A/D converter clock source 00= system clock/2 01= system clock/8 10= system clock/32 11= undefined 2~6 ¾ Unused bit, read as ²0² 7 TEST For test mode used only ACSR (27H) Register Bit No. Label 0 1 ACS0 ACS1 Function 2, 5 ¾ 3 4 PCR0 PCR1 Defines the port B configuration select. If PCR0 and PCR1 are all zero, the ADC circuit is powered off to reduce power consumption 6 EOCB Indicates end of A/D conversion. (0= end of A/D conversion) Each time bits 3~4 change state the A/D should be initialised by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialisation². 7 START Starts the A/D conversion. 0®1®0= Start 0®1= Reset A/D converter and set EOCB to ²1². Defines the analog channel select. Unused bit, read as ²0² ADCR (26H) Register Rev. 1.20 26 April 14, 2006 HT49RV5/HT49CV5 ACS1 ACS0 Analog Channel 0 0 AN0 0 1 AN1 1 0 AN2 1 1 AN3 Analog Input Channel Selection Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADR D7 D6 D5 D4 D3 D2 D1 D0 Note: D0~D7 is the A/D conversion result data bit LSB~MSB. PCR1 PCR0 3 2 1 0 0 0 PB3 PB2 PB1 PB0 0 1 PB3 PB2 PB1 AN0 1 0 PB3 PB2 AN1 AN0 1 1 AN3 AN2 AN1 AN0 Port B Configuration The following programming example illustrates how to setup and implement an A/D conversion. The method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete. Example: using EOCB Polling Method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov mov a,00110000B ADCR,a : ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START clr START Polling_EOC: sz EOCB jmp polling_EOC mov a,ADR mov adr_buffer,a : : jmp Start_conversion Rev. 1.20 ; reset A/D ; start A/D ; poll the ADCR register EOCB bit to detect end of A/D conversion ; continue polling ; read conversion result from the ADR register ; save result to user defined memory ; start next A/D conversion 27 April 14, 2006 HT49RV5/HT49CV5 M in im u m o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d S T A R T E O C B A /D tA P C R 1 ~ P C R 0 s a m p lin g tim e A /D tA D C S 0 0 B s a m p lin g tim e A /D tA D C S 1 1 B 1 1 B s a m p lin g tim e D C S 1 0 B 0 0 B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n A C S 1 ~ A C S 0 0 0 B P o w e r-o n R e s e t 0 1 B 0 0 B 0 1 B S ta rt o f A /D c o n v e r s io n S ta rt o f A /D c o n v e r s io n S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l tA D C A /D c o n v e r s io n tim e N o te : A /D tA D tA C S D C c lo c k m u s t b e fS = 3 2 tA D = 7 6 tA D Y S /2 , fS Y S /8 o r fS Y S R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n A /D tA D C c o n v e r s io n tim e d o n 't c a r e E n d o f A /D c o n v e r s io n A /D tA D C c o n v e r s io n tim e /3 2 A/D Conversion Timing purpose data memory. The VFD display memory can be read and written to only by an indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the VFD driver which then generates the corresponding VFD driving signals. To turn the display on or off, a ²1² or a ²0² is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and VFD pattern for the HT49RV5/ HT49CV5. VFD Display Memory The HT49RV5/HT49CV5 provides an area of embedded data memory for the VFD display. This area is located from 40H to 55H of the RAM at Bank 1. The Bank Pointer (BP; located at 04H of the RAM) is the switch for the RAM and the VFD display memory. When the BP is set as ²1², any data written into 40H~55H will affect the VFD display. When the BP is written as ²0² any data written into 40H~55H is meant to access the general SEG15~ SEG12 SEG11~ SEG8 SEG7~ SEG4 SEG3~ SEG0 Grid0 41HU 41HL 40HU 40HL Grid1 43HU 43HL 42HU 42HL Grid2 45HU 45HL 44HU 44HL Grid3 47HU 47HL 46HU 46HL Grid4 49HU 49HL 48HU 48HL Grid5 4BHU 4BHL 4AHU 4AHL Grid6 4DHU 4DHL 4CHU 4CHL Grid7 4FHU 4FHL 4EHU 4EHL Grid8 51HU 51HL 50HU 50HL Grid9 53HU 53HL 52HU 52HL Grid10 55HU 55HL 54HU 54HL b7 b4 b3 b0 HU HL Higher 4 bits Lower 4 bits VFD Display Memory Rev. 1.20 28 April 14, 2006 HT49RV5/HT49CV5 VFD Display Control Register - VFDC Bit No. 2~0 Label There is a low voltage reset circuit (LVR) implemented in the microcontroller. This function can be enabled/disabled by options. Function Selects the VFD display mode 000= 4 grids, 16 segments 001= 5 grids, 16 segments 010= 6 grids, 16 segments VGS2~ 011= 7 grids, 15 segments VGS0 100= 8 grids, 14 segments 101= 9 grids, 13 segments 110= 10 grids, 12 segments 111= 11 grids, 11 segments 3 ¾ 4 VFDE 7~5 Low Voltage Reset If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: · The low voltage (0.9V~VLVR) has to remain in its origi- nal state for longer than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function. Unused bit, read as ²0² Controls the VFD display (1=enable; 0=disable) · The LVR uses an ²OR² function with the external RES signal to perform a chip reset. Sets the VFD dimming quantity 000= set pulse width to 1/16. 001= set pulse width to 2/16. 010= set pulse width to 4/16. VDM2~V 011= set pulse width to 10/16. DM0 100= set pulse width to 11/16. 101= set pulse width to 12/16. 110= set pulse width to 13/16. 111= set pulse width to 14/16. The relationship between VDD and VLVR is shown below. V D D 5 .5 V V VFD clock source may come from the RTC or the system clock/4 (fSYS/4). 0 .9 V Note: G r id 0 S e g m e n ts O N G r id 1 S e g m e n ts O N A ll S e g m e n ts O F F L V R 2 .2 V At power-on initial, the 11-grid, 11-segment & 1/16 pulse width are set and the VFD display is disabled. G r id 1 O P R 5 .5 V 3 .0 V VFDC (28H) Register G r id 0 V V D D 0 V VOPR is the voltage range for proper chip operation at 4MHz system clock. V E E V D D 0 V V E E V D D 0 V V E E V D D 0 V V E E V D D 0 V V E E VFD Driver Output Rev. 1.20 29 April 14, 2006 HT49RV5/HT49CV5 V D D 5 .5 V V L V R L V R D e te c t V o lta g e 0 .9 V 0 V R e s e t S ig n a l N o r m a l O p e r a tio n R e s e t *1 R e s e t *2 Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before starting normal operation. *2: Since the low voltage has to maintain its original state for longer than 1ms, therefore a 1ms delay enters the reset mode. Options The following shows the configuration options in the HT49RV5/HT49CV5. All these options should be defined in order to ensure a properly functioning system. Options OSC type selection. This option is to decide if an RC or crystal or 32768Hz crystal oscillator is chosen as the system clock. fWDT: WDT clock source selection. There are three types of selections: system clock/4 or RTC OSC or WDT OSC fS: VFD, RTC and Buzzer clock source selection. There are two types of selections: system clock/4 or RTC OSC WDT enable/disable selection. WDT can be enabled or disabled by option. WDT time-out period selection. There are four types of selection: WDT clock source divided by fWDT/212~fWDT/213, fWDT/213~fWDT/214, fWDT/214~fWDT/215 or fWDT/215~fWDT/216 CLR WDT times selection. This option defines the method to clear the WDT by instruction. ²One time² means that the ²CLR WDT² instructions can clear the WDT. ²Two times² means only if both of the ²CLR WDT1² and ²CLR WDT2² instructions have been executed, the WDT can be cleared. Buzzer output frequency selection. There are eight types of frequency signals for buzzer output: fS/2~fS/28, ²fS² means the clock source selected by options. Wake-up selection. This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT by a falling edge. (bit option) Pull-high selection. This option is to determine whether the pull-high resistance is viable or not in the input mode of the I/O ports. PA, PB0~PB3, PC6~PC7, PD0~PD1 and PD4~PD7 can be independently selected. (bit option) RMT Pull-high selection. This option is to determine whether a pull-high resistance is viable or not in the input pin. I/O pins shared with other function selections. PA0/BZ, PA1/BZ, PA3/PFD: PA0, PA1 and PA3 can be set as I/O pins or buzzer outputs. VFD driver clock selection. There are 8 types of frequency signals for the VFD driver circuits: fS/20~fS/27. ²fS² stands for the clock source selection by options. VFD ON/OFF at HALT selection, VFD ON at HALT works only when the VFD clock source selects RTC OSC Rev. 1.20 30 April 14, 2006 HT49RV5/HT49CV5 Options LVR selection LVR has enable or disable options PFD selection. If PA3 is set as a PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1, respectively. PWM selection: (7+1) or (6+2) mode PD0: level output or PWM0 output PD1: level output or PWM1 output INT0 or INT1 triggering edge: Disable; high to low; low to high; low to high or high to low SIOCLK: Serial interface clock. There are falling edge, rising edge or triggering edge CSEN: Serial bus selection: enable or disable WCOL: SBDR write conflict Application Circuits V D D 0 .0 1 m F * S E G G S E G ~ S E V D D 1 0 0 k W 0 .1 m F R E S 0 r id 1 G ~ S E 0 ~ G 1 /G r 1 5 /G G 1 r id id 1 r id 1 0 k W 0 5 0 V F D 6 V E E V F D P o w e r S u p p ly 0 .1 m F 0 .1 m F * V S S O S C C ir c u it S C S C L K S D I S D O O S C 1 O S C 2 S e e r ig h t s id e O S C 1 R O S C /4 O S C 2 O S C 1 C ry s ta l S y s te m O s c illa to r O S C 3 O S C 4 P P P D 4 /IN T 0 P D 6 /T M R 0 P D P D P ~ P D 7 /T M R 1 P P A 0 /B P A 1 /B P A A 3 /P F A 4 ~ P A B 0 /A N B 3 /A N C 6 ~ P C 0 /P W M 1 /P W M C 2 Z Z O S C 2 2 D 7 O S C 1 0 ~ P P D 5 /IN T 1 3 7 O S C 2 0 3 2 7 6 8 H z C ry s ta l S y s te m O s c illa to r O S C 1 a n d O S C 2 le ft u n c o n n e c te d 1 O S C H T 4 9 R V 5 /H T 4 9 C V 5 Note: Y S R M T C 1 3 2 7 6 8 H z fS R C S y s te m O s c illa to r 5 6 k W < R O S C < 1 .5 M W C ir c u it The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. Rev. 1.20 31 April 14, 2006 HT49RV5/HT49CV5 Instruction Set Summary Description Instruction Cycle Flag Affected Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Rev. 1.20 32 April 14, 2006 HT49RV5/HT49CV5 Instruction Cycle Flag Affected Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Mnemonic Description Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Ö: Flag is affected -: Flag is not affected (1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. (3) (1) : (4) Rev. 1.20 and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the ²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. 33 April 14, 2006 HT49RV5/HT49CV5 Instruction Definition ADC A,[m] Add data memory and carry to the accumulator Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADCM A,[m] Add the accumulator and carry to data memory Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. Operation [m] ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADD A,[m] Add data memory to the accumulator Description The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. Operation ACC ¬ ACC+[m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADD A,x Add immediate data to the accumulator Description The contents of the accumulator and the specified data are added, leaving the result in the accumulator. Operation ACC ¬ ACC+x Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ¬ ACC+[m] Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö 34 April 14, 2006 HT49RV5/HT49CV5 AND A,[m] Logical AND accumulator with data memory Description Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²AND² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ AND A,x Logical AND immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²AND² x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ ANDM A,[m] Logical AND data memory with the accumulator Description Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. Operation [m] ¬ ACC ²AND² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ CALL addr Subroutine call Description The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Operation Stack ¬ Program Counter+1 Program Counter ¬ addr Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] ¬ 00H Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 35 April 14, 2006 HT49RV5/HT49CV5 CLR [m].i Clear bit of data memory Description The bit i of the specified data memory is cleared to 0. Operation [m].i ¬ 0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ CLR WDT Clear Watchdog Timer Description The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. Operation WDT ¬ 00H PDF and TO ¬ 0 Affected flag(s) TO PDF OV Z AC C 0 0 ¾ ¾ ¾ ¾ CLR WDT1 Preclear Watchdog Timer Description Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. Operation WDT ¬ 00H* PDF and TO ¬ 0* Affected flag(s) TO PDF OV Z AC C 0* 0* ¾ ¾ ¾ ¾ CLR WDT2 Preclear Watchdog Timer Description Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. Operation WDT ¬ 00H* PDF and TO ¬ 0* Affected flag(s) TO PDF OV Z AC C 0* 0* ¾ ¾ ¾ ¾ CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] ¬ [m] Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 36 April 14, 2006 HT49RV5/HT49CV5 CPLA [m] Complement data memory and place result in the accumulator Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. Operation ACC ¬ [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ DAA [m] Decimal-Adjust accumulator for addition Description The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. Operation If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö DEC [m] Decrement data memory Description Data in the specified data memory is decremented by 1. Operation [m] ¬ [m]-1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ DECA [m] Decrement data memory and place result in the accumulator Description Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC ¬ [m]-1 Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 37 April 14, 2006 HT49RV5/HT49CV5 HALT Enter power down mode Description This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Operation Program Counter ¬ Program Counter+1 PDF ¬ 1 TO ¬ 0 Affected flag(s) TO PDF OV Z AC C 0 1 ¾ ¾ ¾ ¾ INC [m] Increment data memory Description Data in the specified data memory is incremented by 1 Operation [m] ¬ [m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ INCA [m] Increment data memory and place result in the accumulator Description Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC ¬ [m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ JMP addr Directly jump Description The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Operation Program Counter ¬addr Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC ¬ [m] Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 38 April 14, 2006 HT49RV5/HT49CV5 MOV A,x Move immediate data to the accumulator Description The 8-bit data specified by the code is loaded into the accumulator. Operation ACC ¬ x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ MOV [m],A Move the accumulator to data memory Description The contents of the accumulator are copied to the specified data memory (one of the data memories). Operation [m] ¬ACC Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation Program Counter ¬ Program Counter+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ OR A,[m] Logical OR accumulator with data memory Description Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²OR² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ OR A,x Logical OR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ¬ ACC ²OR² x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ ORM A,[m] Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ¬ACC ²OR² [m] Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 39 April 14, 2006 HT49RV5/HT49CV5 RET Return from subroutine Description The program counter is restored from the stack. This is a 2-cycle instruction. Operation Program Counter ¬ Stack Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RET A,x Return and place immediate data in the accumulator Description The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Operation Program Counter ¬ Stack ACC ¬ x Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RETI Return from interrupt Description The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Operation Program Counter ¬ Stack EMI ¬ 1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RL [m] Rotate data memory left Description The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ [m].7 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RLA [m] Rotate data memory left and place result in the accumulator Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ [m].7 Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 40 April 14, 2006 HT49RV5/HT49CV5 RLC [m] Rotate data memory left through carry Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ C C ¬ [m].7 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö RLCA [m] Rotate left through carry and place result in the accumulator Description Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ C C ¬ [m].7 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö RR [m] Rotate data memory right Description The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ [m].0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RRA [m] Rotate right and place result in the accumulator Description Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ [m].0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ RRC [m] Rotate data memory right through carry Description The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ C C ¬ [m].0 Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö 41 April 14, 2006 HT49RV5/HT49CV5 RRCA [m] Rotate right through carry and place result in the accumulator Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. Operation ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ C C ¬ [m].0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ Ö SBC A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SBCM A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. Operation [m] ¬ ACC+[m]+C Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SDZ [m] Skip if decrement data memory is 0 Description The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SDZA [m] Decrement data memory and place result in ACC, skip if 0 Description The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]-1)=0, ACC ¬ ([m]-1) Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 42 April 14, 2006 HT49RV5/HT49CV5 SET [m] Set data memory Description Each bit of the specified data memory is set to 1. Operation [m] ¬ FFH Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SET [m]. i Set bit of data memory Description Bit i of the specified data memory is set to 1. Operation [m].i ¬ 1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SIZ [m] Skip if increment data memory is 0 Description The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]+1)=0, [m] ¬ ([m]+1) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SIZA [m] Increment data memory and place result in ACC, skip if 0 Description The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m]+1)=0, ACC ¬ ([m]+1) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SNZ [m].i Skip if bit i of the data memory is not 0 Description If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m].i¹0 Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 43 April 14, 2006 HT49RV5/HT49CV5 SUB A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+[m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SUBM A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. Operation [m] ¬ ACC+[m]+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SUB A,x Subtract immediate data from the accumulator Description The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. Operation ACC ¬ ACC+x+1 Affected flag(s) TO PDF OV Z AC C ¾ ¾ Ö Ö Ö Ö SWAP [m] Swap nibbles within the data memory Description The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. Operation [m].3~[m].0 « [m].7~[m].4 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SWAPA [m] Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ¬ [m].7~[m].4 ACC.7~ACC.4 ¬ [m].3~[m].0 Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 44 April 14, 2006 HT49RV5/HT49CV5 SZ [m] Skip if data memory is 0 Description If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m]=0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SZA [m] Move data memory to ACC, skip if 0 Description The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m]=0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ SZ [m].i Skip if bit i of the data memory is 0 Description If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if [m].i=0 Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ TABRDC [m] Move the ROM code (current page) to TBLH and data memory Description The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte) Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ TABRDL [m] Move the ROM code (last page) to TBLH and data memory Description The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte) Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ ¾ ¾ ¾ 45 April 14, 2006 HT49RV5/HT49CV5 XOR A,[m] Logical XOR accumulator with data memory Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. Operation ACC ¬ ACC ²XOR² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ XORM A,[m] Logical XOR data memory with the accumulator Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. Operation [m] ¬ ACC ²XOR² [m] Affected flag(s) TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ¬ ACC ²XOR² x Affected flag(s) Rev. 1.20 TO PDF OV Z AC C ¾ ¾ ¾ Ö ¾ ¾ 46 April 14, 2006 HT49RV5/HT49CV5 Package Information 56-pin SSOP (300mil) Outline Dimensions 2 9 5 6 B A 2 8 1 C C ' G H D Symbol Rev. 1.20 a F E Dimensions in mil Min. Nom. Max. A 395 ¾ 420 B 291 ¾ 299 C 8 ¾ 12 C¢ 720 ¾ 730 D 89 ¾ 99 E ¾ 25 ¾ F 4 ¾ 10 G 25 ¾ 35 H 4 ¾ 12 a 0° ¾ 8° 47 April 14, 2006 HT49RV5/HT49CV5 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 48 April 14, 2006