PD - 95489D
IRF2907ZPbF
IRF2907ZSPbF
IRF2907ZLPbF
Features
l
l
l
l
l
l
HEXFET® Power MOSFET
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
D
VDSS = 75V
RDS(on) = 4.5mΩ
G
Description
ID = 160A∗
S
This HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating. These features combine
to make this design an extremely efficient and
reliable device for use in a wide variety of
applications.
TO-220AB
D2 Pak
IRF2907ZPbF IRF2907ZSPbF
TO-262
IRF2907ZLPbF
Absolute Maximum Ratings
Parameter
Max.
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
170
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (See Fig. 9)
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Wirebond Limited)
Units
120
A
160 *
c
IDM
Pulsed Drain Current
PD @TC = 25°C
Maximum Power Dissipation
300
W
Linear Derating Factor
2.0
± 20
W/°C
V
270
mJ
VGS
EAS
680
Gate-to-Source Voltage
Single Pulse Avalanche Energy (Thermally Limited)
EAS (tested)
Single Pulse Avalanche Energy Tested Value
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
TJ
Operating Junction and
TSTG
Storage Temperature Range
c
i
d
h
°C
300 (1.6mm from case )
Mounting torque, 6-32 or M3 screw
RθCS
A
-55 to + 175
10 lbf•in (1.1N•m)
Thermal Resistance
Junction-to-Case k
See Fig.12a,12b,15,16
mJ
Soldering Temperature, for 10 seconds
RθJC
690
Typ.
Parameter
–––
Max.
0.50l
Case-to-Sink, Flat, Greased Surface
0.50
RθJA
Junction-to-Ambient
–––
62
RθJA
Junction-to-Ambient (PCB Mount, steady state)
–––
40
j
–––
Units
°C/W
HEXFET® is a registered trademark of International Rectifier.
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1
07/22/10
IRF2907Z/S/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
V(BR)DSS
∆ΒVDSS/∆TJ
RDS(on)
VGS(th)
Min. Typ. Max. Units
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
LD
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
75
–––
–––
2.0
180
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
0.069
3.5
–––
–––
–––
–––
–––
–––
180
46
65
19
140
97
100
5.0
–––
–––
4.5
4.0
–––
20
250
200
-200
270
–––
–––
–––
–––
–––
–––
–––
LS
Internal Source Inductance
–––
13
–––
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
7500
970
510
3640
650
1020
–––
–––
–––
–––
–––
–––
gfs
IDSS
IGSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
f
f
f
6mm (0.25in.)
from package
pF
Diode Characteristics
Parameter
IS
Continuous Source Current
ISM
(Body Diode)
Pulsed Source Current
VSD
trr
Qrr
ton
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
c
–––
160*
–––
–––
680
–––
–––
–––
–––
41
59
1.3
61
89
G
S
and center of die contact
VGS = 0V
VDS = 25V
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 60V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 60V
Conditions
MOSFET symbol
A
V
ns
nC
D
showing the
integral reverse
G
p-n junction diode.
TJ = 25°C, IS = 75A, VGS = 0V
TJ = 25°C, IF = 75A, VDD = 38V
di/dt = 100A/µs
f
S
f
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L=0.095mH,
RG = 25Ω, IAS = 75A, VGS =10V.
Part not recommended for use above this value.
ISD ≤ 75A, di/dt ≤ 340A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from
0 to 80% VDSS.
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical
repetitive avalanche performance.
2
–––
Conditions
V VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 75A
V VDS = VGS, ID = 250µA
S VDS = 25V, ID = 75A
µA VDS = 75V, VGS = 0V
VDS = 75V, VGS = 0V, TJ = 125°C
nA VGS = 20V
VGS = -20V
ID = 75A
nC VDS = 60V
VGS = 10V
ns VDD = 38V
ID = 75A
RG = 2.5Ω
VGS = 10V
D
nH Between lead,
This value determined from sample failure population.
100% tested to this value in production.
This is applied to D2Pak, when mounted on 1" square PCB
( FR-4 or G-10 Material ). For recommended footprint and
soldering techniques refer to application note #AN-994.
Rθ is measured at TJ of approximately 90°C.
TO-220 device will have an Rth of 0.45°C/W.
∗
Calculated continuous current based on maximum
allowable junction temperature. Bond wire current limit is
160A.Note that current limitations arising from heating of
the device leads may occur with some lead mounting
arrangements. (Refer to AN-1140 http://www.irf.com/
technical-info/appnotes/an-1140.pdf)
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IRF2907Z/S/LPbF
1000
10000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
1000
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
100
100
4.5V
10
4.5V
≤60µs PULSE WIDTH
≤60µs PULSE WIDTH
Tj = 175°C
Tj = 25°C
1
0.1
1
10
10
0.1
100
Fig 1. Typical Output Characteristics
10
100
Fig 2. Typical Output Characteristics
1000
200
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current (Α)
1
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
T J = 175°C
100
10
T J = 25°C
1
VDS = 25V
≤60µs PULSE WIDTH
0.1
2
4
6
8
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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T J = 25°C
150
T J = 175°C
100
50
V DS = 10V
380µs PULSE WIDTH
0
10
0
25
50
75
100
125
150
ID,Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
vs. Drain Current
3
IRF2907Z/S/LPbF
100000
12.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 90A
C, Capacitance(pF)
C oss = C ds + C gd
10000
Ciss
Coss
Crss
1000
100
VDS= 60V
VDS= 38V
10.0
VDS= 15V
8.0
6.0
4.0
2.0
0.0
1
10
100
0
VDS, Drain-to-Source Voltage (V)
150
200
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
10000
ID, Drain-to-Source Current (A)
1000
ISD, Reverse Drain Current (A)
100
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
T J = 175°C
100
TJ = 25°C
10
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100µsec
1msec
100
Limited by package
10
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
DC
0.1
1
0.0
0.5
1.0
1.5
2.0
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
50
2.5
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF2907Z/S/LPbF
180
2.5
160
RDS(on) , Drain-to-Source On Resistance
(Normalized)
Limited By Package
ID, Drain Current (A)
140
120
100
80
60
40
20
0
ID = 90A
VGS = 10V
2.0
1.5
1.0
0.5
25
50
75
100
125
150
-60 -40 -20 0
175
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
T C , Case Temperature (°C)
Fig 10. Normalized On-Resistance
vs. Temperature
Fig 9. Maximum Drain Current vs.
Case Temperature
1
Thermal Response ( Z thJC )
D = 0.50
0.20
0.1
0.10
0.05
τJ
0.02
0.01
0.01
R1
R1
τJ
τ1
R2
R2
τC
τ1
τ2
τ2
τ
Ri (°C/W) τi (sec)
0.279
0.000457
0.221
0.003019
Ci= τi/Ri
Ci i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF2907Z/S/LPbF
EAS , Single Pulse Avalanche Energy (mJ)
1200
15V
ID
TOP
9.0A
13A
BOTTOM 75A
1000
DRIVER
L
VDS
D.U.T
RG
VGS
20V
+
V
- DD
IAS
tp
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
800
600
400
200
tp
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGS
QGD
4.0
Charge
Fig 13a. Basic Gate Charge Waveform
L
DUT
0
1K
Fig 13b. Gate Charge Test Circuit
6
VCC
VGS(th) Gate threshold Voltage (V)
VG
3.5
3.0
2.5
ID = 250µA
2.0
1.5
1.0
-75 -50 -25
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
Fig 14. Threshold Voltage vs. Temperature
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IRF2907Z/S/LPbF
100
Avalanche Current (A)
0.01
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses
0.05
0.10
10
1
0.1
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
EAR , Avalanche Energy (mJ)
300
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 75A
250
200
150
100
50
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
vs. Temperature
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175
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT jmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRF2907Z/S/LPbF
D.U.T
Driver Gate Drive
+
-
P.W.
+
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
V DD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• I SD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
P.W.
Period
*
RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
Period
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
*
VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V DS
V GS
RG
RD
D.U.T.
+
-V DD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRF2907Z/S/LPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
AS S EMBLED ON WW 19, 2000
IN T HE AS S EMBLY LINE "C"
Note: "P" in assembly line pos ition
indicates "Lead - Free"
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 19
LINE C
TO-220AB packages are not recommended for Surface Mount Application.
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
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9
IRF2907Z/S/LPbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
THIS IS AN IRF530S WITH
LOT CODE 8024
AS S EMBLED ON WW 02, 2000
IN T HE AS S EMBLY LINE "L"
INT ERNATIONAL
RECTIFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
F530S
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
OR
INTERNATIONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
F530S
DATE CODE
P = DES IGNATES LEAD - FREE
PRODUCT (OPTIONAL)
YEAR 0 = 2000
WEEK 02
A = AS S EMBLY S ITE CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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IRF2907Z/S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
ASS EMBLED ON WW 19, 1997
IN T HE ASS EMBLY LINE "C"
INTERNAT IONAL
RECT IFIER
LOGO
AS SEMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNAT IONAL
RECT IFIER
LOGO
ASS EMBLY
LOT CODE
PART NUMBER
DAT E CODE
P = DES IGNATES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 7 = 1997
WEEK 19
A = AS SEMBLY SITE CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
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11
IRF2907Z/S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/2010
12
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