ON NCP1216D65R2G Pwm current-mode controller Datasheet

NCP1216, NCP1216A
PWM Current-Mode
Controller for High-Power
Universal Off-Line Supplies
Housed in a SOIC−8 or PDIP−7 package, the NCP1216 represents
an enhanced version of NCP1200 based controllers. Due to its high
drive capability, NCP1216 drives large gate−charge MOSFETs, which
together with internal ramp compensation and built−in frequency
jittering, ease the design of modern AC−DC adapters.
With an internal structure operating at different fixed frequencies,
the controller supplies itself from the high−voltage rail, avoiding the
need of an auxiliary winding. This feature naturally eases the designer
task in some particular applications, e.g. battery chargers or TV sets.
Current−mode control also provides an excellent input audio
susceptibility and inherent pulse−by−pulse control. Internal ramp
compensation easily prevents sub−harmonic oscillations from taking
place in continuous conduction mode designs.
When the current setpoint falls below a given value, e.g. the output
power demand diminishes, the IC automatically enters the so−called
skip cycle mode and provides excellent efficiency at light loads.
Because this occurs at a user adjustable low peak current, no acoustic
noise takes place.
The NCP1216 features an efficient protective circuitry, which in
presence of an over current condition disables the output pulses while
the device enters a safe burst mode, trying to restart. Once the default
has gone, the device auto−recovers.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
No Auxiliary Winding Operation
Current−Mode Control with Adjustable Skip−Cycle Capability
Internal Ramp Compensation
Limited Duty Cycle to 50% (NCP1216A Only)
Internal 1.0 ms Soft−Start (NCP1216A Only)
Built−In Frequency Jittering for Better EMI Signature
Auto−Recovery Internal Output Short−Circuit Protection
Extremely Low No−Load Standby Power
500 mA Peak Current Capability
Fixed Frequency Versions at 65 kHz, 100 kHz, 133 kHz
Internal Temperature Shutdown
Direct Optocoupler Connection
SPICE Models Available for TRANsient and AC Analysis
Pin−to−Pin Compatible with NCP1200 Series
These are Pb−Free and Halide−Free Devices
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MARKING
DIAGRAMS
8
8
1
SOIC−8
D SUFFIX
CASE 751
XXXXX
ALYW
G
1
XXXXXXXXX
AWL
YYWWG
PDIP−7
P SUFFIX
CASE 626B
1
XXXXXX = Specific Device Code
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
PIN CONNECTIONS
Adj 1
8 HV
FB 2
7 NC
CS 3
6 VCC
Gnd 4
5 Drv
DEVICE MARKING AND
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 16 of this data sheet.
Typical Applications
•
•
•
•
High Power AC−DC Converters for TVs, Set−Top Boxes, etc.
Offline Adapters for Notebooks
Telecom DC−DC Converters
All Power Supplies
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 16
1
Publication Order Number:
NCP1216/D
NCP1216, NCP1216A
+
*See Application Section
NCP1216
2
Adj HV 8
7
FB
3
CS Vcc 6
4
GNDDrv 5
1
+
EMI
Filter
Fosc = 35kHz
Rcomp
Universal Input
+
Rsense
Figure 1. Typical Application Example
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Pin Description
1
Adj
Adjust the Skipping Peak Current
This pin lets you adjust the level at which the cycle skipping process
takes place. Shorting this pin to ground, permanently disables the skip
cycle feature.
2
FB
Sets the Peak Current Setpoint
By connecting an Optocoupler to this pin, the peak current setpoint is
adjusted accordingly to the output power demand.
3
CS
Current Sense Input
This pin senses the primary current and routes it to the internal comparator via an L.E.B. By inserting a resistor in series with the pin, you
control the amount of ramp compensation you need.
4
GND
IC Ground
5
Drv
Driving Pulses
The driver’s output to an external MOSFET.
6
VCC
Supplies the IC
This pin is connected to an external bulk capacitor of typically 22 mF.
7
NC
−
8
HV
Generates the VCC from the Line
−
This un−connected pin ensures adequate creepage distance.
Connected to the high−voltage rail, this pin injects a constant current
into the VCC bulk capacitor.
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2
NCP1216, NCP1216A
Adj
1
HV Current Source
FB
Skip Cycle Comparator
Internal VCC
+
−
Clock Jittering
1.1 V
96 k
2
UVLO High and Low
Internal Regulator
8 HV
7 NC
25 k
220 ns
L.E.B
19 k
Current 3
Sense
GND
4
20 k
65 kHz
100 kHz
133kHz
Ramp
Compensation
Pull−up Resistor 57 k
+ Vref
25 k
−
5V
Set Q Flip−Flop Q
DCmax = 75%
6 VCC
Reset
+
−
$500 mA
5 Drv
1 ms SS*
1V
Overload?
Fault Duration
* Available for ”A” version only.
Figure 2. Internal Circuit Architecture
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
16
V
−0.3 to 10
V
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 mF
500
V
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Grounded
450
V
Minimum Operating Voltage on Pin 8 (HV)
28
V
Maximum Current into all Pins except VCC (Pin 6) and HV (Pin 8) when 10 V ESD Diodes are Activated
5.0
mA
Power Supply Voltage, VCC Pin
Maximum Voltage on Low Power Pins (except Pin 8 and Pin 6)
Thermal Resistance Junction−to−Air, PDIP−7 Version
Thermal Resistance Junction−to−Air, SOIC−8 Version
RqJ−A
RqJ−A
100
178
°C/W
Maximum Junction Temperature
TJMAX
150
°C
TSD
155
°C
30
°C
Temperature Shutdown
Hysteresis in Shutdown
Storage Temperature Range
−60 to +150
°C
ESD Capability, HBM Model (All Pins except VCC and HV)
2.0
kV
ESD Capability, Machine Model
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection rated using the following tests:
Human Body Model (HBM) 2000 V per JEDEC Standard JESD22, Method A114E.
Machine Model (MM) 200 V per JEDEC Standard JESD22, Method A115A.
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3
NCP1216, NCP1216A
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Maximum TJ = 150°C, VCC = 11 V unless otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
VCC Increasing Level at which the Current Source Turns Off
6
VCCOFF
11.2
12.2
13.4
(Note 1)
V
VCC Decreasing Level at which the Current Source Turns On
6
VCCON
9.2
10.0
11.0
(Note 1)
V
VCC Decreasing Level at which the Latchoff Phase Ends
6
VCClatch
5.6
V
NCP1216
NCP1216A
6
ICC3
250
320
mA
Internal IC Consumption, No Output Load on Pin 5, FSW = 65 kHz
0°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +125°C
6
ICC1
Internal IC Consumption, No Output Load on Pin 5, FSW = 100 kHz
0°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +125°C
6
ICC1
Internal IC Consumption, No Output Load on Pin 5, FSW = 133 kHz
0°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +125°C
6
ICC1
Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 65 kHz
0°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +125°C
6
ICC2
Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 100 kHz
0°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +125°C
6
ICC2
Internal IC Consumption, 1.0 nF Output Load on Pin 5, FSW = 133 kHz
0°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +125°C
6
ICC2
High−voltage Current Source, VCC = 10 V
8
IC1
High−voltage Current Source, VCC = 0 V
8
IC2
9.0
mA
Output Voltage Rise−time @ CL = 1.0 nF, 10−90% of a 12 V Output Signal
5
Tr
60
ns
Output Voltage Fall−time @ CL = 1.0 nF, 10−90% of a 12 V Output Signal
5
Tf
20
ns
Source Resistance
5
ROH
15
20
35
W
Sink Resistance
5
ROL
5.0
10
18
W
Input Bias Current @ 1.0 V Input Level on Pin 3
3
IIB
Maximum Internal Current Setpoint
3
ILimit
Default Internal Current Setpoint for Skip Cycle Operation
3
ILskip
330
Propagation Delay from Current Detection to Gate OFF State
3
TDEL
80
Leading Edge Blanking Duration
3
TLEB
220
DYNAMIC SELF−SUPPLY
Internal IC Consumption, Latchoff Phase, VCC = 6.0 V
990
1110
1245
1025
1180
1285
1060
1200
1290
1.7
2.0
2.0
2.1
2.4
2.55
2.4
2.9
3.0
8.0
11
mA
mA
mA
mA
mA
mA
INTERNAL STARTUP CURRENT SOURCE (TJ > 0°C)
4.9
(Note 2)
mA
DRIVE OUTPUT
CURRENT COMPARATOR (Pin 5 Unloaded)
0.02
0.93
1.08
mA
1.14
V
mV
130
ns
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. VCCOFF and VCCON min−max always ensure an hysteresis of 2.0 V.
2. Minimum value for TJ = 125°C.
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NCP1216, NCP1216A
ELECTRICAL CHARACTERISTICS (continued)
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Maximum TJ = 150°C, VCC = 11 V unless otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
58.5
57
65
65
71.5
75
90
86
100
100
110
120
120
110
133
133
146
160
Unit
INTERNAL OSCILLATOR (VCC = 11 V, Pin 5 Loaded by 1.0 kW)
Oscillation Frequency, 65 kHz Version
Oscillation Frequency, 100 kHz Version
Oscillation Frequency, 133 kHz Version
fOSC
0°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +125°C
fOSC
0°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +125°C
fOSC
0°C ≤ TJ ≤ +125°C
−40°C ≤ TJ ≤ +125°C
Built−in Frequency Jittering in Percentage of fOSC
fjitter
Maximum Duty−Cycle
NCP1216
NCP1216A
Dmax
75
46.5
kHz
kHz
%
±4.0
69
42
kHz
81
50
%
FEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 kW)
Internal Pullup Resistor
2
Rup
20
Pin 2 (FB) to Internal Current Setpoint Division Ratio
−
Iratio
3.3
Default Skip Mode Level
1
Vskip
Pin 1 Internal Output Impedance
1
Zout
Internal Ramp Level @ 25°C (Note 3)
3
Vramp
Internal Ramp Resistance to CS Pin
3
Rramp
kW
SKIP CYCLE GENERATION
0.9
1.1
1.26
25
V
kW
INTERNAL RAMP COMPENSATION
2.6
2.9
19
3.2
V
kW
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. A 1.0 MW resistor is connected to the ground for the measurement.
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NCP1216, NCP1216A
14.0
50
13.5
40
13.0
VCCOFF (V)
HV PIN LEAKAGE CURRENT @ 500 V
(mA)
TYPICAL CHARACTERISTICS
60
30
20
10
12.0
11.5
0
−50
−25
0
25
50
75
100
125
11.0
−50
−25
0
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 4. VCCOFF vs. Temperature
12.0
1400
11.5
1200
ICC1 (mA)
10.5
10.0
9.0
−50
125
133 kHz
1000
800
65 kHz
100 kHz
600
400
9.5
200
−25
0
25
50
75
100
125
0
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. VCCON vs. Temperature
Figure 6. ICC1 (@ VCC = 11 V) vs. Temperature
150
2.80
2.60
133 kHz
2.40
2.20
100 kHz
2.00
1.80
65 kHz
1.60
133 kHz
130
FOSC (kHz)
ICC2 (mA)
25
Figure 3. High Voltage Pin Leakage Current vs.
Temperature
11.0
VCCON (V)
12.5
1.40
110
100 kHz
90
70
65 kHz
1.20
1.00
−50
−25
0
25
50
75
TEMPERATURE (°C)
100
125
50
−50
Figure 7. ICC2 vs. Temperature
−25
0
25
50
75
TEMPERATURE (°C)
100
Figure 8. Switching Frequency vs.
Temperature
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125
NCP1216, NCP1216A
5.90
400
350
5.80
NCP1216A
5.70
ICC3 (mA)
VCClatch (V)
300
5.60
5.50
250
NCP1216
200
150
100
5.40
5.30
−50
50
−25
0
25
50
75
100
0
−50
125
−25
0
TEMPERATURE (°C)
75
100
125
100
125
Figure 10. ICC3 vs. Temperature
1.13
30
25
CURRENT SENSE LIMIT (V)
DRIVER RESISTANCE (W)
50
TEMPERATURE (°C)
Figure 9. VCClatch vs. Temperature
Source
20
15
10
Sink
5
0
−50
25
−25
0
25
50
75
100
1.08
1.03
0.98
0.93
−50
125
−25
0
25
50
75
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Drive Sink and Source Resistance
vs. Temperature
Figure 12. Current Sense Limit vs. Temperature
1.20
75.0
74.5
DUTY CYCLE (%)
Vskip (V)
1.15
1.10
1.05
74.0
73.5
73.0
72.5
1.00
−50
−25
0
25
50
75
100
72.0
−50
125
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Vskip vs. Temperature
Figure 14. NCP1216 Max Duty−Cycle vs.
Temperature
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7
125
3.10
48.5
3.05
48.0
3.00
47.5
2.95
Vramp (V)
49.0
47.0
46.5
2.90
2.85
46.0
2.80
45.5
2.75
45.0
−50
−25
0
25
50
75
100
125
2.70
−50
−25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. NCP1216A Max Duty−Cycle vs.
Temperature
Figure 16. Vramp vs. Temperature
14
12
10
IC1 (mA)
DUTY CYCLE (%)
NCP1216, NCP1216A
8
6
4
2
−50
−25
0
25
50
75
100
TEMPERATURE (°C)
Figure 17. High Voltage Current Source
(@ VCC = 10 V) vs. Temperature
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8
125
125
NCP1216, NCP1216A
APPLICATION INFORMATION
Over Current Protection (OCP): By continuously
monitoring the FB line activity, NCP1216 enters burst mode
as soon as the power supply undergoes an overload. The
device enters a safe low power operation, which prevents
from any lethal thermal runaway. As soon as the default
disappears, the power supply resumes operation. Unlike
other controllers, overload detection is performed
independently of any auxiliary winding level. In presence of
a bad coupling between both power and auxiliary windings,
the short circuit detection can be severely affected. The DSS
naturally shields you against these troubles.
Wide Duty−Cycle Operation: Wide mains operation requires
Introduction
The NCP1216 implements a standard current mode
architecture where the switch−off event is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part count is the key parameter,
particularly in low−cost AC−DC adapters, TV power
supplies etc. Due to its high−performance High−Voltage
technology, the NCP1216 incorporates all the necessary
components normally needed in UC384X based supplies:
timing components, feedback devices, low−pass filter and
self−supply. This later point emphasizes the fact that ON
Semiconductor’s NCP1216 does NOT need an auxiliary
winding to operate: the product is naturally supplied from
the high−voltage rail and delivers a VCC to the IC. This
system is called the Dynamic Self−Supply (DSS):
Dynamic Self−Supply (DSS): Due to its Very High
Voltage Integrated Circuit (VHVIC) technology,
ON Semiconductor’s NCP1216 allows for a direct pin
connection to the high−voltage DC rail. A dynamic current
source charges up a capacitor and thus provides a fully
independent VCC level to the NCP1216. As a result, there is
no need for an auxiliary winding whose management is
always a problem in variable output voltage designs (e.g.
battery chargers).
Adjustable Skip Cycle Level: By offering the ability to tailor
the level at which the skip cycle takes place, the designer can
make sure that the skip operation only occurs at low peak
current. This point guarantees a noise−free operation with
cheap transformers. Skip cycle offers a proven mean to
reduce the standby power in no or light loads situations.
Internal Frequency Dithering for Improved EMI
Signature: By modulating the internal switching frequency
with the DSS VCC ripple, natural energy spread appears and
softens the controller’s EMI signature.
Wide Switching − Frequency Offered with Different
Options (65 kHz − 100 kHz − 133 kHz): Depending on the
application, the designer can pick up the right device to help
reducing magnetics or improve the EMI signature before
reaching the 150 kHz starting point.
Ramp Compensation: By inserting a resistor between the
Current Sense (CS) pin and the actual sense resistor, it
becomes possible to inject a given amount of ramp
compensation since the internal sawtooth clock is routed to
the CS pin. Sub−harmonic oscillations in Continuous
Conduction Mode (CCM) can thus be compensated via a
single resistor.
a large duty−cycle excursion. The NCP1216 can go up to 75%
typically. For Continuous Conduction Mode (CCM)
applications, the internal ramp compensation lets you fight
against sub−harmonic oscillations.
Low Standby Power: If SMPS naturally exhibit a good
efficiency at nominal load, they begin to be less efficient
when the output power demand diminishes. By skipping
unnecessary switching cycles, the NCP1216 drastically
reduces the power wasted during light load conditions. In
no−load conditions, the NPC1216 allows the total standby
power to easily reach next International Energy Agency
(IEA) recommendations.
No Acoustic Noise While Operating: Instead of skipping
cycles at high peak currents, the NCP1216 waits until the
peak current demand falls below a user−adjustable 1/3 of the
maximum limit. As a result, cycle skipping can take place
without having a singing transformer, one can thus select
cheap magnetic components free of noise problems.
External MOSFET Connection: By leaving the external
MOSFET external to the IC, you can select avalanche proof
devices, which in certain cases (e.g. low output powers), let
you work without an active clamping network. Also, by
controlling the MOSFET gate signal flow; you have an
option to slow down the device commutation, therefore
reducing the amount of ElectroMagnetic Interference
(EMI).
SPICE Model: A dedicated model to run transient
cycle−by−cycle simulations is available but also an
averaged version to help you closing the loop. Ready−to−use
templates can be downloaded in OrCAD’s PSpice and
INTUSOFT’s IsSpice from ON Semiconductor web site, in
the NCP1216 related section.
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9
NCP1216, NCP1216A
Dynamic Self−Supply
Application note AND8069/D details tricks to widen the
NCP1216 driving implementation, in particular for large Qg
MOSFETs. This document can be downloaded at
www.onsemi.com/pub/Collateral/AND8069−D.PDF.
The DSS principle is based on the charge/discharge of the
VCC bulk capacitor from a low level up to a higher level. We
can easily describe the current source operation with a bunch
of simple logical equations:
POWER−ON: If VCC < VCCOFF then the Current Source
is ON, no output pulses
If VCC decreasing > VCCON then the Current Source is
OFF, output is pulsing
If VCC increasing < VCCOFF then the Current Source is
ON, output is pulsing
Typical values are: VCCOFF = 12.2 V, VCCON = 10 V
To better understand the operational principle, Figure 18
offers the necessary light:
Vripple = 2.2 V
Ramp Compensation
Ramp compensation is a known mean to cure
sub−harmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
Continuous Conduction Mode (CCM) with a duty−cycle
greater than 50%. To lower the current loop gain, one usually
injects between 50% and 100% of the inductor down−slope.
Figure 19 depicts how internally the ramp is generated:
DCmax = 75°C
2.9V
VCCOFF = 12.2 V
0V
VCCON = 10 V
OFF, I = 0 mA
−
+
ON, I = 8 mA
30
50
70
2.9
0.75
Vpin8.
Vout ) Vf
Lp
(eq. 2)
Suppose that we select the NCP1216P065 with the above
MOSFET, the total current is
(30 n
65 k) ) 900 m + 2.9 mA.
2.9 mA + 1 W
(eq. 5)
Np
Ns
+ 371 mAńms or37 mVńms
(eq. 6)
when projected over an Rsense of 0.1 W, for instance. If we
select 75% of the down−slope as the required amount of
ramp compensation, then we shall inject 27 mV/ms. Our
internal compensation being of 251 mV/ms, the divider ratio
(divratio) between Rcomp and the 19 kW is 0.107. A few lines
of algebra to determine Rcomp:
(eq. 3)
Supplied from a 350 VDC rail (250 VAC), the heat
dissipated by the circuit would then be:
350 V
65 kHz + 251 mVńms ramp.
In our FLYBACK design, let’s suppose that our primary
inductance Lp is 350 mH, delivering 12 V with a Np : Ns
ratio of 1:0.1. The OFF time primary current slope is thus
given by:
(eq. 1)
The total IC heat dissipation incurred by the DSS only is
given by:
Itotal
Rsense
In the NCP1216, the ramp features a swing of 2.9 V with
a Duty cycle max at 75%. Over a 65 kHz frequency, it
corresponds to a
The DSS behavior actually depends on the internal IC
consumption and the MOSFET’s gate charge Qg. If we
select a 600 V 10 A MOSFET featuring a 30 nC Qg, then we
can compute the resulting average consumption supported
by the DSS which is:
Qg ) ICC1.
CS
Figure 19. Inserting a Resistor in Series with the
Current Sense Information brings Ramp
Compensation
90
Figure 18. The Charge/Discharge Cycle Over a
10 mF VCC Capacitor
Itotal [ Fsw
Rcomp
19 k
From Set−point
Output Pulse
10
L.E.B
(eq. 4)
19 k divratio
+ 2.37 kW
1 * divratio
As you can see, it exists a tradeoff where the dissipation
capability of the NCP1216 fixes the maximum Qg that the
circuit can drive, keeping its dissipation below a given
target. Please see the “Power Dissipation” section for a
complete design example and discover how a resistor can
help to heal the NCP1216 heat equation.
(eq. 7)
Frequency Jittering
Frequency jittering is a method used to soften the EMI
signature by spreading the energy in the vicinity of the main
switching component. NCP1216 offers a $4% deviation of
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10
NCP1216, NCP1216A
the nominal switching frequency whose sweep is
synchronized with the VCC ripple. For instance, with a 2.2 V
peak−to−peak ripple, the NCP1216P065 frequency will
equal 65 kHz in the middle of the ripple and will increase as
VCC rises or decrease as VCC ramps down. Figure 20
portrays the behavior we have adopted:
VCCOFF
VCC Ripple
To better understand how this skip cycle mode takes place,
a look at the operation mode versus the FB level
immediately gives the necessary insight:
FB
68 kHz
4.2 V, FB Pin Open
Normal Current Mode Operation
65 kHz
3.2 V, Upper
Dynamic Range
1V
Skip Cycle Operation
IpMIN = 333 mV / Rsense
62 kHz
VCCON
Figure 21.
When FB is above the skip cycle threshold (1.0 V by
default), the peak current cannot exceed 1.0 V/Rsense. When
the IC enters the skip cycle mode, the peak current cannot go
below Vpin1 / 3.3. The user still has the flexibility to alter this
1.0 V by either shunting pin 1 to ground through a resistor
or raising it through a resistor up to the desired level.
Grounding pin 1 permanently invalidates the skip cycle
operation.
Figure 20. VCC Ripple is Used to Introduce a
Frequency Jittering on the Internal Oscillator
Sawtooth
Skipping Cycle Mode
The NCP1216 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so−called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 22).
Suppose we have the following component values:
Power P1
Power
P2
Power
P3
Lp, primary inductance = 350 mH
Fsw, switching frequency = 65 kHz
Ip skip = 600 mA (or 333 mV / Rsense)
The theoretical power transfer is therefore:
1
2
Lp
Ip2
Fsw + 4 W.
Figure 22. Output Pulses at Various Power Levels
(X = 5 ms/div) P1 < P2 < P3
(eq. 8)
If this IC enters skip cycle mode with a bunch length of
10 ms over a recurrent period of 100 ms, then the total power
transfer is:
4
0.1 + 400 mW.
(eq. 9)
www.onsemi.com
11
NCP1216, NCP1216A
due to the DSS operation. In our example, at
Tambient = 50°C, ICC2 is measured to be 2.9 mA with a
10 A / 600 V MOSFET. As a result, the NCP1216 will
dissipate from a 250 VAC network,
Max Peak
Current
300
Skip Cycle
Current Limit
200
350 V
0
882.7U
1.450M
2.017M
2.585M
Figure 23. The Skip Cycle Takes Place at Low Peak
Currents which Guarantees Noise Free Operation
T
* TAmax
P max + Jmax
+1W
RqJ * A
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the Adj pin 1 level, the
output pulses are disabled as long as FB is pulled below
pin 1. As soon as FB is relaxed, the IC resumes its operation.
Figure 24 depicts the application example:
Q1
ON/OFF
8
2
7
3
6
4
5
(eq. 12)
which barely matches our previous budget. Several
solutions exist to help improving the situation:
1. Insert a Resistor in Series with Pin 8: This resistor will
take a part of the heat normally dissipated by the NCP1216.
Calculations of this resistor imply that Vpin8 does not drop
below 30 V in the lowest mains conditions. Therefore, Rdrop
can be selected with:
Non−Latching Shutdown
1
(eq. 11)
The PDIP−7 package offers a junction−to−ambient thermal
resistance RqJ−A of 100°C/W. Adding some copper area
around the PCB footprint will help decreasing this number:
12 mm x 12 mm to drop RqJ−A down to 75°C/W with 35 m
copper thickness (1 oz.) or 6.5 mm x 6.5 mm with 70 m
copper thickness (2 oz.). For a SOIC−8, the original
178°C/W will drop to 100°C/W with the same amount of
copper. With this later PDIP−7 number, we can compute the
maximum power dissipation that the package accepts at an
ambient of 50°C:
100
315.4U
2.9 mA@TA + 50°C + 1 W
Rdrop v
Vbulkmin * 50 V
8 mA
(eq. 13)
In our case, Vbulk minimum is 120 VDC, which leads to a
dropping resistor of 8.7 kW. With the above example in
mind, the DSS will exhibit a duty−cycle of:
2.9 mAń8 mA + 36%
(eq. 14)
By inserting the 8.7 kW resistor, we drop
8.7 kW * 8 mA + 69.6 V
(eq. 15)
during the DSS activation. The power dissipated by the
NCP1216 is therefore:
Figure 24. Another Way of Shutting Down the IC
without a Definitive Latchoff State
Pinstant * DSSduty * cycle +
(350 * 69) * 8 m * 0.36 + 800 mW
(eq. 16)
A full latching shutdown, including overtemperature
protection, is described in application note AND8069/D.
We can pass the limit and the resistor will dissipate
Power Dissipation
or
1 W * 800 mW + 200 mW
The NCP1216 is directly supplied from the DC rail
through the internal DSS circuitry. The current flowing
through the DSS is therefore the direct image of the
NCP1216 current consumption. The total power dissipation
can be evaluated using:
(VHVDC * 11 V)
ICC2
2
pdrop + 69 * 0.36
8.7 k
(eq. 17)
(eq. 18)
2. Select a MOSFET with a Lower Qg : Certain MOSFETs
exhibit different total gate charges depending on the
technology they use. Careful selection of this component
can help to significantly decrease the dissipated heat.
(eq. 10)
which is, as we saw, directly related to the MOSFET Qg. If
we operate the device on a 90−250 VAC rail, the maximum
rectified voltage can go up to 350 VDC. However, as the
characterization curves show, the current consumption
drops at a higher junction temperature, which quickly occurs
www.onsemi.com
12
NCP1216, NCP1216A
3. Implement Figure 3, from AN8069/D, Solution: This is
another possible option to keep the DSS functionality (good
short−circuit protection and EMI jittering) while driving any
types of MOSFETs. This solution is recommended when the
designer plans to use SOIC−8 controllers.
4. Connect an Auxiliary Winding: If the mains conditions
are such that you simply can’t match the maximum power
dissipation, then you need to connect an auxiliary winding
to permanently disconnect the startup source.
manner with a low duty−cycle. The system auto−recovers
when the fault condition disappears.
During the startup phase, the peak current is pushed to the
maximum until the output voltage reaches its target and the
feedback loop takes over. This period of time depends on
normal output load conditions and the maximum peak
current allowed by the system. The time−out used by this IC
works with the VCC decoupling capacitor: as soon as the
VCC decreases from the VCCOFF level (typically 12.2 V) the
device internally watches for an overload current situation.
If this condition is still present when the VCCON level is
reached, the controller stops the driving pulses, prevents the
self−supply current source to restart and puts all the circuitry
in standby, consuming as little as 350 mA typical (ICC3
parameter). As a result, the VCC level slowly discharges
toward 0 V. When this level crosses 5.6 V typical, the
controller enters a new startup phase by turning the current
source on: VCC rises toward 12.2 V and again delivers
output pulses at the VCCOFF crossing point. If the fault
condition has been removed before VCCON approaches,
then the IC continues its normal operation. Otherwise, a new
fault cycle takes place. Figure 25 shows the evolution of the
signals in presence of a fault.
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true short−circuit protection. A
short−circuit actually forces the output voltage to be at a low
level, preventing a bias current to circulate in the
Optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please note
that this can also happen in case of feedback loss, e.g. a
broken Optocoupler. To account for this situation, NCP1216
hosts a dedicated overload detection circuitry. Once
activated, this circuitry imposes to deliver pulses in a burst
VCC
12.2 V
Regulation
Occurs Here
Latchoff
Phase
10 V
5.6 V
Time
Drv
VCCOFF = 12.2 V
VCCON = 10 V
VCClatch = 5.6 V
Driver
Pulses
Driver
Pulses
Time
Internal
Fault Flag
Fault is
Relaxed
Startup Phase
Time
Fault Occurs Here
Figure 25.
Calculating the VCC Capacitor
If the fault is relaxed during the VCC natural fall down
sequence, the IC automatically resumes.
If the fault still persists when VCC reached VCCON, then the
controller cuts everything off until recovery.
As the above section describes, the fall down sequence
depends upon the VCC level: how long does it take for the
VCC line to go from 12.2 V to 10 V. The required time
www.onsemi.com
13
NCP1216, NCP1216A
Protecting the Controller Against Negative Spikes
depends on the startup sequence of your system, i.e. when
you first apply the power to the IC. The corresponding
transient fault duration due to the output capacitor charging
must be less than the time needed to discharge from 12.2 V
to 10 V, otherwise the supply will not properly start. The test
consists in either simulating or measuring in the lab how
much time the system takes to reach the regulation at full
load. Let’s suppose that this time corresponds to 6ms.
Therefore a VCC fall time of 10 ms could be well
appropriated in order to not trigger the overload detection
circuitry. If the corresponding IC consumption, including
the MOSFET drive, establishes at 2.9 mA, we can calculate
the required capacitor using the following formula:
Dt + DV·C
i
As with any controller built upon a CMOS technology, it
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if a low impedance path is
offered between VCC and GND. If the current sense pin is
often the seat of such spurious signals, the high−voltage pin
can also be the source of problems in certain circumstances.
During the turn−off sequence, e.g. when the user unplugs the
power supply, the controller is still fed by its VCC capacitor
and keeps activating the MOSFET ON and OFF with a peak
current limited by Rsense. Unfortunately, if the quality
coefficient Q of the resonating network formed by Lp and
Cbulk is low (e.g. the MOSFET Rdson + Rsense are small),
conditions are met to make the circuit resonate and thus
negatively bias the controller. Since we are talking about ms
pulses, the amount of injected charge, (Q = I * t),
immediately latches the controller that brutally discharges
its VCC capacitor. If this VCC capacitor is of sufficient value,
its stored energy damages the controller. Figure 26 depicts
a typical negative shot occurring on the HV pin where the
brutal VCC discharge testifies for latchup.
(eq. 19)
with DV = 2.2 V. Then for a wanted Dt of 30 ms, C equals
39.5 mF or a 68 mF for a standard value (including ±20%
dispersions). When an overload condition occurs, the IC
blocks its internal circuitry and its consumption drops to
350 mA typical. This happens at VCC = 10 V and it remains
stuck until VCC reaches 5.6 V: we are in latchoff phase.
Again, using the selected 68 mF and 350 mA current
consumption, this latchoff phase lasts: 780 ms.
0
VCC
5 V/DIV
Vlatch
1 V/DIV
10 ms/DIV
Figure 26. A Negative Spike Takes Place on the Bulk Capacitor at the Switch−off Sequence
Another option (Figure 28) consists in wiring a diode
from VCC to the bulk capacitor to force VCC to reach
VCCON sooner and thus stops the switching activity before
the bulk capacitor gets deeply discharged. For security
reasons, two diodes can be connected in series.
Simple and inexpensive cures exist to prevent from
internal parasitic SCR activation. One of them consists in
inserting a resistor in series with the high−voltage pin to
keep the negative current to the lowest when the bulk
becomes negative (Figure 27). Please note that the negative
spike is clamped to (−2 * Vf) due to the diode bridge. Also,
the power dissipation of this resistor is extremely small since
it only heats up during the startup sequence.
www.onsemi.com
14
NCP1216, NCP1216A
+
Rbulk
> 4.7 k
+
Cbulk
1
8
2
7
3
6
4
5
+
Cbulk
1
8
2
7
3
6
4
5
CVCC
Figure 27.
D3
1N4007
+
CVCC
Figure 28.
A simple resistor in series avoids any latchup in the controller
or one diode forces VCC to reach VCCON sooner.
Soft−Start − NCP1216A only
The NCP1216A features an internal 1.0 ms soft−start
activated during the power on sequence (PON). As soon as
VCC reaches VCCOFF, the peak current is gradually
increased from nearly zero up to the maximum clamping
level (e.g. 1.0 V). This situation lasts during 1ms and further
to that time period, the peak current limit is blocked to
1.0 V until the supply enters regulation. The soft−start is also
activated during the over current burst (OCP) sequence.
Every restart attempt is followed by a soft−start activation.
Generally speaking, the soft−start will be activated when
VCC ramps up either from zero (fresh power−on sequence)
or 5.6 V, the latchoff voltage occurring during OCP.
Figure 29 portrays the soft−start behavior. The time scales
are purposely shifted to offer a better zoom portion.
Figure 29. Soft−start is activated during a startup sequence or an OCP condition
www.onsemi.com
15
NCP1216, NCP1216A
ORDERING INFORMATION
Version
Marking
Package
Shipping†
NCP1216D65R2G
65 kHz
16D06
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1216D100R2G
100 kHz
16D10
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1216D133R2G
133 kHz
16D13
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1216P65G
65 kHz
P1216P065
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1216P100G
100 kHz
P1216P100
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1216P133G
133 kHz
P1216P133
PDIP−7
(Pb−Free)
50 Units/ Rail
NCP1216AD65R2G
65 kHz
16A06
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1216AD100R2G
100 kHz
16A10
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1216AD133R2G
133 kHz
16A13
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1216AP65G
65 kHz
1216AP06
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1216AP100G
100 kHz
P1216AP10
PDIP−7
(Pb−Free)
50 Units / Rail
NCP1216AP133G
133 kHz
P1216AP13
PDIP−7
(Pb−Free)
50 Units / Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
16
NCP1216, NCP1216A
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
17
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP1216, NCP1216A
PACKAGE DIMENSIONS
PDIP−7 (PDIP−8 LESS PIN 7)
P SUFFIX
CASE 626B
ISSUE C
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
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NCP1612/D