AD AD8250 Wide supply range, rail-to-rail output instrumentation amplifier Datasheet

APPLICATIONS
Industrial process controls
Bridge amplifiers
Medical instrumentation
Portable data acquisition
Multichannel systems
–VS
OUT2
OUT1
16 15 14 13
AD8426
11 RG2
RG1 3
10 RG2
+IN1 4
9
6
7
8
+IN2
09490-001
5
–VS
12 –IN2
RG1 2
REF2
–IN1 1
+VS
2 channels in a small, 4 mm × 4 mm LFCSP
LFCSP package has no metal pad
More routing room
No current leakage to pad
Gain set with 1 external resistor
Gain range: 1 to 1000
Input voltage goes below ground
Inputs protected beyond supplies
Very wide power supply range
Single supply: 2.2 V to 36 V
Dual supply: ±1.35 V to ±18 V
Bandwidth (G = 1): 1.5 MHz
CMRR (G = 1): 80 dB minimum
Input noise: 22 nV/√Hz
Typical supply current (per amp): 350 μA
Specified temperature range: −40°C to +125°C
PIN CONFIGURATION
+VS
FEATURES
REF1
Preliminary Technical Data
Wide Supply Range, Rail-to-Rail
Output Instrumentation Amplifier
AD8426
Figure 1.
Table 1. Instrumentation Amplifiers by Category1
General
Purpose
AD8220
AD8221
AD8222
AD8224
AD8228
AD8295
1
Zero
Drift
AD8231
AD8290
AD8293
AD8553
AD8556
AD8557
Military
Grade
AD620
AD621
AD524
AD526
AD624
Low
Power
AD627
AD623
AD8235
AD8236
AD8426
AD8226
AD8227
High Speed
PGA
AD8250
AD8251
AD8253
See www.analog.com for the latest instrumentation amplifiers.
GENERAL DESCRIPTION
The AD8426 is a dual channel, low cost, wide supply range
instrumentation amplifier that requires only one external
resistor to set any gain from 1 to 1000.
The AD8426 is designed to work with a variety of signal
voltages. A wide input range and rail-to-rail output allow the
signal to make full use of the supply rails. Because the input
range also includes the ability to go below the negative supply,
small signals near ground can be amplified without requiring
dual supplies. The AD8426 operates on supplies ranging from
±1.35 V to ±18 V for dual supplies and 2.2 V to 36 V for single
supply.
The robust AD8426 inputs are designed to connect to realworld sensors. In addition to its wide operating range, the
AD8426 can handle voltages beyond the rails. For example,
with a ±5 V supply, the part is guaranteed to withstand ±35 V
at the input with no damage. Minimum as well as maximum input
bias currents are specified to facilitate open-wire detection.
The AD8426 is designed to make PCB routing easy and
efficient. The two amplifiers are arranged in a logical way
so that typical application circuits have short routes and few
vias. Unlike most chip scale packages, the AD8426 does not
have an exposed metal pad on the back of the part, which frees
additional space for routing and vias. The AD8426 offers two in
amps in the equivalent board space of a typical MSOP package.
The AD8426 is ideal for multichannel, space-constrained
industrial applications. Unlike other low cost, low power
instrumentation amplifiers, the AD8426 is designed with a
minimum gain of 1 and can easily handle ±10 V signals. With
its space-saving LFCSP package and 125°C temperature rating,
the AD8426 thrives in tightly packed, zero airflow designs.
The AD8226 is the single channel version of the AD8426.
Rev. PrD
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
AD8426
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Gain Selection ..............................................................................11
Applications ....................................................................................... 1
Reference Terminal .....................................................................11
Pin Configuration ............................................................................. 1
Input Voltage Range ................................................................... 12
General Description ......................................................................... 1
Layout .......................................................................................... 12
Specifications..................................................................................... 3
Input Bias Current Return Path ............................................... 13
Dual-Supply Operation ............................................................... 3
Input Protection ......................................................................... 13
Single-Supply Operation ............................................................. 5
Radio Frequency Interference (RFI) ........................................ 14
Absolute Maximum Ratings............................................................ 8
Applications Information .............................................................. 15
Thermal Resistance ...................................................................... 8
Differential Drive ....................................................................... 15
ESD Caution .................................................................................. 8
Precision Strain Gage ................................................................. 16
Pin Configuration and Function Descriptions ............................. 9
Driving an ADC.......................................................................... 16
Typical Performance Characteristics ........................................... 10
Outline Dimensions ....................................................................... 17
Theory of Operation ...................................................................... 11
Architecture................................................................................. 11
Rev. PrD | Page 2 of 20
Preliminary Technical Data
AD8426
SPECIFICATIONS
DUAL-SUPPLY OPERATION
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 2.
Parameter
COMMON-MODE REJECTION
RATIO (CMRR)
CMRR, DC to 60 Hz
G=1
G = 10
G = 100
G = 1000
CMRR at 5 kHz
G=1
G = 10
G = 100
G = 1000
NOISE
Voltage Noise
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI Noise
G=1
G = 10
G = 100 to 1000
Current Noise
VOLTAGE OFFSET
Input Offset, VOSI
Average Temperature
Coefficient
Output Offset, VOSO
Average Temperature
Coefficient
Offset RTI vs. Supply (PSR)
G=1
G = 10
G = 100
G = 1000
INPUT CURRENT
Input Bias Current1
Average Temperature
Coefficient
Input Offset Current
Test Conditions/
Comments
VCM = −10 V to +10 V
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
Unit
80
100
105
105
86
105
110
110
dB
dB
dB
dB
80
90
90
100
80
90
90
100
dB
dB
dB
dB
Total noise:
eN = √(eNI2 + (eNO/G)2)
f = 1 kHz
22
120
24
125
22
120
24
125
nV/√Hz
nV/√Hz
f = 0.1 Hz to 10 Hz
2
0.5
0.4
100
3
f = 1 kHz
f = 0.1 Hz to 10 Hz
Total offset voltage:
VOS = VOSI + (VOSO/G)
VS = ±5 V to ±15 V
TA = −40°C to +125°C
VS = ±5 V to ±15 V
TA = −40°C to +125°C
2
0.5
0.4
100
3
0.5
300
3
2
1200
12
μV p-p
μV p-p
μV p-p
fA/√Hz
pA p-p
0.5
150
1.5
μV
μV/°C
1
800
8
μV
μV/°C
VS = ±5 V to ±15 V
80
100
105
105
TA = +25°C
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
5
5
5
90
105
110
110
20
15
30
70
TA = +25°C
TA = +125°C
27
25
35
2
2
Rev. PrD | Page 3 of 20
5
5
5
dB
dB
dB
dB
20
15
30
70
27
25
35
nA
nA
nA
pA/°C
1
1
nA
nA
AD8426
Parameter
Average Temperature
Coefficient
REFERENCE INPUT
RIN
IIN
Voltage Range
Reference Gain to Output
Reference Gain Error
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G=1
G = 10
G = 100
G = 1000
Settling Time 0.01%
G=1
G = 10
G = 100
G = 1000
Slew Rate
G=1
G = 5 to 100
GAIN
Gain Range
Gain Error
G=1
G = 5 to 1000
Gain Nonlinearity
G = 1 to 10
G = 100
G = 1000
Gain vs. Temperature2
G=1
G>1
INPUT
Input Impedance
Differential
Common Mode
Input Operating Voltage
Range3
Input Overvoltage Range
OUTPUT
Output Swing
RL = 2 kΩ to Ground
Preliminary Technical Data
Test Conditions/
Comments
TA = −40°C
TA = −40°C to +125°C
Min
A Grade
Typ
Max
3
5
Min
100
7
B Grade
Typ
Max
1
5
1
0.01
1
0.01
kΩ
μA
V
V/V
%
1500
160
20
2
1500
160
20
2
kHz
kHz
kHz
kHz
25
15
40
350
25
15
40
350
μs
μs
μs
μs
0.4
0.6
0.4
0.6
V/μs
V/μs
−VS
100
7
Unit
nA
pA/°C
+VS
−VS
+VS
10 V step
G = 1 + (49.4 kΩ/RG)
1
1000
1
1000
V/V
0.05
0.3
0.02
0.15
%
%
10
75
750
10
75
750
ppm
ppm
ppm
10
10
−100
2
5
−100
ppm/°C
ppm/°C
ppm/°C
VOUT ± 10 V
VOUT = −10 V to +10 V
RL ≥ 2 kΩ
RL ≥ 2 kΩ
RL ≥ 2 kΩ
TA = −40°C to +85°C
TA = +85°C to +125°C
TA = −40°C to +125°C
VS = ±1.35 V to +36 V
0.8||2
0.4||2
TA = +25°C
−VS − 0.1
+VS − 0.8
−VS − 0.1
+VS − 0.8
GΩ||pF
GΩ||pF
V
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
−VS − 0.05
−VS − 0.15
+VS − 40
+VS − 0.6
+VS − 0.9
−VS + 40
−VS − 0.05
−VS − 0.15
+VS − 40
+VS − 0.6
+VS − 0.9
−VS + 40
V
V
V
TA = +25°C
TA = +125°C
TA = −40°C
−VS + 0.4
−VS + 0.4
−VS + 1.2
+VS − 0.7
+VS − 1.0
+VS − 1.1
−VS + 0.4
−VS + 0.4
−VS + 1.2
+VS − 0.7
+VS − 1.0
+VS − 1.1
V
V
V
Rev. PrD | Page 4 of 20
0.8||2
0.4||2
Preliminary Technical Data
Parameter
RL = 10 kΩ to Ground
RL = 100 kΩ to Ground
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
(Per Amplifier)
Test Conditions/
Comments
TA = +25°C
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
Dual-supply operation
TA = +25°C
AD8426
Min
−VS + 0.2
−VS + 0.3
−VS + 0.2
−VS + 0.1
±1.35
350
TA = −40°C
TA = +85°C
TA = +125°C
TEMPERATURE RANGE
A Grade
Typ
Max
+VS − 0.2
+VS − 0.3
+VS − 0.2
+VS − 0.1
13
250
450
525
−40
±18
425
325
525
600
+125
Min
−VS + 0.2
−VS + 0.3
−VS + 0.2
−VS + 0.1
B Grade
Typ
Max
+VS − 0.2
+VS − 0.3
+VS − 0.2
+VS − 0.1
13
±1.35
350
250
450
525
−40
Unit
V
V
V
V
mA
±18
425
V
μA
325
525
600
+125
μA
μA
μA
°C
1
The input stage uses pnp transistors; therefore, input bias current always flows into the part.
The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3
Input voltage range of the AD8426 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the Input Voltage Range section for more information.
2
SINGLE-SUPPLY OPERATION
+VS = 2.7 V, −VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 3.
Parameter
COMMON-MODE REJECTION
RATIO (CMRR)
CMRR, DC to 60 Hz
G=1
G = 10
G = 100
G = 1000
CMRR at 5 kHz
G=1
G = 10
G = 100
G = 1000
NOISE
Voltage Noise
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI Noise
G=1
G = 10
G = 100 to 1000
Current Noise
VOLTAGE OFFSET
Test Conditions/
Comments
VCM = 0 V to 1.7 V
A Grade
Min
Typ
B Grade
Max
Min
Typ
Max
Unit
80
100
105
105
86
105
110
110
dB
dB
dB
dB
80
90
90
100
80
90
90
100
dB
dB
dB
dB
Total noise:
eN = √(eNI2 + (eNO/G)2)
f = 1 kHz
22
120
24
125
22
120
24
125
nV/√Hz
nV/√Hz
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz
Total offset voltage:
VOS = VOSI + (VOSO/G)
2
0.5
0.4
100
3
Input Offset, VOSI
2
0.5
0.4
100
3
300
Rev. PrD | Page 5 of 20
μV p-p
μV p-p
μV p-p
fA/√Hz
pA p-p
150
μV
AD8426
Parameter
Average Temperature
Coefficient
Output Offset, VOSO
Average Temperature
Coefficient
Offset RTI vs. Supply (PSR)
G=1
G = 10
G = 100
G = 1000
INPUT CURRENT
Input Bias Current1
Average Temperature
Coefficient
Input Offset Current
Average Temperature
Coefficient
REFERENCE INPUT
RIN
IIN
Voltage Range
Reference Gain to Output
Reference Gain Error
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G=1
G = 10
G = 100
G = 1000
Settling Time 0.01%
G=1
G = 10
G = 100
G = 1000
Slew Rate
G=1
G = 5 to 100
GAIN
Gain Range
Gain Error
G=1
G = 5 to 1000
Gain vs. Temperature2
G=1
G>1
Preliminary Technical Data
Test Conditions/
Comments
TA = −40°C to +125°C
A Grade
Min
TA = −40°C to +125°C
B Grade
Typ
0.5
Max
3
2
1200
12
Min
Typ
0.5
Max
1.5
Unit
μV/°C
1
800
8
μV
μV/°C
VS = 0 V to 1.7 V
80
100
105
105
TA = +25°C
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
5
5
5
TA = +25°C
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
90
105
110
110
20
15
30
70
27
25
35
5
5
5
dB
dB
dB
dB
20
15
30
70
2
2
3
5
5
100
7
100
7
27
25
35
nA
nA
nA
pA/°C
1
1
1
nA
nA
nA
pA/°C
1
0.01
1
0.01
kΩ
μA
V
V/V
%
1500
160
20
2
1500
160
20
2
kHz
kHz
kHz
kHz
6
6
35
350
6
6
35
350
μs
μs
μs
μs
0.4
0.6
0.4
0.6
V/μs
V/μs
−VS
+VS
−VS
+VS
2 V step
G = 1 + (49.4 kΩ/RG)
1
1000
1
1000
V/V
VOUT = 0.8 V to 1.8 V
VOUT = 0.2 V to 2.5 V
0.04
0.3
0.01
0.1
%
%
TA = −40°C to +85°C
TA = +85°C to +125°C
TA = −40°C to +125°C
5
5
−100
1
2
-100
ppm/°C
ppm/°C
ppm/°C
Rev. PrD | Page 6 of 20
Preliminary Technical Data
Parameter
INPUT
Input Impedance
Differential
Common Mode
Input Operating Voltage
Range3
Input Overvoltage Range
OUTPUT
Output Swing
RL = 10 kΩ to 1.35 V
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
(Per Amplifier)
Test Conditions/
Comments
−VS = 0 V, +VS = 2.7 V
to 36 V
AD8426
A Grade
Min
B Grade
Max
Min
0.8||2
0.4||2
Typ
Max
Unit
TA = +25°C
−0.1
+VS − 0.7
−0.1
+VS − 0.7
GΩ||pF
GΩ||pF
V
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
−0.05
−0.15
+VS − 40
+VS − 0.6
+VS − 0.9
−VS + 40
−0.05
−0.15
+VS − 40
+VS − 0.6
+VS − 0.9
−VS + 40
V
V
V
TA = −40°C to +125°C
0.1
+VS − 0.1
0.1
+VS − 0.1
V
mA
0.8||2
0.4||2
36
V
400
325
500
550
+125
μA
μA
μA
μA
°C
13
Single-supply operation
−VS = 0 V, +VS = 2.7 V
2.2
TA = +25°C
TA = −40°C
TA = +85°C
TA = +125°C
TEMPERATURE RANGE
Typ
13
36
325
250
425
475
−40
1
400
325
500
550
+125
2.2
325
250
425
475
−40
The input stage uses pnp transistors; therefore, input bias current always flows into the part.
The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3
Input voltage range of the AD8426 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the Input Voltage Range section for more information.
2
Rev. PrD | Page 7 of 20
AD8426
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
Supply Voltage
Output Short-Circuit Current
Maximum Voltage at −INx or +INx
Minimum Voltage at −INx or +INx
REFx Voltage
Storage Temperature Range
Specified Temperature Range
Maximum Junction Temperature
ESD
Human Body Model
Charged Device Model
Machine Model
The θJA value in Table 5 assumes a 4-layer JEDEC standard
board with zero airflow.
Rating
±18 V
Indefinite
−VS + 40 V
+VS − 40 V
±VS
−65°C to +150°C
−40°C to +125°C
130°C
Table 5.
Package
16-Lead LFCSP_VQ
ESD CAUTION
1.5 kV
1.5 kV
100 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. PrD | Page 8 of 20
θJA
86
Unit
°C/W
Preliminary Technical Data
AD8426
–VS
OUT2
OUT1
+VS
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16 15 14 13
AD8426
9
6
7
8
Figure 2. Pin Configuration
Table 6. Pin Function Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
−IN1
RG1
RG1
+IN1
+VS
REF1
REF2
−VS
+IN2
RG2
RG2
−IN2
−VS
OUT2
OUT1
+VS
Description
Negative Input, In-Amp 1
Gain-Setting Resistor Terminal, In-Amp 1
Gain-Setting Resistor Terminal, In-Amp 1
Positive Input, In-Amp 1
Positive Supply
Reference Adjust, In-Amp 1
Reference Adjust, In-Amp 2
Negative Supply
Positive Input, In-Amp 2
Gain-Setting Resistor Terminal, In-Amp 2
Gain-Setting Resistor Terminal, In-Amp 2
Negative Input, In-Amp 2
Negative Supply
Output, In-Amp 2
Output, In-Amp 1
Positive Supply
Rev. PrD | Page 9 of 20
+IN2
09490-002
5
–VS
10 RG2
+IN1 4
REF2
11 RG2
RG1 3
+VS
12 –IN2
RG1 2
REF1
–IN1 1
AD8426
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.
6.0
+1.35, +1.95
VREF= 1.35V
1.50
+0.01, +1.28
1.00
+2.61, +1.13
+2.17, +0.90
0.50
+2.61, +0.37
+0.01, +0.31
0.00
‐0.50
0.00, ‐0.45
0.0, +4.25
4.0
2.0
–4.93, +1.77
0
–2.0
–4.93, –2.83
0.0, –5.30
–4.0
‐
–6.0
–6.0
‐
–4.0
–2.0
0
4.0
2.0
6.0
OUTPUT VOLTAGE (V)
Output Voltage (V)
Figure 3. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, Vs = 2.7 V, G = 1
Figure 5. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, Vs = ±5 V, G = 1
20.0
+0.02, +4.25
+2.50, +4.25
VREF= 2.5V
4.00
VREF= 0V
3.00
+0.02, +2.95
+4.90, +3.03
+4.64, +2.03
2.00
+0.01, +0.87
1.00
+4.90, +0.82
0.00
+0.01, -0.30
0
0.5
15.0
VS = ±12V
VS = ±15V
0.0, +14.2
10.0
–14.9, +6.7
5.0
+14.8, +6.8
0.0, +11.2
–11.9, +5.2
+11.9, +5.3
0
–11.9, –6.0
–5.0
–15.0
+11.8, –6.5
0.0, –12.3
–14.9, –7.6
+14.8, –7.9
–10.0
0.0, –15.3
+2.50, -0.40
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
OUTPUT VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
5.00
INPUT COMMON MODE VOLTAGE (V)
+4.90, –2.84
+1.35, ‐0.41
‐1.00
‐1.00
-0.5
+4.87, +1.79
00000-000
+0.01, +1.90
00000-000
2.00
VREF= 0V
INPUT COMMON MODE VOLTAGE (V)
Input Common-Mode Voltage (V)
2.50
5.0 5.5 6
Figure 4. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, Vs = 5 V, G = 1
–20.0
–20.0
–15.0
–10.0
–5.0
0
5.0
10.0
15.0
OUTPUT VOLTAGE (V)
Figure 6. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, Vs = ±15 V, G = 1
Rev. PrD | Page 10 of 20
20.0
Preliminary Technical Data
AD8426
THEORY OF OPERATION
+VS
+VS
RG
NODE 3
NODE 4
–VS
–VS
R1
24.7kΩ
R3
50kΩ
R2
24.7kΩ
+VS
R4
50kΩ
NODE 2
ESD AND
OVERVOLTAGE
PROTECTION
+IN
Q1
R5
50kΩ
A1
A2
VOUT
A3
NODE 1
ESD AND
OVERVOLTAGE
PROTECTION
Q2
+VS
–VS
R6
50kΩ
REF
–IN
–VS
VBIAS
RB
–VS
DIFFERENCE
AMPLIFIER STAGE
GAIN STAGE
09490-003
RB
Figure 7. Simplified Schematic
ARCHITECTURE
Table 7. Gains Achieved Using 1% Resistors
The AD8426 is based on the classic three op amp topology. This
topology has two stages: a gain stage (preamplifier) to provide
differential amplification, followed by a difference amplifier to
remove the common-mode voltage. Figure 7 shows a simplified
schematic of one of the instrumentation amplifiers in the AD8426.
1% Standard Table Value of RG
49.9 kΩ
12.4 kΩ
5.49 kΩ
2.61 kΩ
1.00 kΩ
499 Ω
249 Ω
100 Ω
49.9 Ω
The first stage works as follows: to maintain a constant voltage
across the bias resistor, RB, A1 must keep Node 3 at a constant
diode drop above the positive input voltage. Similarly, A2 keeps
Node 4 at a constant diode drop above the negative input voltage.
Therefore, a replica of the differential input voltage is placed
across the gain setting resistor, RG. The current that flows across
this resistance must also flow through the R1 and R2 resistors,
creating a gained differential signal between the A2 and A1 outputs. Note that, in addition to a gained differential signal, the
original common-mode signal, shifted a diode drop up, is also
still present.
The second stage is a difference amplifier, composed of A3 and
four 50 kΩ resistors. The purpose of this stage is to remove the
common-mode signal from the amplified differential signal.
The transfer function of the AD8426 is
VOUT = G × (VIN+ − VIN−) + VREF
where:
G 1
49.4 kΩ
RG
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the
AD8426, which can be calculated by referring to Table 7 or by
using the following gain equation:
RG 
49.4 kΩ
Calculated Gain
1.990
4.984
9.998
19.93
50.40
100.0
199.4
495.0
991.0
The AD8426 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8426 specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain
error and gain drift are minimal.
REFERENCE TERMINAL
The output voltage of the AD8426 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8426 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
For the best performance, source impedance to the REF
terminal should be kept below 2 Ω. As shown in Figure 8,
the reference terminal, REF, is at one end of a 50 kΩ resistor.
Additional impedance at the REF terminal adds to this 50 kΩ
resistor and results in amplification of the signal connected to
the positive input. The amplification from the additional RREF
can be computed by 2 × (50 kΩ + RREF)/100 kΩ + RREF.
G 1
Rev. PrD | Page 11 of 20
AD8426
Preliminary Technical Data
Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades the CMRR of
the amplifier.
AD8426
VREF
VREF
–
–
+VS
Figure 8. Driving the Reference Pin
To ensure optimum performance of the AD8426 at the PCB
level, care must be taken in the design of the board layout.
The AD8426 pins are arranged in a logical manner to aid in
this task.
INPUT VOLTAGE RANGE
16 15 14 13
The three op amp architecture of the AD8426 applies gain in the
first stage before removing common-mode voltage in the
difference amplifier stage. In addition, the input transistors in
the first stage shift the common-mode voltage up one diode
drop. Therefore, internal nodes between the first and second
stages (Node 1 and Node 2 in Figure 7) experience a combination of gained signal, common-mode signal, and a diode drop.
This combined signal can be limited by the voltage supplies even
when the individual input and output signals are not.
Equation 1 to Equation 3 can be used to understand how the
gain (G), common-mode input voltage (VCM), differential input
voltage (VDIFF), and reference voltage (VREF) interact. The values
for the constants, V−LIMIT, V+LIMIT, and VREF_LIMIT, at different temperatures are shown in Table 8. These three formulas, along with
the input and output range specifications in Table 2 and Table 3,
set the operating boundaries of the part.
(V DIFF )(G)
 V S  V  LIMIT
2
(1)
(V )(G)
 DIFF
 VS  V  LIMIT
2
(2)
VCM 
VCM
(V DIFF )(G )
 VCM  V REF
2
 VS  V REF _ LIMIT
2
(3)
Table 8. Input Voltage Range Constants for Various
Temperatures
Temperature
−40°C
+25°C
+85°C
+125°C
V−LIMIT
−0.55
−0.35
−0.15
−0.05
V+LIMIT
+0.8
+0.7
+0.65
+0.6
VREF_LIMIT
+1.3
+1.15
+1.05
+0.9
AD8426
11 RG2
RG1 3
10 RG2
+IN1 4
9
5
6
7
8
–VS
12 –IN2
RG1 2
REF2
–IN1 1
+IN2
09490-002
OP1177
LAYOUT
–VS
+
AD8426
09490-053
+
OUT2
AD8426
VREF
+VS
AD8426
A typical part functions up to the boundaries described in this
section. However, for best performance, designing with a few
hundred millivolts extra margin is recommended. As signals
approach the boundary, internal transistors begin to saturate,
which can affect frequency and linearity performance.
CORRECT
OUT1
CORRECT
REF1
INCORRECT
supply has more margin. Conversely, at hot temperatures, the part
requires less headroom from the positive supply but is subject
to the worst-case conditions for input voltages near the negative
supply.
Figure 9. Pinout Diagram
Package Considerations
The AD8426 is available in a 16-lead, 4 mm × 4 mm LFCSP with
no exposed paddle. The footprint from another 4 mm × 4 mm
LFCSP part should not be copied because it may not have the
correct lead pitch and lead width dimensions. Refer to the
Outline Dimensions section for the correct dimensions.
Hidden Paddle Package
The AD8426 is available in an LFCSP package with a hidden
paddle. Unlike chip scale packages where the pad limits routing
capability, this package allows routes and vias directly beneath
the chip, so that the full space savings of the small LFCSP can be
realized. Although the package has no metal in the center of the
part, the manufacturing process leaves a very small section of
exposed metal at each of the package corners, as shown in
Figure 10 and in Figure 17 in the Outline Dimensions section.
This metal is connected to –VS through the part. Because of the
possibility of a short, vias should not be placed underneath
these exposed metal tabs.
The common-mode input voltage range shifts upward with temperature. At cold temperatures, the part requires extra headroom
from the positive supply, whereas operation near the negative
Rev. PrD | Page 12 of 20
Preliminary Technical Data
AD8426
References
HIDDEN
PADDLE
The output voltage of the AD8426 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground. This should also help
minimize crosstalk between the two channels.
EXPOSED LEAD
FRAME TABS
NOTES
1. EXPOSED LEAD FRAME TABS AT THE FOUR CORNERS
OF THE PACKAGE ARE INTERNALLY CONNECTED TO
+VS. REFER TO THE OUTLINE DIMENSIONS PAGE, FOR
FURTHER INFORMATION ON PACKAGE AVAILABILITY.
INPUT BIAS CURRENT RETURN PATH
09490-055
BOTTOM VIEW
Figure 10. Hidden Paddle Package, Bottom View
The input bias current of the AD8426 must have a return path
to ground. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 12.
INCORRECT
Common-Mode Rejection Ratio over Frequency
CORRECT
+VS
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp. Such
conversions occur when one input path has a frequency response
that is different from the other. To keep CMRR across frequency
high, the input source impedance and capacitance of each path
should be closely matched. Additional source resistance in the
input path (for example, for input protection) should be placed
close to the in-amp inputs, which minimizes their interaction
with parasitic capacitance from the PCB traces.
+VS
AD8426
AD8426
REF
REF
–VS
–VS
TRANSFORMER
TRANSFORMER
+VS
Parasitic capacitance at the gain setting pins can also affect CMRR
over frequency. If the board design has a component at the gain
setting pins (for example, a switch or jumper), the component
should be chosen so that the parasitic capacitance is as small as
possible.
+VS
AD8426
AD8426
REF
Power Supplies
REF
10MΩ
–VS
A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect
performance.
A 0.1 μF capacitor should be placed as close as possible to each
supply pin. As shown in Figure 11, a 10 μF capacitor can be used
farther away from the part. In most cases, it can be shared by
other precision integrated circuits.
–VS
THERMOCOUPLE
THERMOCOUPLE
+VS
+VS
C
C
C
R
1
fHIGH-PASS = 2πRC
AD8426
REF
AD8426
C
REF
+VS
0.1µF
–VS
10µF
CAPACITIVELY COUPLED
+IN
–VS
CAPACITIVELY COUPLED
Figure 12. Creating an Input Bias Current Return Path
VOUT
AD8426
INPUT PROTECTION
LOAD
REF
0.1µF
–VS
10µF
09490-006
–IN
Figure 11. Supply Decoupling, REF, and Output Referred to Local Ground
The AD8426 has very robust inputs and typically does not
need additional input protection. Input voltages can be up to
40 V from the opposite supply rail. For example, with a +5 V
positive supply and a −8 V negative supply, the part can safely
withstand voltages from −35 V to +32 V. Unlike some other
instrumentation amplifiers, the part can handle large differential input voltages even when the part is in high gain.
The rest of the AD8426 terminals should be kept within the
supplies. All terminals of the AD8426 are protected against ESD.
Rev. PrD | Page 13 of 20
09490-007
R
AD8426
Preliminary Technical Data
+VS
limiting resistors and low leakage diode clamps such as the
BAV199, the FJH1100s, or the SP720 should be used.
0.1µF
RADIO FREQUENCY INTERFERENCE (RFI)
RF interference is often a problem when amplifiers are used in
applications where there are strong RF signals. The precision
circuits in the AD8426 can rectify the RF signals so that they
appear as a dc offset voltage error. To avoid this rectification,
place a low-pass RC filter at the input of the instrumentation
amplifier (see Figure 13). The filter limits both the differential
and common-mode bandwidth, as shown in the following
equations:
FilterFreq uency DIFF
FilterFreq uency CM
where CD  10 CC.
1

2πR(2C D  C C )
1

2πRC C
10µF
CC
1nF
R
+IN
4.02kΩ
CD
10nF
VOUT
AD8426
RG
R
REF
–IN
4.02kΩ
CC
1nF
0.1µF
–VS
09490-008
10µF
Figure 13. RFI Suppression
CD affects the differential signal, and CC affects the commonmode signal. Values of R and CC should be chosen to minimize
RFI. Any mismatch between the R × CC at the positive input
and the R × CC at the negative input degrades the CMRR of the
AD8426. By using a value of CD one order of magnitude larger
than CC, the effect of the mismatch is reduced, and performance
is improved.
Rev. PrD | Page 14 of 20
Preliminary Technical Data
AD8426
APPLICATIONS INFORMATION
DIFFERENTIAL DRIVE
Tips for Best Differential Output Performance
Figure 14 shows how to configure the AD8426 for differential
output.
For best ac performance, an op amp with at least 2 MHz gain
bandwidth and 1 V/μs slew rate is recommended. Good choices
for op amps are the AD8641, AD8515, or AD820.
+IN
AD8426
Keep trace lengths from resistors to the inverting terminal of
the op amp as short as possible. Excessive capacitance at this
node can cause the circuit to be unstable. If capacitance cannot
be avoided, use lower value resistors.
+OUT
–IN
REF
R
R
VBIAS
+
–
OP AMP
For best linearity and ac performance, a minimum positive
supply voltage (+VS) is required. Table 9 shows the minimum
supply voltage required for optimum performance where
VCM_MAX indicates the maximum common-mode voltage
expected at the input of the AD8426.
09490-009
–OUT
RECOMMENDED OP AMPS: AD8515, AD8641, AD820.
RECOMMENDED R VALUES: 5kΩ to 20kΩ.
Table 9. Minimum Positive Supply Voltage
Figure 14. Differential Output Using an Op Amp
The differential output is set by the following equation:
VDIFF_OUT = VOUT+ − VOUT− = Gain × (VIN+ − VIN−)
The common-mode output is set by the following equation:
Temperature
Less than −10°C
−10°C to +25°C
More than +25°C
VCM_OUT = (VOUT+ − VOUT−)/2 = VBIAS
The advantage of this circuit is that the dc differential accuracy
depends on the AD8426 and not on the op amp or the resistors.
This circuit takes advantage of the precise control that the AD8426
has of its output voltage relative to the reference voltage. Op amp
dc performance and resistor matching do affect the dc commonmode output accuracy. However, because common-mode errors
are likely to be rejected by the next device in the signal chain,
these errors typically have little effect on overall system accuracy.
Rev. PrD | Page 15 of 20
Equation
+VS > (VCM_MAX + VBIAS)/2 + 1.4 V
+VS > (VCM_MAX + VBIAS)/2 + 1.25 V
+VS > (VCM_MAX + VBIAS)/2 + 1.1 V
AD8426
Preliminary Technical Data
Option 1 shows the minimum configuration required to drive
a charge sampling ADC. The capacitor provides charge to the
ADC sampling capacitor, and the resistor shields the AD8426
from the capacitance. To keep the AD8426 stable, the RC time
constant of the resistor and capacitor needs to stay above 5 μs.
This circuit is mainly useful for lower frequency signals.
PRECISION STRAIN GAGE
The low offset and high CMRR over frequency of the AD8426
make it an excellent candidate for bridge measurements. The
bridge can be connected directly to the inputs of the amplifier
(see Figure 15).
5V
350Ω
350Ω
350Ω
+IN
+
AD8426
RG
–
–IN
2.5V
Option 3 is useful for applications where the AD8426 needs to
run off a large voltage supply, but drives a single supply ADC.
In normal operation, the AD8426 output stays within the ADC
range, and the AD8616 simply buffers it. However, in a fault
condition, the output of the AD8426 may go outside the supply
range of both the AD8616 and the ADC. This is not an issue in
this circuit, because the 10 kΩ resistor between the two
amplifiers limits the current into the AD8616 to a safe level.
Figure 15. Precision Strain Gage
DRIVING AN ADC
Figure 16 shows several different methods of driving an ADC.
The ADC in the ADuC7026 microcontroller was chosen for this
example because it has an unbuffered, charge sampling
architecture that is typical of most modern ADCs. This type of
architecture typically requires an RC buffer stage between the
ADC and the amplifier to work correctly.
3.3V
OPTION 1: DRIVING LOW FREQUENCY SIGNALS
AD8426
3.3V
AVDD
ADC0
100Ω
REF
3.3V
100nF
ADuC7026
OPTION 2: DRIVING HIGH FREQUENCY SIGNALS
3.3V
AD8426
REF
AD8616
10Ω
ADC1
10nF
+15V
OPTION 3: PROTECTING ADC FROM LARGE VOLTAGES
3.3V
AD8426
10kΩ
REF
AD8616
10Ω
ADC2
10nF
–15V
Figure 16. Driving an ADC
Rev. PrD | Page 16 of 20
AGND
09490-065
350Ω
Option 2 shows a circuit for driving higher frequency signals.
It uses a precision op amp (AD8616) with relatively high bandwidth and output drive. This amplifier can drive a resistor and
capacitor with a much higher time constant and is, therefore,
suited for higher frequency applications.
0.1µF
09490-010
10µF
Preliminary Technical Data
AD8426
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
3.75
BCS SQ
0.65
BSC
13
12
SEATING
PLANE
12° MAX
8
5
4
BOTTOM VIEW
0.80 MAX
0.65 TYP
0.35
0.30
0.25
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-263-VBBC
Figure 17. 16-Lead Lead Frame Chips Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad, with Hidden Paddle
(CP-16-19)
Dimensions shown in millimeters
Rev. PrD | Page 17 of 20
062309-B
1.00
0.85
0.80
0.75
0.60
0.50
1
1.95 REF
SQ
9
TOP VIEW
16
AD8426
Preliminary Technical Data
NOTES
Rev. PrD | Page 18 of 20
Preliminary Technical Data
AD8426
NOTES
Rev. PrD | Page 19 of 20
AD8426
Preliminary Technical Data
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR09490-0-6/11(PrD)
Rev. PrD | Page 20 of 20