HEF4067B 16-channel analog multiplexer/demultiplexer Rev. 6 — 16 November 2011 Product data sheet 1. General description The HEF4067B is a 16-channel analog multiplexer/demultiplexer with four address inputs (A0 to A3), an active LOW enable input (E), sixteen independent inputs/outputs (Y0 to Y15) and a common input/output (Z). The device contains sixteen bidirectional analog switches, each with one side connected to an independent input/output (Y0 to Y15) and the other side connected to the common input/output (Z). With E LOW, one of the sixteen switches is selected (low-impedance ON-state) by A0 to A3. All unselected switches are in the high-impedance OFF-state. With E HIGH all switches are in the high-impedance OFF-state, independent of A0 to A3. The analog inputs/outputs (Y0 to Y15 and Z) can swing between VDD as a positive limit and VSS as a negative limit. VDD to VSS may not exceed 15 V. 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF4067BP 40 C to +85 C DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1 HEF4067BT 40 C to +85 C SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer 5. Functional diagram 9 Y0 8 Y1 A0 10 7 Y2 6 Y3 A1 11 5 Y4 4 Y5 A2 14 3 Y6 2 Y7 A3 13 23 Y8 1-OF-16 DECODER 22 Y9 21 Y10 20 Y11 19 Y12 18 Y13 17 Y14 16 Y15 E 15 1 Z 001aag123 Fig 1. Functional diagram Yn VDD VDD Z VSS 001aag126 Fig 2. Schematic diagram (one switch) HEF4067B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer Y0 Y1 Y2 Y3 Y4 A0 Y5 Y6 Y7 A1 Y8 Y9 Y10 A2 Y11 Y12 Y13 A3 Y14 Y15 E Z 001aag125 Fig 3. Logic diagram HEF4067B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning Z 1 24 VDD Y7 2 23 Y8 Y6 3 22 Y9 Y5 4 21 Y10 Y4 5 20 Y11 Y3 6 Y2 7 Y1 8 17 Y14 Y0 9 16 Y15 HEF4067B 19 Y12 18 Y13 A0 10 15 E A1 11 14 A2 VSS 12 13 A3 001aag124 Fig 4. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description Z 1 common input/output Y0 to Y15 9, 8, 7, 6, 5, 4, 3, 2, 23, 22, 21, 20, 19, 18, 17, 16 independent input/output A0 to A3 10, 11, 14, 13 address input VSS 12 ground (0 V) E 15 enable input (active LOW) VDD 24 supply voltage HEF4067B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer 7. Functional description Table 3. Function table[1] Control Address E A3 A2 A1 A0 L L L L L Y0 = Z L L L L H Y1 = Z L L L H L Y2 = Z L L L H H Y3 = Z L L H L L Y4 = Z L L H L H Y5 = Z L L H H L Y6 = Z L L H H H Y7 = Z L H L L L Y8 = Z L H L L H Y9 = Z L H L H L Y10 = Z L H L H H Y11 = Z L H H L L Y12 = Z L H H L H Y13 = Z L H H H L Y14 = Z L H H H H Y15 = Z H X X X X none [1] Channel ON H = HIGH voltage level; L = LOW voltage level; X = don’t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage II/O input/output current IDD Conditions pins An and E; VI < 0.5 V or VI > VDD + 0.5 V Min Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.5 V - 10 mA supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +85 C HEF4067B Product data sheet [1] All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter Conditions Ptot total power dissipation Tamb = 40 C to +125 C P [1] power dissipation DIP24 [2] SO24 [3] per output Min Max Unit - 750 mW - 500 mW - 100 mW To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Yn, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VSS. [2] For DIP24 packages: above Tamb = 70 C, Ptot derates linearly at 12 mW/K. [3] For SO24 packages: above Tamb = 70 C, Ptot derates linearly at 8 mW/K. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD Conditions Min Typ Max Unit supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air 40 - +85 C t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIL VIH LOW-level input voltage HIGH-level input voltage Conditions VDD VO = 0.5 V or 4.5 V Max Min Max Min Max 5V - 1 - 1 - 1 V VO = 1.0 V or 9.0 V 10 V - 2 - 2 - 2 V VO = 1.5 V or 13.5 V 15 V - 2.5 - 2.5 - 2.5 V VO = 0.5 V or 4.5 V 5V 4 - 4 - 4 - V VO = 1.0 V or 9.0 V 10 V 8 - 8 - 8 - V VO = 1.5 V or 13.5 V 15 V 12.5 - 12.5 - 12.5 - V 15 V - 0.3 - 0.3 - 1.0 A A IO < 1 A input leakage current IOZ OFF-state output output at VDD current output at VSS Product data sheet Min IO < 1 A II HEF4067B Tamb = 40 C Tamb = +25 C Tamb = +85 C Unit VI = 0 V or 15 V 15 V - 1.6 - 1.6 - 12.0 15 V - 1.6 - 1.6 - 12.0 A All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer Table 6. Static characteristics …continued VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter IS(OFF) IDD CI OFF-state leakage current supply current Conditions Tamb = 40 C Tamb = +25 C Tamb = +85 C Unit VDD Min Max Min Max Min Max Z port; all channels OFF; see Figure 5 15 V - - - 1000 - - nA Yn port; per channel; see Figure 6 15 V - - - 200 - - nA all valid input combinations; IO = 0 A 5V - 20 - 20 - 150 A 10 V - 40 - 40 - 300 A 15 V - 80 - 80 - 600 A 15 V - - - 7.5 - - pF input capacitance digital inputs 10.1 Test circuits VDD A0 to A3 VDD or VSS Z Yn E IS VSS VDD VI VO 001aal616 Fig 5. Test circuit for measuring OFF-state leakage current Z port VDD VDD or VSS A0 to A3 Y0 1 Z Yn 2 switch IS E VSS VSS VI VO 001aal617 Fig 6. Test circuit for measuring OFF-state leakage current Yn port HEF4067B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer 10.2 On resistance Table 7. ON resistance Tamb = 25 C; ISW = 200 A; VSS = 0 V. Symbol Parameter Conditions VDD Typ Max Unit RON(peak) ON resistance (peak) VI = 0 V to VDD; see Figure 7 and Figure 8 5V 350 2500 10 V 80 245 15 V 60 175 5V 115 340 10 V 50 160 15 V 40 115 5V 120 365 10 V 65 200 15 V 50 155 RON(rail) ON resistance (rail) VI = 0 V; see Figure 7 and Figure 8 VI = VDD; see Figure 7 and Figure 8 RON ON resistance mismatch between channels VI = 0 V to VDD; see Figure 7 5V 25 - 10 V 10 - 15 V 5 - 10.2.1 On resistance waveform and test circuit 001aae648 400 RON (Ω) VDD = 5 V 300 VSW V 200 VDD VDD or VSS A0 to A3 Z Yn 10 V 100 15 V E VSS VSS ISW VI 0 0 5 Test circuit for measuring RON HEF4067B Product data sheet 15 Iis = 200 A; VSS = 0 V. RON = VSW / ISW. Fig 7. 10 VI (V) 001aag127 Fig 8. Typical RON as a function of input voltage All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer 11. Dynamic characteristics Table 8. Dynamic characteristics Tamb = 25 C; VSS = 0 V; for test circuit see Figure 12. Symbol Parameter Conditions VDD Min Typ Max Unit tPHL HIGH to LOW propagation delay Yn, Z to Z, Yn; see Figure 9 5V - 30 60 ns 10 V - 15 25 ns 15 V - 10 20 ns 5V - 190 380 ns 10 V - 70 145 ns An to Yn, Z; see Figure 10 tPLH LOW to HIGH propagation delay Yn, Z to Z, Yn; see Figure 9 An to Yn, Z; see Figure 10 tPHZ tPLZ tPZH HIGH to OFF-state propagation delay LOW to OFF-state propagation delay OFF-state to HIGH propagation delay E to Yn, Z; see Figure 11 E to Yn, Z; see Figure 11 E to Yn, Z; see Figure 11 E to Yn, Z; see Figure 11 tPZL OFF-state to LOW propagation delay HEF4067B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 15 V - 50 100 ns 5V - 25 50 ns 10 V - 10 20 ns 15 V - 10 20 ns 5V - 175 345 ns 10 V - 70 140 ns 15 V - 50 100 ns 5V - 195 385 ns 10 V - 140 280 ns 15 V - 130 260 ns 5V - 215 435 ns 10 V - 180 355 ns 15 V - 170 340 ns 5V - 155 315 ns 10 V - 70 135 ns 15 V - 50 100 ns 5V - 170 340 ns 10 V - 70 140 ns 15 V - 50 100 ns © NXP B.V. 2011. All rights reserved. 9 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer 11.1 Waveforms and test circuit VDD VI Yn or Z input VM VM An input VM VM VSS 0V tPLH tPLH tPHL tPHL VO VOH Yn or Z output VY Yn or Z output VM VM VX VSS switch OFF VOL switch ON switch OFF 001aag199 001aal618 Measurement points are given in Table 9. Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. Yn, Z to Z, Yn propagation delays Fig 10. Sn to Yn, Z propagation delays VI VM E input VM 0V tPLZ tPZL VDD Yn or Z output VM VX VOL tPHZ VOH tPZH VY Yn or Z output VM 0V switch ON switch OFF switch ON 001aag198 Measurement points are shown in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 11. Enable and disable times Table 9. Measurement points Supply voltage Input VCC VM VI VM VX VY 5 V to 15 V 0.5VDD GND to VDD 0.5VDD 10% 90% HEF4067B Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer VDD VDD VI PULSE GENERATOR VO S1 RL open DUT CL RT 001aag183 Test data is given in Table 10. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator CL = load capacitance including jig and probe capacitance RL = load resistor S1 = test selection switch Fig 12. Test circuit for measuring switching times Table 10. Test data Input Yn, Z Load An and E tr, tf VDD or VSS VDD or VSS 20 ns [1] S1 position VM CL RL tPHL[1] 0.5VDD 50 pF 10 k VDD or VSS VSS tPLH tPZH, tPHZ tPZL, tPLZ other VSS VDD VSS For Yn to Z or Z to Yn propagation delays use VSS. For An or to Yn or Z propagation delays use VDD. HEF4067B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer 11.2 Additional dynamic parameters Table 11. Additional dynamic characteristics VSS = 0 V; Tamb = 25 C. Symbol THD f(3dB) Parameter Conditions total harmonic distortion 3 dB frequency response VDD Typ Max Unit see Figure 13; RL = 10 k; CL = 15 pF; 5 V channel ON; VI = 0.5VDD (p-p); 10 V fi = 1 kHz 15 V [1] 0.25 - % [1] 0.04 - % [1] 0.04 - % see Figure 14; RL = 1 k; CL = 5 pF; channel ON; VI = 0.5VDD (p-p) 5V [1] 13 - MHz 10 V [1] 40 - MHz 70 - 50 15 V [1] iso isolation (OFF-state) see Figure 15; fi = 1 MHz; RL = 1 k; CL = 5 pF; channel OFF; VI = 0.5VDD (p-p) 10 V [1] Vct crosstalk voltage digital inputs to switch; see Figure 16; RL = 10 k; CL = 15 pF; E or An = VDD (square-wave) 10 V Xtalk crosstalk between switches; see Figure 17; fi = 1 MHz; RL = 1 k; VI = 0.5VDD (p-p) 10 V [1] 50 [1] MHz - - 50 dB mV - dB fi is biased at 0.5 VDD; VI = 0.5VDD (p-p). Table 12. Dynamic power dissipation PD PD can be calculated from the formulas shown; VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD Typical formula for PD (W) 5V where: PD = 1000 fi + (fo CL) VDD 2 fi = input frequency in MHz; 10 V PD = 5500 fi + (fo CL) VDD 2 fo = output frequency in MHz; 15 V PD = 15000 fi + (fo CL) VDD2 CL = output load capacitance in pF; VDD = supply voltage in V; (CL fo) = sum of the outputs. 11.2.1 Test circuits VDD VDD VDD or VSS A0 to A3 Z VDD or VSS A0 to A3 Z Yn VSS VSS CL RL D fi CL dB fi 001aag235 001aag129 Fig 13. Test circuit for measuring total harmonic distortion Product data sheet VSS VSS RL HEF4067B Yn E E Fig 14. Test circuit for measuring frequency response All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer VDD VDD or VSS A0 to A3 Y0 1 Z Yn 2 switch E VSS VSS RL CL dB fi 001aal619 Fig 15. Test circuit for measuring isolation (OFF-state) 0.5VDD VDD RL A0 to A3 Y0 1 Z Yn 2 switch E VSS VDD or VSS RL CL V VO G 001aag128 a. Test circuit logic input (An, E) off on off VO Vct 001aal620 b. Input and output pulse definitions Fig 16. Test circuit for measuring crosstalk voltage between digital inputs and switch VDD VDD or VSS VDD A0 to A3 Y0 Z Yn VDD or VSS A0 to A3 Y0 Z Yn E E VSS VSS VSS VSS RL VO RL VI VI RL 001aag130 a. Switch closed condition RL VO 001aag131 b. Switch open condition Fig 17. Test circuit for measuring crosstalk between switches HEF4067B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer 12. Package outline seating plane DIP24: plastic dual in-line package; 24 leads (600 mil) SOT101-1 ME D A2 L A A1 c e Z b1 w M (e 1) b MH 13 24 pin 1 index E 1 12 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.1 0.51 4 1.7 1.3 0.53 0.38 0.32 0.23 32.0 31.4 14.1 13.7 2.54 15.24 3.9 3.4 15.80 15.24 17.15 15.90 0.25 2.2 inches 0.2 0.02 0.16 0.066 0.051 0.021 0.015 0.013 0.009 1.26 1.24 0.56 0.54 0.1 0.6 0.15 0.13 0.62 0.60 0.68 0.63 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT101-1 051G02 MO-015 SC-509-24 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 18. Package outline SOT101-1 (DIP24) HEF4067B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 13 24 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 19. Package outline SOT137-1 (SO24) HEF4067B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 15 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer 13. Abbreviations Table 13. Abbreviations Acronym Description DUT Device Under Test 14. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4067B v.6 20111116 Product data sheet - HEF4067B v.5 Modifications: HEF4067B v.5 • • Legal pages updated. Changes in “General description”, “Features and benefits” and “Applications”. 20100325 Product data sheet - HEF4067B v.4 HEF4067B v.4 20100308 Product data sheet - HEF4067B_CNV v.3 HEF4067B_CNV v.3 19950101 Product specification - HEF4067B_CNV v.2 HEF4067B_CNV v.2 19950101 Product specification - - HEF4067B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 16 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Export might require a prior authorization from competent authorities. HEF4067B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 17 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4067B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 November 2011 © NXP B.V. 2011. All rights reserved. 18 of 19 HEF4067B NXP Semiconductors 16-channel analog multiplexer/demultiplexer 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.2.1 11 11.1 11.2 11.2.1 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 On resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 8 On resistance waveform and test circuit. . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms and test circuit . . . . . . . . . . . . . . . 10 Additional dynamic parameters . . . . . . . . . . . 12 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 November 2011 Document identifier: HEF4067B