Cypress CY3692 200-mhz field programmable zero delay buffer Datasheet

CY23FP12-002
200-MHz Field Programmable Zero Delay Buffer
Features
Functional Description
• Pre-programmed Configurations
• Fully field-programmable
— Input and output dividers
— Inverting/noninverting outputs
•
•
•
•
•
•
•
•
•
•
•
•
— Phase-locked loop (PLL) or fanout buffer configuration
10-MHz to 200-MHz operating range
Split 2.5V or 3.3V outputs
Two LVCMOS reference inputs
Twelve low-skew outputs
— Output-output skew < 200 ps
— Device-device skew < 500 ps
Input-output skew < 250 ps
Cycle-cycle jitter < 100 ps (typical)
Three-stateable outputs
< 50-µA shutdown current
Spread Aware
28-pin SSOP
3.3V operation
Industrial temperature available
The CY23FP12-002 is a pre-programmed version of the
CY23FP12. It features a high-performance fully field-programmable 200 MHz zero delay buffer designed for high speed
clock distribution. The integrated PLL is designed for low jitter
and optimized for noise rejection. These parameters are
critical for reference clock distribution in systems using highperformance ASICs and microprocessors.
The CY23FP12-002 is fully programmable via volume or
prototype programmers enabling the user to define an application-specific Zero Delay Buffer with customized input and
output dividers, feedback topology (internal/external), output
inversions, and output drive strengths. For additional flexibility,
the user can mix and match multiple functions, listed in
Table 2, and assign a particular function set to any one of the
four possible S1-S2 control bit combinations. This feature
allows for the implementation of four distinct personalities,
selectable with S1-S2 bits, on a single programmed silicon.
The CY23FP12-002 also features a proprietary auto-powerdown circuit that shuts down the device in case of a REF
failure, resulting in less than 50 µA of current draw.
The CY23FP12-002 provides twelve outputs grouped in two
banks with separate power supply pins which can be
connected independently to either a 2.5V or a 3.3V rail.
Selectable reference input is a fault tolerance feature which
allows for glitch-free switch over to secondary clock source
when REFSEL is asserted/de-asserted.
Block Diagram
Pin Configuration
SSOP
Top View
VDDA
VDDC
CLKA0
Lock Detect
CLKA1
CLKA2
CLKA3
REFSEL
CLKA4
REF1
REF2
FBK
÷M
÷N
100 to
400MHz
PLL
CLKA5
÷1
VSSA
÷2
÷3
VDDB
÷4
CLKB0
÷X
CLKB1
÷2X
CLKB2
REF2
REF1
1
28
2
27
CLKB0
CLKB1
3
26
4
25
VSSB
CLKB2
CLKB3
VDDB
VSSB
CLKB4
CLKB5
VDDB
VDDC
S2
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
REFSEL
FBK
CLKA0
CLKA1
VSSA
CLKA2
CLKA3
VDDA
VSSA
CLKA4
CLKA5
VDDA
VSSC
S1
CLKB3
Test Logic
S[2:1]
CLKB4
Function
Selection
CLKB5
VSSC
Cypress Semiconductor Corporation
Document #: 38-07644 Rev. **
VSSB
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 25, 2004
CY23FP12-002
Pin Description
.
Pin
Name
I/O
Type
Description
1
REF2
I
LVTTL/LVCMOS
Input reference frequency, 5V-tolerant input.
2
REF1
I
LVTTL/LVCMOS
Input reference frequency, 5V-tolerant input.
3
CLKB0
O
LVTTL
Clock output, Bank B.
4
CLKB1
O
LVTTL
Clock output, Bank B.
5
VSSB
PWR
POWER
Ground for Bank B.
6
CLKB2
O
LVTTL
Clock output, Bank B.
7
CLKB3
O
LVTTL
Clock output, Bank B.
8
VDDB
PWR
POWER
2.5V or 3.3V supply, Bank B.
9
VSSB
PWR
POWER
Ground for Bank B.
10
CLKB4
O
LVTTL
Clock output, Bank B.
11
CLKB5
O
LVTTL
Clock output, Bank B.
12
VDDB
PWR
POWER
2.5V or 3.3V supply, Bank B.
13
VDDC
PWR
POWER
3.3V core supply.
14
S2
I
LVTTL
Select input.
15
S1
I
LVTTL
Select input.
16
VSSC
PWR
POWER
Ground for core.
17
VDDA
PWR
POWER
2.5V or 3.3V supply, Bank A.
18
CLKA5
O
LVTTL
Clock output, Bank A.
19
CLKA4
O
LVTTL
Clock output, Bank A.
20
VSSA
PWR
POWER
Ground for Bank A.
21
VDDA
PWR
POWER
2.5V or 3.3V supply Bank A.
22
CLKA3
O
LVTTL
Clock output, Bank A.
23
CLKA2
O
LVTTL
Clock output, Bank A.
24
VSSA
PWR
POWER
Ground for Bank A.
25
CLKA1
O
LVTTL
Clock output, Bank A.
26
CLKA0
O
LVTTL
CLock output, Bank A.
27
FBK
I
LVTTL
PLL feedback input.
28
REFSEL
I
LVTTL
Reference select input. REFSEL = 0, REF1 is
selected. REFSEL = 1, REF2 is selected.
Document #: 38-07644 Rev. **
Page 2 of 10
CY23FP12-002
CLKB5
/1,/2,/3,/4,
/x,/2x
CLKB4
/1,/2,/3,/4,
/x,/2x
REF
/M
/1,/2,/3,/4,
/x,/2x
PLL
FBK
/N
CLKB3
CLKB2
Output
CLKB1
Function
CLKB0
Select
CLKA5
/1,/2,/3,/4,
/x,/2x
Matrix
CLKA4
/1,/2,/3,/4,
/x,/2x
CLKA3
/1,/2,/3,/4,
/x,/2x
CLKA1
CLKA2
CLKA0
Figure 1. Basic PLL Block Diagram
Below is a list of independent functions that can be
programmed with a volume or prototype programmer on the
“pre-programmed” silicon.
Table 1.
Configuration
Description
Default
DC Drive Bank A
Programs the drive strength of Bank A outputs. The user can select one out +20 mA
of two possible drive strength settings that produce output DC currents in the
range of ±16 mA to ±20 mA.
DC Drive Bank B
Programs the drive strength of Bank B outputs. The user can select one out +20 mA
of two possible drive strength settings that produce output DC currents in the
range of ±16 mA to ±20 mA.
Output Enable for Bank B clocks
Enables/Disables CLKB[5:0] outputs. Each of the six outputs can be disabled Enable
individually if not used, to minimize electromagnetic interference (EMI) and
switching noise.
Output Enable for Bank A clocks
Enables/Disables CLKA[5:0] outputs. Each of the six outputs can be disabled Enable
individually if not used, to minimize EMI and switching noise.
Inv CLKA0
Generates an inverted clock on the CLKA0 output. When this option is
programmed, CLKA0 and CLKA1 will become complimentary pairs.
Non-invert
Inv CLKA2
Generates an inverted clock on the CLKA2 output. When this option is
programmed, CLKA2 and CLKA3 will become complimentary pairs.
Non-invert
Inv CLKA4
Generates an inverted clock on the CLKA4 output. When this option is
programmed, CLKA4 and CLKA5 will become complimentary pairs.
Non-invert
Inv CLKB0
Generates an inverted clock on the CLKB0 output. When this option is
programmed, CLKB0 and CLKB1 will become complimentary pairs.
Non-invert
Inv CLKB2
Generates an inverted clock on the CLKB2 output. When this option is
programmed, CLKB2 and CLKB3 will become complimentary pairs.
Non-invert
Document #: 38-07644 Rev. **
Page 3 of 10
CY23FP12-002
Table 1. (continued)
Configuration
Description
Inv CLKB4
Default
Generates an inverted clock on the CLKB4 output. When this option is
programmed, CLKB4 and CLKB5 will become complimentary pairs.
Non-invert
Pull-down Enable
Enables/Disables internal pulldowns on all outputs
Enable
Fbk Pull-down Enable
Enables/Disables internal pulldowns on the feedback path (applicable to both Enable
internal and external feedback topologies)
Fbk Sel
Selects between the internal and the external feedback topologies
Internal
Below is a list of independent functions, which can be
assigned to each of the four S1 and S2 combinations. When
a particular S1 and S2 combination is selected, the device will
assume the configuration (which is essentially a set of
functions given in Table 2, below) that has been preassigned
to that particular combination.
Table 2.
Function
Description
Default
Output Enable CLKB[5:4] Enables/Disables CLKB[5:4] output pair
Enable
Output Enable CLKB[3:2] Enables/Disables CLKB[3:2] output pair
Enable
Output Enable CLKB[1:0] Enables/Disables CLKB[1:0] output pair
Enable
Output Enable CLKA[5:4] Enables/Disables CLKA[5:4] output pair
Enable
Output Enable CLKA[3:2] Enables/Disables CLKA[3:2] output pair
Enable
Output Enable CLKA[1:0] Enables/Disables CLKA[1:0] output pair
Enable
Auto Power-down Enable Enables/Disables the auto power down circuit, which monitors the reference clock rising Enable
edges and shuts down the device in case of a reference “failure.” This failure is triggered
by a drift in reference frequency below a set limit. This auto power down circuit is
disabled internally when one or more of the outputs are configured to be driven directly
from the reference clock.
PLL Power-down
Shuts down the PLL when the device is configured as a non-PLL fanout buffer.
M[7:0]
Assigns an eight-bit value to reference divider –M. The divider can be any integer value See
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
Table 4
N[7:0]
Assigns an eight-bit value to feedback divider –N. The divider can be any integer value See
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
Table 4
X[6:0]
Assigns a seven-bit value to output divider –X. The divider can be any integer value
from 5 to 130. Divide by 1,2,3, and 4 are preprogrammed on the device and can be
activated by the appropriate output mux setting.
See
Table 4
Divider Source
Selects between the PLL output and the reference clock as the source clock for the
output dividers.
See
Table 4
CLKA54 Source
Independently selects one out of the eight possible output dividers that will connect to See
the CLKA5 and CLKA4 pair. Please refer to Table 3 for a list of divider values.
Table 4
CLKA32 Source
Independently selects one out of the eight possible output dividers that will connect to See
the CLKA3 and CLKA2 pair. Please refer to Table 3 for a list of divider values.
Table 4
CLKA10 Source
Independently selects one out of the eight possible output dividers that will connect to See
the CLKA1 and CLKA0 pair. Please refer to Table 3 for a list of divider values.
Table 4
CLKB54 Source
Independently selects one out of the eight possible output dividers that will connect to See
the CLKB5 and CLKB4 pair. Please refer to Table 3 for a list of divider values.
Table 4
CLKB32 Source
Independently selects one out of the eight possible output dividers that will connect to See
the CLKB3 and CLKB2 pair. Please refer to Table 3 for a list of divider values.
Table 4
CLKB10 Source
Independently selects one out of the eight possible output dividers that will connect to See
the CLKB1 and CLKB0 pair. Please refer to Table 3 for a list of divider values.
Table 4
Document #: 38-07644 Rev. **
See
Table 4
Page 4 of 10
CY23FP12-002
Table 3 is a list of output dividers that are independently
selected to connect to each output pair.
In the default (pre-programmed) state of the device, S1 and S2
pins will function, as indicated in Table 4. One possible
example output is shown in this table. This example is for illustration purposes only, since many other frequency combinations are possible for each pre-programmed configuration.
Table 3.
CLKA/B Source
Output Connects To
0 [000]
REF
1 [001]
Divide by 1
2 [010]
Divide by 2
3 [011]
Divide by 3
4 [100]
Divide by 4
5 [101]
Divide by X
6 [110]
Divide by 2X[1]
Field Programming the CY23FP12-002
The CY23FP12-002 is programmed at the package level, i.e.
in a programmer socket. The CY23FP12-002 is flashtechnology based, so the parts can be reprogrammed up to
100 times. This allows for fast and easy design changes and
product updates, and eliminates any issues with old and outof-date inventory.
Samples and small prototype quantities can be programmed
on the CY3672 programmer. Cypress’s value-added distribution partners and third-party programming systems from BP
Microsystems, HiLo Systems, and others are available for
large production quantities.
CyberClocks Software
CyberClocks is an easy-to-use software application that
allows the user to custom-configure the CY23FP12-002.
Users can specify the REF, PLL frequency, output frequencies
and/or post-dividers, and different functional options. CyberClocks outputs an industry standard JEDEC file used for
programming the CY23FP12-002.
CyberClocks can be downloaded free of charge from the
Cypress website at www.cypress.com.
7 [111]
TEST mode [LOCK signal][2]
Table 4. Pre-Programmed Configuration
CY3672 FTG Development Kit
ClkA0, A1
00
1
25
200
200
ClkA2, A3
00
3
25
200
66.7
ClkA4, A5
00
X=6
25
200
33.3
The Cypress CY3672 FTG Development Kit comes complete
with everything needed to design with the CY23FP12-002 and
program samples and small prototype quantities. The kit
comes with the latest version of CyberClocks and a small
portable programmer that connects to a PC serial port for
on-the-fly programming of custom frequencies.
The JEDEC file output of CyberClocks can be downloaded to
the portable programmer for small-volume programming, or
for use with a production programming system for larger
volumes.
ClkB0, B1
00
X=6
25
200
33.3
CY23FP12-002 Frequency Calculation
ClkB2, B3
00
4
25
200
50
ClkB4, B5
00
Ref
25
200
25
ClkA0, A1
01
4
100
200
50
ClkA2, A3
01
4
100
200
50
ClkA4, A5
01
4
100
200
50
ClkB0, B1
01
4
100
200
50
ClkB2, B3
01
X=8
100
200
25
ClkB4, B5
01
X=8
100
200
25
ClkA0, A1
10
X=8
33.3
266.6
33.3
ClkA2, A3
10
X=8
33.3
266.6
33.3
ClkA4, A5
10
X=8
33.3
266.6
33.3
ClkB0, B1
10
4
33.3
266.6
66.6
ClkB2, B3
10
4
33.3
266.6
66.6
ClkB4, B5
10
4
33.3
266.6
66.6
ClkA0, A1
11
Ref
100
powerdown
100
ClkA2, A3
11
Ref
100
powerdown
100
ClkA4, A5
11
Ref
100
powerdown
100
ClkB0, B1
11
2
100
powerdown
50
ClkB2, B3
11
2
100
powerdown
50
In addition to above divider options, the another option
bypasses the PLL and passes the REF directly to the output.
ClkB4, B5
11
2
100
powerdown
50
FOUT = FREF.
Example Output
Outputs S2, S1 DivSrc
REF Input
Output
(MHz) VCO (MHz) (MHz)
The CY23FP12-002 is an extremely flexible clock buffer with
up to twelve individual outputs, generated from an integrated
PLL.
There are four variables used to determine the final output
frequency. These are the input Reference Frequency M, the N
dividers, and the post divider X.
The basic PLL block diagram is shown in Figure 1. Each of the
six clock outputs pair has many output options available to it.
There are six post divider options: /1, /2, /3, /4, /X, and /2X.
The post divider options can be applied to the calculated PLL
frequency or to the REF directly. The feedback either is
connected to CLKA0 internally or connected to any output
externally.
A programmable divider, M, is inserted between the reference
input, REF, and the phase detector. The divider M can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
A programmable divider, N, is inserted between the feedback
input, FBK, and the phase detector. The divider N can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
So the output can be calculated as following:
FREF / M = FFBK / N.
FPLL = (FREF * N * post divider)/M.
FOUT = FPLL / post divider.
Note:
1. Outputs will be rising edge aligned only to those outputs using this same device setting.
2. When the source of an output pair is set to [111], the output pair becomes lock indicator signal. For example, if the source of an output pair (CLKA0, CLKA1) is
set to [111], the CLKA0 and CLKA1, becomes lock indicator signals. In non-invert mode, CLKA0 and CLKA1 signals will be high when the PLL is in lock mode.
If CLKA0 is in an invert mode, the CLKA0 will be low and the CLKA1 will be high when the PLL is in lock mode.
Document #: 38-07644 Rev. **
Page 5 of 10
CY23FP12-002
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Supply Voltage
Non-functional
–0.5
7
VDC
VIN
Input Voltage REF
Relative to VCC
–0.5
7
VDC
VIN
Input Voltage Except REF
Relative to VCC
–0.5
VDD + 0.5
VDC
LUI
Latch-up Immunity
Functional
TS
Temperature, Storage
Non-functional
TA
Temperature, Operating Ambient
Commercial Temperature
300
mA
–65
+125
°C
0
+70
°C
–40
+85
°C
125
°C
TA
Temperature, Operating Ambient
Industrial Temperature
TJ
Junction Temperature
Industrial Temperature
ØJc
Dissipation, Junction to Case
Functional
34
°C/W
ØJa
Dissipation, Junction to Ambient
Functional
86
°C/W
ESDh
ESD Protection (Human Body Model)
MSL
Moisture Sensitivity Level
GATES
Total Functional Gate Count
Assembled Die
UL–94
Flammability Rating
@ 1/8 in.
FIT
Failure in Time
Manufacturing test
TPU
Power-up time for all VDDs to reach
minimum specified voltage (power
ramps must be monotonic)
2000
V
MSL – 1
class
21375
each
V–0
class
10
ppm
0.05
500
ms
DC Electrical Specifications for CY23FP12-002SC/I
Max.
Unit
VDDC
Parameter
Core Supply Voltage
Description
Test Conditions
3.135
Min.
Typ.
3.465
V
VDDA, VDDB
Bank A, Bank B
Supply Voltage
3.135
3.465
V
2.375
2.625
V
0.3 × VDD
V
Voltage[3]
VIL
Input LOW
VIH
Input HIGH Voltage[3]
Current[3]
0.7 × VDD
V
IIL
Input LOW
50.0
µA
IIH
Input HIGH Current[3] VIN = VDD
50.0
µA
VOL
Output LOW Voltage[4]
VDDA/VDDB = 3.3V, IOL = 16 mA (standard drive)
VDDA/VDDB = 3.3V, IOL = 20 mA (high drive)
VDDA/VDDB = 2.5V, IOL = 16 mA (high drive)
0.5
V
VOH
Output HIGH
Voltage[4]
VDDA/VDDB = 3.3V, IOH = –16 mA (standard drive)
VDDA/VDDB = 3.3V, IOH = –20 mA (high drive)
VDDA/VDDB = 2.5V, IOH = –16 mA (high drive)
IDDS
Power-down Supply
Current
REF = 0 MHz
12
50
µA
IDD
Supply Current
VDDA = VDDB = 2.5V, Unloaded outputs @ 166 MHz
40
65.0
mA
VDDA = VDDB = 2.5V, Loaded outputs @ 166 MHz,
CL = 15 pF
65
100
VDDA = VDDB = 3.3V, Unloaded outputs @ 166 MHz
50
80
VDDA = VDDB = 3.3V, Loaded outputs @ 166 MHz,
CL = 15 pF
100
120
VIN = 0V
VDD – 0.5
V
Notes:
3. Applies to both Ref Clock and FBK.
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document #: 38-07644 Rev. **
Page 6 of 10
CY23FP12-002
Switching Characteristics for CY23FP12-002SC/I [5]
Parameter
Description
Reference
Test Conditions
Frequency[6]
t3
t4
TTB
Unit
200
MHz
V/ns
25
75
%
10
200
MHz
CL = 15 pF, Industrial Temperature
10
166.7
CL = 30 pF, Commercial Temperature
10
100
CL = 15 pF, Commercial Temperature
CL = 30 pF, Industrial Temperature
10
Duty Cycle[5]
VDDA/B = 3.3V, measured at VDD/2
45.0
50.0
55.0
VDDA/B = 2.5V
40.0
50.0
60.0
Rise Time[5]
VDDA/B = 3.3V, 0.8V to 2.0V,
CL = 30 pF (standard drive and high drive)
1.6
VDDA/B = 3.3V, 0.8V to 2.0V,
CL = 15 pF (standard drive and high drive)
0.8
VDDA/B = 2.5V, 0.6V to 1.8V,
CL = 30 pF (high drive only)
2.0
VDDA/B = 2.5V, 0.6V to 1.8V,
CL = 15 pF (high drive only)
1.0
VDDA/B = 3.3V, 0.8V to 2.0V,
CL = 30 pF (standard drive and high drive)
1.6
VDDA/B = 3.3V, 0.8V to 2.0V,
CL = 15 pF (standard drive and high drive)
0.8
VDDA/B = 2.5V, 0.6V to 1.8V,
CL = 30 pF (high drive only)
1.6
VDDA/B = 2.5V, 0.6V to 1.8V,
CL = 15 pF (high drive only)
0.8
Outputs @200 MHz, tracking skew not
included
650
Fall Time[5]
Total Timing Budget,[8,9]
Bank A and B same
frequency
83.3
Total Timing Budget, Bank
A and B different frequency
t5
Max.
1
Reference Duty Cycle
Output Frequency[7]
Typ.
10
Reference Edge Rate
t1
Min.
%
ns
ns
ps
850
Output to Output Skew[5]
All outputs equally loaded
200
Bank to Bank Skew
Same frequency
200
Bank to Bank Skew
Different frequency
400
Bank to Bank Skew
Different voltage, same frequency
400
ps
t6
Input to Output Skew (static Measured at VDD/2, REF to FBK
phase offset)[5]
0
250
ps
t7
Device to Device Skew[5]
Measured at VDD/2
0
500
ps
tJ
Cycle to Cycle Jitter[5]
(Peak-to-peak)
Bank A and B same frequency
200
ps
Cycle to Cycle Jitter[5]
(Peak-to-peak)
Bank A and B different frequency
400
Notes:
5. All parameters are specified with loaded outputs.
6. When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the reference frequency can be lower than 10MHz. With auto powerdown disabled and PLL power-down enabled, the reference frequency can be as low as DC level.
7. When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the output frequency can be lower than 10MHz. With auto power-down
disabled and PLL power-down enabled, the output frequency can be as low as DC level.
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply
voltage, operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output
skew, cycle-cycle jitter, and dynamic phase error.TTB will be equal to or smaller than the maximum specified value at a given frequency.
Document #: 38-07644 Rev. **
Page 7 of 10
CY23FP12-002
Switching Characteristics for CY23FP12-002SC/I [5]
Max.
Unit
ttsk
Parameter
Tracking Skew
Description
Input reference clock @ < 50-KHz modulation
with ±3.75% spread
Test Conditions
Min.
Typ.
200
ps
tLOCK
PLL Lock Time[5]
Stable power supply, valid clock at REF
1.0
ms
TLD
Inserted Loop Delay
Max loop delay for PLL Lock (stable
frequency)
7
ns
Max loop delay to meet Tracking Skew Spec
4
ns
Switching Waveforms
Duty Cycle Timing
t1
t2
1.4V
1.4V
1.4V
All Outputs Rise/Fall Time
OUTPUT
2.0V
0.8V
2.0V
0.8V
3.3V
0V
t4
t3
Output-Output Skew
OUTPUT
1.4V
1.4V
OUTPUT
t5
Input-Output Propagation Delay
INPUT
VDD/2
VDD/2
FBK
t6
Device-Device Skew
VDD/2
FBK, Device 1
VDD/2
FBK, Device 2
t7
Document #: 38-07644 Rev. **
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CY23FP12-002
Test Circuits
Test Circuit # 1
VDD
0.1 µF
CLK OUT
OUTPUTS
C LOAD
V DD
0.1 µF
GND
GND
Test Circuit for all parameters
Ordering Information
Ordering Code
CY23FP12OC-002
CY23FP12OC-002T
CY23FP12OI-002
CY23FP12OI-002T
CY3672
CY3692
Package Type
28-pin SSOP
28-pin SSOP – Tape and Reel
28-pin SSOP
28-pin SSOP – Tape and Reel
Development Kit
CY23FP12S Socket (Label CY3672 ADP006)
Operating Range
Commercial, 0°C to 70°C
Commercial,0°C to 70°C
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
Package Drawing and Dimension
28-lead (5.3 mm) Shrunk Small Outline Package O28
51-85079-*C
Total Timing Budget, TTB, Spread Aware, and CyberClocks are trademarks of Cypress Semiconductor. All product and company
names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07644 Rev. **
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© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY23FP12-002
Document History Page
Document Title: CY23FP12-002 200-MHz Field Programmable Zero Delay Buffer
Document Number: 38-07644
REV.
ECN NO.
Issue Date
Orig. of
Change
**
206761
See ECN
RGL
Document #: 38-07644 Rev. **
Description of Change
New Data Sheet
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