BOARDCOM MGA-13216 High gain, high linearity, very low noise amplifier Datasheet

MGA-13216
High Gain, High Linearity, Very Low Noise Amplifier
Data Sheet
Description
Features
Avago Technologies’ MGA-13216 is a two stage, easy-touse GaAs MMIC Low Noise Amplifier (LNA). The LNA has
low noise with good input return loss and high linearity
achieved through the use of Avago Technologies’ proprietary 0.25 Pm GaAs Enhancement-mode pHEMT process.
Minimum matching needed for input, output and the
inter-stage between the two LNA.
x
x
x
x
x
x
It is designed for optimum use between 1.5 GHz to 2.5
GHz. For optimum performance at lower frequency from
400 MHz to 1.5 GHz, the MGA-13116 is recommended.
Both MGA-13216 & MGA-13116 share the same package
and pinout configuration.
x Low cost small package size: 4.0 x 4.0 x 0.85 mm3
Pin Configuration and Package Marking
TOP VIEW
16
15
12
1
11
2
GND
Pin 2
Pin 3
Pin 10
Pin 11
Pin 13
Pin 16
Vbias
RFinQ1
RFoutQ2
RFoutQ2
RFinQ2
RFoutQ1
All other pins NC
– Not Connected
5
4
6
3
9
7
10
8
AVAGO
13216
YYWW
XXXX
14
13
4.0 x 4.0 x 0.85 mm3 16-lead QFN
BOTTOM VIEW
Optimum frequency of operation 1.5 GHz – 2.5 GHz
Very low noise figure
High gain
High linearity performance
Excellent isolation
GaAs E-pHEMT Technology[1]
Specifications
1.95 GHz; Q1: 5 V, 53 mA (typ) Q2: 5 V, 122 mA (typ)
x
x
x
x
x
0.61 dB Noise Figure
35.8 dB Gain
46 dB RFoutQ1 to RFinQ2 Isolation
40.5 dBm Output IP3
23.6 dBm Output Power at 1dB gain compression
Applications
x Low noise amplifier for cellular infrastructure including
GSM, CDMA, and W-CDMA.
x Other very low noise applications.
Simplified Schematic
Note:
Package marking provides orientation and identification
“13216” = Device Part Number
“YYWW” = Work Week and Year of Manufacture
“XXXX” = Lot Number
C10
C9
R4
R2
C7
R3
C8
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 90 V
ESD Human Body Model = 650 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Vdd2
Vdd1
16
L1
RFIN C1
C5
L3
C6
15
C4
R1
C3
14 13
1
12
2 Q1bias
11
3
Q1
L2
C2
Q2
RFOUT
10
4
9
5
6
7
8
Notes: Enhancement mode technology employs positive gate bias,
thereby eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
MGA-13216 Absolute Maximum Rating [1] TA = 25° C
Thermal Resistance [3]
Symbol
Parameter
Units
Absolute Maximum
Vdd1
Device Voltage
V
5.5
Vdd2
Device Voltage
V
5.5
Idd1
Q1 Drain Current
mA
90
Pd
Power Dissipation (2)
W
1.11
Pin,max
CW RF Input Power
dBm
20
Tj,max
Junction Temperature
°C
150
Tstg
Storage Temperature
°C
-65 to 150
(Vdd1 =5.0V, Idd1 =53mA, Vdd2 =5.0V,
Idd2 =122mA) Tjc = 40.3° C/W
Notes:
1. Operation of this device in excess of any of
these limits may cause permanent damage.
2. Board temperature (Tc) is 25° C. For Tc >100° C,
derate the device power at 24.8 mW per °C
rise in board temperature adjacent to package bottom.
3. Thermal resistance measured using Infrared
Measurement Technique.
Electrical Specifications [1]
RF performance at Vdd1 = 5 V, Vdd2 = 5 V, 1.95 GHz, TA = 25° C, measured on the demo board for 1.95 GHz matching.
Symbol
Parameter and Test Condition
Units
Min.
Typ.
Max.
Idd1
Current at Q1
mA
39
53
67
Idd2
Current at Q2
mA
101
122
143
NF
Noise Figure
dB
–
0.61
0.9
Gain
Gain
dB
34.3
35.8
37.3
OIP3[2]
Output Third Order Intercept Point
dBm
37
40.5
–
OP1dB
Output Power at 1 dB Gain Compression
dBm
22.3
23.6
–
IRL
Input Return Loss, 50 : source
dB
–
-18
–
ORL
Output Return Loss, 50 : load
dB
–
-10.7
–
|S12|
Reverse Isolation
dB
–
55
–
|ISOL1-2|
Isolation between Q1’s Output pin & Q2’s Input pin
dB
–
46
–
Notes:
1. Measurements obtained using demo board described in Figure 7 with component list in Table 1. Input and Output trace loss is not de-embedded
from the measurement.
2. OIP3 test condition: ftone1 = 1.95 GHz, ftone2 = 1.951 GHz with input power of -27 dBm per tone.
3. Use proper bias, heatsink and derating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application
note for more details.
2
Product consistency Distribution Charts [1,2]
LSL
USL
40
50
60
100
Figure 1. Idd1 @ 1. 95 GHz, Vdd1 = 5 V, LSL = 39 mA, Nominal = 53 mA,
USL = 67 mA
USL
0.4
0.5
0.6
0.7
0.8
USL
110
120
130
140
Figure 2. Idd2 @ 1.95 GHz, Vdd2 = 5 V, LSL = 101 mA, Nominal = 122 mA,
USL = 143 mA
LSL
0.9
Figure 3. Noise Figure @ 1. 95 GHz, Vdd1 = 5 V, Vdd2 = 5 V,
Nominal = 0.61 dB, USL = 0.9 dB
USL
35
36
37
Figure 4. Gain @ 1. 95 GHz, Vdd1 = 5 V, Vdd2 = 5 V, LSL = 34.3 dB,
Nominal = 35.8 dB, USL = 37.3 dB
LSL
LSL
37
LSL
38
39
40
41
42
Figure 5. OIP3 @ 1. 95 GHz, Vdd1 = 5 V, Vdd2 = 5 V, LSL = 37 dBm,
Nominal = 40.5 dBm
43
22.5
23
23.5
24
24.5
Figure 6. OP1dB @ 1. 95 GHz, Vdd1 = 5 V, Vdd2 = 5 V, LSL = 22.3 dBm,
Nominal = 23.6 dBm
Notes:
1. Data sample size is 9193 samples taken from 3 different wafers. Future wafers allocated to this product may have nominal values anywhere
between the upper and lower limits.
2. Measurements are made on production test board which represents a trade-off between optimal Gain, NF, OIP3 and OP1dB. Circuit losses have
been de-embedded from actual measurements.
3
C9b
C9a
R3
C8
C11
Vdd2
GND
VDD2
Vdd1
GND
R4b
R4a
IN
Demo Board Schematic
VDD1
GND
VBias
Demo Board Layout
C10
C9
R5
C10 C12
R2
R4
R2
C7
C5b
C7 L3
C5a
C4
C6 R1
C3
OUT
L2
C5
R3
C8
L3
C6
C4
R1
C3
C2
C1 L1
L4
L5
C13
16 15
L1
JAN 2011
AVAGO
Technologies
RFIN
12
2 Q1bias
11
C1
3
MANGROVE
14 13
1
Q1
C2
Q2
RFOUT
10
4
9
5
Figure 7. Demo Board layout diagram.
L2
6
7
8
Figure 8. Demo Board schematic diagram.
– Recommended PCB material is 10 mils Rogers R04350.
– Suggested component values may vary according to layout and PCB material.
Table 1. Component list for 1.95GHz matching
Part
Size
Value
Detail Part Number
Notes
C1
0402
10pF (Murata)
GRM1555C1H100JZ01E
DC Blocking Capacitor
C2
0402
100pF (Murata)
GRM1555C1H101JD01E
DC Blocking Capacitor
C3
0402
3.3pF (Murata)
MCH155A3R3JK
Bypass Capacitor
C4
0402
0.1uF (Murata)
GRM155R61A104KA01D
Bypass Capacitor
C5a
0603
2.2uF (Murata)
GRM188R61A225KE34D
Bypass Capacitor
C6
0402
1000pF (Murata)
GRM155R71H102KA01E
DC Blocking Capacitor
C7, C8
0402
10pF (Murata)
GRM1555C1H100JZ01E
Bypass Capacitors
C9a, C10
0402
4.7uF (Murata)
GRM155R60E475ME760
Bypass Capacitors
C9b
N/A
Not used
Not used
Bypass Capacitors
L1
0402
5.6nH (Toko)
LL1005-FHL5N6S
Input match for NF
L2
0402
4.7nH (Toko)
LL1005-FH4N7S
Output match for Q2
L3
0402
100nH (Toko)
LL1005-FHLR10J
Output match for Q1
R1, R2
0402
0 ohm (Koa)
RK73Z1ELTP
Bridging Resistors
R3
0402
49.9 ohm (Koa)
RK73H1ELTP49R9F
Stabilizing Resistor for Q1
R4b
0402
4.7K ohm (Rohm)
MCR01J472
Biasing Resistor for Q1
4
MGA-13216 Typical Performance in Demoboard for 1.95 GHz
TA = 25° C, Vdd1 = 5.0 V, Vdd2 = 5.0 V, Idd1 = 53 mA, Idd2 = 122 mA
1.2
40.0
1.0
85° C
25° C
-40° C
38.0
Gain (dB)
NF (dB)
0.8
0.6
36.0
34.0
0.4
85° C
25° C
-40° C
0.2
0.0
1300
1500
1700
1900 2100
Frequency (MHz)
2300
2500
32.0
30.0
1300
2700
Figure 9. NF vs Frequency and Temperature
1500
1700
1900 2100 2300
Frequency (MHz)
2500
2700
Figure 10. Gain vs Frequency and Temperature
50.0
26.0
OP1dB (dBm)
OIP3 (dBm)
45.0
40.0
35.0
1500
1700
1900 2100 2300
Frequency (MHz)
2500
85° C
25° C
-40° C
10
-10
S11
S22
S21
S12
0
1
2
3
Frequency (GHz)
4
5
Figure 13. Input Return Loss, Output Return Loss, Gain, & Reverse Isolation
vs Frequency
5
1700
1900 2100 2300
Frequency (MHz)
2500
2700
10
9
8
7
6
5
4
3
2
1
0
85° C
25° C
-40° C
K - factor
IRL, ORL, Gain, Rev Isol (dB)
30
-70
1500
Figure 12. OP1dB vs Frequency and Temperature
50
-50
20.0
1300
2700
Figure 11. OIP3 vs Frequency and Temperature
-30
22.0
85° C
25° C
-40° C
30.0
25.0
1300
24.0
0
2
4
6
8
10 12
Frequency (GHz)
Figure 14. K-factor vs Frequency and Temperature
14
16
18
20
MGA-13216 Typical Performance in Demoboard for 1.95 GHz
TA = 25° C, Vdd1 = 5.0 V, Vdd2 = 5.0 V, Idd1 = 53 mA, Idd2 = 122 mA
-10
0
-20
-25
85° C
25° C
-40° C
-30
-35
1.6
1.8
2
Frequency (GHz)
2.2
-20
2.4
70.0
160.0
60.0
140.0
40.0
30.0
20.0
22
24
0
1
2
3
Vdd1 (V)
4
5
6
85° C
25° C
-40° C
45.0
40.0
35.0
30.0
5
10
15
Pout (dBm)
80.0
60.0
85° C
25° C
-40° C
0.0
0
1
2
3
Vdd2 (V)
Figure 18. Idd2 vs Vdd2 and Temperature
50.0
0
100.0
20.0
Figure 17. Idd1 vs Vdd1 and Temperature
25.0
2
Frequency (GHz)
40.0
85° C
25° C
-40° C
10.0
0.0
18
120.0
Idd2 (mA)
Idd1 (mA)
16
Figure 16. ORL vs Frequency and Temperature
50.0
OIP3 (dBm)
-10
-15
Figure 15. IRL vs Frequency and Temperature
20
Figure 19. OIP3 vs Output Power and Temperature at 1.95 GHz
6
85° C
25° C
- 40° C
-5
ORL (dB)
IRL (dB)
-15
25
4
5
6
MGA-13216 Q1 Typical Scattering Parameters, Vdd1 = 5 V, Idd1 = 53 mA
Freq
GHz
S11
S21
Mag.
Ang.
Mag.
Ang.
Mag.
Ang.
Mag.
Ang.
0.1
0.90
-16.98
37.00
157.64
0.00
48.80
0.54
-16.53
0.5
0.58
-57.10
20.73
112.16
0.01
60.00
0.34
-25.47
0.9
0.41
-78.09
13.42
89.11
0.02
63.96
0.31
-32.94
1.0
0.39
-82.31
12.28
84.68
0.02
64.17
0.30
-35.72
1.5
0.33
-100.68
8.73
65.57
0.03
63.16
0.27
-49.87
1.9
0.32
-111.98
7.10
52.31
0.03
61.03
0.24
-65.97
2.0
0.32
-114.21
6.78
49.09
0.03
60.41
0.23
-70.70
2.5
0.32
-123.78
5.58
33.68
0.04
56.77
0.22
-97.67
3.0
0.32
-131.52
4.74
18.62
0.05
52.16
0.24
-124.98
4.0
0.34
-147.74
3.62
-10.88
0.07
42.70
0.33
-170.16
5.0
0.43
-160.90
2.85
-40.35
0.09
31.33
0.43
152.86
6.0
0.46
-173.17
2.32
-73.07
0.11
15.51
0.57
108.56
7.0
0.42
164.51
1.65
-104.52
0.11
-1.13
0.75
79.33
8.0
0.49
144.57
1.15
-128.97
0.12
-12.89
0.85
66.43
9.0
0.58
135.92
0.87
-153.00
0.13
-25.90
0.88
50.13
10.0
0.59
123.84
0.68
179.70
0.14
-43.85
0.88
25.49
11.0
0.56
104.66
0.49
153.85
0.14
-61.82
0.94
3.72
12.0
0.62
95.03
0.35
133.97
0.14
-74.64
0.96
-8.28
13.0
0.61
83.60
0.24
114.00
0.13
-88.86
0.96
-9.97
14.0
0.57
77.47
0.16
101.52
0.12
-96.62
0.95
-11.26
15.0
0.69
63.81
0.13
83.57
0.13
-112.30
0.95
-22.26
16.0
0.78
48.65
0.09
58.50
0.13
-140.70
0.92
-43.28
17.0
0.77
31.46
0.07
45.20
0.11
-172.63
0.90
-59.64
18.0
0.74
-5.87
0.09
33.11
0.06
123.08
0.87
-70.19
19.0
0.35
-60.87
0.16
-30.74
0.15
-74.65
0.81
-81.91
20.0
0.40
60.14
0.15
-133.62
0.27
-168.80
0.59
-91.00
RF input
Reference Plane
15
14
13
1
12
2
11
3
bias
LNA1
LNA2
4
Figure 20.
7
10
9
5
6
7
S22
MGA-13216 Q1 Typical Noise Parameters, Vdd1 = 5 V,
Idd1 = 53 mA
RF output
Reference Plane
16
S12
8
Freq
GHz
Fmin
dB
*opt
Mag.
*opt
Ang.
Rn/50
1.50
0.51
0.214
58.2
0.0398
1.70
0.52
0.228
93.1
0.0472
1.95
0.61
0.244
112.0
0.0356
2.00
0.59
0.268
119.1
0.0430
2.20
0.58
0.242
141.0
0.0320
2.50
0.62
0.211
159.6
0.0376
2.70
0.66
0.259
-179.0
0.034
2.90
0.75
0.238
178.8
0.0438
Notes: Measurements are made on 10 mils Rogers R04350 TRL Board.
Figure 20 shows the input and output reference plane for Q1.
MGA-13216 Q2 Typical Scattering Parameters, Vdd2 = 5 V, Idd2 = 122 mA
Freq
GHz
S11
S21
Mag.
Ang.
Mag.
Ang.
Mag.
Ang.
Mag.
Ang.
0.1
0.87
171.29
0.14
-111.79
0.00
88.11
0.82
173.63
0.5
0.85
138.30
1.52
-81.16
0.01
96.29
0.77
145.63
0.9
0.69
96.98
5.52
-124.77
0.03
86.36
0.56
112.53
1.0
0.59
84.76
6.84
-140.78
0.03
78.00
0.46
104.58
1.5
0.18
130.00
9.14
138.88
0.05
25.63
0.23
144.28
1.9
0.30
121.10
8.18
98.15
0.05
-1.96
0.28
138.20
2.0
0.30
114.38
8.01
89.78
0.05
-7.84
0.28
135.20
2.5
0.21
68.24
7.54
51.45
0.04
-38.95
0.19
126.38
3.0
0.15
-47.90
7.51
11.84
0.03
-81.84
0.11
159.70
4.0
0.66
169.12
5.52
-78.67
0.02
135.07
0.26
144.46
5.0
0.96
114.66
2.62
-162.85
0.03
69.66
0.16
-134.63
6.0
0.90
85.78
0.78
134.59
0.04
39.96
0.44
-174.12
7.0
0.90
66.82
0.29
99.54
0.04
20.92
0.45
142.19
8.0
0.97
49.53
0.15
61.95
0.04
2.45
0.58
118.39
9.0
0.94
31.72
0.07
18.92
0.03
-23.65
0.69
89.18
10.0
0.96
16.48
0.02
-2.22
0.00
-27.52
0.68
32.18
11.0
0.96
7.02
0.03
70.89
0.02
72.90
0.85
-28.05
12.0
0.97
-0.97
0.04
37.99
0.04
32.78
0.66
-92.36
13.0
0.91
-10.74
0.03
8.76
0.04
0.04
0.57
-160.08
14.0
0.95
-16.10
0.01
-6.28
0.01
-30.22
0.55
139.91
15.0
0.98
-24.91
0.02
119.58
0.02
136.32
0.59
97.39
16.0
0.94
-41.02
0.05
107.64
0.05
111.77
0.65
67.01
17.0
0.96
-54.68
0.09
88.59
0.09
90.04
0.66
37.97
18.0
0.95
-63.44
0.15
61.31
0.15
61.66
0.70
5.63
19.0
0.88
-61.13
0.19
1.11
0.19
1.14
0.52
-29.99
20.0
0.92
-57.92
0.11
55.82
0.11
55.64
0.47
-2.21
15
14
13
1
2
3
12
11
bias
LNA1
LNA2
4
Figure 21.
8
10
9
5
6
7
S22
MGA-13216 Q2 Typical Noise Parameters, Vdd2 = 5 V,
Idd2 = 122 mA
RF input
Reference Plane
16
S12
8
RF output
Reference Plane
Freq
GHz
Fmin
dB
Γopt
Mag.
Γopt
Ang.
Rn/50
1.50
2.21
0.314
-77.0
0.3470
1.70
2.23
0.183
-62.8
0.3638
1.95
2.15
0.188
-81.0
0.2762
2.00
2.20
0.187
-81.5
0.2844
2.20
2.06
0.165
-87.0
0.2558
2.50
2.20
0.140
-99.5
0.2542
2.70
2.29
0.132
-116.7
0.2426
2.90
2.20
0.176
-149.2
0.1972
Notes: Measurements are made on 10 mils Rogers R04350 TRL Board.
Figure 21 shows the input and output reference plane for Q2.
Package Dimensions
Pin 1 Dot
By marking
PIN #1 IDENTIFICATION
CHAMFER 0.30 x 45°
0.40 ±0.10
0.30 ±0.10
AVAGO
13216
YYWW
XXXX
4.00 ±0.10
2.70 ±0.10
Exp.DAP
0.203 Ref.
4.00 ±0.10
2.70 ±0.10
Exp.DAP
0.65 Bsc
1.95
Ref.
0.00 0.10
0.85 ±0.10
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PCB Land Patterns and Stencil Design
4.00
2.70
3.96
2.16
0.65
2.16
3.96
2.70
4.00
0.65
0.40
0.36
0.30
0.27
LAND PATTERN
STENCIL OPENING
2.70
2.16
2.16
2.70
3.96
4.00
0.65
0.36
0.40
0.27
0.30
COMBINATION OF LAND PATTERN & STENCIL OPENING
Notes:
1. All dimensions are in milimeters.
2. 4 mil stencil thickness recommended.
9
Device Orientation
REEL
USER FEED DIRECTION
AVAGO
13216
YYWW
XXXX
CARRIER
TAPE
USER
FEED
DIRECTION
AVAGO
13216
YYWW
XXXX
AVAGO
13216
YYWW
XXXX
TOP VIEW
END VIEW
COVER TAPE
Tape Dimensions
2.00 ±0.05
8.00 ±0.10
Ø 1.50 ±0.10
1.75 ±0.10
4.00 ±0.10
5.50 ±0.05
12.0 ±0.30
–0.10
Ø1.50 ±0.25
0.279 ±0.02
10° MAX
10° MAX
4.25 ±0.10
1.13 ±0.10
4.25 ±0.10
A.
K.
B.
Part Number Ordering Information
Part Number
No. of Devices
Container
MGA-13216-TR1G
1000
7” Reel
MGA-13216-BLKG
100
antistatic bag
10
Reel Dimensions (7 inch reel)
6.25mm EMBOSSED LETTERS
LETTERING THICKNESS: 1.6mm
SLOT HOLE "a"
SEE DETAIL "X"
Ø178.0±0.5
SLOT HOLE "b"
FRONT
BACK
6
PS
SLOT HOLE(2x)
180° APART.
6
PS
RECYCLE LOGO
SLOT HOLE "a": 3.0±0.5mm(1x)
SLOT HOLE "b": 2.5±0.5mm(1x)
FRONT VIEW
12.4
45°
1.5 MIN.
+1.5*
-0.0
+0.5
Ø13.0 -0.2
Ø20.2 MIN.
°
R10.65
120
65°
R5.2
45°
EMBOSSED RIBS
RAISED: 0.25mm, WIDTH: 1.25mm
Ø178.0±0.5
Ø51.2±0.3
BACK VIEW
For product information and a complete list of distributors, please go to our web site:
18.0*
MAX.
SEE DETAIL "Y"
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-2878EN - December 19, 2011
DETAIL "X"
3.5
DETAIL "Y"
(Slot Hole)
1.0
Ø55.0±0.5
BACK
Ø178.0±0.5
FRONT