NSC AD7531JN 10-bit, 12-bit binary multiplying d/a converter Datasheet

DAC1020/DAC1021/DAC1022
10-Bit Binary Multiplying D/A Converter
DAC1220/DAC1222
12-Bit Binary Multiplying D/A Converter
General Description
The DAC1020 and the DAC1220 are, respectively, 10 and
12-bit binary multiplying digital-to-analog converters. A deposited thin film R-2R resistor ladder divides the reference
current and provides the circuit with excellent temperature
tracking characteristics (0.0002%/§ C linearity error temperature coefficient maximum). The circuit uses CMOS current
switches and drive circuitry to achieve low power consumption (30 mW max) and low output leakages (200 nA max).
The digital inputs are compatible with DTL/TTL logic levels
as well as full CMOS logic level swings. This part, combined
with an external amplifier and voltage reference, can be
used as a standard D/A converter; however, it is also very
attractive for multiplying applications (such as digitally controlled gain blocks) since its linearity error is essentially independent of the voltage reference. All inputs are protected
from damage due to static discharge by diode clamps to V a
and ground.
This part is available with 10-bit (0.05%), 9-bit (0.10%), and
8-bit (0.20%) non-linearity guaranteed over temperature
Equivalent Circuit
(note 1 of electrical characteristics). The DAC1020,
DAC1021 and DAC1022 are direct replacements for the 10bit resolution AD7520 and AD7530 and equivalent to the
AD7533 family. The DAC1220 and DAC1222 are direct replacements for the 12-bit resolution AD7521 and AD7531
family.
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Linearity specified with zero and full-scale adjust only
Non-linearity guaranteed over temperature
Integrated thin film on CMOS structure
10-bit or 12-bit resolution
Low power dissipation 10 mW @ 15V typ
Accepts variable or fixed reference b25VsVREFs25V
4-quadrant multiplying capability
Interfaces directly with DTL, TTL and CMOS
Fast settling timeÐ500 ns typ
Low feedthrough errorÐ(/2 LSB @ 100 kHz typ
Note. Switches shown in digital high state
TL/H/5689 – 1
Ordering Information
10-BIT D/A CONVERTERS
0§ C to 70§ C
Temperature Range
NonLinearity
b 40§ C to 85§ C
0.05%
DAC1020LCN
AD7520LN,AD7530LN
0.10%
DAC1021LCN
AD7520KN,AD7530KN
0.20%
DAC1022LCN
Package Outline
DAC1020LCV
DAC1020LIV
AD7520JN,AD7530JN
N16A
V20A
12-BIT D/A CONVERTERS
0§ C to 70§ C
Temperature Range
NonLinearity
b 40§ C to a 85§ C
0.05%
DAC1220LCN
AD7521LN,AD7531LN
DAC1220LCJ
0.20%
DAC1222LCN
AD7521JN,AD7531JN
DAC1222LCJ
Package Outline
N18A
AD7521LD,AD7531LD
AD7521JD,AD7531JD
J18A
Note. Devices may be ordered by either part number.
C1996 National Semiconductor Corporation
TL/H/5689
RRD-B30M96/Printed in U. S. A.
http://www.national.com
DAC1020/DAC1021/DAC1022 10-Bit Binary Multiplying D/A Converter
DAC1220/DAC1222 12-Bit Binary Multiplying D/A Converter
May 1996
Absolute Maximum Ratings (Note 5)
Operating Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
V a to Gnd
Temperature (TA)
DAC1020LIV, DAC1220LCJ,
DAC1222LCJ
DAC1020LCN, DAC1020LCV,
DAC1021LCN
DAC1022LCN, DAC1220LCN
DAC1222LCN
17V
g 25V
VREF to Gnd
Digital Input Voltage Range
V a to Gnd
b 100 mV to V a
DC Voltage at Pin 1 or Pin 2 (Note 3)
b 65§ C to a 150§ C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (plastic)
260§ C
Dual-In-Line Package (ceramic)
300§ C
ESD Susceptibility (Note 4)
Min
Max
Units
b 40
a 85
§C
0
0
0
a 70
a 70
a 70
§C
§C
§C
800V
Electrical Characteristics (V a e 15V, VREF e 10.000V, TA e 25§ C unless otherwise specified)
Parameter
Conditions
Resolution
Linearity Error
10-Bit Parts
9-Bit Parts
8-Bit Parts
Full-Scale Error
b 10V s VREF s a 10V,
(Notes 1 and 2)
Full-Scale Error Tempco
TMINkTAkTMAX,
(Note 2)
Output Leakage Current
IOUT 1
IOUT 2
TMINsTAsTMAX
All Digital Inputs Low
All Digital Inputs High
Power Supply Sensitivity
All Digital Inputs High,
14VsV a s16V, (Note 2),
(Figure 2)
IOUT 2
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Min
Typ
Max
10
15
Bits
0.05
0.10
0.20
% FSR
% FSR
% FSR
0.0002
0.0002
% FS/§ C
1.0
% FS
0.001
0.001
% FS/§ C
200
200
200
200
nA
nA
1.0
0.3
0.005
20
500
All Digital Inputs Low,
VREF e 20 Vp-p @ 100 kHz
J Package (Note 4)
N Package
10
15
All Digital Inputs Low
All Digital Inputs High
All Digital Inputs Low
All Digital Inputs High
40
200
200
40
2
% FS/V
20
500
10
6
2
Units
Max
0.05
0.10
0.20
0.005
RL e 100X from 0 to 99. 95%
FS
All Digital Inputs Switched
Simultaneously
Typ
12
0.3
VREF Input Resistance
Output Capacitance
IOUT 1
Min
10
b 10V s VREF s a 10V,
(Notes 1 and 2)
VREF Feedthrough
DAC1220, DAC1222
TMINkTAkTMAX,
b 10V k VREF k a 10V,
(Note 1) End Point Adjustment Only
(See Linearity Error in Definition of Terms)
DAC1020, DAC1220
DAC1021
DAC1022, DAC1222
Linearity Error Tempco
Full-Scale Current Settling
Time
DAC1020, DAC1021,
DAC1022
9
5
6
2
40
200
200
40
kX
ns
10
mVp-p
9
5
mVp-p
mVp-p
pF
pF
pF
pF
Electrical Characteristics
Parameter
(V a e 15V, VREF e 10.000V, TA e 25§ C unless otherwise specified) (Continued)
DAC1020, DAC1021,
DAC1022
Conditions
Min
Digital Input
Low Threshold
High Threshold
(Figure 1)
TMINkTAkTMAX
TMINkTAkTMAX
Digital Input Current
TMINsTAsTMAX
Digital Input High
Digital Input Low
Supply Current
All Digital Inputs High
All Digital Inputs Low
Operating Power Supply
Range
(Figures 1 and 2)
Typ
Max
DAC1220, DAC1222
Min
Typ
0.8
2.4
0.8
V
V
2.4
5
Units
Max
1
100
1
100
b 50
b 200
b 50
b 200
mA
mA
0.2
0.6
1.6
2
0.2
0.6
1.6
2
mA
mA
15
V
15
5
Note 1: VREF e g 10V and VREF e g 1V. A linearity error temperature coefficient of 0.0002% FS for a 45§ C rise only guarantees 0.009% maximum change in
linearity error. For instance, if the linearity error at 25§ C is 0.045% FS it could increase to 0.054% at 70§ C and the DAC will be no longer a 10-bit part. Note,
however, that the linearity error is specified over the device full temperature range which is a more stringent specification since it includes the linearity error
temperature coefficient.
Note 2: Using internal feedback resistor as shown in Figure 3 .
Note 3: Both IOUT 1 and IOUT 2 must go to ground or the virtual ground of an operational amplifier. If VREF e 10V, every millivolt offset between IOUT 1 or IOUT 2,
0.005% linearity error will be introduced.
Note 4: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 5: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 6: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, iJA, and the ambient temepature, TA. The maximum
allowable power dissipation at any temperature is PD e (TJMAX b TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX e 125§ C, and the typical junction-to-ambient thermal resistance of the J18 package when board mounted is 85§ C/W. For the N18 package, iJA is
120§ C/W, for the N16 this number is 125§ C/W, and for the V20 this number is 95§ C/W.
Typical Performance Characteristics
TL/H/5689 – 2
FIGURE 2. Gain Error Variation vs V a
FIGURE 1. Digital Input Threshold vs
Ambient Temperature
3
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Typical Applications
Operational Amplifier VOS Adjust (Figure 3 )
The following applications are also valid for 12-bit systems
using the DAC1220 and 2 additional digital inputs.
Connect all digital inputs, A1 – A10, to ground and adjust the
potentiometer to bring the op amp VOUT pin to within g 1
mV from ground potential. If VREF is less than 10V, a finer
VOS adjustment is required. It is helpful to increase the resolution of the VOS adjust procedure by connecting a 1 kX
resistor between the inverting input of the op amp to
ground. After VOS has been adjusted, remove the 1 kX.
Operational Amplifier Bias Current (Figure 3 )
The op amp bias current, Ib, flows through the 15k internal
feedback resistor. BI-FET op amps have low Ib and, therefore, the 15k c Ib error they introduce is negligible; they are
strongly recommended for the DAC1020 applications.
VOS Considerations
The output impedance, ROUT, of the DAC is modulated by
the digital input code which causes a modulation of the operational amplifier output offset. It is therefore recommended to adjust the op amp VOS. ROUT is E 15k if more than 4
digital inputs are high; ROUT is E 45k if a single digital input
is high, and ROUT approaches infinity if all inputs are low.
Full-Scale Adjust (Figure 4 )
Switch high all the digital inputs, A1 – A10, and measure the
op amp output voltage. Use a 500X potentiometer, as
shown, to bring ll VOUT ll to a voltage equal to VREF c
1023/1024.
SELECTING AND COMPENSATING THE OPERATIONAL AMPLIFIER
Op Amp Family
CF
Ri
P
VW
Circuit Settling
Time, ts
Circuit Small
Signal BW
LF357
LF356
LF351
LM741
10 pF
22 pF
24 pF
0
2.4k
%
%
%
25k
25k
10k
10k
Va
Va
Vb
Vb
1.5 ms
3 ms
4 ms
40 ms
1M
0.5M
0.5M
200 kHz
VOUT e b VREF
#
TL/H/5689 – 3
A1
A2
A3
A10
a
a
a###
2
4
8
1024
b 10V s VREF s 10V
0 s VOUT s b
J
1023
VREF
1024
where AN e 1 if the AN digital input is high
AN e 0 if the AN digital input is low
FIGURE 3. Basic Connection: Unipolar or 2-Quadrant Multiplying
Configuration (Digital Attenuator)
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4
Typical Applications (Continued)
FIGURE 4. Full-Scale Adjust
FIGURE 5. Alternate Full-Scale Adjust: (Allows Increasing or Decreasing the Gain)
VOUT 1 e b VREF
VOUT2 e VREF
#2
#2
A1
A1
a
a
A2
A3
A10
a
a###
4
8
1024
A2
A3
A10
a
a###
4
8
1024
where VREF can be an AC signal
J
TL/H/5689 – 4
J #2
c
B1
a
B2
B3
B10
a
a###
4
8
1024
J
FIGURE 6. Precision Analog-to-Digital Multiplier
5
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Typical Applications (Continued)
COMPLEMENTARY OFFSET BINARY
(BIPOLAR) OPERATION
DIGITAL INPUT
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
VOUT
0
0
1
0
0
1
a VREF
0
1 VREF c 1022/1024
1
VREF c 2/1024
0
0
1 bVREF c 2/1024
1 bVREF (1022/1024)
Note that:
TL/H/5689–5
VOUT e b VREF
#
A1
A2
A10
1
a
a###a
b
2
4
1024 1024
where: AN e a 1 if AN input is high
#
J
VREF
1023
c
RLADDER
1024
# By doubling the output range we get half the
resolution
# IOUT 1 a IOUT 2 e
J
# The 10M resistor, adds a 1 LSB ‘‘thump’’, to
allow full offset binary operation where the output reaches zero for the half-scale code. If
symmetrical output excursions are required,
omit the 10M resistor.
AN e b 1 if AN input is low
FIGURE 7. Bipolar 4-Quadrant Multiplying Configuration
Operational Amplifiers VOS Adjust (Figure 7 )
Gain Adjust (Full-Scale Adjust)
a)
Assuming that the external 10k resistors are matched to
better than 0.1%, the gain adjust of the circuit is the same
with the one previously discussed.
b)
Switch all the digital inputs high; adjust the VOS potentiometer of op amp B to bring its output to a value equal
tob(VREF/1024) (V).
Switch the MSB high and the remaining digital inputs
low. Adjust the VOS potentiometer of op amp A, to bring
its output value to within a 1 mV from ground potential.
For VREF k 10V, a finer adjust is necessary, as already
mentioned in the previous application.
TL/H/5689 – 6
TRUE OFFSET BINARY OPERATION
DIGITAL INPUT
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
# R4 e (2AVb b 1) R,
VOUT
1
0
0
1
0
0
1
0
0
VREF c 1022/1024
0
b VREF
#
AV b
R2
e
,
R1
AV b b 1
VOUT(PEAK)
R3 a R1 ll R2 e R; AVb e
, R e 20k
VREF
Example: VREF e 2V, VOUT (swing) j g 10V: AVb e 5V
Then R4 e 9R, R1 e 0.8 R2. If R1 e 0.2R then R2 e 0.25R,
R3 e 0.64R
ts e 1.8 ms
FIGURE 9. Bipolar Configuration with
Increased Output Swing
use LM336 for a voltage reference
FIGURE 8. Bipolar Configuration with a Single Op Amp
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6
Typical Applications
(Continued)
VOUT e
#
b VREF
A1
A2
A3
A10
a
a
a...
2
4
8
1024
J
where: VREF can be an AC signal
# By connecting the DAC in the feedback loop of an operational amplifier a linear digitally control gain block can be
realized
# Note that with all digital inputs low, the gain of the amplifier
is infinity, that is, the op amp will saturate. In other words, we
cannot divide the VREF by zero!
FIGURE 10. Analog-to-Digital Divider (or Digitally Gain Controlled Amplifier)
TL/H/5689 – 7
VOUT e VREF
%
A1
A2
A10
a
a...a
2
4
1024
A1
A2
A10
a
a...a
2
4
1024
or VOUT e VREF
–
#
1023 b N
N
J
where: 0 s N s 1023
N e 0 for AN e all zeros
N e 1 for A10 e 1, A1–A9 e 0
.
.
.
N e 1023 for AN e all 1’s
FIGURE 11. Digitally controlled Amplifier-Attenuator
7
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Typical Applications (Continued)
TL/H/5689 – 8
f
# Output frequency e CLK; fMAX j 2 kHz
512
# Output voltage range e 0V b 10V peak
# THD k 0.2%
# Excellent amplitude and frequency stability with temperature
# Low pass filter shown has a 1 kHz corner (for output frequencies below 10 Hz,
filter corner should be reduced)
# Any periodic function can be implemented by modifying the contents of the look
up table ROM
# No start up problems
FIGURE 12. Precision Low Frequency Sine Wave Oscillator Using Sine Look-Up ROM
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8
Typical Applications (Continued)
MM74C00 Ð NAND gates
MM74C32 Ð OR gates
MM74C74 Ð D flip-flop
MM74C193 Ð Binary up/
down counters
TL/H/5689 – 9
# Binary up/down counter digitally ‘‘ramps’’ the DAC
output
# Can stop counting at any desired 10-bit input code
# Senses up or down count overflow and automatically
reverses direction of count
FIGURE 13. A Useful Digital Input Code Generator for DAC Attenuator or Amplifier Circuits
9
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Definition of Terms
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the D/A
full-scale output.
Resolution: Resolution is defined as the reciprocal of the
number of discrete steps in the D/A output. It is directly
related to the number of switches or bits within the D/A. For
example, the DAC1020 has 210 or 1024 steps while the
DAC1220 has 212 or 4096 steps. Therefore, the DAC1020
has 10-bit resolution, while the DAC1220 has 12-bit resolution.
Linearity Error: Linearity error is the maximum deviation
from a straight line passing through the endpoints of the
D/A transfer characteristic. It is measured after calibrating
for zero (see VOS adjust in typical applications) and fullscale. Linearity error is a design parameter intrinsic to the
device and cannot be externally adjusted.
Settling Time: Full-scale settling time requires a zero to fullscale or full-scale to zero output change. Settling time is the
time required from a code transition until the D/A output
reaches within g (/2 LSB of final output value.
Full-Scale Error: Full-scale error is a measure of the output
error between an ideal D/A and the actual device output.
Ideally, for the DAC1020 full-scale is VREFb1 LSB. For
VREF e 10V
and
unipolar
operation,
VFULL-SCALE e 10.0000VÐ9.8 mV e 9.9902V. Full-scale error is adjustable to zero as shown in Figure 5 .
TL/H/5689 – 10
a
(a) End point test after zero and full-scale adjust.
The DAC has 1 LSB linearity error.
b1
b2
(b) By shifting the full-scale calibration on of the DAC of
Figure (b1) we could pass the ‘‘best straight line’’ (b2)
test and meet the g (/2 linearity error specification.
Note. (a), (b1) and (b2) above illustrate the difference between ‘‘end point’’ National’s linearity test (a) and ‘‘best straight line’’ test. Note that both devices in (a) and
(b2) meet the g (/2 LSB linearity error specification but the end point test is a more ‘‘real life’’ way of characterizing the DAC.
Connection Diagrams
DAC102X
Dual-In-Line Package
DAC1020
PLCC Package
DAC122X
Dual-In-Line Package
TL/H/5689 – 12
TL/H/5689–13
TL/H/5689 – 11
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10
11
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Physical Dimensions inches (millimeters) unless otherwise noted
Cavity Dual-In-Line Package (J)
Order Number DAC1220LCJ or DAC1222LCJ
NS Package Number J18A
Molded Dual-In-Line Package (N)
Order Number DAC1020LCN, DAC1021LCN or DAC1022LCN
NS Package Number N16A
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12
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number DAC1220LCN, DAC1221LCN or DAC1222LCN
NS Package Number N18A
13
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DAC1020/DAC1021/DAC1022 10-Bit Binary Multiplying D/A Converter
DAC1220/DAC1222 12-Bit Binary Multiplying D/A Converter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Plastic Leaded Chip Carrier (V)
Order Number DAC1020LCV or DAC1020LIV
NS Package Number V20A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
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2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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