ICST ICS556G-03IT Quad lvds oscillator/buffer Datasheet

ICS556-03
QUAD LVDS OSCILLATOR/BUFFER
Description
Features
The ICS556-03 is a clock oscillator with quad LVDS
outputs. Using a standard 25 MHz crystal, no additional
external components are required to generate quad
LVDS outputs at 25 MHz.
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•
•
•
•
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This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
Packaged in 16-pin TSSOP
Requires no external components
Low Phase Jitter: <1ps from 10 kHz to 10 MHz
Quad, Differential LVDS outputs
Operating voltage of 2.5 Volt
Advanced, low-power, sub-micron CMOS process
Block Diagram
VDD
EN1
EN2
EN3
EN4
CLKA
CLKA
CLKB
25MHz
CLKB
Crystal
Oscillator
CLKC
LVDS
CLKC
CLKD
CLKD
GND
1
MDS 556-03 B
I n t e gra te d C i r c u i t S y s t e m s
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Revision 030204
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ICS556-03
Quad LVDS Oscillator/Buffer
Pin Assignment
EN1
1
16
EN4
VDD
2
15
EN3
A
3
14
D
A
4
13
D
B
5
12
C
B
6
11
EN2
7
10
C
GND
8
9
X2
X1
16-Pin (150 mil) SOIC
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
EN1
Input
Enable pin for Outputs A and A. EN1 high enables A, A outputs.
EN1 low tri states A, A outputs. No Pull-Up resistor.
2
VDD
Power
Power supply. Connect to 2.5 V.
3
A
Output
Differential clock output.
4
A
Output
Inverting differential clock output.
5
B
Output
Inverting differential clock output.
6
B
Output
Differential clock output.
7
EN2
Input
Enable pin for Outputs B and B. EN2 high enables B, B outputs.
EN2 low tri states B, B outputs. No Pull-Up resistor.
8
X2
Input
Crystal connection.
9
X1
Input
Crystal input.
10
GND
Power
Connect to ground.
11
C
Output
Differential clock output.
12
C
Output
Inverting differential clock output.
13
D
Output
Inverting differential clock output.
2
MDS 556-03 B
In te grated Circuit Systems
Pin Description
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ICS556-03
Quad LVDS Oscillator/Buffer
Pin
Number
Pin
Name
Pin
Type
Pin Description
14
D
Output
15
EN3
Input
Enable pin for Outputs C and C. EN4 high enables C, C outputs.
EN3 low tri states C, C outputs.No Pull-Up resistor.
16
EN4
Input
Enable pin for Outputs D and D. EN4 high enables D, D outputs.
EN4 low tri states D, D outputs.No Pull-Up resistor.
Differential clock output.
Quartz Crystal
External Component Selection
The ICS556-03 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
A decoupling capacitor of 0.01µF should be connected
between VDD and GND on pins 2 and 10 as close to
the ICS556-03 possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
LVDS Driver Termination
A general LVDS interface is shown in Figure 2. In a 100
ohm differential transmission line environment, LVDS
drivers require a matched load termination of 100
across near the receiver input. For a multiple LVDS
outputs buffer, if only partial outputs are used, it is
recommended to terminate the un-used outputs.
2.5V
The ICS556-03, a quad 25 MHz LVDS Clock utilizes an
external crystal to generate 4 pairs of low phase noise
outputs. The crystal should be a fundamental mode,
parallel resonant. Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these
capacitors is given by the following equation
Crystal Caps (pf)= (CL-12)x2
In the equation, CL is the crystal Load capacitance. So
for the crystal with 16pF load capacitance, two 8
pF[(16-12)x2] capacitors should be used.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS556-03. There should be no via’s
between the crystal pins and the X1 and X2 device
pins. There should be no signal traces underneath or
close to the crystal.
2.5V
LVDS_Driver
R1
100 ohm
+
-
100 Ohm Differential Transmission Line
Figure 2. Typical LVDS Driver
Termination
3
MDS 556-03 B
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 030204
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ICS556-03
Quad LVDS Oscillator/Buffer
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS556-03. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +70°C
Storage Temperature
-65 to +150°C
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Typ.
Max.
Units
0
+70
°C
+2.375
+2.625
V
Reference crystal parameters
4
MDS 556-03 B
In te grated Circuit Systems
Refer to page 3
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ICS556-03
Quad LVDS Oscillator/Buffer
DC Electrical Characteristics
VDD=2.5 V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Symbol
Conditions
Operating Voltage
VDD
Output High Voltage
VOH
Note 1
Output Low Voltage
VOL
Note 1
Input High Voltage (EN1,
EN2,EN3 & EN4)
VIH
Input High Voltage (EN1,
EN2,EN3 & EN4)
VIL
Operating Supply Current
IDD
Short Circuit Current
Min.
Typ.
2.375
Max.
Units
2.625
V
1.375
V
1.125
2.0
V
V
0.5
V
OE1:4:1
17
mA
OE1:4:0
4
mA
±50
mA
IOS
Note 1: Outputs terminated with 50Ω to VDD/2
AC Electrical Characteristics
VDD = 2.5 V ±5%, Ambient Temperature 0 to +70° C, CL=5 pF, unless stated otherwise
Parameter
Conditions
Min.
Typ.
Max. Units
Input Frequency
25
MHz
Output Frequency
25
MHz
Differential Output Voltages (VOD)
∆ VOD
VOD Magnitude Change
Offset Voltage (VOS)
∆ VOS
250
350
450
mV
-40
0
40
mV
1.125
1.25
1.375
V
3
25
mV
VOS Magnitude Change
Differential Output Short Circuit Current (IOSD)
-3.5
mA
Output Short Circuit Current (IOS)
-3.5
mA
Output Rise Time
20% to 80%, no load
0.8
1.2
ns
Output Fall Time
20% to 80%, no load
0.8
1.2
ns
Output Clock Duty Cycle
Measured at 1.25V,
50
55
%
45
Output Short Circuit Current
±50
Channel Output to output Skew
20
Part to Part Skew
Maximum Output Jitter (p-p)
In te grated Circuit Systems
Phase Noise integrated
from 10 kHz to 10 MHz
2
ps
1.5
ns
525 Ra ce Street, San Jose, CA 9512 6
ps
1.0
5
●
100
40
Phase Jitter (RMS)
MDS 556-03 B
mA
ps
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ICS556-03
Quad LVDS Oscillator/Buffer
Parameter Measurement Information
VDD
VDD = 2.5V±5%
Z = 50
Qx
SCOPE
nCLK
50
VOD
CLK
LVDS
Cross Points
VOS
Z = 50
nQx
50
GND
DIFFERENTIAL INPUT LEVEL
2.5V OUTPUT LOAD AC TEST CIRCUIT
nCLK
80%
VOD
80%
CLK
Pulse Width
Clock
Outputs
20%
20%
tOR
tPERIOD
tPW & tPERIOD
nCLK
tOF
OUTPUT RISE/FALL TIME
VOH
CLK
VOL
t( )
tjit(
)=
t(
) - t( )mean
= Phase Jitter
PHASE JITTER
6
MDS 556-03 B
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
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ICS556-03
Quad LVDS Oscillator/Buffer
VDD
VDD
out
out
DC Input
LVDS
100
DC Input
VOD/ VOD
out
VOS/ VOS
out
VOS SETUP
VOD SETUP
7
MDS 556-03 B
In te grated Circuit Systems
50
50
LVDS
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 030204
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ICS556-03
Quad LVDS Oscillator/Buffer
Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
16
Symbol
E1
A
A1
A2
b
C
D
E
E1
e
L
α
E
INDEX
AREA
1 2
D
A
2
Min
Inches
Max
Min
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.1
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
A
A
1
c
-Ce
SEATING
PLANE
b
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping/Packaging
Package
Temperature
ICS556G-03I
ICS556G-03IT
ICS556-03I
ICS556-03I
Tubes
Tape and Reel
16-pin TSSOP
16-pin TSSOP
-40° to +85°C
-40° to +85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
8
MDS 556-03 B
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 030204
●
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
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