Freescale MPC5602BECLU Microcontroller Datasheet

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5606S
Rev. 1, 10/2008
MPC5606S
LQFP–144
MAPBGA–225
QFN12
20 mm x 20 mm ##_mm_x_##mm
15 mm x 15 mm
MPC560xS Microcontroller
Data Sheet
LQFP–176
24 mm x 24 mm
SOT-343R
##_mm_x_##mm
TBD
PKG-TBD
## mm x ## mm
32-bit MCU for cluster applications with stepper motor, TFT
graphic controller and LCD driver
The MPC5606S family of devices is designed to enable the development of automotive instrument cluster applications by
providing a single-chip solution capable of hosting real-time applications and driving a TFT display directly using an on-chip
color TFT display controller.
MPC5606S devices incorporate a cost-efficient host processor core compliant with the Power Architecture™ embedded
category. The processor is 100% user-mode compatible with the original PowerPC user instruction set architecture (UISA) and
capitalizes on the available development infrastructure of current Power ArchitectureTM devices with full support from
available software drivers, operating systems and configuration code to assist with users' implementations.
Offering high performance processing at speeds up to 64 MHz, the MPC5606S family is optimized for low power consumption
and supports a range of on-chip SRAM and internal flash memories. The 1 MB flash version (MPC5606S) features 160 KB of
on-chip graphics SRAM.
Refer to Table 1 for specific memory and feature sets of the product family members.
This document describes the features of the MPC5606S family of microcontrollers and highlights important electrical and
physical characteristics of the devices. For functional characteristics, refer to the MPC5606S Microcontroller Reference
Manual.
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Preliminary—Subject to Change Without Notice
Table of Contents
1
2
3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 MPC5606S Features. . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 MPC5606S Series Blocks . . . . . . . . . . . . . . . . . . . . . . . .6
1.3.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.3.2 Block Summary . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pinout and Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . .9
2.1 144 LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . .10
2.2 176 LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . .11
2.3 208 MAPBGA Package Pinout . . . . . . . . . . . . . . . . . . .11
2.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.4.1 Pad Configuration during Reset Phases . . . . . .13
2.4.2 Voltage Supply Pins. . . . . . . . . . . . . . . . . . . . . .13
2.4.3 Pad Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.4.4 System Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.4.5 Nexus Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.4.6 Functional Ports A, B, C, D, E, F, G, H, I, J, K . .18
2.4.7 Signal Details. . . . . . . . . . . . . . . . . . . . . . . . . . .36
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .39
3.1.1 Recommended Operating Conditions . . . . . . . .41
3.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .44
3.2.1 General Notes for Specifications at Maximum
Junction Temperature . . . . . . . . . . . . . . . . . . . .45
3.3 EMI (Electromagnetic Interference) Characteristics . . .47
3.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.4.1 Voltage Regulator Electrical Characteristics . . .47
3.4.2 Voltage monitor electrical characteristics. . . . . .48
3.4.3 Low voltage domain power consumption. . . . . .49
3.5 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .50
3.6 I/O Pad Electrical Characteristics . . . . . . . . . . . . . . . . .50
3.6.1 I/O Pad Types . . . . . . . . . . . . . . . . . . . . . . . . . .50
4
3.6.2 I/O Input DC Characteristics . . . . . . . . . . . . . . 50
3.6.3 I/O Output DC Characteristics . . . . . . . . . . . . . 51
3.6.4 I/O Pad Current Specification. . . . . . . . . . . . . . 55
3.7 RESET electrical characteristics . . . . . . . . . . . . . . . . . 57
3.8 Main Oscillator Electrical Characteristics . . . . . . . . . . 59
3.9 Low Power Oscillator Electrical Characteristics. . . . . . 61
3.10 FMPLL Electrical Characteristics. . . . . . . . . . . . . . . . . 62
3.11 Main RC Oscillator Electrical Characteristics . . . . . . . 63
3.12 Low Power RC Oscillator Electrical Characteristics . . 64
3.13 Flash Memory Electrical Characteristics . . . . . . . . . . . 64
3.14 Analog to Digital Converter (ADC) Electrical Characteristics
65
3.14.1 Input Impedance and ADC Accuracy . . . . . . . . 66
3.14.2 ADC Electrical Characteristics . . . . . . . . . . . . . 70
3.15 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.15.1 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 72
3.16 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.16.1 IEEE 1149.1 Interface Timing . . . . . . . . . . . . . 74
3.16.2 Nexus Debug Interface. . . . . . . . . . . . . . . . . . . 77
3.16.3 Interface to TFT LCD Panels . . . . . . . . . . . . . . 78
3.16.4 External Interrupt (IRQ) and Non-Maskable
Interrupt (NMI) Timing . . . . . . . . . . . . . . . . . . . 81
3.16.5 Enhanced Modular I/O Subsystem (eMIOS) Timing
82
3.16.6 FlexCAN Timing . . . . . . . . . . . . . . . . . . . . . . . . 82
3.16.7 Deserial Serial Peripheral Interface (DSPI) . . . 83
3.16.8 I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.16.9 Mechanical Outline Drawings. . . . . . . . . . . . . . 89
3.17 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.18 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
1
Overview
The following sections provide high-level descriptions of the features found on the MPC5606S.
1.1
Device Comparison
..
Table 1. MPC5606S Family
Feature
MPC5602S
CPU
MPC5604S
MPC5606S
e200z0h
Execution Speed
Static - 64 MHz
Flash (ECC)
256 KB
EEPROM Emulation Block
(ECC)
RAM (ECC)
Graphics RAM
512 KB
1 MB
4 × 16 KB
24 KB
48 KB
48 KB
No
No
160 KB
MPU
12 entry
eDMA
16 channels
Display Control Unit
No
No
Yes
Parallel Data Interface
No
No
Yes
Stepper Motor Controller
6 motors
Stepper Motor Stall Detect
Sound Generation
LCD Segment Driver
Yes
Yes
Yes
Using eMIOS
64 × 6
64 × 6
40 × 4, 38 × 61
32 kHz External Crystal
Oscillator
Yes
Real Time Counter and
Autonomous Periodic
Interrupt
Yes
Yes
Periodic Interrupt Timer
4 ch, 32-bit
System Watchdog Timer
Yes
System Timer Module
Yes
4 ch, 32-bit
Timed I/O2
8 ch, 16-bit IC/OC
16 ch, 16-bit OPWM/IC/OC
ADC3
16 channels, 10-bit
CAN (64 Mailboxes)
1 × FlexCAN
CAN Sampler
2 × FlexCAN
2 × FlexCAN
Yes
SCI
2 × LINFlex
SPI
QuadSPI Serial Flash
Interface
2 × DSPI
2 × DSPI
34 × DSPI
No
No
Yes
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
Overview
Table 1. MPC5606S Family (continued)
Feature
MPC5602S
MPC5604S
MPC5606S
2
2
4
GPIO
105
105
105 / 132
Debug
Nexus 1
Nexus 1
Nexus 2+5
144 LQFP
144 LQFP
144 LQFP6
176 LQFP
208 MAPBGA7
I2C
Package
1
2
3
4
5
6
7
Configuration is software-programmable
IC-Input Capture, OC-Output Compare, OPWM-Output Pulse Width Modulation
Support for external multiplexer enabling up to 23 channels
QuadSPI serial Flash controller can be optionally used as a third DSPI
Nexus2+ available on 176 LQFP as alternate pin function and on 208 MAPBGA
Not all features are available simultaneously in 144 LQFP package option
The 208-pin package is not a production package; it is available in limited quantities for tool
development only.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MPC5606S Features
Single issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z0h)
— Compatible with classic PowerPC instruction set
— Includes variable length encoding (VLE) instruction set for smaller code size footprint; with the encoding of
mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over
conventional Book E compliant code
On-chip ECC flash memory with flash controller
— Up to 1 MB primary flash—two 512 KB modules with prefetch buffer and 128-bit data access port
— 64 KB data flash—separate 4×16 KB flash block for EEPROM Emulation with prefetch buffer and 128-bit data
access port
Up to 48 KB on-chip ECC SRAM with SRAM controller
Up to 160 KB on-chip non-ECC graphics SRAM with SRAM controller
Memory protection unit (MPU) with up to 12 region descriptors and 32-byte region granularity to provide basic
memory access permission
Interrupt controller (INTC) with up to 127 peripheral interrupt sources and eight software interrupts
Two frequency-modulated phase-locked loops (FMPLLs)
— Primary FMPLL provides a 64 MHz system clock
— Auxiliary FMPLL is available for use as an alternate, modulated or non-modulated clock source to eMIOS
modules and as alternate clock to the DCU for pixel clock generation
Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus
masters (AMBA 2.0 v6 AHB)
16-channel enhanced direct memory access controller (eDMA) with multiple transfer request sources using a DMA
channel multiplexer
Boot assist module (BAM) for embedded boot code supports boot options including download of code via a serial link
(CAN or SPI)
Display control unit to drive TFT LCD displays. It includes processing of up to four planes that can be blended together
and offers a direct un-buffered hardware bit-blitter of up to 16 software-configurable dynamic layers in order to
drastically minimize graphic memory requirements and provide fast animations. Programmable display resolutions are
available up to WVGA.
Parallel Data Interface for digital video input
The LCD segment driver module has two software programmable configurations:
— Up to 40 front plane drivers and 4 backplane drivers
— Up to 38 frontplane drivers and 6 backplane drivers
Stepper Motor Controller module with high-current drivers for up to six instrument cluster gauges driven in full dual
H-Bridge configuration including full diagnostics for short circuit detection
Stepper motor return-to-zero and stall detection module
Sound generation and playback utilizing PWM channels and eDMA; supports monotonic and polyphonic sound
24 eMIOs channels providing up to 16 PWM and 24 input capture / output compare channels
10-bit analog-to-digital converter (ADC) with a maximum conversion time of 1μs
— 16 internal channels
— Extendable to eight multiplexed external channels
Up to three DSPI (Deserial Serial Peripheral Interface) modules for full-duplex, synchronous, communications with
external devices
QuadSPI serial flash memory controller supporting single, dual and quad modes of operation to interface to external
serial flash memory or optionally can be configured to function as another DSPI module (MPC5606S only)
Two Local Interconnect Network (LIN) controller modules capable of autonomous message handling (master),
autonomous header handling (slave mode), and UART support. Compliant with LIN protocol rev 2.1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
Overview
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.3
1.3.1
Two full CAN 2.0B controllers with 64 configurable buffers each; the bit rate can be programmed up to 1 Mb/s
Up to four Inter-integrated circuit (I2C) internal bus controllers with master/slave bus interface
Up to 132 configurable general purpose pins supporting input and output operations
Real Time Counter (RTC). Clock sources are:
— Internal 128 kHz or 16 MHz RC oscillator supporting autonomous wake-up with 1 ms resolution with maximum
timeout of 2 seconds
— External 32 kHz crystal oscillator, supporting wake-up with 1 s resolution and maximum timeout of one hour
— External 4 - 16 MHz oscillator
System Timers:
— 4-channel 32-bit System Timer Module (STM)—included in processor platform
— 4-channel 32-bit Periodic Interrupt Timer (PIT) module
— System watchdog timer
System Integration Unit (SIU) module to manage resets, external interrupts, GPIO and pad control
System Status and Configuration Module (SSCM) to provide information for identification of the device, last boot
mode, or debug status and provides an entry point for the censorship password mechanism
Clock Generation Module (CGM) to generate system clock sources and provide a unified register interface, enabling
access to all clock sources
Clock Monitor Unit (CMU) to monitor the integrity of the main crystal oscillator and the PLL and act as a frequency
meter, measuring the frequency of one clock source and comparing it to a reference clock
Mode Entry Module (MEM) to control the device power mode, i.e., RUN, HALT, STOP, or STANDBY, control mode
transition sequences, and manage the power control, voltage regulator, clock generation and clock management
modules
Reset Generation Module (RGM) to manage reset assertion and release to the device at initial power-up
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard
Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)
On-chip voltage regulator controller for regulating the 3.3 or 5 V supply voltage down to 1.2 V for core logic (requires
external ballast transistor)
The MPC5606S microcontrollers are offered in the following packages:1
— 144 LQFP, 0.5 mm pitch, 20 mm × 20 mm outline
— 176 LQFP, 0.5 mm pitch, 24 mm × 24 mm outline
— 208 MAPBGA, 1.0 mm pitch, 17 mm × 17 mm outline
MPC5606S Series Blocks
Block Diagram
Figure 1 shows a top-level block diagram of the MPC5606S series.
1. See the device comparison table or orderable parts summary for package offerings for each device in the family.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Overview
Nexus Port JTAG Port
NMI
SRAM
XTAL32/
EXTAL32
XOSC
32 kHz
Data
Nexus 2+
Voltage
Regulator
DMA
Interrupt
Controller
(INTC)
External
Interrupts from
Peripheral
Blocks
DCU
2×
FMPLL
speaker/
buzzer
STM
4×PIT
Power
Control
Unit
SSCM
Sound
Generation
RTC/
API
SRAM
Controller
Instructions
e200z0h
4 x 4 32-bit
Crossbar Switch
XOSC
4-16 MHz
SRAM
FLASH
Controller Controller
SWT
Mode
Entry
Module
BAM
MPU (Memory Protection Unit)
Clock Monitor Unit (CMU)
XTAL/
EXTAL
JTAG
NMI
SIU
IRC
128 kHz
Video
SRAM
Test Controller
Nexus
Port
Controller
IRC
16 MHz
FLASH
QuadSPI
Data
and
Clock
RGB TFT
Output
Parallel
Data
Interface
(PDI)
Clock
Generation
Module
Reset
Generation
Module
40 × 4
LCD
LCD FP
and
BP signals
Peripheral Bridge
SIU
External
Interrupts
Six Gauge
Drivers
16 ch.
10-bit
ADC
Reset Control
External
Interrupt
Request
with
Stepper
Stall Detect
(SSD)
2x
eMIOS
16 + 8 ch.
2×
LINFlex
2×
DSPI
4 × I2C
2×
FlexCAN
IMUX
GPIO &
Pad Control
...
I/O
...
...
...
...
...
Figure 1. MPC5606S Series Block Diagram
1.3.2
Block Summary
Table 2 summarizes the functions of all blocks present in the MPC5606S series microcontrollers. Please note that the presence
and number of blocks varies by device and package.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
7
Overview
Table 2. MPC5606S Series Block Summary
Block
Function
16-channel 2nd-generation Direct Memory
Access (eDMA)
Second-generation platform module capable of performing complex
data transfers with minimal intervention from a host processor via “n”
programmable channels
AHB crossbar switch “lite” (XBAR-Lite)
Internal busmaster
Analog-to-digital converter (ADC)
16-channel, 10-bit analog to digital converter
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed
according to the boot mode of the device
Clock generation module (CGM)
Provides logic and control required for the generation of system and
peripheral clocks
Clock monitor unit (CMU)
Monitors clock source (internal and external) integrity
Display control unit (DCU)
Generates all signals required to drive a TFT LCD display, allowing
blending of data of up to 16 layers; can also display digital
video/graphics in the background plane
Deserial serial peripheral interface (DSPI)
Provides a synchronous serial interface for communication with
external devices
QuadSPI (QSPI)
Provides a synchronous serial bus for communication with external
serial flash memory and is optionally configurable as a third DSPI
module
Enhanced modular input output system
(eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and
variables
FlexCAN (controller area network)
Supports the standard CAN communications protocol
FMPLL (frequency-modulated phase-locked
loop)
Two FMPLLs generate high-speed system clocks and support
programmable frequency modulation
Inter-integrated circuit (I2C™) bus
A two wire bidirectional serial bus that provides a simple and efficient
method of data exchange between devices
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode
LCD driver module
Provides 40 × 4 (frontplane drivers × backplane drivers) or 6 × 38
driver configuration for driving LCD segments
LINflex controller
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Memory protection unit (MPU)
Provides hardware access control for all memory references
generated in a device
Error Correction Status Module (ECSM)
Provides miscellaneous control functions including program-visible
information about the platform configuration and revision levels, a
reset status register, wakeup control for exiting sleep modes, and
generic access error information for the processor core
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
8
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Pinout and Signal Descriptions
Table 2. MPC5606S Series Block Summary (continued)
Block
Function
Mode entry module (MEM)
Provides a mechanism for controlling the device operational mode
and mode transition sequences in all functional states; also manages
the power control unit, reset generation module and clock generation
module, and holds the configuration, control and status registers
accessible for applications
Nexus development interface (NDI) level
Provides real-time development support capabilities in compliance
with the IEEE-ISTO 5001-2003 standard
Peripheral interrupt timer (PIT)
Produces periodic interrupts and triggers
Power control unit (PCU)
Reduces the overall power consumption by disconnecting parts of the
device from the power supply via a power switching device; device
components are grouped into sections called “power domains” which
are controlled by the PCU
Static random-access memory (SRAM)
Provides storage for program code, constants, and variables
Reset generation module (RGM)
Centralizes reset sources and manages the device reset sequence of
the device
Real time counter (RTC)
A free running counter used for time keeping applications, the RTC
can be configured to generate an interrupt at a pre-defined interval
independent of the mode of operation (run mode or low-power mode)
Sound generation logic (SGL)
Provides monotonic and polyphonic sound generation capability
Stepper motor controller (SMC)
A PWM motor controller suitable for driving instruments in a cluster
configuration or any other loads requiring a PWM signal
Stepper stall detect (SDD)
The SSD module connects to one stepper (SM) motor with 2 coils and
is used to monitor the movement of the SM to detect that the attached
gauge pointer has reached the stall position of the scale
System integration unit (SIU)
Provides control over all the electrical pad controls and up 32 ports
with 16 bits of bidirectional, general-purpose input and output signals
and supports up to 32 external interrupts with trigger event
configuration
System status configuration module (SSCM) Provides system configuration and status data, e.g., memory size and
status, device mode and security status, DMA status, etc., device
identification data, debug status port enable and selection, and bus
and peripheral abort enable/disable
2
System timer (STM)
Provides a set of output compare events to support AutoSAR and
operating system tasks
System watchdog timer (SWT)
Provides protection from runaway code
Test control unit (TCU)
An extension of the JTAG controller module, the TCU provides the
means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
Pinout and Signal Descriptions
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
9
Pinout and Signal Descriptions
2.1
144 LQFP Package Pinout
Figure 2 shows the pinout for the 144-pin LQFP package.
WARNING
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PA9/DCU_G1/eMIOSB18/SDA_C/FP14
PA8/DCU_G0/eMIOSB23/SCL_C/FP15
PA7/DCU_R7/eMIOSA16/FP16
PA6/DCU_R6/eMIOSA15/FP17
PA5/DCU_R5/eMIOSA17/FP18
PA4/DCU_R4/eMIOSA18/FP19
PA3/DCU_R3/eMIOSA19/sscm7/FP20
PA2/DCU_R2/eMIOSA20/sscm6/FP21
PA1/DCU_R1/eMIOSA21/sscm5/FP22
PA0/DCU_R0/eMIOSA22/SOUND/FP23
VSS12
VDD12
PF15/SCK_C/FP24
PF14/SOUT_C/CNTX_B/sscm4/FP25
PF13/SIN_C/CNRX_B/sscm3/FP26
PF12/eMIOSB16/PCS_C2/sscm2/FP27
PF11/eMIOSB23/PCS_C1/sscm1/FP28
PF10/eMIOSA16/PCS_C0/sscm0/FP29
PG12/eMIOSA23/SOUND/eMIOSA8/FP30
VSSE_A
VDDE_A
PF9/SCL_B/PCS_B0/TXD_B/FP31
PF8/SDA_B/PCS_B1/RXD_B/FP32
PF7/SCL_A/PCS_B2/FP33
PF6/SDA_A/FP34
VSS12
VDD12
PF5/eMIOSA9/DCU_TAG/FP35
PF4/eMIOSA10/PDI7/FP36
PF3/eMIOSA11/PDI6/FP37
PF1/eMIOSA12/PDI5/eMIOSA21/FP38
PF0/eMIOSA13/PDI4/eMIOSA22/FP39
PB2/TXD_A
PB3/RXD_A
VSSE_E
VDDE_E
Any pins labeled “NC” must not be connected to any external circuit.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144-Pin
LQFP
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PB11/CNTX_B/PDI3/eMIOSA16
PB10/CNRX_B/PDI2/eMIOSA23
PB0/CNTX_A/PDI1
PB1/CNRX_A/PDI0
VSS12
VDD12
PE7/M5C1P/SSD5_3/eMIOSA8
PE6/M5C1M/SSD5_2/eMIOSA9
PE5/M5C0P/SSD5_1/eMIOSA10
PE4/M5C0M/SSD5_0/eMIOSA11
VSSMC
VDDMC
PE3/M4C1P/SSD4_3/eMIOSA12
PE2/M4C1M/SSD4_2/eMIOSA13
PE1/M4C0P/SSD4_1/eMIOSA14
PE0/M4C0M/SSD4_0/eMIOSA15
PD15/M3C1P/SSD3_3
PD14/M3C1M/SSD3_2
PD13/M3C0P/SSD3_1
PD12/M3C0M/SSD3_0
VSSMB
VDDMB
PD11/M2C1P/SSD2_3
PD10/M2C1M/SSD2_2
PD9/M2C0P/SSD2_1
PD8/M2C0M/SSD2_0
PD7/M1C1P/SSD1_3/eMIOSB16
PD6/M1C1M/SSD1_2/eMIOSB17
PD5/M1C0P/SSD1_1/eMIOSB18
PD4/M1C0M/SSD1_0/eMIOSB19
VSSMA
VDDMA
PD3/M0C1P/SSD0_3/eMIOSB20
PD2/M0C1M/SSD0_2/eMIOSB21
PD1/M0C0P/SSD0_1/eMIOSB22
PD0/M0C0M/SSD0_0/eMIOSB23
NMI/PF2
VDDE_B
VSSE_B
PCS_A2/eMIOSB19/RXD_B/PB12
PCS_A1/eMIOSB18/TXD_B/PB13
VDD12
VSS12
eMIOSB20/SCK_A/PB9
eMIOSB21/SOUT_A/PB8
eMIOSB22/SIN_A/PB7
CLKOUT/eMIOSB16/PCS_A0/PH4
MA0/SCK_B/PB4
FABM/MA1/SOUT_B/PB5
ABS[0]/MA2/SIN_B/PB6
VDD12
VSS12
VDDA
VSSA
XTAL32/AN15/PC15
EXTAL32/AN14/PC14
PCS_B0/MA2/AN13/PC13
PCS_B1/MA1/AN12/PC12
PCS_B2/MA0/AN11/PC11
SOUND/AN10(mux)/PC10
AN9/PC9
AN8/PC8
VDDE_C
VSSE_C
AN7/PC7
AN6/PC6
AN5/PC5
AN4/PC4
AN3/PC3
AN2/PC2
AN1/PC1
AN0/PC0
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
FP13/eMIOSB20/DCU_G2/PA10
FP12/eMIOSA13/DCU_G3/PA11
FP11/eMIOSA12/DCU_G4/PA12
FP10/eMIOSA11/DCU_G5/PA13
FP9/eMIOSA10/DCU_G6/PA14
FP8/eMIOSA9/DCU_G7/PA15
VDDE_A
VSSE_A
FP7/SOUND/SCL_D/DCU_B0/PG0
FP6/SDA_D/DCU_B1/PG1
FP5/eMIOSB19/DCU_B2/PG2
FP4/eMIOSB21/DCU_B3/PG3
FP3/eMIOSB17/DCU_B4/PG4
FP2/eMIOSA8/DCU_B5/PG5
FP1/DCU_B6/PG6
FP0/DCU_B7/PG7
BP0/DCU_VSYNC/PG8
BP1/DCU_HSYNC/PG9
BP2/DCU_DE/PG10
BP3/DCU_PCLK/PG11
VLCD/PH5
VDDR
VSSR
RESET
VRC_CTRL
VPP
XTAL
VSSOSC
EXTAL
VSSPLL
VDDPLL
NC
TDI/PH1
TDO/PH2
TMS/PH3
TCK/PH0
Figure 2. 144-pin LQFPPinout
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
10
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Pinout and Signal Descriptions
2.2
176 LQFP Package Pinout
Figure 3 shows the pinout for the 176-pin LQFP package.
WARNING
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PA9/DCU_G1/eMIOSB18/SDA_C/FP14
PA8/DCU_G0/eMIOSB23/SCL_C/FP15
PA7/DCU_R7/eMIOSA16/FP16
PA6/DCU_R6/eMIOSA15/FP17
PA5/DCU_R5/eMIOSA17/FP18
VSSE_A
VDDE_A
PA4/DCU_R4/eMIOSA18/FP19
PA3/DCU_R3/eMIOSA19/sscm7/FP20
PA2/DCU_R2/eMIOSA20/sscm6/FP21
PA1/DCU_R1/eMIOSA21/sscm5/FP22
PA0/DCU_R0/eMIOSA22/SOUND/FP23
VSS12
VDD12
PF15/SCK_C/FP24
PF14/SOUT_C/CNTX_B/sscm4/FP25
PF13/SIN_C/CNRX_B/sscm3/FP26
PF12/eMIOSB16/PCS_C2/sscm2/FP27
PF11/eMIOSB23/PCS_C1/sscm1/FP28
PF10/eMIOSA16/PCS_C0/sscm0/FP29
PG12/eMIOSA23/SOUND/eMIOSA8/FP30
VSSE_A
VDDE_A
PF9/SCL_B/PCS_B0/TXD_B/FP31
PF8/SDA_B/PCS_B1/RXD_B/FP32
PF7/SCL_A/PCS_B2/FP33
PF6/SDA_A/FP34
VSS12
VDD12
PF5/eMIOSA9/DCU_TAG/FP35
PF4/eMIOSA10/PDI7/FP36
PF3/eMIOSA11/PDI6/FP37
PF1/eMIOSA12/PDI5/eMIOSA21/FP38
PF0/eMIOSA13/PDI4/eMIOSA22/FP39
PK1/PDI13/eMIOSA17
PK0/PDI12/eMIOSA18/DCU_TAG
PB2/TXD_A
PB3/RXD_A
PJ15/PDI11/eMIOSA19
PJ14/PDI10/eMIOSA20
PJ13/PDI9/eMIOSB20
PJ12/PDI8/eMIOSB17
VSSE_E
VDDE_E
Any pins labeled “NC” must not be connected to any external circuit.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176-Pin
LQFP
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PB11/CNTX_B/PDI3/eMIOSA16
PB10/CNRX_B/PDI2/eMIOSA23
PB0/CNTX_A/PDI1
PB1/CNRX_A/PDI0
PJ11/PDI7
PJ10/PDI6
PJ9/PDI5
PJ8/PDI4
VSS12
VDD12
PJ3/PDI_PCLK
PJ2/PDI_VSYNC
PJ1/PDI_HSYNC
PJ0/PDI_DE
PE7/M5C1P/SSD5_3/eMIOSA8
PE6/M5C1M/SSD5_2/eMIOSA9
PE5/M5C0P/SSD5_1/eMIOSA10
PE4/M5C0M/SSD5_0/eMIOSA11
VSSMC
VDDMC
PE3/M4C1P/SSD4_3/eMIOSA12
PE2/M4C1M/SSD4_2/eMIOSA13
PE1/M4C0P/SSD4_1/eMIOSA14
PE0/M4C0M/SSD4_0/eMIOSA15
PD15/M3C1P/SSD3_3
PD14/M3C1M/SSD3_2
PD13/M3C0P/SSD3_1
PD12/M3C0M/SSD3_0
VSSMB
VDDMB
PD11/M2C1P/SSD2_3
PD10/M2C1M/SSD2_2
PD9/M2C0P/SSD2_1
PD8/M2C0M/SSD2_0
PD7/M1C1P/SSD1_3/eMIOSB16
PD6/M1C1M/SSD1_2/eMIOSB17
PD5/M1C0P/SSD1_1/eMIOSB18
PD4/M1C0M/SSD1_0/eMIOSB19
VSSMA
VDDMA
PD3/M0C1P/SSD0_3/eMIOSB20
PD2/M0C1M/SSD0_2/eMIOSB21
PD1/M0C0P/SSD0_1/eMIOSB22
PD0/M0C0M/SSD0_0/eMIOSB23
NMI/PF2
VDDE_B
VSSE_B
PCS_A2/eMIOSB19/RXD_B/PB12
PCS_A1/eMIOSB18/TXD_B/PB13
VDD12
VSS12
eMIOSA15/SDA_B/PK10
eMIOSA14/SCL_B/PK11
eMIOSB20/SCK_A/PB9
eMIOSB21/SOUT_A/PB8
eMIOSB22/SIN_A/PB7
CNRX_A/PDI0/PJ4
CNTX_A/PDI1/PJ5
eMIOSA22/CNRX_B/PDI2/PJ6
eMIOSA21/CNTX_B/PDI3/PJ7
CLKOUT/eMIOSB16/PCS_A0/PH4
MA0/SCK_B/PB4
FABM/MA1/SOUT_B/PB5
VDDE_B
VSSE_B
ABS[0]/MA2/SIN_B/PB6
VDD12
VSS12
VDDA
VSSA
XTAL32/AN15/PC15
EXTAL32/AN14/PC14
PCS_B0/MA2/AN13/PC13
PCS_B1/MA1/AN12/PC12
PCS_B2/MA0/AN11/PC11
SOUND/AN10(mux)/PC10
AN9/PC9
AN8/PC8
VDDE_C
VSSE_C
AN7/PC7
AN6/PC6
AN5/PC5
AN4/PC4
AN3/PC3
AN2/PC2
AN1/PC1
AN0/PC0
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
FP13/eMIOSB20/DCU_G2/PA10
FP12/eMIOSA13/DCU_G3/PA11
FP11/eMIOSA12/DCU_G4/PA12
FP10/eMIOSA11/DCU_G5/PA13
FP9/eMIOSA10/DCU_G6/PA14
FP8/eMIOSA9/DCU_G7/PA15
VDDE_A
VSSE_A
FP7/SOUND/SCL_D/DCU_B0/PG0
FP6/SDA_D/DCU_B1/PG1
FP5/eMIOSB19/DCU_B2/PG2
FP4/eMIOSB21/DCU_B3/PG3
FP3/eMIOSB17/DCU_B4/PG4
FP2/eMIOSA8/DCU_B5/PG5
FP1/DCU_B6/PG6
FP0/DCU_B7/PG7
BP0/DCU_VSYNC/PG8
BP1/DCU_HSYNC/PG9
BP2/DCU_DE/PG10
BP3/DCU_PCLK/PG11
VLCD/PH5
VDDR
VSSR
RESET
VRC_CTRL
VPP
XTAL
VSSOSC
EXTAL
VSSPLL
VDDPLL
NC
PDI10/MCKO/PK2
PDI11/MSEO/PK3
PDI12/EVTO/PK4
TDI/PH1
PDI13/EVTI/PK5
PDI14/MDO0/PK6
TDO/PH2
PDI15/MDO1/PK7
TMS/PH3
PDI16/MDO2/PK8
TCK/PH0
PDI17/MDO3/PK9
Figure 3. 176-pin LQFP Pinout
2.3
208 MAPBGA Package Pinout
Figure 4 shows the pinout for the 208-pin BGA package.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
11
Any pins labeled “NC” must not be connected to any external circuit.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
PA0
PJ0
PJ1
PJ3
PJ5
PJ7
PJ14
PF0
PF5
PK9
PK5
NC
NC
PF10
PF11
PF12
B
PA1
VDDE_A
PJ2
PJ4
PJ6
PJ8
PJ15
PF1
PF6
NC
PK6
PK2
NC
NC
VDDE_E
PF13
PA2
PA3
VDDE_A
PJ9
PJ10
PJ12
PK0
PF3
PF7
NC
PK7
PK3
NC
VDDE_
E
NC
PF14
D
PA4
PA5
PG0
VDD12
PJ11
PJ13
PK1
PF4
VDD12
PG12
PK8
PK4
VDD12
NC
NC
PF15
E
PA6
PA7
PG1
PG2
NC
NC
NC
NC
F
PA8
PA9
PG3
PG4
NC
NC
NC
NC
G
PA10
PA11
PG5
PG6
VSS
VSS
VSS
VSS
NC
PE7
PE1
NC
H
PA12
PA13
PA15
PG7
VSS
VSS
VSS
VSS
PE5
PE6
VDDMC
VSSMC
J
RESET
PA14
PG8
PG10
VSS
VSS
VSS
VSS
PE4
PE2
PE0
PD8
K
EXTAL
VDDE_A
PG9
PG11
VSS
VSS
VSS
VSS
PE3
PD13
PD9
PD7
VSSPLL
VDDPLL
NMI/PF2
MDO3
PD15
PD12
VDDMB
VSSM
B
XTAL
VPP
PH3
VREG
BYPASS
PD14
PD11
PD5
PD6
VDDR
VLCD
PH2
VDD12
PK11
PK10
PB8
PB5
PC13
PC9
PC6
PB11
VDDMA
PD10
PD4
PD3
VRC_
PH1
VDDE_B
MDO2
MDO1
PB13
PB7
PB4
PC12
PC8
PC5
PC3
PB10
NC
PD2
PD1
C
MPC560xS Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
L
M
N
P
CTRL
Freescale Semiconductor
R
PH0
VDDE_B
EVTO
PF9
PH4
PB12
PB6
PC15
PC11
PC7
PC4
PC2
PB3
PB2
VDDE_B
PD0
T
MCKO
MSEO
EVTI
PF8
MDO0
PB9
VDDE_C
PC14
PC10
VSSA
VDDA
PC1
PC0
PB1
PB0
VSSMA
Figure 4. 208-pin MAPBGA Pinout
2.4
Signal Description
Pinout and Signal Descriptions
12
WARNING
Pinout and Signal Descriptions
The following sections provide signal descriptions and related information about the functionality and configuration.
2.4.1
Pad Configuration during Reset Phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are floating with the following exceptions:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.4.2
Analog input pins AN[0:9] are pull-up
EVTI (208-pin package only) is pull-up.
PB[6] (FAB) is pull-up. Without external strong pull-up the device starts fetching from flash
RESET pad is driven low. This is released only after PHASE2 reset completion.
Main oscillator pads (EXTAL, XTAL) are tristate.
PA[0] DCU_R0 is pull-up
PB[1] CNRX_A is pull-up
PB[10] CNRX_B is pull-up
PB[12] RXD_B is pull-up
PB[3] RXD_A is pull-up
PB[4] SCK_B is pull-up
PF[0] eMIOSA13 is pull-up
PF[11] eMIOSB23 is pull-up
PF[13] SIN_C is pull-up
PF[2] NMI is pull-up
PF[3] eMIOSA11 is pull-up
PF[5] eMIOSA9 is pull-up
PF[6] SDA_A is pull-up
PF[8] SDA_B is pull-up
PH[0] TCK is pull-up
PH[1] TDI is pull-up
PH[3] TMS is pull-up
PJ[4] PDI0 is pull-up
PJ[6] PDI2 is pull-up
PK[9] MDO3 is pull-up
Voltage Supply Pins
Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
13
Pinout and Signal Descriptions
Table 3. Voltage Supply Pin Descriptions
Pin Number
Supply pin
Function
144 LQFP
176 LQFP
208 MAPBGA
VDD121
1.2 V core supply (1.08 V - 1.32 V)
42, 51, 103, 118,
133
50, 67, 123, 148,
163
D4, D9, D13, N4
VSS12
Low voltage ground for core domain
43, 52, 104, 119,
134
51, 68, 124, 149,
164
—
VSS
Low voltage ground
—
—
G7, G8, G9, G10,
H7, H8, H9, H10,
J7, J8, J9, J10,
K7, K8, K9, K10
VDDA
3.3 V/5 V reference voltage and analog
supply for A/D converter
53
69
T11
VSSA
Reference ground and analog ground for
A/D converter
54
70
T10
VDDR
Voltage regulator VREG supply
22
22
N1
VSSR
Voltage regulator ground
23
23
—
VDDE_A
3.3 V/5 V I/O supply. This supply is
shared with internal flash and 16 MHz
IRC oscillator.
7, 124
7, 154, 170
B2, C3, K2
VSSE_A
3.3 V/5 V I/O supply ground
8, 125
8, 155, 171
—
VDDE_B
3.3 V/5 V I/O supply. 4-16 MHz crystal
oscillator shares this supply.
38
46, 64
P3, R2, R15
VSSE_B
3.3 V/5 V I/O supply ground
39
47, 65
—
VDDE_C
3.3 V/5 V I/O supply. 32 KHz oscillator
shares this supply with ADC.
63
79
T7
VSSE_C
3.3 V/5 V I/O supply ground
64
80
—
VDDE_E
3.3 V/5 V I/O supply
109
133
B15, C14
VSSE_E
3.3 V/5 V I/O supply ground
110
134
—
VDDMA2
Stepper motor 5 V pad supply. SSD
shares this supply.
77
93
N13
VSSMA
Stepper motor ground
78
94
T16
VDDMB2
Stepper motor 5 V pad supply. SSD
shares this supply.
87
103
L15
VSSMB
Stepper motor ground
88
104
L16
Stepper motor 5 V pad supply. SSD
shares this supply.
97
113
H15
VSSMC
Stepper motor ground
98
114
H16
VDDPLL
1.2 V PLL supply
31
31
L2
VDDMC
2
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
14
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Pinout and Signal Descriptions
Table 3. Voltage Supply Pin Descriptions (continued)
Pin Number
Supply pin
Function
144 LQFP
176 LQFP
208 MAPBGA
VSSPLL
PLL ground
30
30
L1
VSSOSC
Oscillator ground
28
28
—
VLCD3
LCD supply option
21
21
N2
VPP4
9 V - 12 V flash test analog write signal
26
26
M2
1
Decoupling capacitors must be connected between these pins and the nearest VSS12 pin.
All stepper motor supplies need to be at same level (3.3 V or 5 V).
3
Refer to LCD segment of Reference manual for usage of VLCD as supply/reference voltage source.
4
This signal needs to be connected to ground during normal operation.
2
2.4.3
Pad Types
In the device the following types of pads are available for system pins and functional port pins:
S = Slow1
M = Medium1,2
F = Fast1,2
I = Input only with analog feature1
J = Input/Output with analog feature
X = Oscillator
2.4.4
System Pins
The system pins are listed in Table 4.
1. Refer to Section 3.6, “I/O Pad Electrical Characteristics, for details
2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (refer to
PCR.SRC in the device reference manual, Pad Configuration Registers (PCR0 - PCR120)).
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
15
Pinout and Signal Descriptions
Table 4. System Pin Descriptions
System pin
I/O
Pad
direction type
Function
RESET
configuration
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
RESET
Bidirectional reset with
Schmitt-Trigger
characteristics and noise
filter.
I/O
M
Input, weak pull
up
24
24
J1
EXTAL
Analog output of the
oscillator amplifier circuit.
Input for the clock
generator in bypass
mode.
O
X
—
29
29
K1
XTAL
Analog input of the
oscillator amplifier circuit.
Needs to be grounded if
oscillator bypass mode is
used.
I
X
—
27
27
M1
EXTAL32
Analog input of the 32KHz
oscillator amplifier circuit.
O
—
56
72
—
XTAL32
Analog output of the 32
KHz oscillator amplifier
circuit. Input for the clock
generator in bypass
mode.
I
—
55
71
—
NMI
Non-Maskable Interrupt
I/O
Input, weak pull
up
37
45
L3
—
25
25
P1
VRC_CTRL Voltage Regulator
external NPN Ballast
base control pin
2.4.5
Nexus Pins
Table 5. Nexus Pins
Pin Number
System pin
Function
144 LQFP
176 LQFP
208 MAPBGA
EVTI
Nexus Event In
—
37
T3
EVTO
Nexus Event Out
—
35
R3
MCKO
Nexus Msg Clock Out
—
33
T1
MDO[0]
Nexus Msg Data Out
—
38
T5
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
16
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Pinout and Signal Descriptions
Table 5. Nexus Pins (continued)
Pin Number
System pin
Function
144 LQFP
176 LQFP
208 MAPBGA
MDO[1]
Nexus Msg Data Out
—
40
P5
MDO[2]
Nexus Msg Data Out
—
42
P4
MDO[3]
Nexus Msg Data Out
—
44
L4
MSE0
Nexus Msg Start/End Out
—
34
T2
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
17
Functional Ports A, B, C, D, E, F, G, H, I, J, K
The functional port pins are listed in Table 6.
Table 6. Port Pin Summary
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
PA[0]
PCR[0]
Option 0
Option 1
Option 2
Option 3
GPIO[0]
DCU_R0
eMIOSA[[22]
SOUND
FP23
SIU
DCU
PWM/Timer
Sound
I/O
M
Input,
Pull Up
135
165
A1
PA[1]
PCR[1]
Option 0
Option 1
Option 2
Option 3
GPIO[1]
DCU_R1
eMIOSA[21]
—
FP22
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
136
166
B1
PA[2]
PCR[2]
Option 0
Option 1
Option 2
Option 3
GPIO[2]
DCU_R2
eMIOSA[20]
—
FP21
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
137
167
C1
PA[3]
PCR[3]
Option 0
Option 1
Option 2
Option 3
GPIO[3]
DCU_R3
eMIOSA[19]
—
FP20
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
138
168
C2
PA[4]
PCR[4]
Option 0
Option 1
Option 2
Option 3
GPIO[4]
DCU_R4
eMIOSA[18]
—
FP19
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
139
169
D1
PA[5]
PCR[5]
Option 0
Option 1
Option 2
Option 3
GPIO[5]
DCU_R5
eMIOSA[17]
—
FP18
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
140
172
D2
PA[6]
PCR[6]
Option 0
Option 1
Option 2
Option 3
GPIO[6]
DCU_R6
eMIOSA[15]
—
FP17
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
141
173
E1
PA[7]
PCR[7]
Option 0
Option 1
Option 2
Option 3
GPIO[7]
DCU_R7
eMIOSA[16]
—
FP16
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
142
174
E2
Pinout and Signal Descriptions
18
2.4.6
Freescale Semiconductor
Table 6. Port Pin Summary (continued)
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
PCR[8]
Option 0
Option 1
Option 2
Option 3
GPIO[8]
DCU_G0
eMIOSB[23]
SCL_C
FP15
SIU
DCU
PWM/Timer
I2C_2
I/O
M
None,
None
143
175
F1
PA[9]
PCR[9]
Option 0
Option 1
Option 2
Option 3
GPIO[9]
DCU_G1
eMIOSB[18]
SDA_C
FP14
SIU
DCU
PWM/Timer
I2C_2
I/O
M
None,
None
144
176
F2
PA[10]
PCR[10]
Option 0
Option 1
Option 2
Option 3
GPIO[10]
DCU_G2
eMIOSB[20]
—
FP13
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
1
1
G1
PA[11]
PCR[11]
Option 0
Option 1
Option 2
Option 3
GPIO[11]
DCU_G3
eMIOSA[13]
—
FP12
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
2
2
G2
PA[12]
PCR[12]
Option 0
Option 1
Option 2
Option 3
GPIO[12]
DCU_G4
eMIOSA[12]
—
FP11
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
3
3
H1
PA[13]
PCR[13]
Option 0
Option 1
Option 2
Option 3
GPIO[13]
DCU_G5
eMIOSA[11]
—
FP10
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
4
4
H2
PA[14]
PCR[14]
Option 0
Option 1
Option 2
Option 3
GPIO[14]
DCU_G6
eMIOSA[10]
—
FP9
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
5
5
J2
PA[15]
PCR[15]
Option 0
Option 1
Option 2
Option 3
GPIO[15]
DCU_G7
eMIOSA[9]
—
FP8
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
6
6
H3
19
Pinout and Signal Descriptions
Preliminary—Subject to Change Without Notice
PA[8]
Freescale Semiconductor
Table 6. Port Pin Summary (continued)
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
PCR[16]
Option 0
Option 1
Option 2
Option 3
GPIO[16]
CANTX_A
PDI1
—
—
SIU
CAN-A
PDI
—
I/O
M
None,
None
106
130
T15
PB[1]
PCR[17]
Option 0
Option 1
Option 2
Option3
GPIO[17]
CANRX_A
PDI0
—
—
SIU
CAN-A
PDI
—
I/O
S
Input,
Pull Up
105
129
T14
PB[2]
PCR[18]
Option 0
Option 1
Option 2
Option3
GPIO[18]
TXD_A
—
—
—
SIU
LIN_A
—
—
I/O
S
None,
None
112
140
R14
PB[3]
PCR[19]
Option 0
Option 1
Option 2
Option3
GPIO[19]
RXD_A
—
—
—
SIU
LIN_A
—
—
I/O
S
Input,
Pull Up
111
139
R13
PB[4]
PCR[20]
Option 0
Option 1
Option 2
Option 3
GPIO[20]
SCK_B
MA0
—
—
SIU
SPI_1
ADC
—
I/O
M
Input,
Pull Up
48
62
P8
PB[5]
PCR[21]
Option 0
Option 1
Option 2
Option 3
GPIO[21]
SOUT_B
MA1
FABM
—
SIU
SPI_1
ADC
Control
I/O
M
Input,
Pull
Down
49
63
N8
PB[6]
PCR[22]
Option 0
Option 1
Option 2
Option 3
GPIO[22]
SIN_B
MA2
ABS[0]
—
SIU
SPI_1
ADC
Control
I/O
S
Input,
Pull Up
50
66
R7
PB[7]
PCR[23]
Option 0
Option 1
Option 2
Option 3
GPIO[23]
SIN_A
eMIOSB[22]
—
—
SIU
SPI_A
PWM/Timer
—
I/O
S
None,
None
46
56
P7
20
Pinout and Signal Descriptions
Preliminary—Subject to Change Without Notice
PB[0]
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
PB[8]
PCR[24]
Option 0
Option 1
Option 2
Option 3
GPIO[24]
SOUT_A
eMIOSB[21]
—
—
SIU
SPI_A
PWM/Timer
—
I/O
M
None,
None
45
55
N7
PB[9]
PCR[25]
Option 0
Option 1
Option 2
Option 3
GPIO[25]
SCK_A
eMIOSB[20]
—
—
SIU
SPI_A
PWM/Timer
—
I/O
M
Input,
Pull Up
44
54
T6
PB[10] PCR[26]
Option 0
Option 1
Option 2
Option 3
GPIO[26]
CNRX_B
PDI2
eMIOSA[23]
—
SIU
CAN-B
PDI
PWM/Timer
I/O
S
Input,
Pull Up
107
131
P13
PB[11] PCR[27]
Option 0
Option 1
Option 2
Option 3
GPIO[27]
CNTX_B
PDI3
eMIOSA[16]
—
SIU
CAN-B
PDI
PWM/Timer
I/O
M
None,
None
108
132
N12
PB[12] PCR[28]
Option 0
Option 1
Option 2
Option 3
GPIO[28]
RXD_B
eMIOSB[19]
PCS_A2
—
SIU
LIN_B
PWM/Timer
SPI_0
I/O
S
Input,
Pull Up
40
48
R6
PB[13] PCR[29]
Option 0
Option 1
Option 2
Option 3
GPIO[29]
TXD_B
eMIOSB[18]
PCS_A1
—
SIU
LIN_B
PWM/Timer
SPI_0
I/O
S
None,
None
41
49
P6
PB[14]
—
—
Reserved
—
—
—
—
—
—
—
A11
PB[15]
—
—
Reserved
—
—
—
—
—
—
—
—
Freescale Semiconductor
PC[0]
PCR[30]
Option 0
Option 1
Option 2
Option 3
GPIO[30]
AN[0]
—
—
—
SIU
ADC
—
—
I
A
Input,
Pull Up
72
88
T13
PC[1]
PCR[31]
Option 0
Option 1
Option 2
Option 3
GPIO[31]
AN[1]
—
—
—
SIU
ADC
—
—
I
A
Input,
Pull Up
71
87
T12
Pinout and Signal Descriptions
21
Table 6. Port Pin Summary (continued)
Freescale Semiconductor
Table 6. Port Pin Summary (continued)
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
PCR[32]
Option 0
Option 1
Option 2
Option 3
GPIO[32]
AN[2]
—
—
—
SIU
ADC
—
—
I
A
Input,
Pull Up
70
86
R12
PC[3]
PCR[33]
Option 0
Option 1
Option 2
Option 3
GPIO[33]
AN[3]
—
—
—
SIU
ADC
—
—
I
A
Input,
Pull Up
69
85
P12
PC[4]
PCR[34]
Option 0
Option 1
Option 2
Option 3
GPIO[34]
AN[4]
—
—
—
SIU
ADC
—
—
I
A
Input,
Pull Up
68
84
R11
PC[5]
PCR[35]
Option 0
Option 1
Option 2
Option 3
GPIO[35]
AN[5]
—
—
—
SIU
ADC
—
—
I
A
Input,
Pull Up
67
83
P11
PC[6]
PCR[36]
Option 0
Option 1
Option 2
Option 3
GPIO[36]
AN[6]
—
—
—
SIU
ADC
—
—
I
A
Input,
Pull Up
66
82
N11
PC[7]
PCR[37]
Option 0
Option 1
Option 2
Option 3
GPIO[37]
AN[7]
—
—
—
SIU
ADC
—
—
I
A
Input,
Pull Up
65
81
R10
PC[8]
PCR[38]
Option 0
Option 1
Option 2
Option 3
GPIO[38]
AN[8]
—
—
—
SIU
ADC
—
—
I
A
Input,
Pull Up
62
78
P10
PC[9]
PCR[39]
Option 0
Option 1
Option 2
Option 3
GPIO[39]
AN[9]
—
—
—
SIU
ADC
—
—
I
A
Input,
Pull Up
61
77
N10
22
Pinout and Signal Descriptions
Preliminary—Subject to Change Without Notice
PC[2]
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
PC[10] PCR[40]
Option 0
Option 1
Option 2
Option 3
GPIO[40]
AN[10]
SOUND
—
—
SIU
ADC
Sound
—
I/O
S
Input,
Pull Up
60
76
T9
PC[11] PCR[41]
Option 0
Option 1
Option 2
Option 3
GPIO[41]
AN[11]
MA0
PCS_B2
—
SIU
ADC
ADC
SPI_B
I/O
S
None,
None
59
75
R9
PC[12] PCR[42]
Option 0
Option 1
Option 2
Option 3
GPIO[42]
AN[12]
MA1
PCS_B1
—
SIU
ADC
ADC
SPI_B
I/O
S
None,
None
58
74
P9
PC[13] PCR[43]
Option 0
Option 1
Option 2
Option 3
GPIO[43]
AN[13]
MA2
PCS_B0
—
SIU
ADC
ADC
SPI_B
I/O
S
None,
None
57
73
N9
PC[14] PCR[44]
Option 0
Option 1
Option 2
Option 3
GPIO[44]
AN[14]
EXTAL32
—
—
SIU
ADC
Osc
—
I/O
S
None,
None
56
72
T8
PC[15] PCR[45]
Option 0
Option 1
Option 2
Option 3
GPIO[45]
AN[15]
XTAL32
—
—
SIU
ADC
Osc
—
I/O
S
None,
None
55
71
R8
PD[0]
PCR[46]
Option 0
Option 1
Option 2
Option 3
GPIO[46]
M0C0M
SSD0_0
eMIOSB[23]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
73
89
R16
PD[1]
PCR[47]
Option 0
Option 1
Option 2
Option 3
GPIO[47]
M0C0P
SSD0_1
eMIOSB[22]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
74
90
P16
Pinout and Signal Descriptions
23
Table 6. Port Pin Summary (continued)
Freescale Semiconductor
Table 6. Port Pin Summary (continued)
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
PCR[48]
Option 0
Option 1
Option 2
Option 3
GPIO[48]
M0C1M
SSD0_2
eMIOSB[21]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
75
91
P15
PD[3]
PCR[49]
Option 0
Option 1
Option 2
Option 3
GPIO[49]
M0C1P
SSD0_3
eMIOSB[20]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
76
92
N16
PD[4]
PCR[50]
Option 0
Option 1
Option 2
Option 3
GPIO[50]
M1C0M
SSD1_0
eMIOSB[19]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
79
95
N15
PD[5]
PCR[51]
Option 0
Option 1
Option 2
Option 3
GPIO[51]
M1C0P
SSD1_1
eMIOSB[18]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
80
96
M15
PD[6]
PCR[52]
Option 0
Option 1
Option 2
Option 3
GPIO[52]
M1C1M
SSD1_2
eMIOSB[17]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
81
97
M16
PD[7]
PCR[53]
Option 0
Option 1
Option 2
Option 3
GPIO[53]
M1C1P
SSD1_3
eMIOSB[16]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
82
98
K16
PD[8]
PCR[54]
Option 0
Option 1
Option 2
Option 3
GPIO[54]
M2C0M
SSD2_0
—
—
SIU
SMD
SSD
—
I/O
SMD None,
None
83
99
J16
PD[9]
PCR[55]
Option 0
Option 1
Option 2
Option 3
GPIO[55]
M2C0P
SSD2_1
—
—
SIU
SMD
SSD
—
I/O
SMD None,
None
84
100
K15
24
Pinout and Signal Descriptions
Preliminary—Subject to Change Without Notice
PD[2]
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
PD[10] PCR[56]
Option 0
Option 1
Option 2
Option 3
GPIO[56]
M2C1M
SSD2_2
—
—
SIU
SMD
SSD
—
I/O
SMD None,
None
85
101
N14
PD[11] PCR[57]
Option 0
Option 1
Option 2
Option 3
GPIO[57]
M2C1P
SSD2_3
—
—
SIU
SMD
SSD
—
I/O
SMD None,
None
86
102
M14
PD[12] PCR[58]
Option 0
Option 1
Option 2
Option 3
GPIO[58]
M3C0M
SSD3_0
—
—
SIU
SMD
SSD
—
I/O
SMD None,
None
89
105
L14
PD[13] PCR[59]
Option 0
Option 1
Option 2
Option 3
GPIO[59]
M3C0P
SSD3_1
—
—
SIU
SMD
SSD
—
I/O
SMD None,
None
90
106
K14
PD[14] PCR[60]
Option 0
Option 1
Option 2
Option 3
GPIO[60]
M3C1M
SSD3_2
—
—
SIU
SMD
SSD
—
I/O
SMD None,
None
91
107
M13
PD[15] PCR[61]
Option 0
Option 1
Option 2
Option 3
GPIO[61]
M3C1P
SSD3_3
—
—
SIU
SMD
SSD
—
I/O
SMD None,
None
92
108
L13
PE[0]
PCR[62]
Option 0
Option 1
Option 2
Option 3
GPIO[62]
M4C0M
SSD4_0
eMIOSA[15]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
93
109
J15
PE[1]
PCR[63]
Option 0
Option 1
Option 2
Option 3
GPIO[63]
M4C0P
SSD4_1
eMIOSA[14]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
94
110
G15
Pinout and Signal Descriptions
25
Table 6. Port Pin Summary (continued)
Freescale Semiconductor
Table 6. Port Pin Summary (continued)
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
PCR[64]
Option 0
Option 1
Option 2
Option 3
GPIO[64]
M4C1M
SSD4_2
eMIOSA[13]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
95
111
J14
PE[3]
PCR[65]
Option 0
Option 1
Option 2
Option 3
GPIO[65]
M4C1P
SSD4_3
eMIOSA[12]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
96
112
K13
PE[4]
PCR[66]
Option 0
Option 1
Option 2
Option 3
GPIO[66]
M5C0M
SSD5_0
eMIOSA[11]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
99
115
J13
PE[5]
PCR[67]
Option 0
Option 1
Option 2
Option 3
GPIO[67]
M5C0P
SSD5_1
eMIOSA[10]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
100
116
H13
PE[6]
PCR[68]
Option 0
Option 1
Option 2
Option 3
GPIO[68]
M5C1M
SSD5_2
eMIOSA[9]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
101
117
H14
PE[7]
PCR[69]
Option 0
Option 1
Option 2
Option 3
GPIO[69]
M5C1P
SSD5_3
eMIOSA[8]
—
SIU
SMD
SSD
PWM/Timer
I/O
SMD None,
None
102
118
G14
PE[8]
—
—
Reserved
—
—
—
—
—
—
—
—
PE[9]
—
—
Reserved
—
—
—
—
—
—
—
—
PE[10]
—
—
Reserved
—
—
—
—
—
—
—
—
PE[11]
—
—
Reserved
—
—
—
—
—
—
—
—
PE[12]
—
—
Reserved
—
—
—
—
—
—
—
—
PE[13]
—
—
Reserved
—
—
—
—
—
—
—
—
PE[14]
—
—
Reserved
—
—
—
—
—
—
—
—
PE[15]
—
—
Reserved
—
—
—
—
—
—
—
—
26
Pinout and Signal Descriptions
Preliminary—Subject to Change Without Notice
PE[2]
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
PF[0]
PCR[70]
Option 0
Option 1
Option 2
Option 3
GPIO[70]
eMIOSA[13]
PDI4
eMIOSA[22]
FP39
SIU
PWM/Timer
PDI
PWM/Timer
I/O
S
Input,
Pull Up
113
143
A8
PF[1]
PCR[71]
Option 0
Option 1
Option 2
Option 3
GPIO[71]
eMIOSA[12]
PDI5
eMIOSA[21]
FP38
SIU
PWM/Timer
PDI
PWM/Timer
I/O
S
None,
None
114
144
B8
PF[2]
PCR[72]
Option 0
Option 1
Option 2
Option 3
GPIO[72]
NMI
—
—
SIU
NMI
—
—
I/O
S
Input,
Pull Up
37
45
L3
PF[3]
PCR[73]
Option 0
Option 1
Option 2
Option 3
GPIO[73]
eMIOSA[11]
PDI6
—
FP37
SIU
PWM/Timer
PDI
—
I/O
M
Input,
Pull Up
115
145
C8
PF[4]
PCR[74]
Option 0
Option 1
Option 2
Option 3
GPIO[74]
eMIOSA[10]
PDI7
—
FP36
SIU
PWM/Timer
PDI
—
I/O
M
None,
None
116
146
D8
PF[5]
PCR[75]
Option 0
Option 1
Option 2
Option 3
GPIO[75]
eMIOSA[9]
DCU_TAG
—
FP35
SIU
PWM/Timer
DCU
—
I/O
M
Input,
Pull Up
117
147
A9
PF[6]
PCR[76]
Option 0
Option 1
Option 2
Option 3
GPIO[76]
SDA_A
—
—
FP34
SIU
I2C_A
—
—
I/O
S
Input,
Pull Up
120
150
B9
PF[7]
PCR[77]
Option 0
Option 1
Option 2
Option 3
GPIO[77]
SCL_A
PCS_B2
—
FP33
SIU
I2C_A
SPI_B
—
I/O
S
None,
None
121
151
C9
—
Pinout and Signal Descriptions
27
Table 6. Port Pin Summary (continued)
Freescale Semiconductor
Table 6. Port Pin Summary (continued)
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
PCR[78]
Option 0
Option 1
Option 2
Option 3
GPIO[78]
SDA_B
PCS_B1
RXD_B
FP32
SIU
I2C_B
SPI_B
LIN_B
I/O
S
Input,
Pull Up
122
152
T4
PF[9]
PCR[79]
Option 0
Option 1
Option 2
Option 3
GPIO[79]
SCL_B
PCS_B0
TXD_B
FP31
SIU
I2C_B
SPI_B
LIN_B
I/O
S
None,
None
123
153
R4
PF[10] PCR[80]
Option 0
Option 1
Option 2
Option 3
GPIO[80]
eMIOSA[16]
PCS_C0
—
FP29
SIU
PWM/Timer
SPI_C
—
I/O
M
None,
None
127
157
A14
PF[11] PCR[81]
Option 0
Option 1
Option 2
Option 3
GPIO[81]
eMIOSB[23]
PCS_C1
—
FP28
SIU
PWM/Timer
SPI_C
—
I/O
M
Input,
Pull Up
128
158
A15
PF[12] PCR[82]
Option 0
Option 1
Option 2
Option 3
GPIO[82]
eMIOSB[16]
PCS_C2
—
FP27
SIU
PWM/Timer
SPI_C
—
I/O
M
None,
None
129
159
A16
PF[13] PCR[83]
Option 0
Option 1
Option 2
Option 3
GPIO[83]
SIN_C
CNRX_B
—
FP26
SIU
SPI_C
CAN_B
—
I/O
M
Input,
Pull Up
130
160
B16
PF[14] PCR[84]
Option 0
Option 1
Option 2
Option 3
GPIO[84]
SOUT_C
CANTX_B
—
FP25
SIU
SPI_C
CAN_B
—
I/O
M
None,
None
131
161
C16
PF[15] PCR[85]
Option 0
Option 1
Option 2
Option 3
GPIO[85]
SCK_C
—
—
FP24
SIU
SPI_C
—
—
I/O
F
None,
None
132
162
D16
28
Pinout and Signal Descriptions
Preliminary—Subject to Change Without Notice
PF[8]
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
PG[0]
PCR[86]
Option 0
Option 1
Option 2
Option 3
GPIO[86]
DCU_B0
SCL_D
SOUND
FP7
SIU
DCU
I2C_3
Sound
I/O
M
None,
None
9
9
D3
PG[1]
PCR[87]
Option 0
Option 1
Option 2
Option 3
GPIO[87]
DCU_B1
SDA_D
—
FP6
SIU
DCU
I2C_3
—
I/O
M
None,
None
10
10
E3
PG[2]
PCR[88]
Option 0
Option 1
Option 2
Option 3
GPIO[88]
DCU_B2
eMIOSB[19]
—
FP5
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
11
11
E4
PG[3]
PCR[89]
Option 0
Option 1
Option 2
Option 3
GPIO[89]
DCU_B3
eMIOSB[21]
—
FP4
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
12
12
F3
PG[4]
PCR[90]
Option 0
Option 1
Option 2
Option 3
GPIO[90]
DCU_B4
eMIOSB[17]
—
FP3
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
13
13
F4
PG[5]
PCR[91]
Option 0
Option 1
Option 2
Option 3
GPIO[91]
DCU_B5
eMIOSA[8]
—
FP2
SIU
DCU
PWM/Timer
—
I/O
M
None,
None
14
14
G3
PG[6]
PCR[92]
Option 0
Option 1
Option 2
Option 3
GPIO[92]
DCU_B6
—
—
FP1
SIU
DCU
—
—
I/O
M
None,
None
15
15
G4
PG[7]
PCR[93]
Option 0
Option 1
Option 2
Option 3
GPIO[93]
DCU_B7
—
—
FP0
SIU
DCU
—
—
I/O
M
None,
None
16
16
H4
Pinout and Signal Descriptions
29
Table 6. Port Pin Summary (continued)
Freescale Semiconductor
Table 6. Port Pin Summary (continued)
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
PCR[94]
Option 0
Option 1
Option 2
Option 3
GPIO[94]
DCU_VSYNC
—
—
BP0
SIU
DCU
—
—
I/O
M
Input,
Pull Up
17
17
J3
PG[9]
PCR[95]
Option 0
Option 1
Option 2
Option 3
GPIO[95]
DCU_HSYNC
—
—
BP1
SIU
DCU
—
—
I/O
M
Input,
Pull Up
18
18
K3
PG[10] PCR[96]
Option 0
Option 1
Option 2
Option 3
GPIO[96]
DCU_DE
—
—
BP2
SIU
DCU
—
—
I/O
M
None,
None
19
19
J4
PG[11] PCR[97]
Option 0
Option 1
Option 2
Option 3
GPIO[97]
DCU_PCLK
—
—
BP3
SIU
DCU
—
—
I/O
M
None,
None
20
20
K4
PG[12] PCR[98]
Option 0
Option 1
Option 2
Option 3
GPIO[98]
eMIOSA[23]
SOUND
eMIOSA[8]
FP30
SIU
PWM/Timer
Sound
PWM/Timer
I/O
S
None,
None
126
156
D10
PG[13]
—
—
Reserved
—
—
—
—
—
—
—
—
PG[14]
—
—
Reserved
—
—
—
—
—
—
—
—
PG[15]
—
—
Reserved
—
—
—
—
—
—
—
—
GPIO[99]
TCK
—
—
—
SIU
JTAG
—
—
I/O
S
Input,
Pull Up
36
43
R1
GPIO[100]
TDI
—
—
—
SIU
JTAG
—
—
I/O
S
Input,
Pull Up
33
36
P2
PH[0]4 PCR[99]
Option 0
Option 1
Option 2
Option 3
PH[1]4 PCR[100] Option 0
Option 1
Option 2
Option 3
30
Pinout and Signal Descriptions
Preliminary—Subject to Change Without Notice
PG[8]
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
PH[2]4 PCR[101] Option 0
Option 1
Option 2
Option 3
GPIO[101]
TDO
—
—
—
SIU
JTAG
—
—
I/O
M
Output,
None
34
39
N3
PH[3]4 PCR[102] Option 0
Option 1
Option 2
Option 3
GPIO[102]
TMS
—
—
—
SIU
JTAG
—
—
I/O
S
Input,
Pull Up
35
41
M3
PH[4]
PCR[103] Option 0
Option 1
Option 2
Option 3
GPIO[103]
PCS_A0
eMIOSB[16]
CLKOUT
—
SIU
SPI_0
PWM/Timer
Control
I/O
F
None,
None
47
61
R5
PH[5]
PCR[104] Option 0
Option 1
Option 2
Option 3
GPIO[104]
VLCD
—
—
—
SIU
LCD
—
—
21
21
—
Freescale Semiconductor
PH[6]
—
—
Reserved
—
—
—
—
—
—
—
—
PH[7]
—
—
Reserved
—
—
—
—
—
—
—
—
PH[8]
—
—
Reserved
—
—
—
—
—
—
—
—
PH[9]
—
—
Reserved
—
—
—
—
—
—
—
—
PH[10]
—
—
Reserved
—
—
—
—
—
—
—
—
PH[11]
—
—
Reserved
—
—
—
—
—
—
—
—
PH[12]
—
—
Reserved
—
—
—
—
—
—
—
—
PH[13]
—
—
Reserved
—
—
—
—
—
—
—
—
PH[14]
—
—
Reserved
—
—
—
—
—
—
—
—
PH[15]
—
—
Reserved
—
—
—
—
—
—
—
—
GPIO[105]
PDI_DE
—
—
—
S
None,
None
—
119
A2
PJ[0]
PCR[105] Option 0
Option 1
Option 2
Option 3
SIU
PDI
—
—
I/O
Pinout and Signal Descriptions
31
Table 6. Port Pin Summary (continued)
Freescale Semiconductor
Table 6. Port Pin Summary (continued)
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
PCR[106] Option 0
Option 1
Option 2
Option 3
GPIO[106]
PDI_HSYNC
—
—
—
SIU
PDI
—
—
I/O
S
None,
None
—
120
A3
PJ[2]
PCR[107] Option 0
Option 1
Option 2
Option 3
GPIO[107]
PDI_VSYNC
—
—
—
SIU
PDI
—
—
I/O
S
None,
None
—
121
B3
PJ[3]
PCR[108] Option 0
Option 1
Option 2
Option 3
GPIO[108]
PDI_PCLK
—
—
—
SIU
PDI
—
—
I/O
M
None,
None
—
122
A4
PJ[4]
PCR[109] Option 0
Option 1
Option 2
Option 3
GPIO[109]
PDI[0]
CNRX_A
—
—
SIU
PDI
CAN-A
—
I/O
S
Input,
Pull Up
—
57
B4
PJ[5]
PCR[110] Option 0
Option 1
Option 2
Option 3
GPIO[110]
PDI[1]
CNTX_A
—
—
SIU
PDI
CAN-A
—
I/O
M
None,
None
—
58
A5
PJ[6]
PCR[111] Option 0
Option 1
Option 2
Option 3
GPIO[111]
PDI[2]
CNRX_B
eMIOSA[22]
—
SIU
PDI
CAN-B
PWM/Timer
I/O
S
Input,
Pull Up
—
59
B5
PJ[7]
PCR[112] Option 0
Option 1
Option 2
Option 3
GPIO[112]
PDI[3]
CNTX_B
eMIOSA[21]
—
SIU
PDI
CAN-B
PWM/Timer
I/O
M
None,
None
—
60
A6
PJ[8]
PCR[113] Option 0
Option 1
Option 2
Option 3
GPIO[113]
PDI[4]
—
—
—
SIU
PDI
—
—
I/O
S
None,
None
—
125
B6
32
Pinout and Signal Descriptions
Preliminary—Subject to Change Without Notice
PJ[1]
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
PJ[9]
PCR[114] Option 0
Option 1
Option 2
Option 3
GPIO[114]
PDI[5]
—
—
—
SIU
PDI
—
—
I/O
S
None,
None
—
126
C4
PJ[10]
PCR[115] Option 0
Option 1
Option 2
Option 3
GPIO[115]
PDI[6]
—
—
—
SIU
PDI
—
—
I/O
S
None,
None
—
127
C5
PJ[11]
PCR[116] Option 0
Option 1
Option 2
Option 3
GPIO[116]
PDI[7]
—
—
—
SIU
PDI
—
—
I/O
S
None,
None
—
128
D5
PJ[12]
PCR[117] Option 0
Option 1
Option 2
Option 3
GPIO[117]
PDI[8]
eMIOSB[17]
—
—
SIU
PDI
PWM/Timer
—
I/O
M
None,
None
—
135
C6
PJ[13]
PCR[118] Option 0
Option 1
Option 2
Option 3
GPIO[118]
PDI[9]
eMIOSB[20]
—
—
SIU
PDI
PWM/Timer
—
I/O
M
None,
None
—
136
D6
PJ[14]
PCR[119] Option 0
Option 1
Option 2
Option 3
GPIO[119]
PDI[10]
eMIOSA[20]
—
—
SIU
PDI
PWM/Timer
—
I/O
M
None,
None
—
137
A7
PJ[15]
PCR[120] Option 0
Option 1
Option 2
Option 3
GPIO[120]
PDI[11]
eMIOSA[19]
—
—
SIU
PDI
PWM/Timer
—
I/O
M
None,
None
—
138
B7
PK[0]
PCR[121] Option 0
Option 1
Option 2
Option 3
GPIO[121]
PDI[12]
eMIOSA[18]
DCU_TAG
—
SIU
PDI
PWM/Timer
DCU
I/O
M
None,
None
—
141
C7
Pinout and Signal Descriptions
33
Table 6. Port Pin Summary (continued)
Freescale Semiconductor
Table 6. Port Pin Summary (continued)
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
PCR[122] Option 0
Option 1
Option 2
Option 3
GPIO[122]
PDI[13]
eMIOSA[17]
—
—
SIU
PDI
PWM/Timer
—
I/O
M
None,
None
—
142
D7
PK[2]
PCR[123] Option 0
Option 1
Option 2
Option 3
GPIO[123]
MCKO
PDI[10]
—
—
SIU
Nexus
PDI
—
I/O
F
None,
None
—
33
B12
PK[3]
PCR[124] Option 0
Option 1
Option 2
Option 3
GPIO[124]
MSEO
PDI[11]
—
—
SIU
Nexus
PDI
—
I/O
M
None,
None
—
34
C12
PK[4]
PCR[125] Option 0
Option 1
Option 2
Option 3
GPIO[125]
EVTO
PDI[12]
—
—
SIU
Nexus
PDI
—
I/O
M
None,
None
—
35
D12
PK[5]
PCR[126] Option 0
Option 1
Option 2
Option 3
GPIO[126]
EVTI
PDI[13]
—
—
SIU
Nexus
PDI
—
I/O
M
None,
None
—
37
—
PK[6]
PCR[127] Option 0
Option 1
Option 2
Option 3
GPIO[127]
MDO0
PDI[14]
—
—
SIU
Nexus
PDI
—
I/O
M
None,
None
—
38
B11
PK[7]
PCR[128] Option 0
Option 1
Option 2
Option 3
GPIO[128]
MDO1
PDI[15]
—
—
SIU
Nexus
PDI
—
I/O
M
None,
None
—
40
C11
PK[8]
PCR[129] Option 0
Option 1
Option 2
Option 3
GPIO[129]
MDO2
PDI[16]
—
—
SIU
Nexus
PDI
—
I/O
M
None,
None
—
42
D11
34
Pinout and Signal Descriptions
Preliminary—Subject to Change Without Notice
PK[1]
Freescale Semiconductor
Table 6. Port Pin Summary (continued)
Port
Pin
PCR
Alternate
Register Function1
Function
Special
Function
Peripheral
Pad RESET
I/O
Type Config.
Direction 2
3
Pin Number
144 LQFP 176 LQFP 208 MAPBGA
MPC560xS Microcontroller Data Sheet, Rev. 1
PCR[130] Option 0
Option 1
Option 2
Option 3
GPIO[130]
MDO3
PDI[17]
—
—
SIU
Nexus
PDI
—
I/O
M
Input,
Pull Up
—
44
A10
PK[10]
PCR[131] Option 0
Option 1
Option 2
Option 3
GPIO[131]
SDA_B
eMIOSA[15]
—
—
SIU
I2C_B
PWM/Timer
—
I/O
S
None,
None
—
52
N6
PK[11]
PCR[132] Option 0
Option 1
Option 2
Option 3
GPIO[132]
SCL_B
eMIOSA[14]
—
—
SIU
I2C_B
PWM/Timer
—
I/O
S
None,
None
—
53
N5
PK[12]
—
—
Reserved
—
—
—
—
—
—
—
—
PK[13]
—
—
Reserved
—
—
—
—
—
—
—
—
PK[14]
—
—
Reserved
—
—
—
—
—
—
—
—
PK[15]
—
—
Reserved
—
—
—
—
—
—
—
—
1
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIU module. PCR.PA = 00 -> Option 0; PCR.PA = 01 -> Option
1; PCR.PA = 10 -> Option 2; PCR.PA = 11-> Option 3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE
bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function
is reported as “—”.
2 A=A, S=Slow, M=Medium, F=Fast, SMD=Stepper Motor Driver
3 Reset configuration is given as I/O direction and pull, e.g., “Input, pullup”.
4 Out of reset pins PH[0:3] are available as JTAG pins (TCK, TDI, TDO and TMS respectively). It is up to the user to configure pins PH[0:3] when
needed.
35
Pinout and Signal Descriptions
Preliminary—Subject to Change Without Notice
PK[9]
Pinout and Signal Descriptions
2.4.7
Signal Details
Table 7. Signal Details
Signal
Peripheral
Description
ABS[0]
BAM
Alternate Boot Select. gives an option to boot by downloading code via
CAN or LIN.
AN[0:15]
Analog-to-digital
conversion (ADC)
Inputs used to bring into the device sensor-based signals for A/D
conversion.
FABM
Force Alternate Boot mode. Forces the device to boot from the external
bus (Can or LIN). If not asserted, the device boots up from the lowest
flash sector containing a valid boot signature.
DCU_DE
Display Control Unit Indicates that valid pixels are present when high; otherwise low to allow
a sub frame display for pixels.
DCU_HSYNC,
Display Control Unit Horizontal sync pulse for TFT-LCD display.
DCU_PCLK
Display Control Unit Output pixel clock for TFT-LCD display
DCU_R[0:7],
DCU_G[0:7]
DCU_B[0:7]
Display Control Unit Red, green and blue color 8 bit Pixel values for TFT-LCD displays.
DCU_TAG
Display Control Unit High indicates certain pixels that can be called as tagged pixels, upon
which internal CRC has been calculated based on pixel values and pixel
position.
DCU_VSYNC
Display Control Unit Vertical sync pulse for TFT-LCD display.
PCS_A[0:2],
PCS_B[0:2],
PCS_C[0:2}
DSPI
Peripheral chip selects when device is in Master mode; not used in slave
modes.
SCK_A,
SCK_B,
SCK_C
DSPI
SPI clock signal - bi-directional.
SIN _A,
SIN _B,
SIN _C
DSPI
SPI data input signal.
SOUT _A,
SOUT _B,
SOUT _C
DSPI
SPI data output signal.
eMIOSA[0:23],
eMIOSB[0:23]
eMIOS
Enhanced Modular Input Output System. 16+9 channel eMIOS for timed
input or output functions.
CNRX_A, CNRX_B FlexCAN
Receive (RX) pins for the CAN bus transceiver.
CNTX_A, CNTX_B
FlexCAN
Transmit (TX) pins for the CAN bus transceiver.
SCL_A,
SCL_B,
SCL_C,
SCL_D
I2C
Bidirectional serial clock compatible with I2C specifications.
SDA_A,
SDA_B,
SDA_C,
SDA_D
I2C
Bidirectional serial data compatible with I2C specifications.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
36
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Pinout and Signal Descriptions
Table 7. Signal Details (continued)
Signal
Peripheral
Description
TCK
JTAG
Debug port serial clock as per JTAG specifications.
TDI
JTAG
Debug port serial data input port as per JTAG standards specifications.
TDO
JTAG
Debug port serial data output port as per JTAG standards specifications.
TMS
JTAG
Debug port Test Mode Select signal for the JTAG TAP controller state
machine and indicates various state transitions for the TAP controller in
the device.
BP[0:3]
LCD
Back plane signals from the LCD controlling the back plane reference
voltage for the LCD display.
FP[0:39]
LCD
Front plane signals for LCD segments.
EVTI
Nexus
Nexus2+ event input trigger.
EVTO
Nexus
Nexus2+ event output trigger.
MCKO
Nexus
Output clock for the development tool
MDO[0:3]
Nexus
Message output port pins that send information bits to the development
tools for messages such as Branch Trace Message (BTM), Ownership
Trace Message (OTM), Data Trace Message (DTM). Only available in
reduced port mode.
MSEO
Nexus
Output pin. Indicates the start or end of the variable length message on
the MDO pins.
PDI[0:17]
Parallel Display
Interface
Video/graphic data in various RGB modes input to the DCU.
PDI_DE
Parallel Display
Interface
Input signal indicates the validity of pixel data on the Input PDI data bus.
For valid Pixel Data this is high, otherwise low.
PDI_HSYNC
Parallel Display
Interface
Input indicates the timing reference for the start of each frame line for the
PDI Input data.
PDI_PCLK
Parallel Display
Interface
Output pixel clock for PDI.
PDI_VSYNC
Parallel Display
Interface
Input indicates the timing reference for the start of a frame for the PDI
input data.
RXD_A
LINFlex-UART
SCI/LIN Receive data signal. This port is used to download the code for
the BAM boot sequence
RXD_B
LINFlex-UART
SCI/LIN Receive data signal. Input pad for the LIN SCI module.
Connects to the internal LIN second port.
TXD_A
LINFlex-UART
This port is used to download the code for the BAM boot sequence
TXD_B
LINFlex-UART
SCI/LIN Transmit data signal. Transmit (output) port for the second LIN
module in the chip .
SOUND
Sound generation
logic (SGL)
Sound signal to the speaker/buzzer.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
37
Pinout and Signal Descriptions
Table 7. Signal Details (continued)
Signal
Peripheral
Description
SSD[0..5]_0
SSD[0..5]_1
SSD[0..5]_2
SSD[0..5]_3
SSD (Stepper Stall
Detect) Interface
Bidirectional SSD inputs and control signals
M[0:5]C0M
M[0:5]C0P
M[0:5]C1M
M[0:5]C1P
Stepper Motor
Control (SMC)
Interface
Controls stepper motors in Dual H bridge configuration.
CLKOUT
Clock generation
module (CGM)
Output clock. It can be selected from several internal clocks of the device
from the clock generation module.
MA[0:2]
ADC
These three control bits are output to enable the selection for an external
Analog Mux for expansion channels.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
38
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3
Electrical Characteristics
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by
internal pull up and pull down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
3.1
Absolute Maximum Ratings
Table 8. Absolute Maximum Ratings
Value
Symbol
VDDA
VSSA
VDDPLL
Parameter
SR Voltage on VDDA pin (ADC reference) with respect
to ground (VSSA)
Conditions
Max
-0.3
+5.5
V
Relative to VDD VDD-0.3
VDD+0.3
VSS-0.1
VSS+0.1
V
1.08
1.32
V
SR Voltage on VSSA (ADC reference) pin with respect
VSS
CC Voltage on VDDPLL (1.2 V PLL supply) pin with
respect to ground (VSSPLL)
Unit
Min
Relative to VDD VDD-0.3
VDD+0.3
VSSPLL
SR Voltage on VSSMC (stepper motor supply ground)
pin with respect to VSS
VSS-0.1
VSS+0.1
V
VDDR
SR Voltage on VDDR pin (regulator supply) with respect
to ground (VSSR)
-0.3
+5.5
V
Relative to VDD VDD-0.3
VDD+0.3
VSSR
SR Voltage on VSSR (regulator ground) pin with
respect to VSS
VSS-0.1
VSS+0.1
V
VDD12
CC Voltage on VDD12 pin with respect to ground
(VSS12)
1.08
1.4
V
VSS12
CC Voltage on VSS12 pin with respect to VSS
VSS-0.1
VSS+0.1
V
VDDE_A1
SR Voltage on VDDE_A (I/O supply) pin with respect to
ground (VSSE_A)
-0.3
+5.5
V
VDDE_B1
SR Voltage on VDDE_B (I/O supply) pin with respect to
ground (VSSE_B)
-0.3
+5.5
V
VDDE_C1
SR Voltage on VDDE_C (I/O supply) pin with respect to
ground (VSSE_C)
-0.3
+5.5
V
VDDE_E1
SR Voltage on VDDE_E (I/O supply) pin with respect to
ground (VSSE_E)
-0.3
+5.5
V
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
39
Electrical Characteristics
Table 8. Absolute Maximum Ratings (continued)
Value
Symbol
Parameter
Conditions
Unit
Min
Max
VDDMA1
SR Voltage on VDDMA (stepper motor supply) pin with
respect to ground (VSSMA)
-0.3
+5.5
V
VDDMB1
SR Voltage on VDDMB (stepper motor supply) pin with
respect to ground (VSSMB)
-0.3
+5.5
V
VDDMC1
SR Voltage on VDDMC (stepper motor supply) pin with
respect to ground (VSSMC)
-0.3
+5.5
V
0
0
V
VSS-0.1
VSS+0.1
V
0
VDDE_A +0.3
V
-0.3
+5.5
V
-0.3
VDD+0.3
VSS2
VSSOSC
VLCD
VIN
SR I/O supply ground
SR Voltage on VSSOSC (oscillator ground) pin with
respect to VSS
SR Voltage on VLCD (LCD supply) pin with respect to
VSS
SR Voltage on any GPIO pin with respect to ground
(VSS)
Relative to VDD
IINJPAD
SR Injected input current on any pin during overload
condition
-10
10
IINJSUM
SR Absolute sum of all injected input currents during
overload condition
-50
50
-55
150
°C
2000
V
TSTORAGE SR Storage temperature
ESDHBM
SR ESD Susceptibility (Human Body Model)
mA
1
Throughout the remainder of this document VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B,
VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC, unless otherwise noted.
2 Throughout the remainder of this document V
SS refers collectively to I/O voltage supply grounds, i.e., VSSE_A,
VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and VSSMC, unless otherwise noted.
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. During overload conditions (VIN > VDD or
VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the
recommended values.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
40
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.1.1
Recommended Operating Conditions
Table 9. Recommended Operating Conditions (3.3 V)
Value
Symbol
VDDA1
VSSA
Parameter
SR Voltage on VDDA pin (ADC reference) with respect
to ground (VSS)
Conditions
Unit
Min
Max
+3.0
+3.6
V
Relative to VDD VDD-0.1
VDD+0.1
VSS-0.1
VSS+0.1
V
1.08
1.32
V
SR Voltage on VSSA (ADC reference) pin with respect
VSS
VDDPLL
CC Voltage on VDDPLL (1.2 V PLL supply) pin with
respect to ground (VSSPLL)
VSSPLL
SR Voltage on VSSMC (stepper motor supply ground)
pin with respect to VSS
VSS-0.1
VSS+0.1
V
VDDR2
SR Voltage on VDDR pin (regulator supply) with respect
to ground (VSSR)
+3.0
+3.6
V
VSSR
Relative to VDD VDD-0.1
VDD+0.1
VSS-0.1
VSS+0.1
V
1.08
1.4
V
VSS-0.1
VSS+0.1
V
+3.0
+3.6
V
0
0
V
SR Voltage on VSSR (regulator ground) pin with
respect to VSS
VDD123,4 CC Voltage on VDD12 pin with respect to ground
(VSS12)
VSS12
VDD5,6,7
VSS8
CC Voltage on VSS12 pin with respect to VSS
SR Voltage on VDD pins (VDDE_A, VDDE_B,
VDDE_C, VDDE_E, VDDMA, VDDMB, VDDMC)
with respect to ground (VSS)
SR I/O supply ground
VDDE_A
SR Voltage on VDDE_A (I/O supply) pin with respect to
ground (VSSE_A)
+3.0
+3.6
V
VDDE_B
SR Voltage on VDDE_B (I/O supply) pin with respect to
ground (VSSE_B)
+3.0
+3.6
V
VDDE_C9 SR Voltage on VDDE_C (I/O supply) pin with respect to
ground (VSSE_C)
+3.0
+3.6
V
VDDE_E
SR Voltage on VDDE_E (I/O supply) pin with respect to
ground (VSSE_E)
+3.0
+3.6
V
VDDMA
SR Voltage on VDDMA (stepper motor supply) pin with
respect to ground (VSSMA)
+3.0
+3.6
V
VDDMB
SR Voltage on VDDMB (stepper motor supply) pin with
respect to ground (VSSMB)
+3.0
+3.6
V
VDDMC
SR Voltage on VDDMC (stepper motor supply) pin with
respect to ground (VSSMC)
+3.0
+3.6
V
VSSOSC
SR Voltage on VSSOSC (oscillator ground) pin with
respect to VSS
0
0
V
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
41
Electrical Characteristics
Table 9. Recommended Operating Conditions (3.3 V) (continued)
Value
Symbol
Parameter
VLCD
SR Voltage on VLCD (LCD supply) pin with respect to
VSS
TVDD
SR VDD slope to ensure correct power up10
Conditions
Unit
Min
Max
0
VDDE_A +0.3
V
0.25
V/µs
°C
TA
SR Ambient temperature under bias
-40
+105
TJ
SR Junction temperature under bias
-40
+150
1
100 nF capacitance needs to be provided between VDDA/VSSA pair.
200 μF capacitance must be connected between VDDR and VSS12.
3
VDD12 cannot be used to drive any external component.
4
Each VDD12/VSS12 supply pair should have a 10 μF capacitor. Absolute combined maximum capacitance is 40 μF.
5 V
DD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC.
6 100 nF capacitance needs to be provided between each V /V
DD SS pair
7 Full electrical specification cannot be guaranteed when voltage drops below 3.0V. In particular, ADC electrical
characteristics and I/O’s DC electrical specification may not be guaranteed.
When voltage drops below VLVDHVL device is reset.
8 V
SS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and
VSSMC) unless otherwise noted.
9 V
DDE_C should not be less than VDDA.
10 Guaranteed by device validation
2
Table 10. Recommended Operating Conditions (5.0 V)
Value
Symbol
VDDA1
Parameter
SR Voltage on VDDA pin (ADC reference) with respect
to ground (VSS)
Conditions
Voltage
drop2
Relative to VDD
VSSA
SR Voltage on VSSA (ADC reference) pin with respect
VSS
VDDPLL
CC Voltage on VDDPLL (1.2 V PLL supply) pin with
respect to ground (VSSPLL)
VSSPLL
SR Voltage on VSSMC (stepper motor supply ground)
pin with respect to VSS
VDDR3
SR Voltage on VDDR pin (regulator supply) with
respect to ground (VSSR)
Voltage
drop2
Relative to VDD
Unit
Min
Max
+4.5
+5.5
+3.0
+5.5
VDD-0.1
VDD+0.1
VSS-0.1
VSS+0.1
V
1.08
1.32
V
VSS-0.1
VSS+0.1
V
+4.5
+5.5
V
+3.0
+5.5
VDD-0.1
VDD+0.1
V
VSSR
SR Voltage on VSSR (regulator ground) pin with
respect to VSS
VSS-0.1
VSS+0.1
V
VDD124,5
CC Voltage on VDD12 pin with respect to ground
(VSS12)
1.08
1.4
V
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
42
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 10. Recommended Operating Conditions (5.0 V) (continued)
Value
Symbol
VSS12
VDD
6,7
VSS8
Parameter
Conditions
CC Voltage on VSS12 pin with respect to VSS
SR Voltage on VDD pins (VDDE_A, VDDE_B,
VDDE_C, VDDE_E, VDDMA, VDDMB, VDDMC)
with respect to ground (VSS)
Voltage drop
2
Unit
Min
Max
VSS-0.1
VSS+0.1
V
+4.5
+5.5
V
0
0
V
SR I/O supply ground
VDDE_A
SR Voltage on VDDE_A (I/O supply) pin with respect
to ground (VSSE_A)
+4.5
+5.5
V
VDDE_B
SR Voltage on VDDE_B (I/O supply) pin with respect
to ground (VSSE_B)
+4.5
+5.5
V
VDDE_C9 SR Voltage on VDDE_C (I/O supply) pin with respect
to ground (VSSE_C)
+4.5
+5.5
V
VDDE_E
SR Voltage on VDDE_E (I/O supply) pin with respect
to ground (VSSE_E)
+4.5
+5.5
V
VDDMA
SR Voltage on VDDMA (stepper motor supply) pin
with respect to ground (VSSMA)
+4.5
+5.5
V
VDDMB
SR Voltage on VDDMB (stepper motor supply) pin
with respect to ground (VSSMB)
+4.5
+5.5
V
VDDMC
SR Voltage on VDDMC (stepper motor supply) pin
with respect to ground (VSSMC)
+4.5
+5.5
V
VSSOSC
SR Voltage on VSSOSC (oscillator ground) pin with
respect to VSS
0
0
V
VLCD
SR Voltage on VLCD (LCD supply) pin with respect to
VSS
0
VDDE_A +0.3
V
TVDD
SR VDD slope to ensure correct power up10
0.25
V/µs
-40
+105
°C
-40
+105
-40
+150
TA
TJ
SR Ambient temperature under bias
SR Junction temperature under bias
1
100 nF capacitance needs to be provided between VDDA/VSSA pair.
Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, I/O DC and ADC electrical
characteristics may not be guaranteed below 4.5 V during the voltage drop sequence.
3 200 μF capacitance must be connected between V
DDR and VSS12.
4 V
cannot
be
used
to
drive
any
external
component.
DD12
5 Each V
DD12/VSS12 supply pair should have a 10 μF capacitor. Absolute combined maximum capacitance is 40 μF.
6
VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC.
7 100 nF capacitance needs to be provided between each V /V
DD SS pair
8 V
refers
collectively
to
I/O
voltage
supply
grounds,
i.e.,
V
SS
SSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and
VSSMC) unless otherwise noted.
9 V
DDE_C should not be less than VDDA.
10
Guaranteed by device validation
2
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
43
Electrical Characteristics
3.2
Thermal Characteristics
Table 11. Thermal Characteristics for 144-pin LQFP1
Symbol
Parameter
Conditions
Convection2
Value
Unit
Single layer board - 1s
50
°C/W
Four layer board - 2s2p
41
°C/W
RθJA
CC
Junction to Ambient Natural
RθJA
CC
Junction to Ambient Natural Convection2
RθJMA
CC
2
Junction to Ambient
@200 ft./min., single layer
board - 1s
41
°C/W
RθJMA
CC
Junction to Ambient2
@200 ft./min., four layer
board- 2s2p
35
°C/W
RθJB
CC
Junction to Board3
29
°C/W
4
RθJCtop
CC
Junction to Case
10
°C/W
ΨJT
CC
Junction to Package Top Natural
Convection5
2
°C/W
1
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
3
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
2
Table 12. Thermal Characteristics for 176-pin LQFP1
Symbol
RθJA
Parameter
CC
Conditions
Junction to Ambient Natural
Convection2
Single layer board - 1s
Convection2
Value
Unit
43
°C/W
RθJA
CC
Junction to Ambient Natural
Four layer board - 2s2p
35
°C/W
RθJMA
CC
Junction to Ambient2
@200 ft./min., single layer
board - 1s
35
°C/W
RθJMA
CC
Junction to Ambient2
@200 ft./min., Four layer
board - 2s2p
30
°C/W
RθJB
CC
Junction to Board3
24
°C/W
RθJCtop
CC
Junction to Case (Top)4
9
°C/W
ΨJT
CC
Junction to Package Top Natural
Convection5
2
°C/W
1
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
3
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
2
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
44
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.2.1
General Notes for Specifications at Maximum Junction Temperature
An estimate of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RθJA * PD)
Eqn. 1
where:
TA= ambient temperature for the package (oC)
RθJA= junction to ambient thermal resistance (oC/W)
PD= power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for
estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a
four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance
is not a constant. The thermal resistance depends on the:
•
•
•
•
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit
board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
•
•
•
One oz. (35 micron nominal thickness) internal planes
Components are well separated
Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the
ambient temperature varies widely within the application. For many natural convection and especially closed box applications,
the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the
device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TB + (RθJB * PD)
Eqn. 2
where:
TB= board temperature for the package perimeter (oC)
RθJB= junction-to-board thermal resistance (oC/W) per JESD51-8S
PD= power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction
temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to
a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal
resistance:
RθJA = RθJC + RθCA
Eqn. 3
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
45
Electrical Characteristics
where:
RθJA = junction to ambient thermal resistance (oC/W)
RθJC= junction to case thermal resistance (oC/W)
RθCA= case to ambient thermal resistance (oC/W)
RθJC s device related and is not affected by other factors. The thermal environment can be controlled to change the
case-to-ambient thermal resistance, RθCA. For example, change the air flow around the device, add a heat sink, change the
mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding
the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat
sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the
junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a
substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the
thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple
estimations and for computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization
parameter (ΨJT) to determine the junction temperature by measuring the temperature at the top center of the package case using
the following equation:
TJ = TT + (ΨJT x PD)
Eqn. 4
where:
TT= thermocouple temperature on top of the package (oC)
ΨJT= thermal characterization parameter (oC/W)
PD= power dissipation in the package (W)
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests
on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from
the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling
effects of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
Middlefield Rd.
CA 94043
805 East
Mountain View,
(415) 964-5111
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
46
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.3
EMI (Electromagnetic Interference) Characteristics
Table 13. EMI Testing Specifications1
Value
Symbol
1
3.4
3.4.1
Parameter
Unit
min
typ
max
—
SR
Scan Range
TBD
TBD
TBD
MHz
—
SR
Operating Frequency
TBD
TBD
TBD
MHz
—
SR
VDD12, VDDPLL Operating Voltages
TBD
TBD
TBD
V
—
SR
VDD, VDDA Operating Voltages
TBD
TBD
TBD
V
—
SR
Maximum Amplitude
TBD
TBD
TBD
dBuV
—
SR
Operating Temperature
TBD
TBD
TBD
oC
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03.
Power Management
Voltage Regulator Electrical Characteristics
The internal voltage regulator requires an external NPN (BCP56 or BCP68) ballast to be connected as shown in Figure 5 as well
as an external capacitance (CREG) to be connected to the device in order to provide a stable low voltage digital supply to the
device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit
the serial inductance of the board to less than 15 nH.
For the MPC5606S microcontroller , 10 µF should be placed between each of the three VDD12/VSS12 supply pairs and also
between the VDDPLL/VSSPLL pair. Additionally, 200 μF should be placed between the VDDR pin and the adjacent VSS pin.
VDDR = 3.0 V to 3.6 V / 4.5 V to 5.5 V, TA = -40 to 105 °C, unless otherwise specified.
VDDR
VRC_CTRL
VDD12
Figure 5. External NPN Ballast Connections
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
47
Electrical Characteristics
Table 14. Voltage Regulator Electrical Characteristics1
No.
Symbol
Parameter
Min
Max
Unit
SR Power supply
3.0
5.5
V
-40
150
°C
1
VDDR
2
TJ
SR Junction temperature
3
IREG
CC Current consumption
4
IL
5
VDD12
Reference included,
@ 55 °C No load
@ Full load
—
CC Output current capacity
DC load current
—
200
mA
CC Output voltage (value @ IL = 0 @ 27°C)
Pre-trimming sigma
< 7 mV
—
1.330
V
Post-trimming
1.270
1.280
Post-trimming
1.145
—
4 capacitances of
10 µF each
10 * 4
Output voltage (value @ IL = Imax)
6
SR External decoupling/stability capacitor
7
LBOND
8
10
1
2
3.4.2
tSU
@ DC @ no load
mA
2
11
µF
ESR of external cap
0.05
0.2
ohm
1 bond wire R + 1
pad R
0.2
1
ohm
0
15
nH
—
-30
dB
CC Bonding Inductance for Bipolar Base Control pad
CC Power supply rejection
9
Conditions
Cload = 10 µF * 4
@ 200 kHz @ no load
-100
@ DC @ 400 mA
-30
@ 200 kHz @ 400 mA
-30
CC
Load current transient
Cload = 10 µF * 4
—
CC
Start-up time after input supply stabilizes2
Cload = 10 µF * 4
—
10% to 90%
of IL (max) in
100 ns
500
µs
All values in this table are PRELIMINARY.
Time after the input supply to the voltage regulator has ramped up (VDDR) and the voltage regulator has asserted
the Power OK signal.
Voltage monitor electrical characteristics
The device implements a Power On Reset module to ensure correct power-up initialization, as well as four low voltage detectors
to monitor the VDD and the VDD12 voltage while device is supplied:
•
•
•
•
•
POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state
LVDHV3 monitors VDD to ensure device reset below minimum functional supply
LVDHV5 monitors VDD when application uses device in the 5.0V ± 10% range
LVDLVCOR monitors power domain No. 1
LVDLVBKP monitors power domain No. 0
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
48
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 15. Low voltage monitor electrical characteristics
Symbol
VPORH
Value2
Conditions1
Parameter
CC Power-on reset threshold
Unit
TA = 25°C,
after trimming
Min
Typ
Max
1.5
—
2.7
—
—
2.8
VLVDHV3H
CC LVDHV3 low voltage detector high threshold
VLVDHV3L
CC LVDHV3 low voltage detector low threshold
2.7
—
—
VLVDHV5H
CC LVDHV5 low voltage detector high threshold
—
—
4.37
VLVDHV5L
CC LVDHV5 low voltage detector low threshold
4.2
—
—
VLVDLVCORH CC LVDLVCOR low voltage detector high threshold
—
—
1.185
VLVDLVCORL CC LVDLVCOR low voltage detector low threshold
1.095
—
—
1
V
VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 / +105°C, unless otherwise specified
All values need to be confirmed during device validation.
2
3.4.3
Low voltage domain power consumption
Table 16 provides DC electrical characteristics for significant application modes. These values are indicative values; actual
consumption depends on the application.
Table 16. DC electrical characteristics
Symbol
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
SR Maximum current
—
—
135
mA
CC RUN mode current
—
130
—
mA
IDDWAIT
CC WAIT mode current
—
30
—
mA
IDDHALT
CC HALT mode current
4.5
—
12
mA
IDDSTOP
CC STOP mode current
IRC 16 MHz oscillator off
—
1.5
—
mA
IDDSTOP
CC STOP mode current
HPVREG off
—
800
—
µA
IDDSTOP
CC STOP mode current
IRC 16 MHz oscillator on
—
4
—
mA
IDDSTDBY CC STANDBY mode current
IRC 16 MHz oscillator off
—
29
—
µA
IDDSTDBY CC STANDBY mode current
IRC 16 MHz oscillator on
—
300
—
µA
IDDMAX
IDDRUN
3
1
VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 / +125 °C
All values need to be confirmed during device validation.
3 Value is for maximum peripherals turned on. May vary significantly based on different configurations, active
peripherals, operating frequency, etc.
2
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
49
Electrical Characteristics
3.5
DC Electrical Specifications
3.6
I/O Pad Electrical Characteristics
3.6.1
I/O Pad Types
The device provides four main I/O pad types depending of the associated alternate functions:
•
•
•
Slow pads are the most common pads, providing a good compromise between transition time and low electromagnetic
emission.
Medium pads provide fast enough transition for the serial communication channels with controlled current to reduce
electromagnetic emission.
Fast pads provide maximum speed. There are used for improved NEXUS debugging capability.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
3.6.2
I/O Input DC Characteristics
Table 17 provides input DC electrical characteristics as described in Figure 6.
VIN
VDD
VIH
VHYS
VIL
VINTERNAL
(SIU register)
Figure 6. I/O Input DC Electrical Characteristics Definition
Table 17. I/O Input DC Electrical Characteristics
Symbol
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
VIH
SR Input high level CMOS
Schmitt Trigger
0.65VDD
VDD+0.4
VIL
SR Input low level CMOS
Schmitt Trigger
-0.4
0.35VDD
VHYS
CC3 Input hysteresis CMOS
Schmitt Trigger
0.1VDD
V
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
50
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105 °C.
All values need to be confirmed during device validation.
3
Parameter value guaranteed by design.
1
2
3.6.3
I/O Output DC Characteristics
The following tables provide DC characteristics for bidirectional pads:
•
•
•
•
Table 18 provides weak pull figures. Both pull-up and pull-down resistances are supported.
Table 19 provides output driver characteristics for I/O pads when in SLOW configuration.
Table 20 provides output driver characteristics for I/O pads when in MEDIUM configuration.
Table 21 provides output driver characteristics for I/O pads when in FAST configuration.
Table 18. I/O Pull-up/Pull-down DC Electrical Characteristics
Symbol
Value2
Conditions1
Parameter
Unit
Min
1
2
Typ
Max
|IWPU|
CC Weak pull-up current absolute value
10
—
|IWPD|
CC Weak pull-down current absolute value
10
—
µA
VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 to +105°C, unless otherwise specified.
All values need to be confirmed during device validation.
Table 19. SLOW Configuration Output Buffer Electrical Characteristics
Symbol
Parameter
Value2
Conditions1
Unit
Min
VOH
VOL
CC Output high level
SLOW configuration
CC Output low level
SLOW configuration
Push Pull, IOH = -2mA,
VDD = 5.0V ± 10%, ipp_hve = 0
(recommended)
0.8VDD
Push Pull, IOH = -2mA,
VDD = 5.0V ± 10%, ipp_hve = 13
0.8VDD
Push Pull, IOH = -1mA,
VDD = 3.3V ± 10%, ipp_hve = 1
(recommended)
VDD-0.
8
Typ
Max
V
Push Pull, IOL = 2mA,
VDD = 5.0V ± 10%, ipp_hve = 0
(recommended)
0.1VDD
Push Pull, IOL = 2mA,
VDD = 5.0V ± 10%, ipp_hve = 13
0.1VDD
Push Pull, IOL = 1mA,
VDD = 3.3V ± 10%, ipp_hve = 1
(recommended)
0.5
V
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
51
Electrical Characteristics
Table 19. SLOW Configuration Output Buffer Electrical Characteristics (continued)
Symbol
Parameter
Conditions
Value2
1
Unit
Min
Ttr
2
3
4
5
6
Max
CC4 Output transition time output pin5 CL = 25pF,
SLOW configuration
VDD = 5.0V ± 10%, ipp_hve = 0
506
CL = 50pF,
VDD = 5.0V ± 10%, ipp_hve = 0
1006
CL = 100pF,
VDD = 5.0V ± 10%, ipp_hve = 0
1254
CL = 25pF,
VDD = 3.3V ± 10%, ipp_hve = 1
406
CL = 50pF,
VDD = 3.3V ± 10%, ipp_hve = 1
506
CL = 100pF,
VDD = 3.3V ± 10%, ipp_hve = 1
754
recommended configuration at
VDD = 5.0V ± 10%, ipp_hve = 0,
VDD = 3.3V ± 10%, ipp_hve = 1
2
VDD = 5.0V ± 10%, ipp_hve = 1
7
ΔItr50 CC4 Current slew at CL = 50pF
SLOW configuration
1
Typ
ns
mA/ns
VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 to +105°C, unless otherwise specified
All values need to be confirmed during device validation.
This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are
configured in input or in high impedance state.
Data based on characterization results, not tested in production
CL calculation should include device and package capacitances (CPKG < 5pF).
Data based on simulation results, not tested in production
Table 20. MEDIUM Configuration Output Buffer Electrical Characteristics
Symbol
Parameter
Value2
Conditions1
Unit
Min
VOH
CC Output high level
MEDIUM configuration
Push Pull, IOH = -2mA,
VDD = 5.0V ± 10%, ipp_hve = 0
(recommended)
0.8VDD
Push Pull, IOH = -1mA,
VDD = 5.0V ± 10%, ipp_hve = 13
0.8VDD
Push Pull, IOH = -1mA,
VDD = 3.3V ± 10%, ipp_hve = 1
(recommended)
VDD-0.8
Typ
Max
V
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
52
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 20. MEDIUM Configuration Output Buffer Electrical Characteristics (continued)
Symbol
Parameter
Conditions
Value2
1
Unit
Min
VOL
Ttr
CC Output low level
MEDIUM configuration
CC4 Output transition time output
pin5
MEDIUM configuration
ΔItr50 CC4 Current slew at CL = 50pF
MEDIUM configuration
Typ
Max
Push Pull, IOL = 2mA,
VDD = 5.0V ± 10%, ipp_hve = 0
(recommended)
0.1VDD
Push Pull, IOL = 1mA,
VDD = 5.0V ± 10%, ipp_hve = 13
0.1VDD
Push Pull, IOL = 1mA,
VDD = 3.3V ± 10%, ipp_hve = 1
(recommended)
0.5
CL = 25pF,
VDD = 5.0V ± 10%, ipp_hve = 0
10
CL = 50pF,
VDD = 5.0V ± 10%, ipp_hve = 0
20
CL = 100pF,
VDD = 5.0V ± 10%, ipp_hve = 0
40
CL = 25pF,
VDD = 3.3V ± 10%, ipp_hve = 1
12
CL = 50pF,
VDD = 3.3V ± 10%, ipp_hve = 1
25
CL = 100pF,
VDD = 3.3V ± 10%, ipp_hve = 1
40
recommended configuration at
VDD = 5.0V ± 10%, ipp_hve = 0
VDD = 3.3V ± 10%, ipp_hve = 1
7
VDD = 5.0V ± 10%, ipp_hve = 1
16
V
ns
mA/ns
VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 to +105°C, unless otherwise specified
All values need to be confirmed during device validation.
3 This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are
configured in input or in high impedance state.
4 Data based on characterization results, not tested in production
5 C calculation should include device and package capacitance (C
L
PKG < 5pF).
1
2
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
53
Electrical Characteristics
Table 21. FAST Configuration Output Buffer Electrical Characteristics
Symbol
Parameter
Value2
Conditions1
Unit
Min
VOH
VOL
Ttr
CC Output high level
FAST configuration
CC Output low level
FAST configuration
Push Pull, IOH = -14mA,
VDD = 5.0V ± 10%, ipp_hve = 0
(recommended)
0.8VDD
Push Pull, IOH = -7mA,
VDD = 5.0V ± 10%, ipp_hve = 13
0.8VDD
Push Pull, IOH = -11mA,
VDD = 3.3V ± 10%, ipp_hve = 1
(recommended)
VDD-0.8
Typ
Max
V
Push Pull, IOL = 14mA,
VDD = 5.0V ± 10%, ipp_hve = 0
(recommended)
0.1VDD
Push Pull, IOL = 7mA,
VDD = 5.0V ± 10%, ipp_hve = 13
0.1VDD
Push Pull, IOL = 11mA,
VDD = 3.3V ± 10%, ipp_hve = 1
(recommended)
0.5
CC4 Output transition time output CL = 25pF,
pin5
VDD = 5.0V ± 10%, ipp_hve = 0
FAST configuration
CL = 50pF,
VDD = 5.0V ± 10%, ipp_hve = 0
4
CL = 100pF,
VDD = 5.0V ± 10%, ipp_hve = 0
12
CL = 25pF,
VDD = 3.3V ± 10%, ipp_hve = 1
4
CL = 50pF,
VDD = 3.3V ± 10%, ipp_hve = 1
7
CL = 100pF,
VDD = 3.3V ± 10%, ipp_hve = 1
12
VDD = 5.0V ± 10%, ipp_hve = 0
(recommended configuration)
55
VDD = 3.3V ± 10%, ipp_hve = 1
(recommended configuration)
40
VDD = 5.0V ± 10%, ipp_hve = 1
100
ΔItr504 CC Current slew at CL = 50pF
FAST configuration
V
ns
6
mA/n
s
VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 to +105°C, unless otherwise specified
All values need to be confirmed during device validation.
3 This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are
configured in input or in high impedance state.
4
Data based on characterization results, not tested in production
5 C calculation should include device and package capacitance (C
L
PKG < 5pF).
1
2
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
54
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.6.4
I/O Pad Current Specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as
described in Table 22.
Table 23 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG
maximum value.
In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain
below the IDYNSEG maximum value.
Table 22. I/O Supply Segment
Supply segment
Package
1
2
3
4
5
6
A1
B2
C3,4
D5
E6
144 LQFP
pins 1 - 21
pins 113 - 144
pins 22 - 52
pins 53 - 72
pins 73 - 102
pins 103 - 112
176 LQFP
pins 1 - 21
pins 143 - 176
pins 22 - 68
pins 69 - 88
pins 89 - 118
pins 119 - 142
LCD pad segment containing pad supplies VDDE_A
Misc. pad segment containing pad supplies VDDE_B
ADC pad segment containing pad supplies VDDE_C
ADC VDDA and VDDE_C should be at the same voltage level
Stepper Motor pad segment containing I/O supplies VDDMA, VDDMB, VDDMC
Misc pad segment containing pad supplies VDDE_E
Table 23. I/O Consumption
Symbol
Parameter
Value2
Conditions1
Unit
Min
ISWTSLW CC3 Dynamic I/O current for SLOW
configuration
ISWTMED CC3 Dynamic I/O current for MEDIUM
configuration
ISWTFST3 CC3 Dynamic I/O current for FAST
configuration
Typ
Max
CL = 25pF,
VDD = 5.0V ± 10%, ipp_hve = 0
20
CL = 25pF,
VDD = 3.3V ± 10%, ipp_hve = 1
16
CL = 25pF,
VDD = 5.0V ± 10%, ipp_hve = 0
29
CL = 25pF,
VDD = 3.3V ± 10%, ipp_hve = 1
17
CL = 25pF,
VDD = 5.0V ± 10%, ipp_hve = 0
110
CL = 25pF,
VDD = 3.3V ± 10%, ipp_hve = 1
50
mA
mA
mA
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
55
Electrical Characteristics
Table 23. I/O Consumption (continued)
Symbol
Parameter
Value2
1
Conditions
Unit
Min
IRMSSLW
CC RMS I/O current for SLOW
configuration
IRMSMED CC Average I/O current for SLOW
configuration
IRMSFST
IDYNSEG
IAVGSEG
CC Average I/O current for SLOW
configuration
Typ
Max
CL = 25 pF, 2 MHz
VDD = 5.0 V ± 10%, ipp_hve = 0
2.33
CL = 25 pF, 4 MHz
VDD = 5.0 V ± 10%, ipp_hve = 0
3.23
CL = 100 pF, 2 MHz
VDD = 5.0 V ± 10%, ipp_hve = 0
6.64
CL = 25 pF, 2 MHz
VDD = 3.3 V ± 10%, ipp_hve = 1
1.63
CL = 25 pF, 4 MHz
VDD = 3.3 V ± 10%, ipp_hve = 1
2.33
CL = 100 pF, 2 MHz
VDD = 3.3 V ± 10%, ipp_hve = 1
4.74
CL = 25 pF, 2 MHz
VDD = 5.0 V ± 10%, ipp_hve = 0
6.63
CL = 25 pF, 4 MHz
VDD = 5.0 V ± 10%, ipp_hve = 0
13.43
CL = 100 pF, 2 MHz
VDD = 5.0 V ± 10%, ipp_hve = 0
18.34
CL = 25 pF, 2 MHz
VDD = 3.3 V ± 10%, ipp_hve = 1
5.03
CL = 25 pF, 4 MHz
VDD = 3.3 V ± 10%, ipp_hve = 1
8.53
CL = 100 pF, 2 MHz
VDD = 3.3 V ± 10%, ipp_hve = 1
11.04
CL = 25 pF, 2 MHz
VDD = 5.0V ± 10%, ipp_hve = 0
22.03 mA
CL = 25 pF, 4 MHz
VDD = 5.0V ± 10%, ipp_hve = 0
33.03
CL = 100 pF, 2 MHz
VDD = 5.0V ± 10%, ipp_hve = 0
56.04
CL = 25 pF, 2 MHz
VDD = 3.3V±10%, ipp_hve = 1
14.03
CL = 25 pF, 4 MHz
VDD = 3.3 V ± 10%, ipp_hve = 1
20.03
CL = 100 pF, 2 MHz
VDD = 3.3 V ± 10%, ipp_hve = 1
25.04
SR Sum of all the dynamic and static I/O VDD = 5.0 V ± 10%, ipp_hve = 0
current within a supply segment
VDD = 3.3 V ± 10%, ipp_hve = 1
110
SR Sum of all the static I/O current within VDD = 5.0 V ± 10%, ipp_hve = 0
a supply segment
VDD = 3.3 V ± 10%, ipp_hve = 1
70
mA
mA
mA
65
mA
65
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
56
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105°C, unless otherwise specified
All values need to be confirmed during device validation.
3
Data based on simulation results, not tested in production
4
Data based on characterization results, not tested in production
1
2
3.7
RESET electrical characteristics
The device implements a dedicated bidirectional RESET pin.
Figure 7. Start-up reset requirements
VDD
VDDMIN
RESET
VIH
VIL
device reset forced by RESET
device start-up phase
TRSTREM
Figure 8. Noise filtering on reset signal
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
57
Electrical Characteristics
Table 24. Reset electrical characteristics
Symbol
Parameter
Value2
1
Unit
Conditions
Min
SR Input High Level CMOS
Schmitt Trigger
0.65VDD
VDD+0.4
V
VIL
SR Input low Level CMOS
Schmitt Trigger
-0.4
0.35VDD
V
VHYS
CC3 Input hysteresis CMOS
Schmitt Trigger
0.1VDD
Ttr
4
5
6
CC4 Output transition time output
pin6
MEDIUM configuration
SR RESET Input Filtered Pulse
WNFRS
SR RESET Input Not Filtered
Pulse
|IWPU|
3
CC4 Output low level
WFRST
T
1
Max
VIH
VOL
2
Typ
V
Push Pull, IOL = 2mA,
VDD = 5.0V ± 10%, ipp_hve = 0
(recommended)
0.1VDD
Push Pull, IOL = 1mA,
VDD = 5.0V ± 10%, ipp_hve = 15
0.1VDD
Push Pull, IOL = 1mA,
VDD = 3.3V ± 10%, ipp_hve = 1
(recommended)
0.5
CL = 25pF,
VDD = 5.0V ± 10%, ipp_hve = 0
10
CL = 50pF,
VDD = 5.0V ± 10%, ipp_hve = 0
20
CL = 100pF,
VDD = 5.0V ± 10%, ipp_hve = 0
40
CL = 25pF,
VDD = 3.3V ± 10%, ipp_hve = 1
12
CL = 50pF,
VDD = 3.3V ± 10%, ipp_hve = 1
25
CL = 100pF,
VDD = 3.3V ± 10%, ipp_hve = 1
40
1000
CC4 Weak pull-up current absolute
value
10
-
V
ns
40
ns
-
ns
µA
VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 / +105oC, unless otherwise specified
All values need to be confirmed during device validation.
Data based on characterization results, not tested in production
Guaranteed by design simulation.
This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
the reference manual).
CL calculation should include device and package capacitance (CPKG < 5pF).
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
58
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.8
Main Oscillator Electrical Characteristics
The device provides an oscillator/resonator driver. Figure 9 describes a simple model of the internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
EXTAL
CL
Crystal
EXTAL
RP
XTAL
CL
DEVICE
VDD
I
R
EXTAL
XTAL
Resonator
DEVICE
XTAL
DEVICE
Figure 9. Crystal Oscillator and Resonator Connection Scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
59
Electrical Characteristics
VDD
VDDMIN
VXTAL
1/fXOSCHS
VXOSCHS
90%
VXOSCHSOP
10%
TXOSCHSSU
valid internal clock
Figure 10. Main Oscillator Electrical Characteristics
Table 25. Main Oscillator Electrical Characteristics
Symbol
fXOSCHS
gmXOSCHS
VXOSCHS
Parameter
Oscillator
transconductance
CC3 Oscillation amplitude
VXOSCHSOP CC3 Oscillation operating
point
Unit
Min
Typ
Max
4.0
—
16.0
MHz
VDD = 3.3 V ± 10%,
OSCILLATOR_MARGIN = 0
4.11
5.59
7.38
mA/V
VDD = 5.0 V ± 10%,
OSCILLATOR_MARGIN = 0
3.67
5.04
6.73
VDD = 3.3 V ± 10%,
OSCILLATOR_MARGIN = 1
4.93
6.70
8.86
VDD = 5.0 V ± 10%,
OSCILLATOR_MARGIN = 1
4.54
6.22
8.31
fOSC = 4 MHz,
VDD = 3.3 V ± 10%
2.51
—
—
fOSC = 16 MHz,
VDD = 3.3 V ± 10%
1.68
—
—
fOSC = 4 MHz,
VDD = 5.0 V ± 10%
4.74
—
—
fOSC = 16 MHz,
VDD = 5.0 V ± 10%
3.02
—
—
VDD = 3.3 V ± 10% VEXTAL
0.894
—
1.143
0.894
—
1.146
0.904
—
1.166
0.904
—
1.169
SR Oscillator frequency
CC3
Value2
Conditions1
VXTAL
VDD = 5.0 V ± 10% VEXTAL
VXTAL
V
V
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
60
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 25. Main Oscillator Electrical Characteristics (continued)
Symbol
Parameter
CC3 Oscillator consumption
IXOSCHS
TXOSCHSSU CC3 Oscillator start-up time
Conditions
Value2
1
Unit
Min
Typ
Max
fOSC = 4 MHz
—
—
2.43
fOSC = 16 MHz
—
—
2.52
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 0
—
—
6.0
fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1
—
—
1.8
mA
ms
VIH
SR Input high level CMOS
Schmitt Trigger
Oscillator bypass mode
0.65VDD
VDD+0.4
V
VIL
SR Input low level CMOS
Schmitt Trigger
Oscillator bypass mode
-0.4
0.35VDD
V
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 Data based on simulation results, not tested in production
2
3.9
Low Power Oscillator Electrical Characteristics
The device provides a low power oscillator/resonator driver.
PC[15]
PC[15]
Resonator
Crystal
CX
RF
PC[14]
PC[14]
CY
DEVICE
DEVICE
Figure 11. Crystal Oscillator and Resonator Connection Scheme
NOTE
PC[14]/PC[15] must not be directly used to drive external circuits.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
61
Electrical Characteristics
VDD
VDDMIN
VXTAL
1/fXOSCLP
VXOSCLP
90%
10%
TXOSCLPSU
valid internal clock
Figure 12. Low Power Oscillator Electrical Characteristics
Table 26. Low Power Oscillator Electrical Characteristics
Symbol
Parameter
fXOSCLP
SR Oscillator frequency
VXOSCLP
CC3 Oscillation amplitude
IXOSCLP
CC3
Value2
Conditions1
Unit
Min
Typ
Max
32
-
40
kHz
VDD=3.3V±10%,
1.12
1.33
1.74
V
VDD=5.0V±10%,
1.12
1.37
1.74
Oscillator consumption
5
µA
TXOSCLPSU CC3 Oscillator start-up time
2
s
VIH
SR Input high level CMOS
Schmitt Trigger
Oscillator bypass mode 0.65VDD
VDD+0.4
V
VIL
SR Input low level CMOS
Schmitt Trigger
Oscillator bypass mode
0.35VDD
V
-0.4
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 Granted by device validation
2
3.10
FMPLL Electrical Characteristics
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main
oscillator driver.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
62
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 27. FMPLL Electrical Characteristics
Symbol
Value2
Conditions1
Parameter
Unit
Min
SR PLL reference clock3
fPLLIN
ΔPLLIN
SR PLL reference clock duty cycle
4
fPLLOUT CC
fCPU
TLOCK
Typ
4
64
MHz
40
60
%
16
64
MHz
645
MHz
Stable oscillator (fPLLIN = 16 MHz)
200
µs
3
PLL output clock frequency
CC4 System clock frequency
CC4 PLL lock time
Max
4
ΔTPKJIT CC
PLL jitter (pk to pk)
fPLLIN = 16 MHz (resonator)
500
ps
ΔTLTJIT
4
PLL long term jitter
fPLLIN = 16 MHz (resonator)
1.5
ns
4
mA
IPLL
1
CC
CC6 Oscillator consumption
TA = 25°C
VDDPLL = 1.2 V ± 10%, TA = -40 to +105 °C, unless otherwise specified.
All values need to be confirmed during device validation.
PLLIN clock retrieved directly from XOSCHS clock. Input characteristics are granted when oscillator is used in
functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN.
Data based on device simulation.
fCPU 64 MHz can be achieved only at up to 105 °C
Data based on characterization results, not tested in production
2
3
4
5
6
3.11
Main RC Oscillator Electrical Characteristics
The device provides a 16 MHz internal RC oscillator. This is used as the default clock at the power-up of the device.
Table 28. Main RC Oscillator Electrical Characteristics
Symbol
Parameter
Value2
Conditions1
Unit
Min
CC3 RC oscillator high frequency
TA = 25 °C, trimmed
IRCMRUN
CC3 RC oscillator high frequency current in
running mode
TA = 25 °C, trimmed
IRCMPWD
CC3 RC oscillator high frequency current in power TA = 25 °C
down mode
ΔRCMTRI
M
CC3 RC oscillator precision after trimming of fRC TA = 25 °C
fRCM
ΔRCMVAR CC4 RC oscillator variation in temperature and
supply with respect to fRC at TA = 55 °C in
high-frequency configuration
Typ
Max
16
MHz
200
µA
10
µA
-1
+1
%
-5
+5
%
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105 °C, unless otherwise specified.
All values need to be confirmed during device validation.
3 Guaranteed by device simulation, not tested in production
4
Guaranteed by device characterization, not tested in production
2
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
63
Electrical Characteristics
3.12
Low Power RC Oscillator Electrical Characteristics
The device provides a low power internal RC oscillator. This can be used as the reference clock for the RTC module.
Table 29. Low Power RC Oscillator Electrical Characteristics
Symbol
Parameter
Conditions
Value2
1
Unit
Min
CC3 RC oscillator low frequency
fRCL
3
CC RC oscillator low frequency current
IRCL
Typ
TA = 25 °C, trimmed
Max
128
kHz
TA = 25 °C, trimmed
5
µA
ΔRCLTRIM CC3 RC oscillator precision after trimming of fRCL TA = 25 °C
-2
+2
%
High frequency
ΔRCLVAR CC RC oscillator variation in temperature and
supply with respect to fRC at TA = 55 °C in high configuration
frequency configuration
-10
+10
%
3
3
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105 °C, unless otherwise specified.
All values need to be confirmed during device validation.
3
Guaranteed by device simulation, not tested in production
2
3.13
Flash Memory Electrical Characteristics
Table 30. Program and Erase Specifications
Symbol
Parameter
Min Value
Typical
Value1
Initial
Max2
Max3
Unit
Tdwprogram
Double Word (64 bits) Program Time4
—
22
500
μs
T16kpperase
16 KB Block Pre-program and Erase Time
—
500
5000
ms
T32kpperase
32 KB Block Pre-program and Erase Time
—
600
5000
ms
T128kpperase
128 KB Block Pre-program and Erase Time
—
1300
7500
ms
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3 The maximum program & erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4
Actual hardware programming times. This does not include software overhead.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
64
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 31. Flash Module Life
Value
Symbol
Parameter
3.14
Unit
Min
Typ
P/E
Number of program/erase cycles per block for
16 Kbyte blocks over the operating
temperature range (TJ)
—
100,000
—
cycles
P/E
Number of program/erase cycles per block for
32 Kbyte blocks over the operating
temperature range (TJ)
—
10,000
100,000
(TBD)
cycles
P/E
Number of program/erase cycles per block for
128 Kbyte blocks over the operating
temperature range (TJ)
—
1,000
100,000
(TBD)
cycles
Blocks with 0 - 1,000 P/E
cycles
20
—
years
Blocks with 10,000 P/E
cycles
10
—
years
Blocks with 100,000 P/E
cycles
1-5
(TBD)
—
years
Retention Minimum data retention at 85 °C average
ambient temperature1
1
Conditions
Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
Analog to Digital Converter (ADC) Electrical Characteristics
The device provides a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
65
Electrical Characteristics
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = VDDA / 1024
1018
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
5
(5)
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error OSE
Figure 13. ADC Characteristics and Error Definitions
3.14.1
Input Impedance and ADC Accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources
charge during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
66
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330kΩ is obtained (REQ =
1 / (fc*CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage
partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit
must be designed to respect the Equation 5:
Eqn. 5
R S + R F + R L + R SW + R AD
1
V A • --------------------------------------------------------------------------- < --- LSB
R EQ
2
Equation 5 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW
and RAD) can be neglected with respect to external resistances.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
VA
Filter
RF
Current Limiter
RL
CF
Channel
Selection
Sampling
RSW1
RAD
CP1
CP2
CS
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
Current Limiter Resistance
RL
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
Figure 14. Input Equivalent Circuit (Precise Channels)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
67
Electrical Characteristics
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
Filter
RS
Current Limiter
RF
RS
RF
CF
RL
RSW
RAD
CP
CS
Extended
Switch
Sampling
RSW1
RSW2
RAD
RL
CF
VA
Channel
Selection
CP1
CP3
CP2
CS
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance (two contributions RSW1 and RSW2)
Sampling Switch Impedance
Pin Capacitance (three contributions, CP1, CP2 and CP3)
Sampling Capacitance
Figure 15. Input Equivalent Circuit (Extended Channels)
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are
initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 14): A charge sharing phenomenon
is installed when the sampling phase is started (A/D switch close).
Voltage Transient on CS
VCS
VA
VA2
ΔV < 0.5 LSB
1
2
τ1 < (RSW + RAD) CS << TS
τ2 = RL (CS + CP1 + CP2)
VA1
TS
t
Figure 16. Transient Behavior during Sampling Phase
In particular two different transient periods can be distinguished:
•
A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series,
and the time constant is
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
68
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
CP • CS
τ 1 = ( R SW + R AD ) • --------------------CP + CS
Eqn. 6
Equation 6 can again be simplified considering only CS as an additional worst condition. In reality, the transient is
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS
is always much longer than the internal time constant:
Eqn. 7
τ 1 < ( R SW + R AD ) • C S « T S
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance
according to Equation 8:
Eqn. 8
V A1 • ( C S + C P1 + C P2 ) = V A • ( C P1 + C P2 )
•
A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance
RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality
would be faster), the time constant is:
Eqn. 9
τ 2 < R L • ( C S + C P1 + C P2 )
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time TS, a constraints on RL sizing is obtained:
Eqn. 10
10 • τ 2 = 10 • R L • ( C S + C P1 + C P2 ) < TS
Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source
impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2
(at the end of the charge transfer transient) will be much higher than VA1. Equation 11 must be respected (charge
balance assuming now CS already charged at VA1):
Eqn. 11
VA2 • ( C S + C P1 + C P2 + C F ) = V A • C F + V A1 • ( C P1 + C P2 + C S )
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to
provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of
the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
69
Electrical Characteristics
Analog Source Bandwidth (VA)
TC ≤ 2 RFCF (Conversion Rate vs. Filter Pole)
fF = f0 (Anti-aliasing Filtering Condition)
Noise
2 f0 ≤ fC (Nyquist)
f0
f
Anti-Aliasing Filter (fF = RC Filter pole)
fF
Sampled Signal Spectrum (fC = conversion Rate)
f0
f
fC
f
Figure 17. Spectral Representation of Input Signal
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF),
according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater
than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS,
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the
sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on CS; from the two charge balance equations above, it is simple to derive Equation 12 between the ideal and real sampled
voltage on CS:
Eqn. 12
VA
C P1 + C P2 + C F
----------- = ------------------------------------------------------V A2
C P1 + C P2 + C F + C S
From this formula, in the worst case (when VA is maximum, that is for instance 5V), assuming to accept a maximum error of
half a count, a constraint is evident on CF value:
Eqn. 13
C F > 2048 • C S
3.14.2
ADC Electrical Characteristics
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
70
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 32. ADC Electrical Characteristics
Symbol
Parameter
Value2
Conditions1
Unit
Min
Typ
Max
VSSA
SR Voltage on VSSA (ADC
reference) pin with
respect to ground (VSS)3
-0.1
0.1
V
VDDA
SR Voltage on VDDA pin
(ADC reference) with
respect to ground (VSS)
VDD-0.1
VDD+0.1
V
VAINx
SR Analog input voltage4
VSSA-0.1
VDDA+0.1
V
fADC
SR ADC analog frequency
6
32
MHz
1.5
µs
tADC_PU SR ADC power up delay
tADC_S
CC5
Sample
time6
fADC = 32 MHz,
ADC_conf_sample_input = 17
0.5
fADC = 6 MHz,
ADC_conf_sample_input =
127
tADC_C CC5 Conversion time7
fADC = 32 MHz,
ADC_conf_comp = 2
µs
21
0.625
µs
CS
CC5 ADC input sampling
capacitance
3
pF
CP1
CC5 ADC input pin
capacitance 1
3
pF
CP2
CC5 ADC input pin
capacitance 2
1
pF
CP3
CC5 ADC input pin
capacitance 3
1
pF
RSW1
CC5 Internal resistance of
analog source
3
kΩ
RSW2
CC5 Internal resistance of
analog source
2
kΩ
RAD
CC5 Internal resistance of
analog source
0.1
kΩ
IINJ
SR Input current Injection
Current injection on one ADC
input, different from the
converted one
-10
10
mA
INL
CC5 Integral Non Linearity
No overload
-1.5
1.5
LSB
DNL
CC5 Differential Non Linearity No overload
-1.0
1.0
LSB
-1.0
1.0
LSB
-1.0
1.0
LSB
5
OFS
CC Offset error
GNE
CC5
Gain error
After offset cancellation
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
71
Electrical Characteristics
Table 32. ADC Electrical Characteristics (continued)
Symbol
Value2
1
Parameter
Conditions
Unit
Min
TUEP
TUEX
1
2
3
4
5
6
7
CC5 Total Unadjusted Error for No overload
precise channels, input
overload conditions on
only pins
adjacent channel
-2
CC5 Total Unadjusted Error for No overload
extended channel,
overload conditions on
adjacent channel
-3
Typ
Max
2
LSB
LSB
3
LSB
LSB
VDDA = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105 °C, unless otherwise specified.
All values need to be confirmed during device validation.
Analog and digital VSS must be common (to be tied together externally).
VAINx may exceed VSSA and VDDA limits, remaining on absolute maximum ratings, but the results of the conversion
will be clamped respectively to 0x000 or 0x3FF
Guaranteed by design
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the
end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC_S depend on programming.
This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the
time to load the result’s register with the conversion result.
3.15
AC Specifications
3.15.1
Pad AC Specifications
Table 33. Pad AC specifications (5.0 V, IPP_HVE=1)1
Num
1
2
Tswitchon1
(ns)
Pad
Slow
Medium
Rise/Fall2
(ns)
Current slew3
(mA/ns)
Frequency
(MHz)
Load drive
(pF)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
1.5
-
30
6
-
50
-
-
4
0.04
-
2
25
1.5
-
30
9
-
100
-
-
2
0.04
-
2
50
1.5
-
30
12
-
125
-
-
2
0.04
-
2
100
1.5
-
30
16
-
150
-
-
2
0.04
-
2
200
1
-
15
3
-
10
-
-
40
2.5
-
7
25
1
-
15
5
-
20
-
-
20
2.5
-
7
50
1
-
15
9
-
40
-
-
13
2.5
-
8
100
1
-
15
12
-
70
-
-
7
2.5
-
8
200
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
72
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 33. Pad AC specifications (5.0 V, IPP_HVE=1)1 (continued)
Num
3
Tswitchon1
(ns)
Pad
Fast
Rise/Fall2
(ns)
Current slew3
(mA/ns)
Frequency
(MHz)
Load drive
(pF)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
1
-
6
1
-
4
-
-
100
18
-
55
25
1
-
6
1.5
-
6
-
-
80
18
-
55
50
1
-
6
3
-
12
-
-
40
18
-
55
100
1
-
6
5
-
16
-
-
25
18
-
55
200
4
Symmetric
1
-
5
1
-
4
-
-
50
10
-
25
25
5
Pull Up/Down
(5.5 V max)
-
-
-
-
-
5000
-
-
-
-
-
-
50
1
Propagation delay from VDD/2 of internal signal to Pchannel/Nchannel on condition
Slope at rising/falling edge
3 Data based on characterization results, not tested in production
2
Table 34. Pad AC specifications (3.3 V, IPP_HVE=0)1
Num
1
2
3
Tswitchon1
(ns)
Pad
Slow
Medium
Fast
Rise/Fall2
(ns)
Current slew3
(mA/ns)
Frequency
(MHz)
Load drive
(pF)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
3
-
40
4
-
40
-
-
4
0.01
-
2
25
3
-
40
6
-
50
-
-
2
0.01
-
2
50
3
-
40
10
-
75
-
-
2
0.01
-
2
100
3
-
40
14
-
100
-
-
2
0.01
-
2
200
1
-
15
2
-
12
-
-
40
2.5
-
7
25
1
-
15
4
-
25
-
-
20
2.5
-
7
50
1
-
15
8
-
40
-
-
13
2.5
-
7
100
1
-
15
14
-
70
-
-
7
2.5
-
7
200
1
-
6
1
-
4
-
-
72
3
-
40
25
1
-
6
1.5
-
7
-
-
55
3
-
40
50
1
-
6
3
-
12
-
-
40
3
-
40
100
1
-
6
5
-
18
-
-
25
3
-
40
200
4
Symmetric
1
-
6
2
-
6
-
-
50
3
-
25
25
5
Pull Up/Down
(3.6 V max)
-
-
-
-
-
7500
-
-
-
-
-
-
50
1
Propagation delay from VDD/2 of internal signal to Pchannel/Nchannel on condition
Slope at rising/falling edge
3 Data based on characterization results, not tested in production
2
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
73
Electrical Characteristics
VDD/2
Pad
Data Input
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
VOH
VOL
Pad
Output
Figure 18. Pad Output Delay
3.16
AC Timing
3.16.1
IEEE 1149.1 Interface Timing
Table 35. JTAG Interface Timing1
Num
Characteristic
Min
Max
Unit
tJCYC
CC2 TCK Cycle Time
100
—
ns
2
tJDC
CC2
40
60
ns
3
tTCKRISE
CC2 TCK Rise and Fall Times (40% – 70%)
—
3
ns
tTMSS, tTDIS
CC2
TMS, TDI Data Setup Time
5
—
ns
tTMSH, tTDIH
CC2
TMS, TDI Data Hold Time
25
—
ns
6
tTDOV
CC2
TCK Low to TDO Data Valid
—
35
ns
7
tTDOI
CC2 TCK Low to TDO Data Invalid
0
—
ns
tTDOHZ
CC2
TCK Low to TDO High Impedance
—
30
ns
tBSDV
CC2
TCK Falling Edge to Output Valid
—
35
ns
1
4
5
8
9
2
TCK Clock Pulse Width (Measured at VDD/2)
10
tBSDVZ
CC
TCK Falling Edge to Output Valid out of High
Impedance
—
50
ns
11
tBSDHZ
CC2 TCK Falling Edge to Output High Impedance
—
50
ns
12
tBSDST
CC2 Boundary Scan Input Valid to TCK Rising Edge
50
—
ns
tBSDHT
CC2
50
—
ns
13
1
Symbol
TCK Rising Edge to Boundary Scan Input Invalid
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 3.0 V to 5.5 V, TA = -40 to
105 °C, and CL = 50 pF with SRC = 0b11.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
74
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
2
Parameter values guaranteed by design.
TCK
2
3
2
1
3
Figure 19. JTAG Test Clock Input Timing
TCK
4
5
TMS, TDI
6
7
8
TDO
Figure 20. JTAG Test Access Port Timing
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
75
Electrical Characteristics
TCK
9
11
Output
Signals
10
Output
Signals
12
13
Input
Signals
Figure 21. JTAG Boundary Scan Timing
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
76
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.16.2
Nexus Debug Interface
Table 36. Nexus Debug Port Timing1
Num
1
2
Symbol
tMCYC
tMDC
Characteristic
CC2
MCKO Cycle Time
CC
2
MCKO Duty Cycle
2
Max
Unit
22
—
ns
40
60
%
–2
14
ns
–2
14
ns
3
3
tMDOV
CC
4
tMSEOV
CC2
tEVTOV
CC
2
MCKO Low to EVTO Data Valid
–2
14
ns
2
EVTI Pulse Width
4
—
tTCYC
5
MCKO Low to MDO Data Valid
Min
MCKO Low to MSEO Data Valid3
3
6
tEVTIPW
CC
7
tEVTOPW
CC2
EVTO Pulse Width
1
—
tMCYC
8
tTCYC
CC2
TCK Cycle Time4
100
—
ns
tTDC
CC2
TCK Duty Cycle
40
60
%
10
tNTDIS, tNTMSS
CC2
TDI, TMS Data Setup Time
25
—
ns
11
tNTDIH, tNTMSH
CC2
TDI, TMS Data Hold Time
5
—
ns
12
tJOV
CC2
TCK Low to TDO Data Valid
0
35
ns
9
1
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is
measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 3.0 V to 5.5V, TA
= -40 to 105 °C, and CL = 50 pF (Cl=30 pF on MCKO), with SRC = 0b11.
2 Parameter values guaranteed by design.
3 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
4 The system clock frequency needs to be three times faster that the TCK frequency.
Figure 22. Nexus Clock Timing
1
2
MCKO
3
4
5
MDO
MSEO
EVTO
Output Data Valid
Figure 23. Nexus Output Timing
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
77
Electrical Characteristics
TCK
9
8
9
Figure 24. Nexus TCK Timing
TCK
10
11
TMS, TDI
12
TDO
Figure 25. Nexus TDI, TMS, TDO Timing
3.16.3
Interface to TFT LCD Panels
Figure 26 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with
positive polarity. The sequence of events for active matrix interface timing is:
•
DCU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode,
DCU_CLK runs continuously. This signal frequency could be from 5 to 66 MHz depending on the panel type.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
78
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
•
•
•
DCU_HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse.
DCU_VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
DCU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display.
When disabled, the data is invalid and the trace is off.
DCU_VSYNC
LINE 1
DCU_HSYNC
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
DCU_HSYNC
DCU_DE
1
2
3
m-1
m
DCU_CLK
DCU_LD[23:0]
Figure 26. TFT LCD InterfaceTiming Overview1
3.16.3.1
Interface to TFT LCD Panels—Pixel Level Timings
Figure 27 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and data. All parameters
shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DCU_CLK signal
(meaning the data and sync signals change on the rising edge) and active-high polarity of the DCU_HSYNC, DCU_VSYNC
and DCU_DE signals. The user can select the polarity of the DCU_HSYNC and DCU_VSYNC signals via the SYN_POL
register, whether active-high or active-low. The default is active-high. The DCU_DE signal is always active-high.
Pixel clock inversion and a flexible programmable pixel clock delay are also supported. They are programmed via the DCU
Clock Confide Register (DCCR) in the system clock module.
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H, BP_H and FP_H
parameters are programmed via the HSYN PARA register. The PW_V, BP_V and FP_V parameters are programmed via the
VSYN_PARA register.
Table 37. LCD Interface Timing Parameters—Horizontal and Vertical
Num
Symbol
Characteristic
Value
Unit
1
tPCP
CC1
31.25
ns
2
tPWH
CC1
HSYNC pulse width
PW_H * tPCP
ns
3
tBPH
CC1
HSYNC back porch width
BP_H * tPCP
ns
4
tFPH
CC1
HSYNC front porch width
FP_H * tPCP
ns
tSW
CC1
Screen width
DELTA_X * tPCP
ns
5
Display pixel clock period
1. In Figure 26, the “DCU_LD[23:0]” signal is an aggregation of the DCU’s RGB signals—DCU_R[0:7], DCU_G[0:7] and
DCU_B[0:7].
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
79
Electrical Characteristics
Table 37. LCD Interface Timing Parameters—Horizontal and Vertical (continued)
Num
Characteristic
1
Value
Unit
6
tHSP
CC
HSYNC (line) period
(PW_H + BP_H + FP_H + DELTA_X ) *
tPCP
ns
7
tPWV
CC1
VSYNC pulse width
PWV * tHSP
ns
tBPV
CC1
VSYNC back porch width
BP_V * tHSP
ns
tFPV
CC1
VSYNC front porch width
FP_V * tHSP
ns
tSH
1
CC
Screen height
DELTA_Y * tHSP
ns
tVSP
CC1
VSYNC (frame) period
(PW_V + BP_V + FP_V + DELTA_Y ) *
tHSP
ns
8
1
Symbol
Parameter values guaranteed by design.
tHSP
Start of line
tPWH
tFPH
tSW
tBPH
tPCP
DCU_CLK
DCU_LD[23:0]
Invalid Data
2
1
3
DELTA_X
Invalid Data
DCU_HSYNC
DCU_DE
Figure 27. Horizontal Sync Timing
tVSP
Start of Frame
tSH
tBPV
tPWV
tFPV
tHCP
DCU_HSYNC
DCU_LD[23:0]
(Line Data)
Invalid Data
1
2
3
DELTA_Y
Invalid Data
DCU_HSYNC
DCU_DE
Figure 28. Vertical Sync Pulse
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
80
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.16.3.2
Interface to TFT LCD Panels—Access Level
Table 38. LCD Interface Timing Parameters1,2,3,4—Access Level
Num
1
2
3
4
5
Symbol
Characteristic
Min.
Value
Typical
Value
31.25
—
40
—
Max. Value
Unit
1
tCKP
CC5
PDI Clock Period
2
tCHD
CC5
Duty cycle
3
tDSU
5
CC
interface data setup time
6
—
ns
4
tDHD
CC5
PDI interface data access hold time
1
—
ns
5
tCSU
CC5
PDI interface control signal setup time
3
—
ns
6
tCHD
CC5
PDI interface control signal hold time
1
—
ns
5
ns
60
%
7
CC
TFT interface data valid after pixel clock
—
6
ns
8
CC5
TFT interface HSYNC valid after pixel clock
—
5
ns
9
CC5
TFT interface VSYNC valid after pixel clock
—
5.5
ns
10
CC5
TFT interface DE valid after pixel clock
—
5.6
ns
11
CC5
TFT interface hold time for data and control
bits
12
CC5
Relative skew between the data bits
2
—
—
ns
3.7
ns
The characteristics in this table are based on the assumption that data is output at +ve edge and displays latch data
on -ve edge
Intra bit skew is less than 2 ns
Load CL = 50 pf for frequency up to 20 MHz
Load CL = 25 pf for display freq from 20 to 32 MHz
Parameter values guaranteed by design.
tCHD
tCSU
tDSU
tDHD
DCU_HSYNC
DCU_VSYNC
DCU_DE
DCU_CLK
tCKH
tCKL
DCU_LD[23:0]
Figure 29. LCD Interface Timing Parameters—Access Level
3.16.4
External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Timing
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
81
Electrical Characteristics
Table 39. IRQ and NMI Timing
Num
2
Characteristic
Min.
Value
Max.
Value
Unit
tIPWL
CC1 IRQ/NMI Pulse Width Low
200
—
ns
2
tIPWH
CC1
200
—
ns
3
tICYC
CC1 IRQ/NMI Edge to Edge Time2
400
—
ns
Min.
Value2
Max.
Value
Unit
1
1
Symbol
IRQ/NMI Pulse Width High
Parameter values guaranteed by design.
Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.
1,2
1,2
3
Figure 30. IRQ and NMI Timing
3.16.5
Enhanced Modular I/O Subsystem (eMIOS) Timing
Table 40. eMIOS Timing1
Num
1
2
Symbol
Characteristic
tMIPW
CC3 eMIOS Input Pulse Width
4
—
tCYC
tMOPW
CC3
1
—
tCYC
eMIOS Output Pulse Width
1
eMIOS timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = -40 to 105 °C,
and CL = 50 pF with SRC = 0b00
2
There is no limitation on the peripheral for setting the minimum pulse width, the actual width is restricted by the pad
delays. Refer to the pad specification section for the details.
3 Parameter values guaranteed by design.
3.16.6
FlexCAN Timing
The CAN functions are available as TX pins at normal IO pads and as RX pins at the always on domain. There is no filter for
the wakeup dominant pulse. Any high-to-low edge can cause wakeup if configured.
Table 41. FlexCAN Timing1
Num
Symbol
Characteristic
Min.
Value
Max.
Value
Unit
1
tCANOV
CC2 CTNX Output Valid after CLKOUT Rising Edge (Output
Delay)
—
22.48
ns
2
tCANSU
CC2 CNRX Input Valid to CLKOUT Rising Edge (Setup
Time)
—
12.46
ns
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
82
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
1
FlexCAN timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = -40 to 105 °C,
and CL = 50 pF with SRC = 0b00.
2
Parameter values guaranteed by design.
3.16.7
Deserial Serial Peripheral Interface (DSPI)
Table 42. DSPI Timing1
Num
1
2
4
5
6
7
CC2
tCSC
2
CC
2
SCK Cycle TIme3,4
5
PCS to SCK Delay
6
Max
Unit
60
—
ns
-
—
ns
CC
After SCK Delay
20
—
ns
4
tSDC
CC2
SCK Duty Cycle
tSCK/2
–2ns
tSCK/2
ns
+ 2ns
5
tA
CC2
Slave Access Time
(PCSx active to SOUT driven)
—
25
ns
6
tDIS
CC2
Slave SOUT Disable Time
(PCSx inactive to SOUT High-Z or invalid)
—
25
ns
7
tSUI
CC2
Data Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
35
5
5
35
—
—
—
—
ns
ns
ns
ns
Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
–4
10
26
–4
—
—
—
—
ns
ns
ns
ns
Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA=0)
Master (MTFE = 1, CPHA=1)
—
—
—
—
15
35
30
15
ns
ns
ns
ns
Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
–15
5.5
0
–15
—
—
—
—
ns
ns
ns
ns
10
3
tSCK
Min
tASC
9
1
Characteristic
3
8
2
Symbol
tHI
tSUO
tHO
CC2
CC2
CC2
DSPI timing specified at VDDE_x = 3.0 V to 5.5V, TA = -40 to 105 °C, and CL = 50 pF with SRC = 0b11.
Parameter values guaranteed by design.
The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate.
The actual minimum SCK Cycle Time is limited by pad performance.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK], program PSSCK=2 &
CSSCK = 2
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
This delay value is corresponding to SMPL_PT=00b which is bit field 9 and 8 of DSPI_MCR register.
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
83
Electrical Characteristics
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
7
8
First Data
SIN
Last Data
Data
10
SOUT
First Data
9
Data
Last Data
Figure 31. DSPI Classic SPI Timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
8
SCK Output
(CPOL=1)
7
SIN
Data
First Data
10
SOUT
First Data
Last Data
9
Data
Last Data
Figure 32. DSPI Classic SPI Timing — Master, CPHA = 1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
84
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3
2
PCSx
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
First Data
SOUT
7
6
Data
Last Data
Data
Last Data
8
First Data
SIN
9
10
Figure 33. DSPI Classic SPI Timing — Slave, CPHA = 0
PCSx
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
9
5
10
SOUT
First Data
7
SIN
Data
Last Data
Data
Last Data
6
8
First Data
Figure 34. DSPI Classic SPI Timing — Slave, CPHA = 1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
85
Electrical Characteristics
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
7
SIN
8
First Data
Last Data
Data
10
SOUT
9
First Data
Data
Last Data
Figure 35. DSPI Modified Transfer Format Timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
8
7
SIN
First Data
Data
10
SOUT
First Data
Data
Last Data
9
Last Data
Figure 36. DSPI Modified Transfer Format Timing — Master, CPHA = 1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
86
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3
2
PCSx
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
10
9
5
First Data
SOUT
Data
Last Data
8
7
Data
First Data
SIN
6
Last Data
Figure 37. DSPI Modified Transfer Format Timing — Slave, CPHA = 0
PCSx
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
9
5
10
First Data
SOUT
7
SIN
Data
Last Data
Data
Last Data
6
8
First Data
Figure 38. DSPI Modified Transfer Format Timing — Slave, CPHA = 1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
87
Electrical Characteristics
3.16.8
I2C Timing
Table 43. I2C Input Timing Specifications—SCL and SDA
Num
1
2
Symbol
Characteristic
Min. Value
Max. Value
Unit
1
—
CC1 Start condition hold time
2
—
IP-Bus Cycle2
2
—
CC1 Clock low time
8
—
IP-Bus Cycle2
4
—
CC1 Data hold time
0.0
—
ns
6
—
CC1 Clock high time
4
—
IP-Bus Cycle2
7
—
CC1 Data setup time
0.0
—
ns
2
—
IP-Bus Cycle2
2
—
IP-Bus Cycle2
1
Start condition setup time (for repeated start
condition only)
8
—
CC
9
—
CC1 Stop condition setup time
Parameter values guaranteed by design.
Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device
Table 44. I2C Output Timing Specifications—SCL and SDA
Num
Symbol
Characteristic
Min. Value
Max. Value
Unit
11
—
CC2 Start condition hold time
6
—
IP-Bus Cycle3
21
—
CC2 Clock low time
10
—
IP-Bus Cycle2
34
—
CC2 SCL/SDA rise time
—
99.6
ns
41
—
CC2 Data hold time
7
—
IP-Bus Cycle2
51
—
CC2 SCL/SDA fall time
—
99.5
ns
1
6
—
CC2
Clock high time
10
—
IP-Bus Cycle2
71
—
CC2 Data setup time
2
—
IP-Bus Cycle2
81
—
CC2 Start condition setup time (for repeated start
condition only)
20
—
IP-Bus Cycle2
91
—
CC2 Stop condition setup time
10
—
IP-Bus Cycle2
Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output
timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed in IFDR.
2
Parameter values guaranteed by design.
3 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device
4 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
1
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
88
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
5
6
2
SCL
1
4
7
8
3
9
SDA
Figure 39. I2C Input/Output Timing
3.16.9
3.17
Mechanical Outline Drawings
144 LQFP
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
89
Electrical Characteristics
Figure 40. LQFP144 Mechanical Drawing (Part 1 of 3)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
90
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Figure 41. LQFP144 Mechanical Drawing (Part 2 of 3)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
91
Electrical Characteristics
Figure 42. LQFP144 Mechanical Drawing (Part 3 of 3)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
92
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.18
176 LQFP
Figure 43. LQFP176 Mechanical Drawing (Part 1 of 3)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
93
Electrical Characteristics
Figure 44. LQFP176 Mechanical Drawing (Part 2 of 3)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
94
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Figure 45. LQFP176 Mechanical Drawing (Part 3 of 3)
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
95
Ordering Information
4
Ordering Information
Table 45 shows the orderable part numbers for the MPC5606S series.
Table 45. Orderable Part Number Summary
Flash/SRAM
Package
Speed
(MHz)
MPC5602SEMLQ 256 KB/24 KB
144 LQFP
64
MPC5604SEMLQ 512 KB/48 KB
144 LQFP
64
MPC5604SEMLQ 512 KB/48 KB
Part Number
MPC5606SEMLQ
MPC5606SEMLU
1
144 LQFP
64
1
144 LQFP
64
1
176 LQFP
64
1 MB/48 KB
1 MB/48 KB
Device also includes 160 KB of graphics SRAM.
Figure 46. Commercial product code structure
Example code:
M
PC
56
0
4
S
E
M
LL
R
Qualification Status
PowerPC Core
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Optional fields
Temperature spec.
Package Code
R = Tape & Reel (blank if Tray)
1
Qualification Status
Flash Size (z0 core)
Temperature spec.
M = MC status
S = Auto qualified
P = PC status
2 = 256 KB
4 = 512 KB
6 = 1024 KB
C = –40° C to 85°C
V = –40° C to 105°C
M = –40° C to 125°C
Automotive Platform
Product
Package Code
56 = PPC in 90nm
57 = PPC in 65nm
B = Body
C = Gateway
LQ = 144 LQFP
LU = 176 LQFP
MG = 208 MAPBGA1
208 MAPBGA available only as development package for Nexus2+
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
96
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Ordering Information
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
97
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Document Number: MPC5606S
Rev. 1
10/2008
Preliminary—Subject to Change Without Notice
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