Fairchild MM74HC540MTC Inverting octal 3-state buffer octal 3-state buffer Datasheet

Revised February 1999
MM74HC540 • MM74HC541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate CMOS technology. They possess high drive current outputs which enable high speed
operation even when driving large bus capacitances.
These circuits achieve speeds comparable to low power
Schottky devices, while retaining the advantage of CMOS
circuitry, i.e., high noise immunity, and low power consumption. Both devices have a fanout of 15 LS-TTL equivalent
inputs.
The MM74HC540 is an inverting buffer and the
MM74HC541 is a non-inverting buffer. The 3-STATE control gate operates as a two-input NOR such that if either G1
or G2 are HIGH, all eight outputs are in the high-impedance state.
In order to enhance PC board layout, the MM74HC540 and
MM74HC541 offers a pinout having inputs and outputs on
opposite sides of the package. All inputs are protected from
damage due to static discharge by diodes to VCC and
ground.
Features
■ Typical propagation delay: 12 ns
■ 3-STATE outputs for connection to system buses
■ Wide power supply range: 2–6V
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Output current: 6 mA
Ordering Code:
Order Number
Package Number
MM74HC540WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC540SJ
MM74HC540MTC
MTC20
Package Description
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC540N
N20A
MM74HC541WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC541SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC541MTC
MM74HC541N
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HC540
© 1999 Fairchild Semiconductor Corporation
Top View
MM74HC541
DS005341.prf
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MM74HC540 • MM74HC541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
September 1983
MM74HC540 • MM74HC541
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
(Note 2)
−0.5 to +7.0V
Supply Voltage (VCC)
DC Input Voltage (VIN)
−1.5 to VCC +1.5V
DC Output Voltage (VOUT)
−0.5 to VCC +0.5V
Clamp Diode Current (ICD)
±20 mA
DC Output Current, per pin (IOUT)
±35 mA
Supply Voltage (VCC)
(VIN, VOUT)
Operating Temperature Range (TA)
Storage Temperature Range (TSTG)
−65°C to +150°C
(Note 3)
600 mW
S.O. Package only
500 mW
VCC
V
+85
°C
1000
ns
VCC = 4.5V
500
ns
VCC = 6.0V
400
ns
Note 2: Unless otherwise specified all voltages are referenced to ground.
(Soldering 10 seconds)
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
260°C
DC Electrical Characteristics
(Note 4)
Conditions
VCC
TA = 25°C
Typ
TA = −40 to 85°C TA = −55 to 125°C
Guaranteed Limits
Units
Minimum HIGH Level
2.0V
1.5
1.5
1.5
V
Input Voltage
4.5V
3.15
3.15
3.15
V
6.0V
4.2
4.2
4.2
V
Maximum LOW Level
2.0V
0.5
0.5
0.5
V
4.5V
1.35
1.35
1.35
V
6.0V
1.8
1.8
1.8
V
Input Voltage
VOH
0
−40
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Lead Temperature (TL)
VIL
V
(tr, tf) VCC = 2.0V
Power Dissipation (PD)
VIH
Units
6
Input Rise or Fall Times
±70 mA
per pin (ICC)
Parameter
Max
2
DC Input or Output Voltage
DC VCC or GND Current,
Symbol
Min
Minimum HIGH Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
2.0
1.9
1.9
1.9
V
4.5V
4.5
4.4
4.4
4.4
V
6.0V
6.0
5.9
5.9
5.9
V
|IOUT| ≤ 6.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|IOUT| ≤ 7.8 mA
6.0V
5.7
5.48
5.34
5.2
V
VIN = VIH or VIL
VOL
Maximum LOW Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
0
0.1
0.1
0.1
V
4.5V
0
0.1
0.1
0.1
V
6.0V
0
0.1
0.1
0.1
V
|IOUT| ≤ 6.0 mA
4.5V
0.2
0.26
0.33
0.4
V
|IOUT| ≤ 7.8 mA
6.0V
0.2
0.26
0.33
0.4
V
VIN = VCC or GND
6.0V
±0.1
±1.0
±1.0
µA
Maximum 3-STATE
VIN = VIH or VIL, G = VIH
6.0V
±0.5
±5
±10
µA
Output Leakage
VOUT = VCC or GND
6.0V
8.0
80
160
µA
VIN = VIH or VIL
IIN
Maximum Input
Current
IOZ
Current
ICC
Maximum Quiescent
VIN = VCC or GND
Supply Current
IOUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2
MM74HC540 • MM74HC541
AC Electrical Characteristics
VCC = 5V, TA = 25°C, tr = tf = 6 ns
Symbol
tPHL, tPLH
Parameter
Conditions
Guaranteed
Typ
Limit
Units
CL = 45 pF
12
18
ns
CL = 45 pF
14
20
ns
Maximum Output Enable
RL = 1 kΩ
17
28
ns
Time
CL = 45 pF
15
25
ns
Maximum Propagation
Delay (540)
tPHL, tPLH
Maximum Propagation
Delay (541)
tPZH, tPZL
tPHZ, tPLZ
Maximum Output Disable
RL = 1 kΩ
Time
CL = 5 pF
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TA = 25°C
Typ
TA = −40 to 85°C TA = −55 to 125°C
Guaranteed Limits
Units
tPHL, tPLH Maximum Propagation
CL = 50 pF
2.0V
55
100
126
149
ns
Delay (540)
CL = 150 pF
2.0V
83
150
190
224
ns
CL = 50 pF
4.5V
12
20
25
30
ns
CL = 150 pF
4.5V
22
30
38
45
ns
CL = 50 pF
6.0V
11
17
21
25
ns
CL = 150 pF
6.0V
18
26
32
38
ns
tPHL, tPLH Maximum Propagation
CL = 50 pF
2.0V
58
115
145
171
ns
Delay (541)
CL = 150 pF
2.0V
83
165
208
246
ns
CL = 50 pF
4.5V
14
23
29
34
ns
CL = 150 pF
4.5V
17
33
42
49
ns
CL = 50 pF
6.0V
11
20
25
29
ns
CL = 150 pF
6.0V
14
28
35
42
ns
ns
tPZH, tPZL Maximum Output Enable
Time
tPHZ, tPLZ Maximum Output Disable
Time
tTHL, tTLH Maximum Output Rise
RL = 1 kΩ
CL = 50 pF
2.0V
75
150
189
224
CL = 150 pF
2.0V
100
200
252
298
ns
CL = 50 pF
4.5V
15
30
38
45
ns
CL = 150 pF
4.5V
30
40
50
60
ns
CL = 50 pF
6.0V
13
26
32
38
ns
CL = 150 pF
6.0V
17
34
43
51
ns
RL = 1 kΩ
2.0V
75
150
189
224
ns
CL = 50 pF
CL = 50 pF
and Fall Time
4.5V
15
30
38
45
ns
6.0V
13
26
32
38
ns
2.0V
25
60
75
90
ns
4.5V
7
12
15
18
ns
6
10
13
15
6.0V
CPD
CIN
Power Dissipation
G = VIH
10
Capacitance (Note 5)
G = VIL
50
Maximum Input
ns
pF
pF
5
10
10
10
pF
15
20
20
20
pF
Capacitance
COUT
Maximum Output Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
3
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MM74HC540 • MM74HC541
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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4
MM74HC540 • MM74HC541
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
5
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MM74HC540 • MM74HC541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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