HM5216165 Series EO 16 M LVTTL Interface SDRAM (512-kword × 16-bit × 2-bank) 100 MHz/83 MHz L E0167H10 (Ver. 1.0) (Previous ADE-203-280C (Z)) Jun. 12, 2001 Description All inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance. t uc • • • • 3.3 V Power supply Clock frequency: 100 MHz/83 MHz LVTTL interface Single pulsed RAS 2 Banks can operates simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8/full page 2 variations of burst sequence Sequential (BL = 1/2/4/8/full page) Interleave (BL = 1/2/4/8) Programmable CAS latency: 1/2/3 Byte control by DQMU and DQML Refresh cycles: 4096 refresh cycles/64 ms 2 variations of refresh Auto refresh Self refresh od • • • • • • • • Pr Features Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. HM5216165 Series Ordering Information Type No. EO HM5216165TT-10H HM5216165TT-12 Frequency Package 100 MHz 83 MHz 400-mil 50-pin plastic TSOP II (TTP-50D) Pin Arrangement HM5216165TT Series 1 50 VSS I/O0 2 49 I/O15 I/O1 3 48 I/O14 VSSQ 4 47 VSSQ I/O2 5 46 I/O13 I/O3 6 45 I/O12 VCCQ 7 44 VCCQ I/O4 8 43 I/O11 I/O5 9 42 I/O10 VSSQ 10 41 VSSQ I/O6 11 40 I/O9 I/O7 12 39 I/O8 38 L VCC 13 14 WE 15 CAS 16 RAS 17 CS 18 A11 19 A10 20 A0 21 A1 A2 NC 36 DQMU 35 CLK 34 CKE 33 NC 32 A9 31 A8 30 A7 22 29 A6 23 28 A5 A3 24 27 A4 VCC 25 26 VSS Data Sheet E0167H10 t uc 37 (Top view) 2 VCCQ od Pr VCCQ DQML HM5216165 Series Pin Description Pin name Function EO A0 to A11 Address input Row address A0 to A10 Column address A0 to A7 Bank select address A11 I/O0 to I/O15 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe command DQMU DQML CLK CKE VSS VCCQ VSS Q NC Write enable command Upper byte input/output mask Lower byte input/output mask Clock input Clock enable Pr VCC L WE Power for internal circuit Ground for internal circuit Power for I/O pin Ground for I/O pin No connection t uc od Data Sheet E0167H10 3 HM5216165 Series Block Diagram EO A0 – A11 A0 – A7 Column address buffer L Sense amplifier & I/O bus Memory array Column decoder Bank 0 2048 row X 256 column X 16 bit Bank 1 2048 row X 256 column X 16 bit od Control logic & timing generator DQMU DQML WE CKE CLK Data Sheet E0167H10 4 t uc I/O0 – I/O15 CAS Output buffer Memory array CS Sense amplifier & I/O bus Row decoder Pr Column decoder Row decoder Input buffer Refresh counter Row address buffer RAS Column address counter A0 – A11 HM5216165 Series Pin Functions EO CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. L A0 to A10 (input pins): Row address (AX0 to AX10) is determined by A0 to A10 level at the bank active command cycle CLK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A11 (BS) is precharged. Pr A11 (input pin): A11 is a bank select signal (BS). The memory array of the HM5216165 is divided into bank 0 and bank 1, both which contain 2048 row × 256 column × 16 bits. If A11 is Low, bank 0 is selected, and if A11 is High, bank 1 is selected. CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock suspend modes. od DQMU/DQML (input pins): DQMU controls upper byte and DQML controls lower byte input/output buffers. Read operation: If DQMU/DQML is High, the output buffer becomes High-Z. If the DQMU/DQML is Low, the output buffer becomes Low-Z. Write operation: If DQMU/DQML is High, the previous data is held (the new data is not written). If DQMU/DQML is Low, the data is written. t uc I/O0 to I/O15 (I/O pins): Data is input to and output from these pins. These pins are the same as those of a conventional DRAM. VCC and VCC Q (power supply pins): 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer). VSS and V SS Q (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.) Data Sheet E0167H10 5 HM5216165 Series Command Operation EO Command Truth Table The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. Symbol CKE n-1 n CS RAS CAS WE A0 A11 A10 to A9 Ignore command DESL H × H × × × × × × No operation NOP H × L H H H × × × Burst stop in full page BST H × L H H L × × × Column address and read command READ H × L H L H V L V Read with auto-precharge READ A H × L H L H V H V Column address and write command WRIT H × L H L L V L V Write with auto-precharge WRIT A H × L H L L V H V Row address strobe and bank act. ACTV H × L L H H V V V Precharge select bank PRE H × L L H L V L × PALL H × L L H L × H × REF/SELF H V L L L H × × × MRS × L L L L V V V L Function Refresh Mode register set Pr Precharge all bank H Note: H: VIH. L: VIL. ×: V IH or VIL. V: Valid address input od Ignore command [DESL]: When this command is set (CS is High), the synchronous DRAM ignore command input at the clock. However, the internal status is held. No operation [NOP]: This command is not an execution command. However, the internal operations continue. t uc Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page (256)), and is illegal otherwise. Full page burst continues until this command is input. When data input/output is completed for a full-page of data (256), it automatically returns to the start address, and input/output is performed repeatedly. Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0 to AY7) and the bank select address (BS). After the read operation, the output buffer becomes High-Z. Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4, or 8. When the burst length is full-page (256), this command is illegal. Data Sheet E0167H10 6 HM5216165 Series EO Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY7) and the bank select address (A11) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY7) and the bank select address (A11). Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4, or 8, or after a single write operation. When the burst length is full-page (256), this command is illegal. Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A11 (BS) and determines the row address (AX0 to AX10). When A11 is Low, bank 0 is activated. When A11 is High, bank 1 is activated. L Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A11. If A11 is Low, bank 0 is selected. If A11 is High, bank 1 is selected. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Pr Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to A11) at the mode register set cycle. For details, refer to the mode register configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. od DQM Truth Table Function Symbol CKE n-1 n DQMU DQML Upper byte write enable/output enable ENBU H × L × Lower byte write enable/output enable ENBL H × × L Upper byte write inhibit/output disable MASKU H × H × Lower byte write inhibit/output disable MASKL H × × H t uc Note: H: VIH. L: VIL. ×: V IH or VIL. I DOD is needed. The HM5216165 series can mask input/output data by means of DQMU and DQML. DQMU masks the upper byte and DQML masks the lower byte. During reading, the output buffer is set to Low-Z by setting DQMU/DQML to Low, enabling data output. On the other hand, when DQMU/DQML is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQMU/DQML to Low. When DQMU/DQML is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQMU/DQML. For details, refer to the DQM control section of the HM5216165 operating instructions. Data Sheet E0167H10 7 HM5216165 Series CKE Truth Table Function CKE n-1 n CS RAS CAS WE Address Active Clock suspend mode entry H L H × × × × Any Clock suspend L L × × × × × Clock suspend Clock suspend mode exit L H × × × × × Idle Auto refresh command H H L L L H × Idle Self refresh entry H L L L L H × Idle Power down entry H L L H H H × H L H × × × × L H L H H H × L H H × × × × L H L H H H × L H H × × × × EO Current state Power down L Self-refresh Self refresh exit Power down exit REF SELF SELFX Note: H: VIH. L: VIL. ×: V IH or VIL. Pr Clock suspend mode entry: The synchronous DRAM enters clock suspend mode from active mode by setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as shown below. od ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. READ suspend and READ A suspend: The data being output is held (and continues to be output). WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During clock suspend mode, keep the CKE to Low. t uc Clock suspend mode exit: The synchronous DRAM exits from clock suspend mode by setting CKE to High during the clock suspend state. IDLE: In this state, all banks are not selected, and completed precharge operation. Auto refresh command [REF]: When this command is input from the IDLE state, the synchronous DRAM starts auto refresh operation. (The auto refresh is the same as the CBR refresh of conventional DRAMs.) During the auto refresh operation, refresh address and bank select address are generated inside the synchronous DRAM. For every auto refresh cycle, the internal address counter is updated. Accordingly, 4096 times are required to refresh the entire memory. Before executing the auto refresh command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed after auto refresh, no precharge command is required after auto refresh. Data Sheet E0167H10 8 HM5216165 Series Self refresh entry [SELF]: When this command is input during the IDLE state, the synchronous DRAM starts self refresh operation. After the execution of this command, self refresh continues while CKE is Low. Since self refresh is performed internally and automatically, external refresh operations are unnecessary. EO Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit. Self refresh exit: When this command is executed during self refresh mode, the synchronous DRAM can exit from self refresh mode. After exiting from self refresh mode, the synchronous DRAM enters the IDLE state. L Power down exit: When this command is executed at the power down mode, the synchronous DRAM can exit from power down mode. After exiting from power down mode, the synchronous DRAM enters the IDLE state. Function Truth Table Pr The following table shows the operations that are performed when each command is issued in each mode of the synchronous DRAM. Current state CS RAS CAS WE Address Command Operation Precharge H × L H L H L H L × × DESL Enter IDLE after t RP H H × NOP Enter IDLE after t RP H L × BST NOP L H BA, CA, A10 READ/READ A ILLEGAL H L L BA, CA, A10 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV ILLEGAL L L H L BA, A10 PRE, PALL NOP L L L H × REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H × × × × DESL NOP L H H H × L H H L × BST L H L H BA, CA, A10 READ/READ A ILLEGAL L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV Bank and row active L L H L BA, A10 PRE, PALL L L L H × REF, SELF L L L L MODE MRS NOP t uc od Idle × NOP NOP NOP Refresh Mode register set Data Sheet E0167H10 9 HM5216165 Series CS RAS CAS WE Address Command Operation Row active H × × × × DESL NOP L H H H × NOP NOP L H H L × BST NOP L H L H BA, CA, A10 READ/READ A Begin read L H L L BA, CA, A10 WRIT/WRIT A Begin write L L H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 L L H L BA, A10 PRE, PALL Precharge L L L H × REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H × × × × DESL Continue burst to end L H H H × NOP Continue burst to end L H H L × BST Burst stop on full page L H L H BA, CA, A10 READ/READ A Continue burst read to CAS latency and new read L H L L L L L L L L H EO Current state L Read Pr L BA, CA, A10 WRIT/WRIT A Term burst read/start write H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 H L BA, A10 PRE, PALL Term burst read and Precharge L H × REF, SELF ILLEGAL L L MODE MRS ILLEGAL × × × × L H H H × L H H L × L H L H L H L L L L od Read with auto-precharge L Continue burst to end and precharge NOP Continue burst to end and precharge BST ILLEGAL BA, CA, A10 READ/READ A ILLEGAL L BA, CA, A10 WRIT/WRIT A ILLEGAL H H BA, RA ACTV L H L BA, A10 PRE, PALL L L L H × REF, SELF L L L L MODE MRS Data Sheet E0167H10 10 t uc DESL Other bank active ILLEGAL on same bank*3 ILLEGAL ILLEGAL ILLEGAL HM5216165 Series CS RAS CAS WE Address Command Operation Write H × × × × DESL Continue burst to end L H H H × NOP Continue burst to end L H H L × BST Burst stop on full page L H L H BA, CA, A10 READ/READ A Term burst and new read L H L L BA, CA, A10 WRIT/WRIT A Term burst and new write L L H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 L L H L BA, A10 PRE, PALL Term burst write and precharge*2 L L L H × REF, SELF ILLEGAL EO Current state L Write with auto-precharge L L L MODE MRS ILLEGAL H × × × × DESL Continue burst to end and precharge L H H H × NOP Continue burst to end and precharge L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READ A ILLEGAL L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV Other bank active ILLEGAL on same bank*3 L L H L BA, A10 PRE, PALL ILLEGAL L L L H × REF, SELF ILLEGAL L L L L MODE MRS ILLEGAL H × × × × DESL Enter IDLE after t RC L H H H × NOP Enter IDLE after t RC L H H L × BST Enter IDLE after t RC L H L H BA, CA, A10 READ/READ A ILLEGAL L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL L L H H BA, RA ACTV ILLEGAL L L H L BA, A10 PRE, PALL L L L H × REF, SELF L L L L MODE MRS t uc od Pr Refresh (auto refresh) L ILLEGAL ILLEGAL ILLEGAL Notes: 1. H: VIH. L: VIL. ×: V IH or VIL. The other combinations are inhibit. 2. An interval of t DPL is required between the final valid data input and the precharge command. 3. If tRRD is not satisfied, this operation is illegal. Data Sheet E0167H10 11 HM5216165 Series From [PRECHARGE] EO To [DESL], [NOR] or [BST]: When these commands are executed, the synchronous DRAM enters the IDLE state after tRP has elapsed from the completion of precharge. From [IDLE] To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto refresh or self refresh). L To [MRS]: The synchronous DRAM enters the mode register set cycle. From [ROW ACTIVE] To [DESL], [NOP] or [BST]: These commands result in no operation. Pr To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. From [READ] od To [PRE], [PALL]: These commands set the synchronous DRAM to precharge mode. (However, an interval of t RAS is required.) To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst. t uc To [READ], [READ A]: Data output by the previous read command continues to be output. A f t e r CAS latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters precharge mode. Data Sheet E0167H10 12 HM5216165 Series From [READ with AUTO PRECHARGE] EO To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the synchronous DRAM then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. From [WRITE] To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. L To [BST]: This command stops a full-page burst. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. Pr To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM then enters precharge mode. From [WRITE with AUTO-PRECHARGE] od To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the synchronous DRAM enters precharge mode. To [ACTV]: This command makes the other bank active. (However, an interval of tRC is required.) Attempting to make the currently active bank active results in an illegal command. From [REFRESH] t uc To [DESL], [NOP], [BST]: After an auto-refresh cycle (after tRC), the synchronous DRAM automatically enters the IDLE state. Data Sheet E0167H10 13 HM5216165 Series Simplified State Diagram EO SELF REFRESH SR ENTRY SR EXIT MRS MODE REGISTER SET REFRESH IDLE *1 AUTO REFRESH L CKE CKE_ IDLE POWER DOWN ACTIVE ACTIVE CLOCK SUSPEND CKE_ Pr CKE ROW ACTIVE BST (on full page) WRITE Write WRITE SUSPEND CKE_ WRITE READ WRITE WITH AP READ READ CKE CKE CKE_ READA CKE READA SUSPEND PRECHARGE PRECHARGE PRECHARGE Automatic transition after completion of command. Transition resulting from command input. t uc POWER ON READ SUSPEND READ WITH AP PRECHARGE WRITEA PRECHARGE POWER APPLIED WRITE WITH AP Read CKE_ od READ WITH AP CKE_ WRITEA SUSPEND READ WITH AP WRITE CKE WRITE WITH AP BST (on full page) Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. Data Sheet E0167H10 14 HM5216165 Series Mode Register Configuration EO The mode register is set by the input to the address pins (A0 to A11) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A11, A10, A9, A8: (OPCODE): The synchronous DRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. Burst read and BURST WRITE: Burst write is performed for the specified burst length starting from the column address specified in the write cycle. Burst read and SINGLE WRITE: Data is only written to the column address specified during the write cycle, regardless of the burst length. L A7: Keep this bit Low at the mode register set cycle. A6, A5, A4: (LMODE): These pins specify the CAS latency. A3: (BT): A burst type is specified. When full-page burst is performed, only “sequential” can be selected. Pr A2, A1, A0: (BL): These pins specify the burst length. A11 A10 A9 A8 OPCODE A7 A6 0 A5 A4 LMODE A3 BT 0 A1 A0 BL od A6 A5 A4 CAS Latency 0 A2 A3 Burst Type 0 R 0 Sequential 1 A2 A1 A0 0 0 1 1 0 1 0 2 0 1 1 3 0 1 X X R 0 Interleave 0 0 1 1 0 0 1 2 2 1 0 4 4 1 1 8 8 A8 0 0 0 0 X X 0 1 X X 1 0 X X 1 1 Write mode Burst read and burst write R Burst read and SINGLE WRITE 0 0 R R t uc A9 BT=1 0 1 A11 A10 Burst Length BT=0 1 0 1 R R 1 1 0 R R 1 1 1 F.P. R F.P. =Full Page (256) R is Reserved(inhibit) R X: 0 or 1 Data Sheet E0167H10 15 HM5216165 Series Burst Sequence EO Burst length = 4 Burst length = 2 Starting Ad. Addressing(decimal) A0 Sequence Interleave Starting Ad. Addressing(decimal) A1 0 0, 1, 0, 1, 0 1 1, 0, 1, 0, 0 A0 Sequence Interleave 0 0, 1, 2, 3, 0, 1, 2, 3, 1 1, 2, 3, 0, 1, 0, 3, 2, 1 0 2, 3, 0, 1, 2, 3, 0, 1, 1 1 3, 0, 1, 2, 3, 2, 1, 0, Burst length = 8 Addressing(decimal) Starting Ad. L A1 0 0 A0 Sequence 0 0, 1, 2, 3, 4, 5, 6, 7, Interleave 0, 1, 2, 3, 4, 5, 6, 7, 0 0 1 1, 2, 3, 4, 5, 6, 7, 0, 1, 0, 3, 2, 5, 4, 7, 6, 0 1 0 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 6, 7, 4, 5, 0 1 1 3, 4, 5, 6, 7, 0, 1, 2, 3, 2, 1, 0, 7, 6, 5, 4, 1 0 0 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 1 0 1 5, 6, 7, 0, 1, 2, 3, 4, 5, 4, 7, 6, 1, 0, 3, 2, 1 1 0 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 4, 5, 2, 3, 0, 1, 1 1 1 7, 0, 1, 2, 3, 4, 5, 6, 7, 6, 5, 4, 3, 2, 1, 0, t uc od Pr A2 Data Sheet E0167H10 16 HM5216165 Series Operation of HM5216165 Series EO Read/Write Operations Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Either bank 0 or bank 1 is activated according to the status of the A11 pin, and the row address (AX0 to AX10) is activated by the A0 to A10 pins at the bank active command cycle. An interval of tRCD is required between the bank active command input and the following read/write command input. L Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CAS Latency-1) cycle after read command set. HM5216165 series can perform a burst read operation. The burst length can be set to 1, 2, 4, 8 or full-page (256). The start address for a burst read is specified by the column address (AY0 to AY7) and the bank select address (A11) at the read command set cycle. In a read operation, data output starts after the number of cycles specified by the CAS Latency. The CAS Latency can be set to 1, 2, 3. When the burst length is 1, 2, 4, or 8, the Dout buffer automatically becomes High-Z at the next cycle after the successive burst-length data has been output. When the burst length is full-page (256), data is repeatedly output until the burst stop command is input. The CAS latency and burst length must be specified at the mode register. Pr CAS Latency CLK t RCD Address ACTV Row CL = 1 Dout CL = 2 Column out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 t uc CL = 3 READ od Command CL: CAS latency Burst length = 4 Data Sheet E0167H10 17 HM5216165 Series Burst Length EO CLK t RCD Command ACTV READ Address Row Column out 0 BL = 1 out 0 out 1 BL = 2 Dout out 0 out 1 out 2 out 3 BL = 4 L out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 BL = 8 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8 out 255 out 0 out 1 BL = full page (256) BL: Burst length CAS latency = 2 Pr Write operation: Burst write or single write mode is selected by the OPCODE (A11, A10, A9, A8) of the mode register. Burst write CLK t RCD Command ACTV WRIT Address Row Column BL = 1 in 0 in 0 in 1 in 0 in 1 in 2 in 3 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 BL = 2 Din BL = 4 BL = 8 BL = full page (256) in 8 in 255 in 0 in 1 CAS latency = 1, 2, 3 Data Sheet E0167H10 18 t uc od A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column address (AY0 to AY7) and the bank select address (A11) at the write command set cycle. HM5216165 Series Single write EO A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is only written to the column address (AY0 to AY7) and the bank select address (A11) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0). CLK Command Active Row L Address t RCD Din Write Column in 0 CAS latency = 1, 2, 3 Burst length = 1, 2, 4, 8, full page t uc od Pr Data Sheet E0167H10 19 HM5216165 Series Auto Precharge EO Read with auto precharge: In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by l APR is required before execution of the next command. CAS latency Precharge start cycle 3 2 cycle before the final data is output 2 1 cycle before the final data is output 1 same cycle as the final data is output L CLK CL = 1 Command READ ACTV Pr out0 Dout out1 out2 out3 lAPR CL = 2 Command READ out0 Dout Dout READ out2 out3 lAPR od CL = 3 Command out1 ACTV ACTV out0 out1 out2 out3 lAPR Note: Internal auto-precharge starts at the timing indicated by " ". At CLK = 50 MHz ( lAPR changes depending on the operating frequency. ) t uc Data Sheet E0167H10 20 HM5216165 Series EO Write with auto precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval of lAPW is required between the final valid data input and input of the next command. Burst Write (Burst Length = 4) CLK Command ACTV L I/O (input) WRIT in0 in1 in2 in3 lAPW Single Write Command I/O (input) WRIT in Pr CLK ACTV Full-page Burst Stop od lAPW t uc Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. The timing from command input to the last data changes depending on the CAS latency setting. In addition, the BST command is valid only during full-page burst mode, and is invalid with burst lengths 1, 2, 4 and 8. CAS latency BST to valid data BST to high impedance 1 0 1 2 1 2 3 2 3 Data Sheet E0167H10 21 HM5216165 Series CAS Latency = 1, Burst Length = full page EO CLK BST Command I/O (output) out out out out out l BSR l BSH 0 cycle 1 cycle L CAS Latency = 2, Burst Length = full page CLK I/O (output) Pr BST Command out out out out out out l BSH = 2 cycle CAS Latency = 3, Burst Length = full page CLK BST Command out out out out out t uc I/O (output) od l BSR = 1 cycle out l BSR = 2 cycle Data Sheet E0167H10 22 out l BSH = 3 cycle HM5216165 Series EO Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same cycle as the BST command and in subsequent cycles. In addition, the BST command is only valid during full-page burst mode, and is invalid with burst lengths of 1, 2, 4 and 8. And an interval of tDPL is required between the BST command and the next precharge command. Burst Length = full page CLK I/O (input) L Command in BST PRE/PALL in t DPL t uc od Pr I BSW = 0 cycle Data Sheet E0167H10 23 HM5216165 Series Command Intervals EO Read command to Read command interval: Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cycle. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (same ROW address in same bank) Command Address (A0-A10) L CLK ACTV Row Dout READ Column A Column B Pr BS (A11) READ out A0 out B0 out B1 out B2 out B3 Bank0 Active CAS Latency = 3 Burst Length = 4 Bank0 Column =A Column =B Column =A Column =B Dout Read Read Dout od Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (different bank) t uc CLK Command ACTV ACTV READ READ Address (A0-A10) Row 0 Row 1 Column A Column B BS (A11) Dout out A0 out B0 out B1 out B2 out B3 Bank0 Active Bank1 Bank0 Bank1 Active Read Read Bank0 Bank1 Dout Dout Data Sheet E0167H10 24 CAS Latency = 3 Burst Length = 4 HM5216165 Series Write command to Write command interval: EO Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 cycle. In the case of burst writes, the second write command has priority. WRITE to WRITE Command Interval (same ROW address in same bank) CLK Command BS (A11) Din WRIT WRIT L Address (A0-A10) ACTV Row Column A Column B in A0 in B1 in B3 in B2 Burst Write Mode Burst Length = 4 Bank0 Column =A Column =B Write Write Pr Bank0 Active in B0 Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. od Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. In the case of burst write, the second write command has priority. WRITE to WRITE Command Interval (different bank) CLK Address (A0-A10) ACTV Row 0 ACTV WRIT Row 1 WRIT Column A Column B BS (A11) Din in A0 Bank0 Active in B0 in B1 in B2 in B3 Bank1 Bank0 Bank1 Active Write Write t uc Command Burst Write Mode Burst Length = 4 Data Sheet E0167H10 25 HM5216165 Series Read command to Write command interval: EO Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 cycle. However, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. READ to WRITE Command Interval (1) CLK Command READ WRIT L CL=1 DQMU /DQML CL=2 CL=3 Pr in B0 Din in B1 in B2 in B3 Burst Length = 4 Burst write High-Z Dout READ to WRITE Command Interval (2) Command DQMU /DQML CL=1 Dout CL=2 READ od CLK WRIT 2 clock High-Z High-Z t uc High-Z CL=3 Din Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. Data Sheet E0167H10 26 HM5216165 Series Write command to Read command interval: EO Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 cycle. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. WRITE to READ Command Interval (1) CLK Command Din READ L DQMU/DQML WRIT in A0 Dout out B1 out B0 out B2 out B3 Pr Column=A Write Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank0 CAS Latency Column=B Read Column=B Dout WRITE to READ Command Interval (2) Command WRIT READ DQMU/DQML Din in A0 in A1 out B0 Column=A Write CAS Latency Column=B Read Column=B Dout out B1 out B2 out B3 t uc Dout od CLK Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank0 Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-active command. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed (as in the case of the same bank and the same address). Data Sheet E0167H10 27 HM5216165 Series EO Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by lHZP, there is a possibility that burst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the cycles defined by lEP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (same bank): To output all data CAS Latency = 1, Burst Length = 4 CLK Dout L Command READ out A0 PRE/PALL out A1 out A2 out A3 l EP = 0 cycle CL=1 Pr CAS Latency = 2, Burst Length = 4 CLK Command READ PRE/PALL out A0 CL=2 out A1 out A2 CLK PRE/PALL out A0 CL=3 Data Sheet E0167H10 out A1 t uc READ Dout 28 out A3 l EP = -1 cycle CAS Latency = 3, Burst Length = 4 Command od Dout out A2 l EP = -2 cycle out A3 HM5216165 Series READ to PRECHARGE Command Interval (same bank): To stop output data EO CAS Latency = 1, Burst Length = 1, 2, 4, 8 CLK Command READ PRE/PALL High-Z Dout out A0 l HZP =1 L CAS Latency = 2, Burst Length = 1, 2, 4, 8 CLK Command READ PRE/PALL Pr High-Z Dout out A0 l HZP =2 CAS Latency = 3, Burst Length = 1, 2, 4, 8 Command READ PRE/PALL od CLK High-Z Dout out A0 l HZP =3 t uc Data Sheet E0167H10 29 HM5216165 Series Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cycle. EO WRITE to PRECHARGE Command Interval (same bank): However, if the burst write operation is unfinished, the input data must be masked by means of DQMU and DQML for assurance of the cycle defined by tDPL. WRITE to PRECHARGE Command Interval (same bank) Burst Length = 4 (To stop write operation) Command L CLK WRIT PRE/PALL DQM t DPL CLK Command WRIT Pr Din PRE/PALL Din in A0 in A1 t DPL Burst Length = 4 (To write all data) CLK Command PRE/PALL WRIT DQM Din in A0 in A1 in A2 in A3 t DPL Data Sheet E0167H10 30 t uc od DQM HM5216165 Series Bank active command interval: Same bank: The interval between the two bank-active commands must be no less than tRC. EO In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. Bank active to bank active for same bank CLK ACTV Command BS (A11) L Address (A0-A10) ACTV ROW ROW t RC Pr Bank 0 Active Bank 0 Active Bank active to bank active for different bank CLK ACTV Address (A0-A10) ROW:0 BS (A11) od Command ACTV ROW:1 Bank 0 Active Bank 1 Active t uc t RRD Data Sheet E0167H10 31 HM5216165 Series Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than tRSA . EO CLK Command MRS ACTV Address (A0-A11) CODE BS & ROW L Mode Register Set t RSA Bank Active t uc od Pr Data Sheet E0167H10 32 HM5216165 Series DQM Control EO The DQMU and DQML mask the lower and upper bytes of the I/O data, respectively. The timing of DQMU/DQML is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQMU/DQML. By setting DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQMU/DQML during reading is 2. CLK L DQMU /DQML I/O (output) High-Z out 0 out 1 out 3 Pr lDOD = 2 Latency Writing: Input data can be masked by DQMU/DQML. By setting DQMU/DQML to Low, data can be written. In addition, when DQMU/DQML is set to High, the corresponding data is not written, and the previous data is held. The latency of DQMU/DQML during writing is 0. ; ;; od CLK DQMU /DQML I/O (input) in 0 in 3 in 1 t uc l DID = 0 Latency Data Sheet E0167H10 33 HM5216165 Series Refresh EO Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the autorefresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4096 cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer becomes HighZ after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. L Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A selfrefresh is terminated by a self-refresh exit command. If you use distributed auto-refresh mode with 15.6 µs interval in normal read/write cycle, auto-refresh should be executed within 15.6 µs immediately after exiting from and before entering into self refresh mode. If you use address refresh or burst auto-refresh mode in normal read/write cycle, 4096 cycles of distributed auto-refresh with 15.6 µs interval should be executed within 64 ms immediately after exiting from and before entering into self refresh mode. Others Pr Power-down mode: The synchronous DRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the synchronous DRAM exits from the power down mode, and command input is enabled from the next cycle. In this mode, internal refresh is not performed. od Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the synchronous DRAM enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the synchronous DRAM terminates clock suspend mode, and command input is enabled from the next cycle. For details, refer to the “CKE Truth Table”. Power-up sequence: During power-up sequence, the DQMU/DQML and the CKE must be set to High. When 200 µs has past after power on, all banks must be precharged using the precharge command. After tRP delay, set 8 or more auto refresh commands. And set the mode register set command to initialize the mode register. t uc Data Sheet E0167H10 34 HM5216165 Series Absolute Maximum Ratings Symbol Value Unit Note Voltage on any pin relative to V SS VT –1.0 to +4.6 V 1 Supply voltage relative to VSS VCC –1.0 to +4.6 V 1 Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C EO Parameter Note: 1. Respect to V SS L Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Supply voltage Input low voltage Min Max Unit Notes VCC, VCCQ 3.0 3.6 V 1 Pr Input high voltage Symbol VSS , VSS Q 0 0 V VIH 2.0 4.6 V 1, 2 VIL –0.3 0.8 V 1, 3 Notes: 1. All voltage referred to VSS 2. VIH (max) = 5.5 V for pulse width ≤ 5 ns 3. VIL (min) = –1.0 V for pulse width ≤ 5 ns t uc od Data Sheet E0167H10 35 HM5216165 Series DC Characteristics (Ta = 0 to 70°C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V) EO Parameter Operating current Standby current (Bank Disable) HM5216165 -10H Symbol I CC1 — Max 130 Min — Max 105 Unit mA Test conditions Notes Burst length = 1 1, 2, 4 t RC = min I CC2 L Active standby current (Bank active) Min -12 I CC3 — 3 — 3 mA CKE = VIL, t CK = min 5 — 2 — 2 mA CKE = VIL CLK = VIL or VIH Fixed 6 — 50 — 41 mA CKE = VIH, NOP command t CK = min 3 — 7 — 7 mA CKE = VIL, t CK = min, 1, 2 I/O = High-Z Pr 51 — 43 mA CKE = VIH, NOP command t CK = min, I/O = High-Z 1, 2, 3 I CC4 — 65 — 55 mA t CK = min, BL = 4 1, 2, 4 I CC4 — 100 — 85 mA (CAS latency = 3) I CC4 — 150 — 125 mA Refresh current I CC5 — 85 — 70 mA t RC = min Self refresh current I CC6 — 2 — 2 mA VIH ≥ VCC – 0.2 VIL ≤ 0.2 V Input leakage current I LI –10 10 –10 10 µA 0 ≤ Vin ≤ VCC Output leakage current I LO –10 10 –10 10 µA 0 ≤ Vout ≤ VCC I/O = disable Output high voltage VOH 2.4 — 2.4 — V I OH = –2 mA Output low voltage VOL — 0.4 — 0.4 V Burst operating current (CAS latency = 1) (CAS latency = 2) 7 t uc od — I OL = 2 mA Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signal transition is once per two CLK cycles. 4. Input signal transition is once per one CLK cycle. 5. After power down mode, CLK operating current. 6. After power down mode, no CLK operating current. 7. After self refresh mode set, self refresh current. Data Sheet E0167H10 36 HM5216165 Series Capacitance (Ta = 25°C, VCC, VCCQ = 3.3 V ± 0.3 V) Symbol Min Max Unit Notes Input capacitance (Address) CI1 2 5 pF 1, 3 Input capacitance (Signals) CI2 2 5 pF 1, 3 Output capacitance (I/O) CO 4 7 pF 1, 2, 3 EO Parameter Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQMU/DQML = VIH to disable Dout. 3. This parameter is sampled and not 100% tested. L AC Characteristics (Ta = 0 to 70°C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V) Parameter (CAS latency = 2) (CAS latency = 3) CLK high pulse width CLK low pulse width Symbol Min -12 Max Min Max Unit Notes ns 1 t CK 30 — 36 — t CK 15 — 18 — t CK 10 — 12 — t CKH 3 — 4 — ns 1 t CKL 3 — 4 — ns 1 ns 1, 2 t AC od Access time from CLK (CAS latency = 1) -10H Pr System clock cycle time (CAS latency = 1) HM5216165 27 — 32 — 9 — 12 — 7.5 — 9 3 — 3 — ns 1, 2 0 — 0 — ns 1, 2, 3 — 13 — 15 ns 1, 4 t HZ — 7 Data-in setup time t DS 2 — Data in hold time t DH 1 — Address setup time t AS 2 — Address hold time t AH 1 — CKE setup time t CES 2 — CKE setup time for power down exit t CESP 2 — CKE hold time t CEH 1 — (CAS latency = 2) t AC (CAS latency = 3) t AC Data-out hold time t OH CLK to Data-out low impedance t LZ CLK to Data-out high impedance (CAS latency = 1) t HZ (CAS latency = 2, 3) t uc — — 9 3 — ns 1 1 — ns 1 3 — ns 1 1 — ns 1 3 — ns 1, 5 3 — ns 1 1 — ns 1 Data Sheet E0167H10 37 HM5216165 Series AC Characteristics (Ta = 0 to 70°C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V) (cont) EO HM5216165 -10H -12 Symbol Min Max Min Max Unit Notes Command (CS, RAS, CAS, WE, DQM) setup time t CS 2 — 3 — ns 1 Command (CS, RAS, CAS, WE, DQM) hold time t CH 1 — 1 — ns 1 Ref/Active to Ref/Active command period t RC 90 — 100 — ns 1 Active to precharge command period t RAS 60 120000 70 120000 ns 1 Active to precharge on full page mode t RASC — 120000 — 120000 ns 1 Active command to column command (same bank) t RCD 30 — 30 — ns 1 Precharge to active command period t RP 30 — 30 — ns 1 Write recovery or data-in to precharge lead t DPL time 15 — 15 — ns 1 Active (a) to Active (b) command period t RRD 20 — 20 — ns 1 Transition time (rise to fall) tT 1 5 1 5 ns t REF — 64 — 64 ms L Parameter Pr Refresh period AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.40 V. Access time is measured at 1.40 V. Load condition is CL = 50 pF with current source. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CKE rising edge except power down exit command. Test Conditions • Input and output timing reference levels: 1.4 V • Input waveform and output load: See following figures 2.8 V 80% Input 20% V SS Output I/O t uc od Notes: 1. 2. 3. 4. 5. 500 Ω +1.4 V CL t T tT Data Sheet E0167H10 38 HM5216165 Series Relationship Between Frequency and Minimum Latency EO HM5216165 Parameter -10H Frequency (MHz) tCK (ns) -12 100 10 66 15 33 30 83 12 55 18 28 36 Notes Active command to column command (same bank) t RCD 3 2 1 3 2 1 1 Active command to active command (same bank) t RC 9 6 3 9 6 3 = [tRAS + tRP] 1 Active command to precharge command t RAS (same bank) 6 4 2 6 4 2 1 Precharge command to active command t RP (same bank) 3 2 1 3 2 1 1 Write recovery or data-in to precharge command (same bank) t DPL 2 1 1 2 1 1 1 Active command to active command (different bank) t RRD 2 2 1 2 2 1 1 Self refresh exit time I SREX 2 2 2 2 2 2 2 Last data in to active command (Auto precharge, same bank) I APW 5 3 2 5 3 2 = [tDPL + tRP] Self refresh exit to command input I SEC 9 6 3 9 6 3 = [tRC] Precharge command to high impedance (CAS latency = 3) I HZP 3 3 3 3 3 3 L Symbol I HZP (CAS latency = 1) I HZP od Pr (CAS latency = 2) 2 2 — 2 2 — — 1 — — 1 1 1 1 1 1 1 –2 –2 –2 –2 –2 –2 — –1 –1 — –1 –1 — — 0 — — 0 Column command to column command I CCD 1 1 1 1 1 1 Write command to data in latency I WCD 0 0 0 0 0 0 DQM to data in I DID 0 0 0 0 0 0 DQM to data out I DOD 2 2 2 2 2 2 CKE to CLK disable I CLE 1 1 1 1 1 1 Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) (CAS latency = 3) I APR I EP (CAS latency = 2) I EP (CAS latency = 1) I EP t uc — Data Sheet E0167H10 39 HM5216165 Series Relationship Between Frequency and Minimum Latency (cont) EO HM5216165 Parameter -10H -12 Symbol 100 10 66 15 33 30 83 12 55 18 28 36 Register set to active command t RSA 1 1 1 1 1 1 CS to command disable I CDD 0 0 0 0 0 0 Power down exit to command input I PEC 1 1 1 1 1 1 Burst stop to output valid data hold (CAS latency = 3) I BSR 2 2 2 2 2 2 (CAS latency = 2) I BSR — 1 1 — 1 1 (CAS latency = 1) I BSR — — 0 — — 0 I BSH 3 3 3 3 3 3 I BSH — 2 2 — 2 2 Pr L Frequency (MHz) tCK (ns) Burst stop to output high impedance (CAS latency = 3) (CAS latency = 2) (CAS latency = 1) Burst stop to write data ignore I BSH — — 1 — — 1 I BSW 0 0 0 0 0 0 Notes Notes: 1. t RCD to tRRD are recommended value. 2. When self refresh exit is executed, CKE should be kept “H” longer than l SREX from exit cycle. t uc od Data Sheet E0167H10 40 HM5216165 Series Timing Waveforms EO ; ;; ; ; ; ;;;;;; Read Cycle t CK t CKH t CKL CLK t RC VIH CKE t RP t RAS ; ;;;; ;; ; ;;;; ; t RCD t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH CS RAS t CS t CH CAS t CS t CH L t CS t CH t CS t CH t AS t AH A11 t AS t AH A10 t AS t AH Address t CS t CH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH od t CH t CS DQMU /DQML I/O(input) t AC I/O(output) t AC Bank 0 Read t LZ t OH t AC t OH t AC t OH Bank 0 Precharge t HZ Burst length = 4 Bank0 Access = VIH or VIL t uc Bank 0 Active t CS t CH t CS t CH Pr WE t CS t CH Data Sheet E0167H10 41 ; ; ; ; ; ; ;;;;; HM5216165 Series Write Cycle EO t CK t CKH t CKL CLK t RC VIH CKE t RP t CS t CH t CS t CH t CS t CH ; ; ;; ;; t CS t CH t RAS t RCD CS t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH RAS CAS L t CS t CH t CS t CH WE t AS t AH t CS t CH t CS t CH t CS t CH t AS t AH t AS t AH t CS t CH t AS t AH A11 Pr t AS t AH t AS t AH A10 t AS t AH Address t AS t AH t CS DQMU /DQML t AS t AH t AS t AH I/O(input) t CH t DH t DS t DH t DS t DH od t DS t DH tDS t AS t AH t RWL I/O(output) Bank 0 Active Bank 0 Write Bank 0 Precharge Burst length = 4 Bank0 Access = VIH or VIL t uc Data Sheet E0167H10 42 HM5216165 Series ; ; ; ; ;;;;;;;;;; ; ; ; ; ;;;;;;;;;; ;; Mode Register Set Cycle 1 EO 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK CKE VIH CS RAS CAS ; WE A11(BS) DQMU /DQML I/O(output) L Address code R: b valid C: b’ C: b b b+3 b’ b’+1 b’+2 b’+3 High-Z I/O(input) Precharge If needed t RSA t RCD Output mask tRCD = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL Pr t RP Mode Bank 1 register Active Set Bank 1 Read t uc od Data Sheet E0167H10 43 ;; HM5216165 Series ; ; ; ; ;;;;;;;; ; ;;;;;; ; ;; Read Cycle/Write Cycle 1 2 EO 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE Read cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL VIH CS RAS CAS WE A11(BS) CKE CS RAS R:a Bank 0 Active C:a Bank 0 Read R:b C:b a C:b' a+1 a+2 a+3 b C:b" b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 High-Z Bank 1 Active L Address DQMU /DQML I/O (output) I/O (input) Bank 1 Bank 0 Read Precharge Bank 1 Read Bank 1 Read Bank 1 Precharge VIH Write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL CAS WE Address DQMU /DQML I/O (output) I/O (input) R:a C:a Pr A11(BS) R:b C:b C:b' C:b" High-Z a Bank 0 Active Bank 0 Write a+1 a+2 a+3 Bank 1 Active b Bank 1 Write b+1 b+2 b+3 b' Bank 0 Precharge Bank 1 Write b'+1 b" Bank 1 Write b"+1 b"+2 b"+3 Bank 1 Precharge t uc od Data Sheet E0167H10 44 ;;;;;;; ;;;;;;;; ; ; ; ; ; ;;;; HM5216165 Series Read/Single Write Cycle 1 EO 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE VIH CS RAS CAS WE A11(BS) CKE R:a C:a R:b L Address DQMU /DQML I/O (input) I/O (output) Bank 0 Active Bank 0 Read C:a' C:a a a a+1 a+2 a+3 Bank 1 Active a a+1 a+2 a+3 Bank 0 Bank 0 Write Read Bank 0 Precharge Bank 1 Precharge VIH CS CAS WE A11(BS) R:a C:a R:b C:a C:b C:c ; Address DQMU /DQML I/O (input) I/O (output) Pr RAS a Bank 0 Read Bank 1 Active a+1 c a+3 od a Bank 0 Active b Bank 0 Write Bank 0 Bank 0 Write Write Bank 0 Precharge Read/Single write RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL t uc Data Sheet E0167H10 45 ;;;;;;; ;;;;;;;; ; ; ; ; ; ;;;; HM5216165 Series Read/Burst Write Cycle 1 EO 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE VIH CS RAS CAS WE A11(BS) CKE R:a C:a R:b L Address DQMU /DQML I/O (input) I/O (output) Bank 0 Active Bank 0 Read C:a' C:a a a a+1 a+2 a+3 Bank 1 Active a a+1 a+2 a+3 Bank 0 Bank 0 Write Read Bank 0 Precharge Bank 1 Precharge VIH CS CAS WE A11(BS) R:a C:a R:b C:a C:b C:c ; Address DQMU /DQML I/O (input) I/O (output) Pr RAS a Bank 0 Read Bank 1 Active a+1 c a+3 od a Bank 0 Active b Bank 0 Write Bank 0 Bank 0 Write Write Bank 0 Precharge Read/Single write RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL t uc Data Sheet E0167H10 46 ; ; ;;;;;;;; HM5216165 Series Full Page Read/Write Cycle 1 2 3 EO 0 4 5 6 7 8 9 260 261 262 263 264 265 266 267 268 269 CLK CKE VIH Read cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page = VIH or VIL CS RAS CAS WE A11(BS) CKE CS RAS CAS R:a Bank 0 Active VIH C:a R:b a a+1 a+2 a-2 a+3 a-1 a a+1 a+2 a+3 a+4 a+5 High-Z Bank 0 Read Bank 1 Active Burst stop L Address DQMU /DQML I/O (output) I/O (input) Bank 1 Precharge Write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page = VIH or VIL WE Address DQMU /DQML I/O (output) I/O (input) R:a C:a Pr A11(BS) R:b High-Z a Bank 0 Active Bank 0 Write a+1 a+2 a+3 a+4 a+5 a+6 a+1 a+2 Bank 1 Active a+3 a+4 a+5 Burst stop Bank 1 Precharge t uc od Data Sheet E0167H10 47 HM5216165 Series ; ;;;;;;;;;;; ;;;;;;;;;; ;;;;;;;;;; Auto Refresh Cycle 1 EO 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a a+1 CLK CKE VIH CS RAS CAS WE A11(BS) Address L I/O(output) t RP Auto Refresh Precharge If needed C:a R:a A10=1 DQMU /DQML I/O(input) High-Z t RC tRC Active Bank 0 Auto Refresh Read Bank 0 Pr ; Self Refresh Cycle Refresh cycle and Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL CLK ISREX CKE Low CS RAS CAS WE A11(BS) A10=1 High-Z tRP Precharge command If needed tRC Self refresh entry command Self refresh exit ignore command or No operation Next Self refresh entry clock command enable Data Sheet E0167H10 48 t uc Address DQMU /DQML I/O(imput) I/O(output) CKE High od CKE Next Auto clock refresh enable Self refresh cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 =VIH or VIL HM5216165 Series EO ; ; ; ; ; ; ; ; ; ;;;;;;;;;;;;;; ; ; ; ; ; ; ; ; ;;;;;;; Clock Suspend Mode 0 1 2 t CESP 3 4 5 t CES t CEH 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL CS RAS CAS WE A11(BS) R:a Bank0 Active clock Active suspend start CKE CS C:a R:b a L Address DQMU /DQML I/O (output) I/O (input) C:b a+1 a+2 a+3 b b+1 b+2 b+3 High-Z Active clock Bank0 suspend end Read Bank1 Active Read suspend start Read suspend end Bank1 Read Bank0 Precharge Earliest Bank1 Precharge Write cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL RAS WE A11(BS) Address DQMU /DQML I/O (output) I/O (input) Pr CAS C:a R:b R:a C:b High-Z a Active clock suspend start Active clock Bank0 Bank1 supend end Write Active a+3 b Write suspend start Write suspend end b+1 b+2 b+3 Bank1 Bank0 Write Precharge Earliest Bank1 Precharge t uc od Bank0 Active a+1 a+2 Data Sheet E0167H10 49 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;;;;;;;;;;;;;;;; ;;;;;;;; HM5216165 Series Power Down Mode EO CLK CKE Low CKE CS RAS CAS WE L A11(BS) Address R: a A10=1 DQMU /DQML Pr I/O(input) High-Z I/O(output) Power down cycle RAS-CAS delay=3 CAS latency=2 Burst length=4 = VIH or VIL ; tRP Power down entry Precharge command If needed 0 1 2 3 4 CLK CKE VIH 6 7 8 9 10 CAS WE Address DQMU /DQML Valld 49 50 51 code VIH 52 53 54 55 Valld High-Z I/O tRP tRC All banks Auto Refresh Precharge tRC Auto Refresh Data Sheet E0167H10 50 48 t uc CS RAS 5 od Power Up Sequence Power down mode exit Active Bank 0 tRSA Mode register Bank active Set If needed HM5216165 Series Package Dimensions EO HM5216165TT Series (TTP-50D) Unit: mm 20.95 21.35 Max 26 L 0.80 11.76 ± 0.20 0.10 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-50D — — 0.50 g t uc od Dimension including the plating thickness Base material dimension 0° – 5° 0.68 1.20 Max 0.13 M Pr 1.15 Max 0.80 0.13 ± 0.05 0.27 ± 0.07 0.25 ± 0.05 25 0.145 ± 0.05 0.125 ± 0.04 1 10.16 50 Data Sheet E0167H10 51 HM5216165 Series Cautions EO 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. L od Pr C Elpida Memory, Inc. 2001 t uc Data Sheet E0167H10 52