Intersil ISL80111 Ultra low dropout 1a, 2a, 3a low input voltage nmos ldo Datasheet

Ultra Low Dropout 1A, 2A, 3A Low Input Voltage NMOS
LDOs
ISL80111, ISL80112, ISL80113
Features
The ISL80111, ISL80112, and ISL80113 are ultra low dropout
LDOs providing the optimum balance between performance, size
and power consumption in size constrained designs for data
communication, computing, storage and medical applications.
These LDOs are specified for 1A, 2A and 3A of output current and
are optimized for low voltage conversions.Operating with a VIN of
1V to 3.6V and with a legacy 3.3V to 5V on the BIAS, the VOUT is
adjustable from 0.8V to 3.3V. With a VIN PSRR greater than 40dB
at 100kHz makes these LDOs an ideal choice in noise sensitive
applications. The guaranteed ±1.6% VOUT accuracy overall
conditions lends these parts to suppling an accurate voltage to
the latest low voltage digital ICs.
• Ultra low dropout: 75mV at 3A, (typ)
ISL80111, ISL80112, ISL80113
1.2V ±5%
VIN
9
CIN
10µF
3.3V ±10%
VBIAS
CBIAS
1µF
EN
OPEN DRAIN COMPATIBLE
VOUT
VIN
10 VIN
VOUT 2
4 VBIAS
PG
7 ENABLE
ADJ
1.0V
VOUT
1
COUT
10µF
6
PGOOD
R3
1.0kΩ
3
R4
1.0kΩ
GND
5
• Very fast load transient response
• Extensive protection and reporting features
• VIN range: 1V to 3.6V, VOUT range: 0.8V to 3.3V
• Small 10 Ld 3x3 DFN package
Applications
• Noise-sensitive instrumentation and medical systems
• Data acquisition and data communication systems
• Storage, telecommunications and server equipment
• Low voltage DSP, FPGA and ASIC core power supplies
• Post-regulation of switched mode power supplies
DROPOUT VOLTAGE, BIAS = 5V (mV)
An enable input allows the part to be placed into a low quiescent
current shutdown mode. A submicron CMOS process is utilized for
this product family to deliver best-in-class analog performance
and overall value for applications in need of input voltage
conversions typically below 2.5V. It also has the superior load
transient regulation unique to a NMOS power stage. These LDOs
consume significantly lower quiescent current as a function of
load compared to bipolar LDOs.
• Excellent VIN PSRR: 70dB at 1kHz (typ)
• ±1.6% guaranteed VOUT accuracy for -40ºC < TJ < +125ºC
FIGURE 1. TYPICAL APPLICATION SCHEMATIC
IOUT = 1A
60
IOUT = 0A
IOUT = 2A
40
IOUT = 3A
BIAS = 5V
VIN = 3.3V
VOUT = 2.5V
COUT = 10µF
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 3. VIN PSRR vs LOAD CURRENT (ISL80113)
November 1, 2013
FN7841.2
1
ΔVADJ +25°C NORMALIZED (%)
PSRR (dB)
3A
80
70
2A
60
50
40
1A
30
20
10
0
-40
25
85
TEMPERATURE (°C)
125
1.015
80
0
90
FIGURE 2. DROPOUT VOLTAGE OVER-TEMP AND IOUT
100
20
100
1.010
1.005
1.000
0.995
0.990
0.985
-40
0
25
85
TEMPERATURE (°C)
125
FIGURE 4. ΔVADJ vs TEMPERATURE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL80111, ISL80112, ISL80113
Block Diagram
VIN
VBIAS
CURRENT
LIMIT
BIAS
UVLO
VIN
UVLO
VIN
M3
DRIVER
EN
R7
IL
IL/10,000
VOUT
THERMAL
SHUTDOWN
EN
EN
ADJ
-
EN
+
ENABLE
M1 POWER NMOS
PG
M7
500mV
-
+
-
M2
+
425mV
+
-
*R3
GND
Pin Configuration
ISL80111, ISL80112, ISL80113
(10 LD 3X3 DFN)
TOP VIEW
VOUT
1
10 VIN
VOUT
2
9 VIN
ADJ
3
VBIAS
4
GND
5
EPAD
(GND)
8 NC
Pin Descriptions
PIN
NUMBER
PIN NAME
1, 2
VOUT
3
ADJ
4
VBIAS
5
GND
6
PG
VOUT in regulation signal. Logic low defines
when VOUT is not in regulation. Range 0V to
BIAS
7
ENABLE
VIN independent chip enable. TTL and CMOS
compatible. Range 0V to VBIAS
8
NC
No Connect
9, 10
VIN
Input supply pins. Range 1.0V to 3.6V
7 ENABLE
6 PG
EPAD
2
DESCRIPTION
Output voltage pin. Range 0.8V to 3.3V
ADJ pin for externally setting VOUT. Range
0.5V to VOUT
Bias voltage pin for internal control circuits.
Range 2.9V to 5.5V
Ground pin
EPAD at ground potential. It is recommended
to solder the EPAD to the ground plane.
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
VOUT
(V)
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG
DWG. #
ISL80111IRAJZ
1ADJ
ADJ
-40 to +85
10 Ld 3x3 DFN
L10.3x3
ISL80112IRAJZ
2ADJ
ADJ
-40 to +85
10 Ld 3x3 DFN
L10.3x3
ISL80113IRAJZ
3ADJ
ADJ
-40 to +85
10 Ld 3x3 DFN
L10.3x3
ISL80111EVAL1Z
ISL80111 Evaluation Board
ISL80112EVAL1Z
ISL80112 Evaluation Board
ISL80113EVAL1Z
ISL80113 Evaluation Board
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information pages for ISL80111, ISL80112, and ISL80113. For more information on MSL
please see Tech Brief TB363.
3
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
Absolute Maximum Ratings (Note4)
Thermal Information
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 to +6V
VOUT Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +4V
PG, ENABLE, SENSE/ADJ, Relative to GND (Note 5) . . . . . . . . . -0.3 to +6V
VBIAS Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
PG Rated Current (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . 4000V
Machine Model (Tested per JESD22-115-A) . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V
Latch Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
10 Ld 3x3 DFN Package (Notes 7, 8). . . . .
48
4
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions (Notes 4, 6)
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VIN Relative to GND (ISL80113) (Note 9) . . . . . . . . . . . . VOUT + 0.4V to 5V
VIN Relative to GND (ISL80112) (Note 9) . . . . . . . . . . . . VOUT + 0.3V to 5V
VIN Relative to GND (ISL80111) (Note 9) . . . . . . . . . . . . VOUT + 0.2V to 5V
Nominal VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 3.3V
PG, ENABLE, SENSE/ADJ, SS Relative to GND . . . . . . . . . . . . . . .0V to 5.5V
VBIAS Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 5.5V
VBIAS Relative to VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8V minimum
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. Absolute maximum ratings define limits of safe operation. Extended operation at these conditions may compromise reliability. Exceeding these limits
will result in damage. Recommended operating conditions define limits where specifications are guaranteed.
5. Absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
6. Electromigration specification defined as lifetime average junction temperature of +110°C where maximum rated DC current = lifetime average
current.
7. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
8. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
9. Minimum operating voltage applied to VIN is 1V if VIN - VDO < 1V
Electrical Specifications
Unless otherwise specified, VIN = VOUT + 0.4V, VBIAS = 2.9V, VOUT = 1.2V, CBIAS = 1µF, CIN = 10µF,
COUT = 2.2µF, TJ = +25°C, IL = 0mA. Applications must follow thermal guidelines of the package to determine worst-case junction temperature. Please
refer to “Power Dissipation” on page 13 and Tech Brief TB379.
Boldface limits apply over junction temperature (TJ) range, -40°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA where datasheet limits
are defined.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
2.3
2.9
V
2.1
2.8
V
DC CHARACTERISTICS
VBIAS UVLO
VBIAS UVLO Hysteresis
UVLO_BIAS_r
VBIAS Rising
UVLO_BIAS_f
VBIAS Falling
1.55
UVLOB_HYS
DC ADJ Pin Voltage Accuracy
VADJ
0.2
1.0V ≤ VIN ≤ 3.6V, ILOAD = 0A, 2.9V ≤ VBIAS ≤ 5.5V,
VOUT = VADJ
494
V
502
510
mV
DC Input Line Regulation
ΔVOUT
VOUT + 0.4V ≤ VIN ≤ 3.6V
0.01
0.9
mV
DC Bias Line Regulation
ΔVOUT
2.9V<VBIAS<5.5V with respect to ADJ pin
0.3
1.4
mV
DC Output Load Regulation
ΔVOUT
0A ≤ ILOAD ≤ 3A
-0.2
2
mV
VADJ = 0.5V
10
80
nA
10
mA
Feedback Input Current
-2
VIN Quiescent Current
IQ (VIN)
VOUT = 2.5V
8
VIN Quiescent Current
IQ (VIN)
VOUT = 3.3,
10.6
4
mA
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
Electrical Specifications
Unless otherwise specified, VIN = VOUT + 0.4V, VBIAS = 2.9V, VOUT = 1.2V, CBIAS = 1µF, CIN = 10µF,
COUT = 2.2µF, TJ = +25°C, IL = 0mA. Applications must follow thermal guidelines of the package to determine worst-case junction temperature. Please
refer to “Power Dissipation” on page 13 and Tech Brief TB379.
Boldface limits apply over junction temperature (TJ) range, -40°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA where datasheet limits
are defined. (Continued)
PARAMETER
SYMBOL
VIN Quiescent Current
IQ (VIN)
TEST CONDITIONS
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
VOUT = 1.0V
3.5
0 ≤ IL ≤ 3A, VBIAS = 5.5V
2.9
4.6
mA
ENABLE Pin = 0.2V, TJ = +125°C
3
20
µA
ILOAD = 1A, VOUT = 1.2V, 2.9V ≤ VBIAS ≤ 5V
27
90
mV
ILOAD = 2A, VOUT = 1.2V, 2.9V ≤ VBIAS ≤ 5V
53
115
mV
ILOAD = 3A, VOUT = 1.2V, 2.9V ≤ VBIAS ≤ 5V
75
140
mV
ILOAD = 1A, VOUT = 1.2V
1.1
1.3
V
ILOAD = 2A, VOUT = 1.2V
1.2
1.4
V
ILOAD = 3A, VOUT = 1.2V
1.3
1.5
V
VOUT = 0.2V
5.2
A
Output Short Circuit Current
(2A Version)
VOUT = 0.2V
3.2
A
Output Short Circuit Current
(1A Version)
VOUT = 0.2V
2.2
A
VBIAS Quiescent Current
IQ (VBIAS)
Ground Pin Current in
Shutdown
ISHDN
VIN Dropout Voltage
(Note 11)
VDO(VIN)
VBIAS Dropout Voltage
(Note 11)
VDO(BIAS)
mA
OVERCURRENT PROTECTION
Output Short Circuit Current
(3A Version)
ISC
OVER-TEMPERATURE PROTECTION
Thermal Shutdown
Temperature
TSD
160
°C
Thermal Shutdown
Hysteresis
TSDn
20
°C
AC CHARACTERISTICS
Input Supply Ripple Rejection
PSRR(VIN)
f = 120Hz, ILOAD = 1A
80
dB
PSRR(VBIAS)
f = 120Hz, ILOAD = 1A
60
dB
ILOAD = 10mA, BW = 100Hz ≤ f ≤ 100kHz
100
µVRMS
ILOAD = 3A, f = 10Hz
7
µV/√Hz
ILOAD = 3A, f = 100Hz
3
µV/√Hz
tEN
COUT = 10µF, ILOAD = 1A
50
µs
tBIAS
COUT = 10µF, EN = BIAS
100
µs
Output Noise Voltage
eN(RMS)
Spectral Noise Density
eN
DEVICE START-UP CHARACTERISTICS
EN Start-up Time
BIAS Start-up Time
ENABLE PIN CHARACTERISTICS
Turn-on Threshold (Rising)
VOUT + 0.4V ≤ VIN ≤ 3.6V, 2.9V ≤ VBIAS ≤ 5.5V
400
680
850
mV
Hysteresis (Rising Threshold)
1.2V ≤ VIN ≤ 3.6V, 2.9V ≤ VBIAS ≤ 5.5V
60
260
330
mV
PGTH
2.9V ≤ VBIAS ≤ 5.5V
71
82
93
%VOUT
PGHYS
2.9V ≤ VBIAS ≤ 5.5V
PG PIN CHARACTERISTICS
PG Flag Falling Threshold
PG Flag Hysteresis
5
9.3
%VOUT
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
Electrical Specifications
Unless otherwise specified, VIN = VOUT + 0.4V, VBIAS = 2.9V, VOUT = 1.2V, CBIAS = 1µF, CIN = 10µF,
COUT = 2.2µF, TJ = +25°C, IL = 0mA. Applications must follow thermal guidelines of the package to determine worst-case junction temperature. Please
refer to “Power Dissipation” on page 13 and Tech Brief TB379.
Boldface limits apply over junction temperature (TJ) range, -40°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA where datasheet limits
are defined. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 10)
TYP
MAX
(Note 10)
UNITS
PG Flag Low Voltage
ISINK = 500µA
90
130
mV
PG Flag Leakage Current
PG = VBIAS = 5.5V
11
300
nA
PG Flag Sink Current
7
10
mA
NOTES:
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
11. Dropout is defined by the difference in supply (VIN, VBIAS) and VOUT when the supply produces a 2% drop in VOUT from its nominal value, output
voltage set to 2.5V.
12. For normal operation, VIN must always be less than or equal to the voltage applied to VBIAS. Part is protected against fault conditions where VIN can
be greater than VBIAS.
6
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
Typical Operating Performance
TJ = +25°C, ILOAD = 0A.
Unless otherwise noted, VIN = 1.8V, VBIAS = 3.3V, VOUT = 1.2V, CIN = COUT = 10µF,
18
90
80
70
3A V
= 3.3V
BIAS
2A V
= 3.3V
BIAS
3A V
= 5V
BIAS
60
50
2A V
= 5V
BIAS
40
30
20
10
0
1A V
= 3.3V
BIAS
1A V
= 5V
BIAS
-40
25
TEMPERATURE (°C)
16
PERCENTAGE OF POPULATION
VIN DROPOUT VOLTAGE (mV)
100
14
12
10
8
6
4
2
0
125
500.0 500.5 501.0 501.5 502.0 502.5 503.0 503.5 504.0
VADJ @ +25°C (mV)
FIGURE 5. DROPOUT vs VBIAS
FIGURE 6. VADJ DISTRIBUTION
0.00
-0.10
1.010
-0.20
-0.30
1.005
Δ VOUT (mV)
ΔVADJ +25°C NORMALIZED (%)
1.015
1.000
0.995
-0.50
-0.60
-0.70
-0.80
0.990
-0.90
0.985
-40
0
25
85
TEMPERATURE (°C)
-1.00
125
FIGURE 7. ΔVADJ vs TEMPERATURE
1.2200
1.205
1.2175
1.204
-40
0
25
85
TEMPERATURE (°C)
125
1.203
OUTPUT VOLTAGE (V)
1.2125
1.2100
1.2075
1.2050
1.2025
1.2000
1.1975
1.1950
1.1925
1.1900
0
IOUT = 0A - 3A
FIGURE 8. LOAD REGULATION vs TEMPERATURE
1.2150
OUTPUT VOLTGE (V)
-0.40
1.0
1.5
2.0
2.5
LOAD CURRENT (A)
FIGURE 9. LOAD REGULATION, VOUT vs IOUT
7
1.201
1.200
1.199
1.198
1.197
1.196
VIN = 1.6V, VBIAS = 2.9V
0.5
1.202
3.0
VVBIAS=3.7V
BIAS = 3.7V
1.195
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
INPUT VOLTAGE (V)
FIGURE 10. VIN LINE REGULATION
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
Typical Operating Performance
TJ = +25°C, ILOAD = 0A. (Continued)
Unless otherwise noted, VIN = 1.8V, VBIAS = 3.3V, VOUT = 1.2V, CIN = COUT = 10µF,
1.205
4.5
BIAS GROUND CURRENT (mA)
OUTPUT VOLTAGE (V)
1.204
1.203
1.202
1.201
1.200
1.199
1.198
1.197
1.196
1.195
2.9
3.2
3.5
3.8
4.1
4.4
BIAS VOLTAGE (V)
4.7
3.0
2.5
2.0
0
1
2
OUTPUT CURRENT(A)
3
3.2
VBIAS = 5V
VOUT = 3.3V
10
9
8
VBIAS = 3.3V
VOUT = 1.8V
7
6
5
VBIAS = 5V
VOUT = 1.8V
VBIAS = 5V
VOUT = 1.0V
VBIAS = 3.3V
4 V
OUT = 1.0V
3
VBIAS = 3.3V
VOUT = 0.8V
2
1.4
VBIAS = 5V
VOUT = 0.8V
1.8
2.2
2.6
3.0
VIN INPUT VOLTAGE (V)
3.4
3.8
3.0
2.8
2.6
2.4
2.2
VVIN=1.6V
OUT = 0.8V
2.0
2.9
FIGURE 13. INPUT GROUND CURRENT vs VIN and VOUT
3.2
3.5
3.8
4.1
4.4
BIAS VOLTAGE (V)
4.7
5.0
FIGURE 14. INPUT GROUND CURRENT vs VBIAS
3.45
3.1
VBIAS = 5V
3.0 V
OUT = 0.8V
2.9
VBIAS = 5V
VOUT = 1.2V
VBIAS = 5V
VOUT = 2.5V
2.8
2.7 V
BIAS = 3.3V
2.6 VOUT = 0.8V
VBIAS = 3.3V
VOUT = 1.2V
2.5
2.4
VBIAS = 3.3V
VOUT = 2.5V
2.3
1.4
1.8
2.2
2.6
3.0
INPUT VOLTAGE (V)
3.4
FIGURE 15. BIAS GROUND CURRENT vs VIN and VOUT
8
3.8
BIAS GROUND CURRENT (mA)
3.2
BIAS GROUND CURRENT (mA)
BIAS = 2.9V
FIGURE 12. BIAS GROUND CURRENT vs LOAD CURRENT
BIAS INPUT GROUND CURRENT (mA)
VIN INPUT GROUND CURRENT (mA)
3.5
1.5
5.0
11
2.2
1.0
BIAS = 5V
VVIN=1.6V
IN = 1.6V
FIGURE 11. VBIAS LINE REGULATION
1
1.0
4.0
3.25
3.05
2.85
2.65
2.45
2.25
2.05
1.85
2.9
VIN = 1.6V
3.2
3.5
3.8
4.1
4.4
BIAS VOLTAGE (V)
4.7
5.0
FIGURE 16. BIAS GROUND CURRENT vs VBIAS
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
Typical Operating Performance
TJ = +25°C, ILOAD = 0A. (Continued)
Unless otherwise noted, VIN = 1.8V, VBIAS = 3.3V, VOUT = 1.2V, CIN = COUT = 10µF,
12
VIN INPUT CURRENT (mA)
10
EN
8
VOUT
6
4
PGOOD
VBIAS = 5.0V
VOUT = 3.6V
2
0
1.0
1.5
1.8
2.5
IIN
3.3
OUTPUT VOLTAGE(V)
FIGURE 18. ENABLE START-UP WITH PGOOD
FIGURE 17. VIN IQ vs VOUT VOLTAGE
ISL80111 CURRENT LIMITING @ 2.1A
DURING TURN-ON OC EVENT
VOUT
EN
PGOOD
VOUT
PGOOD
IIN
IOUT
CLOAD = 1000µF
FIGURE 19. ISL8011X INTO AND OUT OF THERMAL SHUTDOWN
FIGURE 20. ISL80111 ENABLED INTO OVERCURRENT
ISL80113 CURRENT LIMITING @ 5A
DURING TURN-ON OC EVENT
ISL80112 CURRENT LIMITING @ 3.4A
DURING TURN-ON OC EVENT
EN
EN
VOUT
VOUT
PGOOD
PGOOD
IIN
IIN
CLOAD = 1000µF
FIGURE 21. ISL80112 ENABLED INTO OVERCURRENT
9
CLOAD = 1000µF
FIGURE 22. ISL80113 ENABLED INTO OVERCURRENT
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
Typical Operating Performance
TJ = +25°C, ILOAD = 0A. (Continued)
Unless otherwise noted, VIN = 1.8V, VBIAS = 3.3V, VOUT = 1.2V, CIN = COUT = 10µF,
IOUT = 200mA
IOUT = 1.1A
IOUT =100mA
IOUT = 0.1A
VOUT (5mV/DIV)
VOUT (20mV/DIV)
TIME (20µs/DIV)
TIME (20µs/DIV)
FIGURE 23. 100mA LOAD TRANSIENT RESPONSE
FIGURE 24. 1A LOAD TRANSIENT RESPONSE
IOUT = 2.1A
IOUT = 3.1A
IOUT = 0.1A
IOUT = 0.1A
VOUT (20mV/DIV)
VOUT (50mV/DIV)
TIME (20µs/DIV)
TIME (20µs/DIV)
FIGURE 25. 2A LOAD TRANSIENT RESPONSE
FIGURE 26. 3A LOAD TRANSIENT RESPONSE
100
PSRR (dB)
IOUT = 1A
60
IOUT = 0A
IOUT = 2A
40
IOUT = 3A
20
80
PSRR (dB)
80
100
BIAS = 5V
VIN = 3.3V
VOUT = 2.5V
COUT = 10µF
BIAS = 5V
VIN = 3.3V
VOUT = 2.5V
COUT = 10µF
60
IOUT = 0A
40
IOUT = 2A
IOUT = 3A
20
IOUT = 1A
0
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 27. VIN PSRR vs LOAD CURRENT
10
1M
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 28. BIAS PSRR vs LOAD CURRENT
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
Typical Operating Performance
TJ = +25°C, ILOAD = 0A. (Continued)
100
80
IOUT = 2A
IOUT = 1A
IOUT = 2A
IOUT = 3A
40
20
60
IOUT = 0A
IOUT = 1A
IOUT = 3A
40
20
0
100
1k
10k
100k
0
1M
100
1k
FREQUENCY (Hz)
1M
100
BIAS = 5V
VIN = 3.3V
VOUT = 2.5V
IOUT = 3A
60
COUT = 10µF
COUT = 2.2µF
BIAS = 5V
VIN = 3.3V
VOUT = 2.5V
IOUT = 1A
80
40
COUT = 20µF
PSRR (dB)
80
PSRR (dB)
100k
FIGURE 30. VBIAS PSRR vs LOAD CURRENT
100
60
COUT = 10µF
COUT = 2.2µF
40
COUT = 20µF
20
20
100
1k
10k
100k
0
1M
100
1k
FREQUENCY (Hz)
100
60
IOUT = 0A
IOUT = 2A
IOUT = 3A
40
20
0
100
100
1M
BIAS = 5V
VIN = 3.3V
VOUT = 2.5V
COUT = 5x2.2µF
80
IOUT = 1A
PSRR (dB)
80
100k
FIGURE 32. VIN PSRR vs COUT
BIAS = 5V
VIN = 3.3V
VOUT = 2.5V
COUT = 5x2.2µF
IOUT = 1A
10k
FREQUENCY (Hz)
FIGURE 31. VIN PSRR vs COUT
PSRR (dB)
10k
FREQUENCY (Hz)
FIGURE 29. VVIN PSRR vs LOAD CURRENT
0
BIAS = 3.3V
VIN = 1.5V
VOUT = 1.0V
COUT = 10µF
80
PSRR (dB)
PSRR (dB)
100
BIAS = 3.3V
VIN = 1.5V
VOUT = 1.0V
COUT = 10µF
IOUT = 0A
60
Unless otherwise noted, VIN = 1.8V, VBIAS = 3.3V, VOUT = 1.2V, CIN = COUT = 10µF,
60
IOUT = 0A
40
IOUT = 2A
IOUT = 3A
20
0
1k
10k
100k
FREQUENCY (Hz)
FIGURE 33. VIN PSRR vs LOAD CURRENT
11
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 34. VBIAS PSRR vs LOAD CURRENT
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
MAX POWER (VIN-VOUT) x IOUT (W)
Unless otherwise noted, VIN = 1.8V, VBIAS = 3.3V, VOUT = 1.2V, CIN = COUT = 10µF,
3.0
2.5
300 lfm
2.0
1.5
1.0
0 lfm
0.5
0.0
25 30 35 40 45 50 55 60 65 70 75 80 85 105 125
INPUT VOLTAGE NOISE (µV/√Hz)
Typical Operating Performance
TJ = +25°C, ILOAD = 0A. (Continued)
1000
VBIAS = 5V
VIN = 3.8V
VOUT = 3.3V
IOUT = 3A
100
10
1
VBIAS = 3.8V
VIN = 1.28V
VOUT = 1V
IOUT = 3A
0.1
0.1
1
TEMPERATURE (°C)
FIGURE 35. CONTINUOUS POWER LIMIT vs AIR TEMP AND FLOW
Functional Description
The ISL80111, ISL80112 and ISL80113 are high-performance,
low-dropout regulators featuring an NMOS pass device. Benefits
of using an NMOS as a pass device include low input voltage,
stability over a wide range of output capacitors, and ultra low
dropout voltage. The ISL80111, ISL80112 and ISL80113 are
ideal for post regulation of switch mode power supplies.
The ISL80111, ISL80112 and ISL80113 also integrate enable,
power-good indicator, current limit protection, and thermal
shutdown functions into a space-saving 3x3 DFN package.
Input Voltage Requirements
The VIN pin provides the high current to the drain of the NMOS
pass transistor. The specified minimum input voltage is 1V and
dropout voltage for this family of LDOs has been conservatively
specified.
10
100
1k
FREQUENCY (Hz)
10k
100k
FIGURE 36. INPUT VOLTAGE NOISE vs BIAS VOLTAGE
PGOOD pin should not be pulled up to a voltage source greater
than VBIAS. A PGOOD fault can be caused by the output voltage
going below 84% of the nominal output voltage. PGOOD does not
function during thermal shutdown as the VOUT is less than the
minimum regulation voltage during that time.
Output Voltage Selection
An external resistor divider is used to scale the output voltage
relative to the internal reference voltage. This voltage is then fed
back to the error amplifier. The output voltage can be
programmed to any level between 0.8V and 4V. Referring to
Figure 1 the external resistor divider, R3 and R4, is used to set
the output voltage as shown in Equation 1. The recommended
value for R4 is 500Ω to 1kΩ. R3 is then chosen according to
Equation 2.
⎛ R3
⎞
V OUT = 0.5V × ⎜ ------- + 1⎟
⎝ R4
⎠
(EQ. 1)
V OUT
R 3 = R 4 × ⎛ ---------------- – 1⎞
⎝ 0.5V
⎠
(EQ. 2)
Bias Voltage Requirements
The VBIAS input powers the internal control circuits, reference
voltage, and LDO gate driver. The difference between the VBIAS
voltage and the output voltage must be greater than the VBIAS
dropout voltage specified in the “Electrical Specifications” table
beginning on Page 4. The minimum VBIAS input is 2.9V.
Current Limit Protection
Soft-start Operation
The ISL80111, ISL80112, and ISL80113 incorporate protection
against overcurrent due to a short, overload condition applied to
the output and the in-rush current that occurs at start-up. The
LDO performs as a constant current source when the output
current exceeds the current limit threshold noted in “Electrical
Specifications” on page 4. If the short or overload condition is
removed from VOUT, then the output returns to normal voltage
mode regulation. In the event of an overload condition, the LDO
might begin to cycle on and off due to the die temperature
exceeding the thermal fault condition.
The ISL8011x has an internal 100µs typical soft-start function to
prevent excessive in-rush current during start-up.
Thermal Fault Protection
Enable Operation
The ENABLE turn-on threshold is typically 600mV with a
hysteresis of 100mV. This pin must not be left floating. When this
pin is not used, it must be tied to VBIAS. A 1kΩ to 10kΩ pull-up
resistor is required for applications that use open collector or
open drain outputs to control the ENABLE pin.
Power-good Operation
The PGOOD flag is an open-drain NMOS that can sink up to 10mA
during a fault condition. Applications not using this feature must
connect this pin to ground. The PGOOD pin requires an external
pull-up resistor, which is typically connected to the VOUT pin. The
12
If the die temperature exceeds (typically) +160°C, the LDO
output shuts down until the die temperature cools to (typically)
+140°C. The level of power, combined with the thermal
impedance of the package (+48°C/W), determines whether the
junction temperature exceeds the thermal shutdown
temperature.
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
External Capacitor
Requirements
External capacitors are required for proper operation. To ensure
optimal performance, careful attention must be paid to the
layout guidelines and selection of capacitor type and value.
Input Capacitor
The minimum input capacitor required for proper operation is
10µF with a ceramic dielectric. This minimum capacitor must be
connected to the VIN and ground pins of the LDO no further than
0.5cm away.
Output Capacitor
The ISL8011x applies state-of-the-art internal compensation to
simplify selection of the output capacitor. Stable operation over
the full temperature range, VIN range, VOUT range, and load
extremes is guaranteed for all capacitor types and values,
assuming a 1µF X5R/X7R is used for local bypass on VOUT. This
minimum capacitor must be connected to the VOUT and ground
pins of the LDO no further than 0.5cm away.
Lower-cost Y5V and Z5U type ceramic capacitors are acceptable,
if the size of the capacitor is larger, to compensate for the
significantly lower tolerance over X5R/X7R types. Additional
capacitors of any value, in ceramic, POSCAP, or alum/tantalum
electrolytic types, can be placed in parallel to improve PSRR at
higher frequencies or load-transient AC output voltage
tolerances.
46
44
θJA (°C/W)
See Figure 35 for maximum continuous power dissipation
guidance for ambient temperature and linear air flow rate. This
graph ignores the insignificant power dissipation contribution of
the BIAS pin.
42
40
38
36
34
2
4
6
8
10
12
14
16
18
20
22
2
EPAD-MOUNT COPPER LAND AREA ON PCB (mm )
24
FIGURE 37. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
THERMAL VIAS θJA vs EPAD-MOUNT COPPER LAND
AREA ON PCB
For safe operation, ensure that power dissipation calculated in
Equation 3 (PD) is less than the maximum allowable power
dissipation, PD(MAX).
The DFN package uses the copper area on the PCB as a heat
sink. For heat sinking, the EPAD of this package must be
soldered to the copper plane (GND plane). Figure 37 shows a
curve for the θJA of the DFN package for different copper area
sizes.
General PowerPAD Design Considerations
The following is an example of how to use vias to remove heat
from the IC.
Filling the thermal pad area with vias is recommended. A typical
via array is to fill the thermal pad footprint with vias spaced such
that they are center on center 3x the radius apart from each
other. Keep the vias small but not so small that their inside
diameter prevents solder from wicking through the holes during
reflow.
Bias Capacitor
The minimum input capacitor required for proper operation is
1µF with a ceramic dielectric. This minimum capacitor must be
connected to the VBIAS and ground pins of the LDO no further
than 0.5cm away. When the VBIAS pin is connected to the VIN
pin, a total of 10µF of X5R/X7R connected to the VIN pin and
ground is sufficient.
Power Dissipation and Thermals
Power Dissipation
Junction temperature must not exceed the range specified in the
“Recommended Operating Conditions” section on Page 4. Power
dissipation can be calculated with Equation 3.
P D = ( V IN – V OUT ) × I OUT + V BIAS × IQ ( BIAS ) + V IN × IQ ( V IN )
(EQ. 3)
FIGURE 38. PCB VIA PATTERN
Connect all vias to the round plane. For efficient heat transfer, it
is important that the vias have low thermal resistance. Do not
use “thermal relief” patterns to connect the vias. It is important
to have a complete connection of the plated through-hole to each
plane.
The maximum allowable junction temperature, TJ(MAX), and the
maximum expected ambient temperature, TA(MAX), determine
the maximum allowable power dissipation, as shown in
Equation 4, where θJA is the junction-to-ambient thermal
resistance.
P D ( MAX ) = ( T J ( MAX ) – T A ) ⁄ θ JA
13
(EQ. 4)
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
ISL80111, ISL80112, ISL80113
Split Supply LDO Evaluation
Board User Guide
Description
The ISL8011XEVAL1Z provides a simple platform to evaluate
performance of the ISL8011X family of split supply LDOs.
Jumpers are provided to easily set popular output voltages.
The ISL80111, ISL80112, and ISL80113 are single-output LDOs
specified for 1A, 2A, 3A of output current and are optimized for
less than 2.5V and less output voltage conversions. The
ISL8011X supports VIN voltages down to 1V, provided a standard
legacy 3.3V or 5V is applied on the VBIAS pin. The output voltage
is adjustable from 0.8V to 3.3V.
An enable input, having a threshold < 1V, allows the part to be
placed into a low quiescent current shutdown mode. A submicron
CMOS process is utilized for this product family to deliver
best-in-class analog performance and overall value for
applications in need of input voltage conversions to typically
below 2.5V. It also has the superior load transient regulation
unique to a NMOS power stage.
These LDOs consume significantly lower quiescent current as a
function of load compared to bipolar LDOs. This lower
consumption translates into higher efficiency and the ability to
consider packages with smaller footprints. The quiescent current
has been modestly compromised in design to enable leading
class fast load transient response and load regulation.
What’s Inside
• The evaluation kit contains the following:
• The ISL80113EVAL1Z with the appropriate parts installed
• The ISL80111, ISL80112, ISL80113 data sheet
Test Steps
1. Select the desired output voltage by shorting one of the
jumpers from JP2 through JP5.
2. Connect both the BIAS and VIN supplies and the load. Enable
the IC using jumper JP6 (bottom position) or via a signal on
the center post, observe the output.
3. The shipped configuration is enabled and VOUT = 3.3V.
4. Scope shots taken from ISL8011XEVAL1Z boards.
FIGURE 39. ISL80113EVAL1Z (TOP PCB LEFT, PHOTOGRAPH RIGHT)
14
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
Schematic
Bill of Materials
REFERENCE
DESIGNATOR
VALUE
U1
DESCRIPTION
MANUFACTURER
ISL80111, ISL80112 or ISL80113 as noted on Intersil
the evaluation board
C1, C3
10µF
CAP, SMD, 0805, 50V, 10%
Generic
C2
1µF
CAP, SMD, 0603
Generic
R1
1kΩ
RES, SMD, 0603, 1%
Generic
R2
2.05kΩ
RES, SMD, 0603, 1%
Generic
R3
2.61kΩ
RES, SMD, 0603, 1%
Generic
R4
4.02kΩ
RES, SMD, 0603, 1%
Generic
R5
5.62kΩ
RES, SMD, 0603, 1%
Generic
R6
1kΩ
RES, SMD, 0603, 1%
Generic
R7
100kΩ
RES, SMD, 0603, 1%
Generic
JP1, JP2, JP3,
JP4, JP5, JP6
Jumper
Generic
TP1, TP2, TP3
TP4, TP5, TP6
Terminal Connector
Generic
15
PART
NUMBER
ISL80111IRAJZ,
ISL80112IRAJZ,
ISL80113IRAJZ
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
November 1, 2013
FN7841.2
Electrical Spec table: Bold the Min and Max values.
Page 4- Electrical Spec table title area: Removed “Unless otherwise noted, all parameters are guaranteed
over the conditions specified as follows” and replaced by “Unless otherwise specified”.
Updated POD to latest revision from rev 7 to rev 8. The changes as follow: Corrected L-shaped leads in
Bottom view and land pattern so that they align with the rest of the leads (L shaped leads were shorter)
June 5, 2012
FN7841.1
Ordering Information table on Page 3: Changed evaluation board names from: ISL80111IRAJEVALZ,
ISL80112IRAJEVALZ and ISL80113IRAJEVALZ to ISL80111EVAL1Z, ISL80112EVAL1Z and
ISL80113VAL1Z.
Changed POD L10.3x3 on Page 17 to latest revision from Rev 6 to Rev 7. Change to POD is as follows:
Removed package outline and included center to center distance between lands on recommended land
pattern.
Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm and
0.30mm from the terminal tip." since it is not applicable to this package. Renumbered notes accordingly.
Figure 6 VADJ Distribution , corrected "Y" scale units from (0.18, 0.16, 0.14, 0.12, 0.10, 0.08, 0.06, 0.04,
0.02, and 0.00) to (18, 16,14,12,10, 8, 6, 4, 2, and 0).
Electrical Specifications table on Page 4 "Added UVLO rising spec to show max of 2.9V so implementation
at 3.3V is not a math problem".
March 30 2012
FN7841.0
Initial Release and Added “UVLO _BIAS _r” spec on pg 4. Modified Figures 13 - 17.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN7841.2
November 1, 2013
ISL80111, ISL80112, ISL80113
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 8, 7/12
3.00
5
PIN #1 INDEX AREA
A
B
1
5
PIN 1
INDEX AREA
(4X)
3.00
2.00
8x 0.50
2
10 x 0.23
0.10
1.60
TOP VIEW
10x 0.35
BOTTOM VIEW
(4X)
0.10 M C A B
0.415
0.200
0.23
0.35
(10 x 0.55)
SEE DETAIL "X"
(10x 0.23)
1.00
MAX
0.10 C
BASE PLANE
2.00
0.20
C
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
C
0.20 REF
4
1.60
0.05
2.85 TYP
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Tiebar shown (if present) is a non-functional feature.
5.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
17
FN7841.2
November 1, 2013