Sanyo LV4147W Bi-cmos lsi for lcd panel drive single chip ic Datasheet

Ordering number : EN8928A
Bi-CMOS LSI
For LCD Panel Drive
LV4147W
Single Chip IC
Overview
The LV4147W is single chip IC for LCD panel drive.
Functions
• Analog block RGB Decoder/Driver
• Digital block Timing Generator
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Maximum supply voltage
Conditions
Ratings
Unit
VCC1 max
Analog LOW type
6
V
VCC2 max
Analog HIGH type
12
V
VDD max
Digital type
4.5
V
350
mW
Allowable power dissipation
Pd max
Ta ≤ 75°C * Mounted on a board.
Operating temperature
Topr
-15 to +75
°C
Storage temperature
Tstg
-40 to +125
°C
Input pin voltage
VINA
Analog input pin
-0.3 to VCC1
V
VIND
Digital input pin (Except pin 10, 11 and 12)
-0.3 to VDD+0.3
V
VIND
Digital input pin (10, 11, 12pin)
-0.3 to +4.5
V
* : Mounted on a board :
30×30×1.6mm3,
glass epoxy board
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
50907 TI PC B8-6537 No.8928-1/26
LV4147W
Operating Ratings at Ta = 25°C
Parameter
Recommended supply voltage
Operating voltage range
Symbol
Conditions
Ratings
Unit
VCC1
Analog LOW type
3.0
V
VCC2
Analog HIGH type
7.0
V
VDD
Digital type
3.0
V
VCC1op
Analog LOW type
2.7 to 3.6
V
VCC2op
Analog HIGH type
6 to 9.5
V
VDDop
Digital type
2.7 to 3.6
V
Input Signal Voltage
Parameter
Recommended
Y input signal
input signal
Color
voltage
Difference
Symbol
Yin
Conditions
Ratings
Unit
Sync chip - white
0.5
Vp-p
B-Yin
75% Color bar signal
0.3
Vp-p
R-Yin
75% Color bar signal
0.24
Vp-p
input signal
Electrical DC Characteristics
Unless otherwise specified, settings 1 and 2 must be made.
Unless otherwise specified, VCC1 = 3.0V, VCC2 = VCCCOM = 7.0V, GND1 = GND2 = GNDCOM = 0,
VDD1 = VDD2 = 3.0V, VSS1 = VSS2 = 0, Ta = 25°C
[Current Characteristics]
Parameter
Current dissipation VCC1,
Symbol
ICC1
analog LOW
Current dissipation VCC2,
ICC2
analog HIGH
Current dissipation VDD, logic
Ratings
Conditions
min
typ
Unit
max
Enter SIG3 to (A), (D) and (E).
TRAP OFF
18
26
33
Measure the current value of ICC1.
TRAP ON
20
28
35
mA
2
4
6
mA
110,000
and
130,000
modes
7
10
13
mA
180,000
mode
8.5
12
15.5
mA
Enter SIG3 to (A)
mA
Measure the current value of ICC2.
IDD1
Enter SIG3 to (A)
Measure the current value of IDD11 and
IDD21.
IDD2
IDD1, IDD2, IDD3 = IDD11+IDD21
[Digital block input/output characteristics]
Parameter
L-level input voltage
H-level input voltage
Symbol
VIL
VIH
Conditions
typ
Digital block input pin (Note 1)
VOH1
IOH = -1.2mA (Note 2)
L-level output voltage
VOL1
IOL = 1.2mA (Note 2)
tTLH
Load 50pF (see Fig. 3)
0.3VDD
0.7VDD
ΔT
V
V
VDD -0.2
V
0.3
tTHL
Cross point time difference
Unit
max
Digital block input pin (Note 1)
H-level output voltage
Output transition time
Ratings
min
Load 50pF
V
30
ns
30
ns
10
ns
53
%
CKH1/CKH2 and CKV1/CKV2 and CKH3/CKH4
(See Fig. 4)
CHK duty
DTYHC
Load 50pF
47
50
Measure the duty of CKH1, CKH2, CKH3 and CKH4.
(Note 1) Digital block input pins : LOAD, DATA, SCLK
(Note 2) Digital block output pins : Pins 15 to 31, 33, 34
No.8928-2/26
LV4147W
Electrical AC Characteristics (1)
Unless otherwise specified, the setting 1 and 2 must be made.
Unless otherwise specified, VCC1 = 3.0V, VCC2 = VCCCOM = 7.0V, GND1 = GND2 = GNDCOM = 0,
VDD1 = VDD2 = 3.0V, VSS1 = VSS2 = 0, Ta = 25°C
Unless otherwise specified, measure the non-inverted output of TP40, TP43, and TP45.
[Y signal system]
Parameter
Symbol
Contrast characteristics, TYP
GCNTTP
Conditions
min
Enter SIG3 to (A) and measure the ratio between the output
typ
max
unit
14
16
18
dB
-2
1
4.5
dB
19
21
23
dB
amplitude (white to black) and input amplitude of TP43.
Contrast characteristics, MIN
GCNTMN
Enter SIG3 to (A) and measure the ratio between the output
amplitude (white to black) and input amplitude of TP43.
Max. video gain
GV
Enter SIG3 to (A) and measure the ratio between the output
amplitude (white to black) and input amplitude of TP43.
Y signal frequency
FTRPN0
characteristics
Assume that the output amplitude of
TRAP OFF
MHz
6.0
TP43 when SIG1 (0dB, 100kHz) is
entered to (A) is 0dB. Change the input
FTRPNT
signal frequency to change and
TRAP ON
NTSC
3.0
PAL
3.5
MAX
11
determine the frequency at which the
output amplitude becomes -3dB.
FTRPPL
Picture quality adjustment
GSHP1X
variable amount 1
(TRAP OFF)
Assume that the output amplitude of TP43 when
14
dB
SIG6 (100kHz) is entered in (A) is 0dB. Determine the
GSHP1N
output amplitude ratio of the input SIG6 (2.5MHz).
MIN
-3
GSHP2X
Assume that the output amplitude of TP43 when
MAX
0
180,000 mode
Picture quality adjustment
variable amount 2
(TRAP OFF)
11
14
dB
SIG6 (100kHz) is entered in (A) is 0dB. Determine the
GSHP2N
output amplitude ratio of the input SIG6 (1.8MHz).
MIN
-1
GSHP3X
Assume that the output amplitude of TP43 when
MAX
2
110,000 and 130,000 modes
Picture quality adjustment
variable amount 3
(TRAP ON)
8
11
dB
SIG6 (100kHz) is entered in (A) is 0dB. Determine the
GSHP3N
output amplitude ratio of the input SIG6 (1.8MHz).
MIN
-5
GSHP4X
Assume that the output amplitude of TP43 when
MAX
-2
110,000 and 130,000 modes
Picture quality adjustment
variable amount 4
(TRAP ON)
6
9
dB
SIG6 (100kHz) is entered in (A) is 0dB. Determine the
GSHP4N
output amplitude ratio of the input SIG6 (2.0MHz).
TDYTRN
Enter SIG8 to (A). Measure the delay
MIN
-6
-3
180,000 mode
Y signal input/output delay
rate
TRAP ON
200
300
400
ns
TRAP OFF
250
350
450
ns
time from the input signal 2T pulse
TDYTRP
peak to the peak of TP43 non-inverted
output.
[Color difference signal system]
Parameter
Color difference input color
Symbol
GEXCMX
adjustment
Conditions
Input SIG4 (VL = 0mV) to (A) and SIG1 (0dB,
Ratings
min
typ
+3
Unit
max
+5
dB
100kHz) to (D) and assume that the output
GEXCMN
amplitude (100kHz) of TP40 when COL = 128 is
VCOCOL = 0 is VC2. Assume also that the output
-20
-15
1.0
1.2
dB
amplitude of TP40 when SIG1 is -10dB and COL =
255 is VC1. Calculate as follows :
GEXCMX = 20log (VC1 / VCO) +10
GEXCMN = 20log (VC2 / VC0)
Color difference balance
VEXCBL
Input SIG4 (VL = 0mV) to (A) and SIG1 (0dB,
0.8
100kHz) to (D) and (E). Assume that the output
amplitude (100kHz) of TP40 is VB and that
(100kHz) of TP45 is VR. Calculate as follows :
VEXCBL = VR / VB
Continued on next page.
No.8928-3/26
LV4147W
Continued from preceding page.
Parameter
Symbol
Color difference input balance
GEXRMX
min
typ
Input SIG4 (VL = 0mV) to (A) and SIG1 (-6dB,
Unit
max
-5
-2
dB
100kHz) to (D) and (E). Assume that the output
adjustment R
GEXRMN
Color difference input balance
Ratings
Conditions
GEXBMX
adjustment B
GEXBMN
amplitude (100kHz) of TP45 and that (100kHz) of
TP40 when TINT = 128 are VRO and VB0
respectively. The output amplitude of TP45 and
+2
+3
dB
+2
+3
dB
that of TP40 when TINT=255 are VR1 and VB1
respectively. Assume also that the output
-5
-2
dB
amplitude of TP45 and that of TP40 when TINT = 0
are VR2 and VB2 respectively. Then, calculate as
follows :
GEXRMX = 20log (VR1 / VR0)
GEXRMN = 20log (VR2 / VR0)
GEXBMX = 20log (VB1 / VB0)
GEXBMN = 20log (VB2 / VB0)
G-γ matrix characteristics
VEXGBN
Input SIG4 (VL = 0mV) to (A) and SIG1
NTSC
0.23
0.26
0.29
PAL
0.17
0.20
0.23
0.46
0.51
0.56
(0dB, 100kHz) to (D). Assume that the
output amplitude (100kHz) of TP40 is
VEXGBP
VEXB and that of TP43 is VEXBG.
Calculate as follows ;
VEXGB = VEXBG / VEXB
VEXGR
Input SIG4 (VL = 0mV) to (A) and SIG1 (0dB,
100kHz) to (E). Assume that the output amplitude
(100kHz) of TP45 is VEXR and that of TP43 is
VEXRG. Calculate as follows ;
VEXGR = VEXRG / VEXR
[RGB signal system]
Parameter
RGB signal and PCD output
Symbol
Conditions
VOUT
Enter SIG4 (VL = 0mV) to (A) and adjust BRIGHT
of serial bus to set TP43 output to 3Vp-p. Then,
DC voltage
Ratings
min
3.3
typ
Unit
max
3.5
3.7
V
0
120
mV
measure the DC voltage of TP38, TP40, and
TP43.
RGB signal and PCD output
ΔVOUT
DC voltage difference
Determine the maximum value of difference of
measured values of TP40, TP43, and TP45 of
VOUT as described in the above item.
User brightness change rate
UBRTMX
Measure the change rate of the black level of
2.0
3.0
V
TP40, TP43, and TP45 outputs when SIG2 is
entered to (A) and U-BRT is changed from 128 to
255.
UBRTMN
Measure the change rate of the white level of
-3
-2.0
V
TP40, TP43, and TP45 outputs when SIG2 is
entered to (A) and U-BRT is changed from 128 to
0.
Brightness change rate
BRTMX
Measure the change rate of the black level of
2.0
2.5
V
TP40, TP43, and TP45 outputs when SIG2 is
entered to (A) and BRT is changed from 128 to
255.
BRTMN
Measure the change rate of the white level of
-2.5
-2.0
V
TP40, TP43, and TP45 outputs when SIG2 is
entered to (A) and BRT is changed from 128 to 0.
Antipole output change rate
COMMX
Enter SIG2 to (A), and measure the TP38 output
4.6
Vp-p
amplitude when COM = 255.
COMMN
Enter SIG2 to (A), and measure the TP38 output
1.5
Vp-p
amplitude when COM = 0.
Sub-brightness R change
rates
SBBRTR
Enter SIG4 (VL = 0mV) to (A) and measure the
difference between the black level of TP45 output
±1.3
±1.7
V
when R-BRT = 128 and the black level of output
when R-BRT = 0 and R-BRT = 255.
Continued on next page.
No.8928-4/26
LV4147W
Continued from preceding page.
Parameter
Sub-brightness B change
Symbol
Conditions
SBBRTB
Enter SIG4 (VL = 0mV) to (A) and measure the
difference between the black level of TP40 output
rates
Ratings
min
typ
Unit
max
±1.3
±1.7
-0.6
0
V
when B-BRT = 128 and the black level of output
when B-BRT = 0 and 255.
Gain difference between RGB
ΔGRGB
signals
Determine the level difference of non-inverted
0.6
dB
output amplitude (white to black) of TP40, TP43,
and TP45 when SIG3 is entered to (A).
Sub-contrast R change rate
SBCNTR
Measure the non-inverted output (white to black) of
±2.0
dB
±2.0
dB
TP45 for the non-inverted output (white to black) of
TP43 when SIG3 is entered to (A) and when
R-CNT = 0 and R-CNT = 255.
Sub-contrast B change rate
SBCNTB
Input SIG3 to (A) and measure the difference of
the level for B-CNT = 0 and 255 from the TP40
non-inverted output (white-black) when B-CNT =
128.
RGB inverted/non-inverted
ΔGINV
gain difference
Determine the difference of inverted output
-0.5
0
0.5
dB
300
mV
amplitude for the non-inverted output amplitude
(white to black) of TP40, TP43, and TP45 when
SIG3 is entered to (A).
Black level potential difference
ΔVBL
between RGB signals
Determine the difference between highest and
lowest black levels for inverted and non-inverted
outputs of TP40, TP43, and TP45 when SIG3 is
entered to (A).
Gamma gain
GγL
Enter SIG7 to (A) and set the amplitude (black to
23.0
26.0
29.0
dB
GγM
white) of non-inverted output of TP43 to 3.5Vp-p
12.0
15.0
18.0
dB
18.0
22.0
26.0
dB
0
IRE
GγH
with CONT and set the level to 1.5V through
BRIGHT adjustment.Measure VG1, VG2, and
VG3 and calculated as follows :
GγL = 20log (VG1/0.0357)
GγM = 20log (VG2/0.0357)
GγH = 20log (VG3/0.0357) (See Fig. 5)
γ1 adjustment variable range
Vγ1MN
Enter SIG7 to (A) and set the TP43 output (black to
Vγ1MX
black) to 3Vp-p through BRIGHT adjustment.
100
IRE
100
IRE
Read the γ gain change point at γ1 = 0, γ1 = 255 by
referring to the IRE level of input signal :
Vγ1MN for γ1 = 0
Vγ1MX for γ1 = 255
γ2 adjustment variable range
Vγ2MN
Enter SIG7 to (A) and set the TP43 output (black to
Vγ2MX
black) to 3Vp-p through BRIGHT adjustment.
0
IRE
Read the γ gain change point at γ2 = 0, γ2 = 255
by referring to the IRE level of input signal :
Vγ1MN for γ2 = 0
Vγ1MX for γ2 = 255
PCD transition time
tCOMH
Enter SIG3 to (A) and set the output amplitude of
1.5
3
μs
tCOML
TP38 to 3Vp-p. Measure tCOMH for rise and
1.5
3
μs
tCOML for fall. Load : 20000pF
RGB output whitelimiter level
VWLIMN
Enter SIG2 to (A) and measure the amplitude of
VWLIMX
the white side limiter level of inverted /
4
Vp-p
2.2
Vp-p
non-inverted TP38, 40, 43, and 45 output.
VWLIMX when WLIM = 15 and VWLIMN when
WLIM = 0.
RGB output black limiter
variable range
VBLIMX
Enter SIG2 to (A) and measure the amplitude of
VBLIMN
the black side limiter level of inverted/non-inverted
4.5
Vp-p
2
Vp-p
TP43 output. VBLIMX for BLIM = 255 and VBLIMN
for BLIM = 0
White limiter DC voltage
VWLIM
Enter SIG4 (VL = 0mV) to (A) and measure the DC
voltage of TP40, TP43, and TP45.
3.3
3.5
3.7
V
Black limiter DC voltage
VBLIM
Input SIG4 (VL = 350mV) to (A) and adjust BLIM to
set the output of TP43 and TP40 to 3Vp-p.
3.3
3.5
3.7
V
Measure the DC voltage of TP 40, TP43, and
TP45.
No.8928-5/26
LV4147W
[Filter characteristics]
Parameter
TRAP attenuation amount
Symbol
Ratings
Conditions
min
typ
Unit
max
ATRAPN
Input SIG1 (0dB, 3.58MHz and
NTSC
-15
-20
dB
ATRAPP
4.43MHz) in (A) and measure the TP43
PAL
-15
-20
dB
1.6
1.9
MHz
output with a spectrum analyzer.
Assuming that the TP43 amplitude in
the TRAP ON mode is 0dB, determine
the attenuation in the COMP input
mode.
R-Y, B-Y LPF characteristics
DEMLPF
Input SIG4 (VL = 150mV) in (A) and SIG1
(100kHz) in (B). In this case, assume that the
1.2
amplitude of 100kHz component of TP40, TP45
output is 0dB. Change the SIG1 frequency at
which the output amplitude of TP40, TP45
becomes -3dB.
[Sync separation, TG system]
Parameter
Input sync signal width
Ratings
Symbol
Conditions
WSSEP
Enter SIG4 (VL = 0mV, VS = 143mV, WS variable)
to (A) and confirm synchronization with the TP24
sensitivity
min
typ
Unit
max
μs
2.0
HD output. Narrow WS of SIG5 from 4.7μs and
determine WS at which synchronization between
the input and TP24HD output is lost.
Sync separation input
VSSEP
sensitivity
Enter SIG4 (VL = 0mV, WS = 4.7μs, VS variable)
to (A) and confirm synchronization with the TP24
40
60
mV
HD output. Reduce VS of SIG4 from 143mV and
determine VS at which synchronization between
the input and TP24HD output is lost.
Sync separation output delay
TDSYL
Enter SIG4 (VL = 0mV, WS = 4.7μs, and VS =
300
500
700
ns
rate
TDSYH
143mV) to (A) and measure the delay rate from
4.7
5.0
5.3
μs
TP6RPD output. Assume that TDSYL is for a
period from fall of input HSYNC to fall of RPD
output and that TDSYH is for the period up to rise
of RPD output.
Horizontal pull-in range
HPLLN
Enter SIG4 (VL = 0 mV, WS = 4.7μs,
NTSC
±500
Hz
HPLLP
and VS = 143mV, horizontal frequency
PAL
±500
Hz
variable) to (A) and confirm
synchronization with TP24 HD output.
Change the horizontal frequency of
SIG5 and determine the frequency fH at
which synchronization is established
from the condition in which input / output
synchronization is lost. Calculate as
follows : HPLLN = fH-15734
HPLLP = fH-15625
No.8928-6/26
LV4147W
[External input output characteristics]
Parameter
Symbol
External RGB input threshold
VTEXTB
Conditions
Enter SIG4 (VL = 0mV) to (A) and SIG5
value
(VL variable) to (C), increase the amplitude (VL)
from 0V. Assume that the voltage at which TP40,
VTEXTW
TP43, and TP45 outputs become the black level is
Ratings
min
typ
Unit
max
0.55
0.7
0.85
V
1.62
1.8
1.95
V
VTEXTB. Further increase the amplitude and
assume the voltage at which they become the
white level.
Propagation delay time
TD1EXT
between external RGB outputs
TD2EXT
Enter SIG4 (VL = 0mV) to (A) and SIG5 (VL = 3V)
to (C) and measure the rise delay TD1EXT and fall
50
90
130
ns
70
100
150
ns
0
V
delay TD2EXT of TP40, TP43, and TP45 outputs.
(See Fig. 2)
External RGB output blanking
EXTBK
Enter SIG4 (VL = 0mV) to (A) and SIG5
(VL = 1.0V) to (C) and measure the difference of
TP40, TP43, and TP45 from the black level.
EXTWT
Enter SIG4 (VL = 0mV) to (A) and SIG5
(VL = 2.7V) to (C). Measure the difference of
TP40, Tp43, and TP45 from the black level.
TEXMIN
Enter SIG4 (VL = 0mV) to (A) and SIG5
level
External RGB output white
level
External RGB input minimum
pulse width
3.0
V
150
ns
(VL = 2.7V) to (C) and measure the minimum pulse
width at which TP40, TP43, and TP45 outputs
reach the white side limiter.
Package Dimensions
unit : mm (typ)
3281
9.0
7.0
33
64
17
1
0.4
16
0.18
0.5
32
7.0
49
9.0
48
0.125
0.1
1.55max
(1.35)
(0.5)
SANYO : LQFP64(7X7)
No.8928-7/26
LV4147W
Conditions of setting to measure the electric characteristics
Following settings must be made before measurement of electric characteristics.
Setting 1. System reset
Turn ON SW58 and start V58 from GND in order to perform system reset for MOS block.
(See fig. 1-1.)
The default value is set for the serial bus.
Setting 2. Horizontal AFC adjustment
Enter SIG5 (VL = 0mV) to (A) and adjust VCOADJ so that the width of WL and
WH becomes equal in the TP6 output waveform. (See fig. 1-2.)
(Note) In order to measure the 2MHz or more band for measurement items, such as the Y-system frequency
characteristics or sharpness characteristics, it is necessary to pass through the sample hold circuit
via serial bus.
VDD1, VDD2
V58(RESET)
Tr
Tr > 10μs
Fig.1-1 System reset
SIG5
V-sync
TP6
TP6
Approx.1/2VDD
Fig.1-2 Horizontal AFC adjustment
No.8928-8/26
LV4147W
Electric characteristics measurement method
3V
SIG6
0V
100%
50%
P40, 43, 45
Non-inverted output
TD1EXT
TD2EXT
Fig.2 Delay between external RGB input/output
tTHL
tTLH
90%
10%
Fig.3 Output transition time measurement contitions
ΔT
50%
ΔT
Fig.4 Cross point time difference measurement conditions
White
Non-inverted output
VG3
VG2
3.5V
VG1
Black
1.5V
Input
Fig.5 γ characteristics measurement conditions
No.8928-9/26
LV4147W
Block Diagram
Pin Description
Pin No.
Pin Name
I/O
Pin Description
1
EXTR
I
External digital R input (used also for the test)
2
EXTG
I
External digital G input (used also for the test)
3
EXTB
I
External digital B input (used also for the test)
4
TRAP
O
External trap connection pin
5
VDD1
6
RPD
7
VSS1
Oscillator cell input (3V)
O
Phase comparison output
Oscillator cell GND
8
TEST2
I
Test pin 2
9
TEST3
O
Test pin 3
10
LOAD
I
Load input for serial bus
11
DATA
I
Data input for serial bus
12
SCLK
I
Clock input for serial bus
13
TEST1
I
Test pin 1
14
VDD2
Digital 1 system power supply (3V)
Common
For MONI
For EVF
only
only
○
○
○
○
○
○
○
○
○
○
○
○
○
○
Continued on next page.
No.8928-10/26
LV4147W
Continued from preceding page.
Pin No.
Pin Name
I/O
Pin Description
15
XSTH2
O
EVF H-start reverse phase output
16
STH2
O
EVF H-start output
17
XSTH1
O
Monitor H-start reverse phase output
18
STH1
O
Monitor H-start output
19
CKH4
O
EVF H-clock 2 output
20
CKH3
O
EVF H-clock 1 output
21
CKH2
O
Monitor H-clock 2 output
22
CKH1
O
Monitor H-clock 1 output
23
XDSG
O
Drain hold timing pulse reverse-phase output
24
DSG
O
Drain hold timing pulse output
25
BLHD
O
Backlight HD output
26
HD
O
H drive output
27
XSTV/STV2
O
V-start reverse phase output/EVF V start output
28
STV
O
V start output
29
CKV2/CKV4
O
V clock 2 output/EVF CKV2
30
CKV1/CKV2
O
V clock 1 output/Monitor CKV2
31
VD
O
32
VSS2
33
XENB
O
Enable reverse-phase output
34
ENB
O
Enable output
35
SCAN
O
For scan selection (for monitor)
36
FBCOM
I
37
GNDCOM
38
COMOUT
39
VCCCOM
40
V drive output
Digital 1 system GND
Time constant pin for antipole output DC return
Antipole output gland
O
Antipole output
BOUT
O
B output
41
FBB
I
Time constant pin for B-output DC return
42
GND2
43
GOUT
O
G output
44
FBG
I
Time constant pin for G-output DC return
45
ROUT
O
R output
46
FBR
I
47
VCC2
48
SIGCENT
Antipole output power supply (7V)
Output system ground
Time constant pin for R-output DC return
Output system power supply
I
Output DC level setting pin
Analog 3V power supply
Common
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
-
51
NC
-
52
NC
-
53
BYIN
I
B-Y input
54
RYIN
I
R-Y input
○
○
55
NC
-
56
VREG
O
Reference voltage
○
57
NC
58
RESET
I
System reset
59
YIN
I
Brightness signal input
60
START-UP
I
Power-ON blanking time constant pin
61
SYNCIN
I
Sync input
○
○
○
○
62
VSEPTC
64
GND1
O
Filter F0 adjustment
3V ground
(○)
(○ )
○
○
○
○
○
○
○
○
○
○
○
○
○
○
VCC1
F0ADJ
(○)
(○ )
○
NC
63
only
○
○
50
Time constant and external VD input for vertical sync
For EVF
only
○
○
49
separation
For MONI
○
○
○
No.8928-11/26
LV4147W
Analog pin function description
Pin Name
Pin Voltage
1
EXTR
-
Pin Description
2
EXTG
RGB outputs become the black level when the
3
EXTB
threshold value is about 0.7V for Vth1 and
The external digital signal is entered. All of
about 1.8V for Vth2 and any one of RGB
exceeds Vth1 and become the white level only
for the output in which the input exceeds Vth2.
Connect to the ground when not using.
Equivqlent Circuit
VCC1
25μA
1
2
3
300Ω
GND1
4
TRAP
1.0V
0.7V
50kΩ
Pin No.
External trap pin.
Trap can be inserted into Y-signal by
VCC1
connecting L and C in series to GND when
75μA
1kΩ
TRAP ON is set.
300Ω
4
200μA
GND1
13
TEST1
-
Test pin.
Connect this pin normally to GND for use.
VDD2
100kΩ
20kΩ
13
20kΩ
GND1
35
SCAN
-
100kΩ
Scan select control output pin. Output from
VCC2
the open collector
35
GND2
FBCOM
1.5V
Feedback circuit smoothing capacitor pin for
precharge output DC level control. Because of
high impedance, a capacitor with small
VCC1
1kΩ
leakage is used.
36
GND1
37
GNDCOM
0V
38
COMOUT
VCC2/2
1kΩ
1kΩ
100kΩ
36
1kΩ
Gland of antipole output
Antipole output
VCCCOM
150Ω
38
20Ω
GNDCOM
39
VCCCOM
7V
Power supply for antipole output
Continued on next page.
No.8928-12/26
LV4147W
Continued from preceding page.
Pin Name
Pin Voltage
40
BOUT
VCCC2/2
43
GOUT
45
ROUT
Pin Description
Equivqlent Circuit
RGB primary color signal output.
VCC2
40
43
45
20Ω
20Ω
40μA
Pin No.
GND2
1.5V
1kΩ
Feedback circuit smoothing capacitor pin for
41
FBB
44
FBG
RGB output DC level control.Because of high
46
FBR
impedance, a capacitor with small leakage is
VCC1
used.
1kΩ
41
44
1kΩ
1kΩ
46
1kΩ
100kΩ
GND1
GND2
0V
47
VCC2
7V
48
SIGCENT
VCC2/2
VCC2 ground.
Power supply of output system
Apply external voltage when the signal output
DC voltage is to be used for those other than
VCC2
1/2 VCC2.
48
300Ω
150kΩ
42
150kΩ
GND2
49
VCC1
3.0V
53
BYIN
1.7V
54
RYIN
Analog 3V power supply.
Enter the color difference of R-Y/B-Y.
The clamp level in this case is about 1.7V.
VCC1
53
4kΩ
1kΩ
10kΩ
54
5kΩ
GND1
56
VREG
2.0V
4kΩ
40μA
30μA
Regulator output pin. Connect an external
capacitor of 1μF or more.
VCC1
56
18.5kΩ
GND1
30kΩ
Continued on next page.
No.8928-13/26
LV4147W
Continued from preceding page.
Pin No.
Pin Name
Pin Voltage
58
RESET
-
Pin Description
Equivqlent Circuit
C-MOS circuit reset pin. Normally, connect a
capacitor between this pin and GND during
use.
VDD2
2μA
(Threshold value = 2.0V)
300Ω
58
1kΩ
GND1
59
YIN
1.6V
Y signal input pin. The standard input signal
VCC1
level is 0.5Vp-p (from sync chip to 100%
white).
59
1kΩ
20μA
GND1
60
START-UP
-
Time constant connection pin to set the RGB
output to the black level at power ON.
VDD2
1μA
Connect the pin to VDD2 when not using.
300Ω
(Threshold value = 2.0V)
60
1kΩ
GND1
61
SYNCIN
1.6V
Input pin for sync separation.
VDD2
61
1kΩ
1kΩ
500Ω
GND1
62
VSEPTC
1.7V
Time constant connection pin for vertical sync
separation. (The pin is used also for external
VDD2
12μA
0.6μA
500Ω
VD input.)
1kΩ
62
GND1
63
f0ADJ
1.5V
1kΩ
20μA
20μA
Reference current generation pin for filter.
15kΩ is connected between this pin and GND
VCC1
200Ω
to generate the reference current. (Keep the
5pF
pin open for trap OFF mode.)
500Ω
63
GND1
64
GND1
0V
500Ω
5pF
3V ground.
No.8928-14/26
LV4147W
Digital pin function description
Pin Name
Pin Voltage
5
VDD1
-
Power supply dedicated for VCO.
Equivalent Circuit
6
RPD
-
Phase comparator output.
Pin Description
6
VDDVCO
1kΩ
100kΩ
GND1
7
VSS1
0
Digital ground for VCO.
8
TEST2
-
Test pin.Normally, connect the input side
9
TEST3
(TEST2) to GND during use.
1kΩ 5kΩ 10kΩ
100kΩ
Pin No.
1.5V
VDD1
8
600Ω
9
VSS1
10
LOAD
11
DATA
12
SCLK
-
Serial bus input pin.
VDD2
2kΩ
VSS2
14
VDD2
-
Digital output pin.
15
XSTH2
-
Digital output pin.
16
STH2
17
XSTH1
18
STH1
19
CKH4
20
CKH3
21
CKH2
22
CKH1
23
XDSG
24
DSG
25
BLHD
26
HD
27
XSTV/STV2
28
STV
29
CKV2/CKV4
30
CKV1/CKV2
31
VD
33
XENB
34
ENB
32
VSS2
VDD2
VSS2
O
Digital ground.
No.8928-15/26
2
H-level output voltage
L-level output voltage
Output transition time
Cross point time difference
CKH duty
Contrast characteristics, TYP
Contrast characteristics, MIN
Video max. gain
Y signal frequency
Picture quality variable amount 1
6
7
8
9
10
11
12
13
14
15
18
17
16
H-level input voltage
5
Input signal,
(A) = SIG3
ΔT
GSHP4X
GSHP3N
(A) = SIG6
(A) = SIG6
(A) = SIG6
A
A
A
A
A
(A) = SIG6
GSHP2N
GSHP3X
A
A
(A) = SIG6
(A) = SIG6
A
GSHP2X
GSHP1N
(A) = SIG6
A
(A) = SIG1
FTRPPL
GSHP1X
A
(A) = SIG1
FTRPNT
A
A
A
A
(A) = SIG1
(A) = SIG3
(A) = SIG3
(A) = SIG3
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
2
A
A
A
A
1
FTRPNO
GV
GCNTMN
GCNTTP
(A) = SIG3
(A) = SIG3
tTHL
DTYHC
(A) = SIG3
(A) = SIG3
(A) = SIG3
(A) = SIG3
tTLH
VOL1
VOH1
VIH
(A) = SIG3
(A) = SIG3
IDD2
VIL
(A) = SIG3
(A) = SIG3
(A) = SIG3
(A) = SIG4 (VL = 0mV)
condition, etc.
IDD1
ICC2
ICC1
Symbol
(A) = SIG6
GSHP4N
(TRAP ON) 180,000 mode
Note: PLL must be reset when the panel mode is changed.
variable amount 4
Picture quality adjustment
Picture quality adjustment
variable amount 3
(TRAP ON) 110,000 and
130,000 modes
Picture quality adjustment
variable amount 2
(TRAP OFF) 110,000 and
130,000 modes
(TRAP OFF) 180,000 mode
L-level input voltage
4
Current dissipation
VDD(110,000 and 130,000)
Current dissipation
VDD(180,000)
Current dissipation VCC2
1
3
Current dissipation VCC1
0
Parameter
(Setting 2, horizontal AFC
adjustment)
No.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
3
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
48
SW set
B
B
B
B
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
53
B
B
B
B
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
54
Mode set
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
NT
NT
NT
NT
-
-
-
-
PAL
NT
-
-
-
-
NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
ON
180,000
180,000
110,000
110,000
ON
ON
ON
ON
110,000 OFF
110,000 OFF
180,000 OFF
180,000 OFF
180,000
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ON
180,000
ALL
ALL
ALL
1
1
1
1
1
1
1
1
1
1
1
1
1
ALL
ON
ON
ON
-
-
-
-
-
-
-
-
ON
ON
ON
ON
ON
S/H
180,000 OFF
-
-
-
-
-
-
-
-
-
-
-
180,000
110,000
-
-
-
58 System Panel TRAP
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
TINT
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
COL
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
BRT
128
128
128
128
128
128
128
128
128
128
128
255
0
128
128
128
128
128
128
128
128
128
128
128
128
128
128
CNT
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
R-B
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
B-B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
γ1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
PLL
DAC set
γ2
0
255
0
255
0
255
0
255
128
128
180
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
PIC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BLM1 UBRT RCNT BCNT COM WLIM
LV4147W
No.8928-16/26
Y signal input/output delay rate
Color difference input color
19
20
ΔGRGB
Antipole output change rate
Sub-brightness R change rate
Sub-brightness B change rate
Gain difference between RGB
signals
Sub-contrast R change rate
Sub-contrast B change rate
29
30
31
32
33
34
SBCNTB
SBCNTR
(A) = SIG3
(A) = SIG3
(A) = SIG3
(A) = SIG4
(A) = SIG4
(A) = SIG2
COMMN
SBBRTR
(A) = SIG2
(A) = SIG2
BRTMN
COMMX
(A) = SIG2
BRTMX
RGB inverted/non-inverted gain
ΔGINV
(A) = SIG3
difference
36 Black level potential difference
ΔVBL
(A) = SIG3
between RG signals
Note: PLL must be reset when the panel mode is changed.
35
SBBRTB
User brightness change rate
(A) = SIG2
UBRTMN
28
(A) = SIG2
User brightness change rate
27
(Calculation)
UBRTMX
ΔVOUT
26
(A) = SIG4
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
3
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
RGB output DC voltage
difference
A
VOUT
RGB output DC voltage
25
A
A
(A) = SIG4, (D) = SIG1
VEXGR
A
A
(A) = SIG4, (D) = SIG1
A
VEXGBP
A
A
A
(A) = SIG4, (D) = SIG1
A
A
A
A
A
A
A
A
A
A
A
2
A
A
A
A
A
1
VEXGBN
GEXBMN (A) = SIG4, (D) = (E) = SIG1
GEXBMX (A) = SIG4, (D) = (E) = SIG1
GEXRMN (A) = SIG4, (D) = (E) = SIG1
GEXRMX (A) = SIG4, (D) = (E) = SIG1
G-Y matrix characteristics
adjustment B
Color difference input balance
(A) = SIG4, (D) = SIG1
VEXCBL (A) = SIG4, (D) = (E) = SIG1
GEXCMN
(A) = SIG4, (D) = SIG1
(A) = SIG8
TDYTRP
GEXCMX
(A) = SIG8
condition, etc.
Input signal,
TDYTRN
Symbol
24
23
Color difference input balance
22
adjustment R
Color difference balance
21
adjustment
Parameter
No.
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
48
SW set
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
A
A
A
A
B
B
A
A
A
B
B
53
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
A
B
B
B
B
A
A
A
B
B
B
B
54
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PAL
NT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ON
OFF
58 System Panel TRAP
Mode set
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
S/H
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0
255
0
255
128
128
128
128
128
TINT
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0
255
128
128
COL
128
128
128
128
128
160
160
128
128
0
255
128
128
ADJ
ADJ
128
128
128
128
128
128
128
128
128
128
128
128
BRT
128
128
70
70
128
128
128
128
128
255
255
255
255
128
128
128
128
128
128
128
128
128
128
128
128
128
128
CNT
128
128
128
128
128
128
SET
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
R-B
128
128
128
128
128
SET
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
B-B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
γ1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
γ2
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
PLL
DAC set
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
PIC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
128
128
128
128
128
128
128
128
128
128
128
0
255
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
SET
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
SET
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
64
64
64
64
64
64
64
0
255
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BLM1 UBRT RCNT BCNT COM WLIM
LV4147W
No.8928-17/26
γ2 adjustment variable range
Antipole output transition time
RGB output white limiter
39
40
41
(A) = SIG4, (C) = SIG5
TEXMIN
External RGB input minimum
pulse width
54
55
Note: PLL must be reset when the panel mode is changed.
(A) = SIG4, (C) = SIG5
(A) = SIG4, (C) = SIG5
EXTBK
EXTWT
External RGB output white level
53
(A) = SIG4, (C) = SIG5
(A) = SIG4, (C) = SIG5
TD2EXT
Propagation delay time between TD1EXT
external RGB outputs
(A) = SIG4, (C) = SIG5
VTEXTW
(A) = SIG4, (C) = SIG5
(A) = SIG4
HPLLP
VTEXTB
(A) = SIG4
HPLLN
External RGB output blanking
level
52
External RGB input threshold
51
voltage
Horizontal pull-in range
50
(A) = SIG4
TDSYH
(A) = SIG4
rate
(A) = SIG4
TDSYL
Sync separation output delay
VSSEP
Sync separation input sensitivity
49
(A) = SIG4
WSSEP
48
(A) = SIG4, (D) = (E) = SIG1
DEMLPF
Input sync signal amplitude
sensitivity
47
R-Y, B-Y LPF characteristics
46
(A) = SIG1
(A) = SIG4
(A) = SIG1
TRAP attenuation amount
45
VBLIM
(A) = SIG4
(A) = SIG2
(A) = SIG2
B
B
B
B
B
B
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
3
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
(A) = SIG2
A
(A) = SIG2
ATRAPP
Black limiter DC voltage
44
VWLIM
VBLIMX
VBLIMN
VWLIMX
VWLIMN
A
A
A
A
A
A
A
A
A
2
A
A
(A) = SIG3
(A) = SIG7
Vγ2MX
tCOM
(A) = SIG7
Vγ2MN
(A) = SIG7
Vγ1MX
(A) = SIG7
GγH
(A) = SIG7
(A) = SIG7
Vγ1MN
A
(A) = SIG7
GγL
GγM
A
1
Input signal,
condition, etc.
Symbol
ATRAPN
White limiter DC voltage
variable range
RGB output black limiter
43
42
γ1 adjustment variable range
38
Operating voltage
Gamma gain
Parameter
37
No.
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
48
SW set
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
53
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
54
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
-
-
-
-
-
-
-
PAL
NT
-
-
-
-
-
PAL
NT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ON
ON
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRAP
Mode set
58 System Panel
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
S/H
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
TINT
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
COL
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0
255
0
0
255
255
128
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
BRT
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
60
60
60
60
ADJ
ADJ
ADJ
CNT
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
R-B
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
B-B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
255
0
120
120
120
γ1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
255
0
0
0
210
210
210
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
PLL
DAC set
γ2
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
PIC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADJ
64
255
0
64
64
0
0
0
0
0
0
0
0
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0
0
0
0
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
ADJ
64
64
64
64
64
64
64
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
0
0
15
0
0
0
0
0
0
0
0
0
BLM1 UBRT RCNT BCNT COM WLIM
LV4147W
No.8928-18/26
LV4147W
Input sine wave (1)
SG No.
Sine wave
With/without sine wave video signal
SIG1
(Amplitude, Frequency variable)
150mV
← Value shown in the left 0dB
143mV
SIG2
357mV
143mV
SIG3
150mV
5-step staircase wave
143mV
SIG4
VL amplitude variable
VS variable : 143mV, unless otherwise specified.
VL
WS variable : 4.7μs, unless otherwise specified.
VS
fH variable : NTSC 15.734kHz
PAL 15.625kHz,
WS
unless otherwise specified.
fH
Input sine wave (2)
SG No.
Sine wave
SIG5
30μs
5μs
GND
VL
VL amplitude variable
SYNC
timing
SIG6
75mV
Frequency variable
175mV
143mV
SIG7
10-step staircase wave
357mV
143mV
SIG8
357mV
sin2
2T pulse
143mV
No.8928-19/26
LV4147W
Serial bus communication specifications
(1) Conditions for serial transfer
DATA
D15 D14 D13 D12 D11 D10 D9
ts1
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
th1
50%
SCLK
tw1L
tw1H
LOAD
50%
ts0
Parameter
th0
Symbol
Conditions
min
tw2
typ
max
unit
Serial transfer
Data setup time
Data holdup time
Pulse width
ts0
LOAD setup time to start SCLK.
150
ns
ts1
DATA setup time to start SCLK.
150
ns
th0
LOAD hold time to start SCLK
150
ns
th1
Data hold time to start SCLK.
150
ns
tw1L
SCLK pulse width.
160
ns
tw1H
SCLK pulse width.
160
ns
tw2
LOAD pulse width.
1.0
μs
No.8928-20/26
LV4147W
(2) 3-wave serial format
DATA
SCLK
LOAD
Data length : 16bit
Clock frequency : 3MHz or less
Only when SCLK is input in 16-bit clock while LOAD is in the L period, DATA is accepted at rise of
LOAD.
Note : When SCLK is in 15-bit or 17-bit clock while LOAD is in the L period, DATA is not accepted.
(3) Data output timing
1. Various mode settings
DATA accepted at rise of LOAD is set at fall of the vertical sync signal.
When the data is transmitted several times for the same item, the data immediately before the vertical sync signal
becomes valid.
2. Setting of the electric volume
Concurrently with acceptance of DATA at rise of LOAD, the D/A output data is changed.
No.8928-21/26
LV4147W
(4) Data specifications 1
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Description
Default
○
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Not used
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Not used
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TRAP ON
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
TRAP OFF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Not used
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Not used
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
System changeover NTSC
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
System changeover PAL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
External VSYNC input OFF
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
External VSYNC input ON
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Y/color difference clamp position, pedestal
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Y/color difference clamp position, SYNC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Sample hold phase SHS1
(Note 1)
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Sample hold phase SHS2
(Note 1)
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Sample hold phase SHS3
(Note 1)
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
Sample hold phase ALL through
(Note 1)
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
HD output polarity, positive
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
HD output polarity, negative
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
VD output polarity, positive
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
VD output polarity, negative
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Panel selection 521 × 218 : 110,000 mode
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
Panel selection 557 × 234 : 130,000 mode
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
Panel selection 800 × 225: 180,000 mode
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
For test. Do not set this bit to "1".
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Field overlap method, odd number on even number
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
Field overlap method, even number on odd number
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Normal mode
(Note 6)
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
521×218 (EVF) + 557×234 (monitor) driving
(Note 6-3)
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
BLHD output ON
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
BLHD output Stop
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Normal mode
○
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
For test. Do not set this bit to "1".
×
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
For test. Do not set this bit to "1".
×
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
For test. Do not set this bit to "1".
×
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
Skipping OFF mode for PAL (Indication of no skipping)
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
For test. Do not set this bit to "1".
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
Not used
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
Not used
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
Not used
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
Normal mode
○
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
For test. Do not set this bit to "1".
×
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
For test. Do not set this bit to "1".
×
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
For test. Do not set this bit to "1".
×
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
For test. Do not set this bit to "1".
×
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
Not used
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
For test. Do not set this bit to "1".
×
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
For test. Do not set this bit to "1".
×
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
For test. Do not set this bit to "1".
×
○
○
○
○
○
○
○
○
○
○
○
○
○
Sync generator function, OFF
Sync generator functionON (output other than HD, VD, BLHD, and SPCLK is turned OFF).
×
No.8928-22/26
LV4147W
(4) Data specifications 2
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HC5 HC4 HC3 HC2 HC1
Description
Default
0
0
0
0
0
1
0
0
×
×
×
0
0
0
0
0
1
0
1
×
×
×
H-position setting, 2/fh x 31 steps
(Note 2)
10000
V-position setting, 1H x 4 steps
(Note 3)
010
0
0
0
0
0
1
1
0
×
×
×
0
0
0
0
0
1
1
1
×
×
×
HD6 HD5 HD4 HD3 HD2
HD phase setting, 4/fh x 31 steps
(Note 4)
00000
HW5 HW4 HW3 HW2 HW1
BLHD pulse setting, 2/fh x 31 steps
(Note 5)
10000
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Monitor horizontal inversion, normal scan mode
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
Monitor horizontal inversion, reverse scan mode
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Monitor vertical inversion, normal scan mode
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
Monitor vertical inversion, reverse scan mode
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
EVF horizontal inversion, normal scan mode
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
EVF horizontal inversion, reverse scan mode
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
EVF vertical inversion, normal scan mode
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
EVF vertical inversion, reverse scan mode
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Scan changeover pin, normalSCAN pin : OPEN
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
Scan changeover pin, reverse scanSCAN pin : OPEN
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Not used
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
Not used
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
VCO sensitivity changeover 1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
VCO sensitivity changeover 2
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
VCO sensitivity changeover 3
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
VCO sensitivity changeover 4
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
Monitor scan stop mode
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
1
Monitor display mode
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
EVF scan stop mode
0
0
0
0
1
0
0
1
0
0
0
0
1
1
0
0
EVF display mode
○
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
blanking period CHK/STH stop OFF (NORMAL)
○
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
blanking period CKH/STH stop ON (power save mode)
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
H blanking period CKH stop OFF (NORMAL)
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
H blanking period CKH stop ON (power save mode)
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
Panel connection form MODE 1
(Note 6-1)
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
Panel connection form MODE 2
(Note 6-2)
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
Normal mode
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
For test. Do not set this bit to “1”.
D6
D5
D4
D3
D2
D1
D0
×
×
VP2 VP1 VP0
○
○
○
○
○
○
○
(Note 6-4)
○
(Note 6-4)
○
○
○
×
(4) Data specifications 3 (DAC set)
D15 D14 D13 D12 D11 D10 D9
D8
D7
Description
Default
1
0
0
0
0
0
0
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
TINT adjustment
10000000
1
0
0
0
0
0
0
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
COLOR adjustment
10000000
1
0
0
0
0
0
1
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
BRIGHT adjustment
10010101
1
0
0
0
0
0
1
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
CONTRAST adjustment
10001100
1
0
0
0
0
1
0
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
R-BRIGHT adjustment
10000000
1
0
0
0
0
1
0
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
B-BRIGHT adjustment
10000000
1
0
0
0
0
1
1
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
γ-1 adjustment
01100100
1
0
0
0
0
1
1
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
γ-2 adjustment
00000000
1
0
0
0
1
0
0
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
Antipole output amplitude adjustment
01010000
1
0
0
0
1
0
0
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
R-CONT adjustment
10000000
1
0
0
0
1
0
1
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
B-CONT adjustment
10000000
1
0
0
0
1
0
1
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
BLKLIMT adjustment
10101100
1
0
0
0
1
1
0
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
Not used
00000000
1
0
0
0
1
1
0
1
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
PICTURE adjustment
10000000
1
0
0
0
1
1
1
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
USER-BRIGHT adjustment
10000000
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
VCO adjustment
10000000
1
0
0
0
1
1
1
1
1
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
×
×
×
×
DA3 DA2 DA1 DA0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
WHTLIMT adjustment
0000
Test mode. Do not set this address.
No.8928-23/26
LV4147W
(Note 1) Sample hold phase
S/H pulse timing
CKH1
S/H1
R
S/H4
A
S/H4
S/H2
G
B
B
S/H4
S/H3
C
SH1
Horizontal inversion
Normal scan
SHS2
SHS3
SH1
B
A
C
SH2
through
through
SH3
A
SH4
C
(Note 2) H-Position set
(step 1 = 2×1/fvco)
SH3
Horizontal inversion
SHS1
SH1 : SH pulse for R signal
SH3 : SH pulse for B signal
SH2
SH4
Reverse scan
SHS1
SHS2
SHS3
SH1
B
A
C
through
SH2
A
C
B
C
B
SH3
through
through
Through
B
A
SH4
C
B
A
SH2 : SH pulse for G signal
SH4 : Common SH pulse for RGB signal
: 1/fvco ≈ 90ns <521×218, 557×234 mode>
: 1/fvco ≈ 60ns <881×228 mode>
CLK (fh)
10001(+1)
STH
10000 (Default)
01111 (-1)
Step 1
Step 1
Step 15
Step 16
Center
No.8928-24/26
LV4147W
(Note 3) V-Position set
000
-2H
001
-1H
2H
STV
010
(DEFAULT)
+1H
011
+2H
100
(Note 4) HD phase set
(step 1 = 4×1/fvco)
HSYNC
00000
HD
(Default)
11111
HD
Step 31
(Note 5) BLHD phase set
(step 1 = 2×1/fvco)
00000
Step 16
Approx.6μs
BLHD
10000
Step 15
(Default)
11111
ON/OFF (output L fixed) possible with the serial bus
No.8928-25/26
LV4147W
(Note 6) Output signal by mode
MODE1 (Note 6-1)
Pin No.
MODE2 (Note 6-2)
Normal
Pin symbol
Common For EVF
Normal
For
monitor
Common For EVF
STH1
17
XSTH1
22
CKH1
21
CKH2
28
STV
○
27
XSTV/STV2
○
30
CKV1/CKV2
○
29
CKV2/CKV4
○
34
ENB
33
XENB
24
PCG
23
XPCG
○
○
○
○
16
STH2
15
XSTH2
20
CKH3
19
CKH4
For
monitor
Common For EVF
○
○
○
○
○
○
○
○
18
Scan OFF
(521×218)+ (557×234) (Note 6-3)
○
○
*
○
(STV2)
*
○
(CKV4)
○
○
○
○
○
○
○
○
○
*
(CKV2)
○
*
(CKV4)
○
○
○
○
○
○
○
○
○
○
○
○
(Note 6-4)
For
Motor
EVF
monitor
OFF
OFF
○
○
○
○
○
“L”
←
*
○
(CKV2)
*
“H”
←
“L”
←
“H”
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
“L”
←
“H”
←
“L”
←
“H”
* : Generated with an external inverte
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PS No.8928-26/26