LODEV L8C204JC12 512/1k/2k/4k x 9-bit asynchronous fifo Datasheet

L8C201/202/203/204
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
512/1K/2K/4K x 9-bit Asynchronous FIFO
DEVICES INCORPORATED
FEATURES
DESCRIPTION
❑ First-In/First-Out (FIFO) using
Dual-Port Memory
❑ Advanced CMOS Technology
❑ High Speed — to 10 ns Access Time
❑ Asynchronous and Simultaneous
Read and Write
❑ Fully Expandable by both Word
Depth and/or Bit Width
❑
❑
❑
❑
Empty and Full Warning Flags
Half-Full Flag Capability
Auto Retransmit Capability
Package Styles Available:
• 28-pin Plastic DIP
• 32-pin Plastic LCC
• 28-pin Ceramic Flatpack
The L8C201, L8C202, L8C203, and
L8C204 are dual-port First-In/FirstOut (FIFO) memories. The FIFO
memory products are organized as:
L8C201 — 512 x 9-bit
L8C202 — 1024 x 9-bit
L8C203 — 2048 x 9-bit
L8C204 — 4096 x 9-bit
Each device utilizes a special algorithm
that loads and empties data on a firstin/first-out basis. Full and Empty flags
are provided to prevent data overflow
and underflow. Three additional pins
are also provided to allow for unlimited
expansion in both word size and depth.
Depth Expansion does not result in a
flow-through penalty. Multiple devices
are connected with the data and control
signals in parallel. The active device is
determined by the Expansion In (XI)
and Expansion Out (XO) signals which
are daisy chained from device to
device.
L8C201/202/203/204 BLOCK DIAGRAM
These FIFOs are designed to have the
fastest data access possible. Even in
lower cycle time applications, faster
access time can eliminate timing
bottlenecks as well as leave enough
margin to allow the use of the devices
without external bus drivers.
DATA INPUTS
D8-0
9
W
WRITE
CONTROL
WRITE
POINTER
RAM ARRAY
512 x 9-bit
1K x 9-bit
2K x 9-bit
4K x 9-bit
The read and write operations are
internally sequential through the use
of ring pointers. No address information is required to load and unload
data. The write operation occurs
when the Write (W) signal is LOW.
Read occurs when Read (R) goes
LOW. The nine data outputs go to the
high impedance state when R is
HIGH. Retransmit (RT) capability
allows for reset of the read pointer
when RT is pulsed LOW, allowing for
retransmission of data from the
beginning. Read Enable (R) and Write
Enable (W) must both be HIGH
during a retransmit cycle, and then R
is used to access the data. A Half-Full
(HF) output flag is available in the
single device and width expansion
modes. In the depth expansion
configuration, this pin provides the
Expansion Out (XO) information
which is used to tell the next FIFO that
it will be activated.
The FIFOs are designed for those
applications requiring asychronous
and simultaneous read/writes in
multiprocessing and rate buffer
applications.
READ
POINTER
THREE-STATE
BUFFERS
R
DATA OUTPUTS
Q8-0
READ
CONTROL
RESET
LOGIC
FLAG
LOGIC
XI
EXPANSION
LOGIC
RS
FL/RT
EF
FF
XO/HF
FIFO Products
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L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
RS — Reset
Reset is accomplished whenever the
Reset (RS) input is taken to a LOW
state. During reset, both internal read
and write pointers are set to the first
location. A reset is required after
power-up before a write operation can
take place. Both the Read Enable (R)
and Write Enable (W) inputs must be
in the HIGH state during the window
shown (i.e., tWHSH before the rising
edge of RS) and should not change
until tSHWL after the rising edge of
RS. Hall-Full Flag (HF) will be reset to
high after Reset (RS).
W — Write Enable
The FIFOs can be made to retransmit
data when the Retransmit Enable
control (RT) input is pulsed LOW. A
retransmit operation will set the
internal read pointer to the first location
and will not affect the write pointer.
Read Enable (R) and Write Enable (W)
must be in the HIGH state during
retransmit. This feature is useful when
less than the full memory has been
written between resets. Retransmit will
affect the Half-Full Flag (HF), depending on the relative locations of the read
and write pointers. The retransmit
feature is not compatible with the
Depth Expansion Mode.
BS
To prevent data overflow, the Full
Flag (FF) will go LOW, inhibiting
further write operations. Upon the
completion of a valid read operation,
the Full Flag (FF) will go HIGH after
tRHFH, allowing a valid write to
begin. When the FIFO is full, the
internal write pointer is blocked from
W, so external changes in W will not
affect the FIFO when it is full.
This is a dual-purpose input. In the
Depth Expansion Mode, this pin is
grounded to indicate that it is the first
loaded (see Operating Modes). In the
Single Device Mode, this pin acts as
the retransmit input. The Single
Device Mode is initiated by grounding
the Expansion In (XI).
O
A write cycle is initiated on the falling
edge of this input if the Full Flag (FF)
is not set. Data setup and hold time
must be adhered to with respect to the
rising edge of the Write Enable (W).
Data is stored in the RAM array
sequentially and independently of any
on-going read operation.
FL/RT — First Load/Retransmit
R — Read Enable
O
A read cycle is initiated on the falling
edge of the Read Enable (R) provided
the Empty Flag (EF) is not set. The
data is accessed on a First-In/FirstOut basis, independent of any ongoing write operation. After Read
Enable (R) goes HIGH, the Data
Outputs (D8-0) will return to a high
impedance condition until the next
read operation. When all the data has
been read from the FIFO, the Empty
Flag (EF) will go LOW, allowing the
Outputs
FF — Full Flag
The Full Flag (FF) will go LOW,
inhibiting further write operations,
indicating that the device is full. If the
read pointer is not moved after Reset
(RS), the Full Flag (FF) will go LOW
after 512 writes for the L8C201, 1024
writes for the L8C202, 2048 writes for
the L8C203, and 4096 writes for the
L8C204.
TE
Inputs
“final” read cycle but inhibiting
further read operations with the data
outputs remaining in a high impedance state. Once a valid write operating has been accomplished, the Empty
Flag (EF) will go HIGH after tWHEH
and a valid read can then begin.
When the FIFO is empty, the internal
read pointer is blocked from R so
external changes in R will not affect
the FIFO.
EF — Empty Flag
The Empty Flag (EF) will go LOW,
inhibiting further read operations,
when the read pointer is equal to the
write pointer, indicating that the
device is empty.
XO/HF — Expansion Out/Half-Full Flag
LE
SIGNAL DEFINITIONS
XI — Expansion In
This input is a dual-purpose pin.
Expansion In (XI) is grounded to
indicate an operation in the single
device mode. Expansion In (XI) is
connected to Expansion Out (XO) of
the previous device in the Depth
Expansion or Daisy Chain Mode.
D8-0 — Data Input
Data input signals for 9-bit wide data.
Data has setup and hold time requirements with respect to the rising edge
of W.
This is a dual-purpose output. In the
Single Device Mode, when Expansion
In (XI) is grounded, this output acts as
an indication of a half-full memory.
After half of the memory is filled and
at the falling edge of the next write
operation, the Half-Full Flag (HF) will
be set to LOW and will remain set
until the difference between the write
pointer and read pointer is less than or
equal to one-half of the total memory
of the device. The Half-Full Flag (HF)
is then deasserted by the rising edge
of the read operation.
In the Depth Expansion Mode,
Expansion In (XI) is connected to
Expansion Out (XO) of the previous
device. This output acts as a signal to
the next device in the daisy chain by
providing a pulse to the next device
when the previous device reaches the
last location of memory.
Q8-0 — Data Output
Data outputs for 9-bit wide data. This
data is in a high impedance condition
whenever Read Enable (R) is in a
HIGH state or the device is empty.
FIFO Products
2
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L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
OPERATING MODES
Single Device Mode
A single FIFO may be used when the
application requirements are for the
number of words in a single device.
The FIFOs are in a Single Device
Configuration when the Expansion In
(XI) control input is grounded. In this
mode the Half-Full Flag (HF), which is
an active-low output, is the active
function of the combination pin XO/
HF.
4. External logic is needed to generate
a composite Full Flag (FF) and
Empty Flag (EF). This requires the
ORing of all EFs and ORing of all
FFs (i.e., all must be set to generate
the correct composite FF or EF).
5. The Retransmit (RT) function and
Half-Full Flag (HF) are not available in the Depth Expansion Mode.
Bidirectional Mode
LE
BS
The FIFOs can easily be adapted to
applications where the requirements
are for greater than the number of
words in a single device. Any depth
can be attained by adding additional
FIFOs. The FIFOs operates in the
Depth Expansion configuration when
the following conditions are met:
O
Depth Expansion (Daisy Chain) Mode
TE
Applications which require data
buffering between two systems (each
system capable of read and write
Width Expansion Mode
operations) can be achieved by pairing
Word width may be increased simply FIFOs. Care must be taken to assure
by connecting the corresponding input that the appropriate flag is monitored
control signals of multiple devices.
by each system (i.e., FF is monitored
Status flags (EF, FF, and HF) can be
on the device when W is used; EF is
detected from any one device. Any
monitored on the device when R is
word width can be attained by adding used). Both Depth Expansion and
additional FIFOs. Flag detection is
Width Expansion may be used in this
accomplished by monitoring the FF,
mode.
EF, and HF signals on either (any)
device used in the width expansion
configuration. Do not connect any
output signals together.
1. The first device must be designated
by grounding the First Load (FL)
control input.
O
2. All other devices must have FL in
the HIGH state.
3. The Expansion Out (XO) pin of
each device must be tied to the
Expansion In (XI) pin of the next
device with the last device connecting back to the first.
FIFO Products
3
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L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –0.5 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Temperature Range (Ambient)
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
Supply Voltage
4.5 V ≤ VCC ≤ 5.5 V
4.5 V ≤ VCC ≤ 5.5 V
4.5 V ≤ VCC ≤ 5.5 V
TE
Mode
Active Operation, Commercial
Active Operation, Industrial
Active Operation, Military
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 5)
Symbol
LE
L8C201/202/203/204
Parameter
Test Condition
VOH
Output High Voltage
VCC = 4.5 V, IOH = –2.0 mA
VOL
Output Low Voltage
VCC = 4.5 V, IOL = 8.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
IIX
Input Leakage Current
IOZ
Output Leakage Current
ICC2
Min
Typ
Max Unit
2.4
V
V
2.0
VCC
+0.3
V
–0.5
0.8
V
±1
µA
R ≥ VIH, GND ≤ VOUT ≤ VCC
±10
µA
VCC Current, TTL Inactive
All Inputs = VIH MIN (Note 6)
15
mA
ICC3
VCC Current, CMOS Standby
All Inputs = VCC (Note 12)
5
mA
CIN
Input Capacitance
Ambient Temp = 25°C, VCC = 4.5 V
5
pF
COUT
Output Capacitance
Test Frequency = 1 MHz (Note 9)
7
pF
O
0.4
(Note 3)
O
BS
Ground ≤ VIN ≤ VCC
L8C201/202/203/204-
Symbol
Parameter
Test Condition
40
30
25
20
15
12
10
Unit
ICC1
VCC Current, Active
(Note 5)
90
95
100
110
120
150
180
mA
FIFO Products
4
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L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Commercial and Industrial Operating Range
ASYNCHRONOUS AND RESET TIMING (ns)
L8C201/202/203/204–
25
Min
15
tRLRL
Read Cycle Time (MHz)
tRLQV
Read Low to Output Valid (Access Time)
tRHRL
Read High to Read Low (Notes 8, 9)
10
10
8
5
tRLRH
Read Low to End of Read Cycle (Notes 8, 9)
25
15
12
10
tRHQV
Read High to Output Valid
5
tRHQZ
Read High to Output High Z (Note 14)
tWLWL
Write Cycle Time (Note 9)
tWLWH
Write Low to Write High (Notes 8, 9)
tWHWL
Write High to End of Write Cycle (Notes 8, 9)
tDVWH
Data Valid to Write High (Notes 8, 9)
tWHDX
Write High to Data Change (Notes 8, 9)
tSLSH
Reset Cycle Time (Notes 9, 10)
tSLWL
Reset Low to Write Low (Notes 9, 10)
tWHSH
Write High to Reset High (Notes 9, 10)
tRHSH
Read High to Reset High (Notes 9, 10)
tSHWL
Reset High to Write Low (Notes 9, 10)
tSLEL
Reset Low to Empty Flag Low
tSLHH
Reset Low to Half-Full Flag High
tSLFH
Reset Low to Full Flag High
Min
Max
20
15
Min
5
15
10
5
15
15
35
25
20
15
25
15
12
10
10
10
8
5
15
10
8
8
0
0
0
0
25
15
12
10
35
25
20
15
25
15
12
10
25
15
12
10
10
10
8
5
LE
Max
15
12
TE
5
20
25
15
12
10
25
15
12
10
25
15
12
10
WRITE OPERATION
tRLRL
tRLQV
Q8-0
tRLRH
tRLQV
tRHRL
BS
R
Max
25
25
O
AND
35
Min
10
Parameter
ASYNCHRONOUS READ
Max
12
Symbol
tRHQV
tRHQZ
DATA-OUT VALID
DATA-OUT VALID
tWLWL
tWLWH
tWHWL
W
tDVWH
D8-0
tWHDX
DATA-IN VALID
DATA-IN VALID
O
RESET TIMING
tSLWL
tSLSH
RS
tWHSH
tSHWL
W
tRHSH
R
tSLEL
EF
tSLHH, tSLFH
HF, FF
FIFO Products
5
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Commercial and Industrial Operating Range
FULL/EMPTY FLAG AND RETRANSMIT TIMING (ns)
L8C201/202/203/204–
25
Min
15
Max
Min
12
Parameter
tRLQV
Read Low to Output Valid (Access Time)
25
15
12
10
tRLEL
Read Low to Empty Flag Low
25
15
12
10
tRHFH
Read High to Full Flag High
25
15
12
10
tWHEH
Write High to Empty Flag High
25
15
12
10
tWLFL
Write Low to Full Flag Low
tTLAL
Retransmit Cycle Time
tTLTH
Retransmit Low to End of Retransmit Cycle (Notes 8, 9, 10)
tAHTH
Read/Write High to Retransmit High (Notes 8, 9, 10)
tTHAL
Retransmit High to Read/Write Low (Note 9)
FULL FLAG FROM LAST WRITE TO FIRST READ
IGNORED
WRITE
R
W
tWLFL
FIRST READ
Max
15
Min
12
10
35
25
20
15
25
15
12
10
25
15
12
10
10
10
8
5
ADDITIONAL
READS
Max
ADDITIONAL
WRITES
LE
LAST WRITE
Min
TE
25
Max
10
Symbol
tRHFH
O
FF
EMPTY FLAG FROM LAST READ TO FIRST WRITE
LAST READ
R
BS
W
IGNORED
READ
tRLEL
EF
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
tWHEH
tRLQV
O
DATA
OUT
VALID
VALID
RETRANSMIT
tTLAL
tTLTH
RT
tAHTH
tTHAL
W, R
HF, EF, FF
FLAG VALID
FIFO Products
6
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Commercial and Industrial Operating Range
FULL/HALF-FULL/EMPTY FLAG TIMING (ns)
L8C201/202/203/204–
25
Min
15
tRHFH
Read High to Full Flag High
tEHRH
Read Pulse Width After Empty Flag High
tRHHH
Read High to Half-Full Flag High
25
15
12
10
tWHEH
Write High to Empty Flag High
25
15
12
10
tWLHL
Write Low to Half-Full Flag Low
tFHWH
Write Pulse Width After Full Flag High (Note 9)
R
O
FULL FLAG TIMING
BS
15
15
Min
12
Max
10
10
12
TE
LE
EF
Max
12
25
tWHEH
Min
15
15
25
W
R
Max
25
25
EMPTY FLAG TIMING
FF
Min
10
Parameter
W
Max
12
Symbol
12
10
10
tEHRH
tRHFH
tFHWH
HALF-FULL FLAG TIMING
O
HALF-FULL OR LESS
MORE THAN
HALF-FULL
HALF-FULL OR LESS
W
R
tWLHL
tRHHH
HF
FIFO Products
7
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L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Commercial and Industrial Operating Range
EXPANSION TIMING (ns)
L8C201/202/203/204–
25
Read/Write to Expansion Out Low (Note 11)
25
15
12
12
tAHOH
Read/Write to Expansion Out High (Note 11)
25
15
12
12
tXLXH
Expansion In Pulse Width (Notes 9, 11)
25
15
12
10
tXHXL
Expansion In High to Expansion In Low (Notes 9, 11)
10
10
10
10
tALXL
Read/Write Low to Expansion In Low (Notes 9, 11)
15
12
8
8
EXPANSION OUT
WRITE TO
LAST PHYSICAL
LOCATION
Max
Min
Max
Min
Max
READ FROM
LAST PHYSICAL
LOCATION
LE
R
tALOL
tAHOH
XO
EXPANSION IN
XI
tALXL
tAHOH
tXHXL
WRITE TO
FIRST PHYSICAL
LOCATION
tALXL
READ FROM
FIRST PHYSICAL
LOCATION
O
BS
W
tALOL
O
tXLXH
R
Min
10
tALOL
W
Max
12
Parameter
TE
Min
15
Symbol
FIFO Products
8
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L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Military Operating Range
ASYNCHRONOUS AND RESET TIMING (ns)
L8C201/202/203/204–
40
Min
30
Parameter
tRLRL
Read Cycle Time (MHz)
tRLQV
Read Low to Output Valid (Access Time)
tRHRL
Read High to Read Low (Notes 8, 9)
10
10
10
tRLRH
Read Low to End of Read Cycle (Notes 8, 9)
40
30
20
tRHQV
Read High to Output Valid
5
tRHQZ
Read High to Output High Z (Note 14)
tWLWL
Write Cycle Time (Note 9)
tWLWH
Write Low to Write High (Notes 8, 9)
tWHWL
Write High to End of Write Cycle (Notes 8, 9)
tDVWH
Data Valid to Write High (Notes 8, 9)
tWHDX
Write High to Data Change (Notes 8, 9)
tSLSH
Reset Cycle Time (Notes 9, 10)
tSLWL
Reset Low to Write Low (Notes 9, 10)
tWHSH
Write High to Reset High (Notes 9, 10)
tRHSH
Read High to Reset High (Notes 9, 10)
tSHWL
Reset High to Write Low (Notes 9, 10)
tSLEL
Reset Low to Empty Flag Low
tSLHH
Reset Low to Half-Full Flag High
tSLFH
Reset Low to Full Flag High
AND
50
Max
40
Max
30
5
20
5
TE
LE
Min
30
25
20
15
50
40
30
40
30
20
10
10
10
20
18
12
0
0
0
40
30
20
50
40
30
40
30
20
40
30
20
10
10
10
50
40
30
50
40
30
50
40
30
WRITE OPERATION
tRLRL
tRLQV
Q8-0
tRLRH
tRLQV
tRHRL
BS
R
Min
40
O
ASYNCHRONOUS READ
Max
20
Symbol
tRHQV
tRHQZ
DATA-OUT VALID
DATA-OUT VALID
tWLWL
tWLWH
tWHWL
W
tDVWH
D8-0
tWHDX
DATA-IN VALID
DATA-IN VALID
O
RESET TIMING
tSLWL
tSLSH
RS
tWHSH
tSHWL
W
tRHSH
R
tSLEL
EF
tSLHH, tSLFH
HF, FF
FIFO Products
9
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Military Operating Range
FULL/EMPTY FLAG AND RETRANSMIT TIMING (ns)
L8C201/202/203/204–
40
Min
30
Max
Min
20
Symbol
Parameter
Max
tRLQV
Read Low to Output Valid (Access Time)
40
30
20
tRLEL
Read Low to Empty Flag Low
30
30
20
tRHFH
Read High to Full Flag High
35
30
20
tWHEH
Write High to Empty Flag High
35
30
20
tWLFL
Write Low to Full Flag Low
tTLAL
Retransmit Cycle Time
tTLTH
Retransmit Low to End of Retransmit Cycle (Notes 8, 9, 10)
tAHTH
Read/Write High to Retransmit High (Notes 8, 9, 10)
tTHAL
Retransmit High to Read/Write Low (Note 9)
FULL FLAG FROM LAST WRITE TO FIRST READ
IGNORED
WRITE
R
W
tWLFL
FIRST READ
ADDITIONAL
READS
Max
20
50
40
30
40
30
20
40
30
20
10
10
10
ADDITIONAL
WRITES
LE
LAST WRITE
30
TE
35
Min
tRHFH
O
FF
EMPTY FLAG FROM LAST READ TO FIRST WRITE
LAST READ
IGNORED
READ
R
BS
W
tRLEL
EF
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
tWHEH
tRLQV
O
DATA
OUT
VALID
VALID
RETRANSMIT
tTLAL
tTLTH
RT
tAHTH
tTHAL
W, R
HF, EF, FF
FLAG VALID
FIFO Products
10
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Military Operating Range
FULL/HALF-FULL/EMPTY FLAG TIMING (ns)
L8C201/202/203/204–
40
Min
30
Parameter
tRHFH
Read High to Full Flag High
tEHRH
Read Pulse Width After Empty Flag High
tRHHH
Read High to Half-Full Flag High
50
40
30
tWHEH
Write High to Empty Flag High
35
30
20
tWLHL
Write Low to Half-Full Flag Low
tFHWH
Write Pulse Width After Full Flag High (Note 9)
R
O
FULL FLAG TIMING
BS
R
Max
20
20
40
TE
LE
EF
Min
30
50
tWHEH
Max
30
40
W
FF
Min
35
40
EMPTY FLAG TIMING
W
Max
20
Symbol
30
30
20
tEHRH
tRHFH
tFHWH
HALF-FULL FLAG TIMING
O
HALF-FULL OR LESS
MORE THAN
HALF-FULL
HALF-FULL OR LESS
W
R
tWLHL
tRHHH
HF
FIFO Products
11
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Military Operating Range
EXPANSION TIMING (ns)
L8C201/202/203/204–
40
tALOL
Read/Write to Expansion Out Low (Note 11)
40
30
20
tAHOH
Read/Write to Expansion Out High (Note 11)
40
30
20
tXLXH
Expansion In Pulse Width (Notes 9, 11)
40
30
20
tXHXL
Expansion In High to Expansion In Low (Notes 9, 11)
10
10
10
tALXL
Read/Write Low to Expansion In Low (Notes 9, 11)
10
10
10
EXPANSION OUT
WRITE TO
LAST PHYSICAL
LOCATION
W
Min
Max
Min
Max
READ FROM
LAST PHYSICAL
LOCATION
LE
R
tALOL
tAHOH
XO
EXPANSION IN
XI
tALXL
tAHOH
tXHXL
WRITE TO
FIRST PHYSICAL
LOCATION
tALXL
READ FROM
FIRST PHYSICAL
LOCATION
O
BS
W
tALOL
O
tXLXH
R
Max
20
Parameter
TE
Min
30
Symbol
FIFO Products
12
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
FIGURE 1. FIFO MEMORY (DEPTH EXPANSION) BLOCK DIAGRAM
W
R
XO
EF
FF
9
D 8-0
L8C20X
XI
9
Q 8-0
V CC
FL
XO
FF
9
EMPTY
EF
L8C20X
XI
9
FL
XO
FF
9
9
LE
RS
XI
FL
O
TABLE 1.
EF
L8C20X
TE
FULL
RESET AND RETRANSMIT (SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE)
INPUTS
INTERNAL STATUS
OUTPUTS
RS
RT
XI
Read Pointer
Write Pointer
EF
FF
HF
Reset
0
X
0
Location Zero
Location Zero
0
1
1
Retransmit
1
0
0
Location Zero
Unchanged
X
X
X
Read/Write
1
1
0
Increment
Increment
X
X
X
TABLE 2.
BS
MODE
RESET AND FIRST LOAD TRUTH TABLE (DEPTH EXPANSION/COMPOUND EXPANSION MODE)
INPUTS
INTERNAL STATUS
OUTPUTS
RS
RT
XI
Read Pointer
Write Pointer
EF
FF
Reset First Device
0
0
(1)
Location Zero
Location Zero
0
1
Reset All Others
0
1
(1)
Location Zero Disabled
Location Zero Disabled
0
1
Read/Write
1
(2)
(1)
X
X
X
X
O
MODE
(1) See Figure 1 (Depth Expansion Block Diagram)
(2) Unchanged
FIFO Products
13
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
NOTES
3. This product provides hard clamping of
transient undershoot. Input levels below
ground will be clamped beginning at –0.6 V.
A current in excess of 100 mA is required to
reach –2 V. The device can withstand indefinite operation with inputs as low as –3 V
subject only to power dissipation and bond
wire fusing constraints.
4. “Typical” supply current values are not
shown but may be approximated. At a VCC
of +5.0 V, an ambient temperature of +25°C
and with nominal manufacturing parameters, the operating supply currents will be
approximately 3/4 or less of the maximum
values shown.
R 1 480 Ω
+5 V
OUTPUT
10. When cascading devices, the reset pulse
width must be increased to equal tSLSH +
tSLHH.
11. It is not recommended that Logic Devices and other vendor parts be cascaded
together. The parts are designed to be pinfor-pin compatible but temperature and
voltage compensation may vary from vendor to vendor. Logic Devices can only guarantee the cascading of Logic Devices parts to
other Logic Devices parts.
INCLUDING
JIG AND
SCOPE
R2
255 Ω
30 pF
FIGURE 2b.
12. Tested with output open and RS = FL
= XI = R = W = VCC.
OUTPUT
INCLUDING
JIG AND
SCOPE
13. At any given temperature and voltage
condition, output disable time is less than
output enable time for any given device.
14. Transition is measured ±200 mV from
steady state voltage with specified loading
in Fig. 2b. This parameter is sampled and
not 100% tested.
15. This product is a very high speed device
and care must be taken during testing in
order to realize valid test information. Inadequate attention to setups and procedures
can cause a good part to be rejected as faulty.
Long high-inductance leads that cause supply bounce must be avoided by bringing the
VCC and ground planes directly up to the
contactor fingers. A 0.01 µF high frequency
capacitor is also required between VCC and
ground. To avoid signal reflections, proper
terminations must be used.
R1 480Ω
+5 V
R2
255Ω
5 pF
FIGURE 3.
+3.0 V
GND
90%
10%
<3 ns
90%
10%
<3 ns
O
5. Tested with outputs open and data inputs changing at the specified read and
write cycle rate. The device is neither full or
empty for the test.
FIGURE 2a.
TE
2. The products described by this specification include internal circuitry designed to
protect the chip from damaging substrate
injection currents and accumulations of
static charge. Nevertheless, conventional
precautions should be observed during
storage, handling, and use of these circuits
in order to avoid exposure to excessive electrical stress values.
ments of all parts. Responses from the internal circuitry are specified from the point of
view of the device. Access time, for example, is specified as a maximum since
worst-case operation of any device always
provides data within that time.
LE
1. Maximum Ratings indicate stress specifications only. Functional operation of these
products at values beyond those indicated
in the Operating Conditions table is not
implied. Exposure to maximum rating conditions for extended periods may affect reliability of the tested device.
BS
6. Tested with outputs open in the worst
static input control signal combination (i.e.,
W, R, XI, FL, and RS).
7. These parameters are guaranteed but not
100% tested.
8. Test conditions assume input transition
times of 5 ns or less, reference levels of 1.5 V,
output loading for specified IOL and IOH
plus 30 pF (Fig. 2a), and input pulse levels of
0 to 3.0 V (Fig. 3).
O
9. Each parameter is shown as a minimum
or maximum value. Input requirements are
specified from the point of view of the external system driving the chip. For example,
tRLRH is specified as a minimum since the
external system must supply at least that
much time to meet the worst-case require-
FIFO Products
14
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C201 — ORDERING INFORMATION
28-pin — 0.3" wide
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
Plastic DIP
(P10)
O
Speed
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
TE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LE
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
28-pin — 0.6" wide
Plastic DIP
(P9)
0°C to +70°C — COMMERCIAL SCREENING
ns
ns
ns
ns
L8C201PC25
L8C201PC15
L8C201PC12
L8C201PC10
BS
25
15
12
10
L8C201NC25
L8C201NC15
L8C201NC12
L8C201NC10
–40°C to +85°C — COMMERCIAL SCREENING
ns
ns
ns
ns
L8C201PI25
L8C201PI15
L8C201PI12
L8C201PI10
L8C201NI25
L8C201NI15
L8C201NI12
L8C201NI10
O
25
15
12
10
FIFO Products
15
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C201 — ORDERING INFORMATION
28-pin
4 3
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
5
2 1 32 31 30
29
6
28
7
27
8
9
10
26
Top
View
25
24
11
23
12
22
D6
D7
NC
FL/RT
RS
EF
XO/HF
Q7
Q6
Plastic J-Lead Chip Carrier
(J6)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
Ceramic Flatpack
(M2)
O
Speed
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LE
Q3
Q8
GND
NC
R
Q4
Q5
13
21
14 15 16 17 18 19 20
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
TE
D3
D8
W
NC
VCC
D4
D5
32-pin — 0.490" x 0.590"
0°C to +70°C — COMMERCIAL SCREENING
ns
ns
ns
ns
L8C201JC25
L8C201JC15
L8C201JC12
L8C201JC10
BS
25
15
12
10
–40°C to +85°C — COMMERCIAL SCREENING
25
15
12
10
ns
ns
ns
ns
L8C201JI25
L8C201JI15
L8C201JI12
L8C201JI10
–55°C to +125°C — COMMERCIAL SCREENING
L8C201MM40
L8C201MM30
L8C201MM20
O
40 ns
30 ns
20 ns
–55°C to +125°C — MIL-STD-883 COMPLIANT
40 ns
30 ns
20 ns
L8C201MMB40
L8C201MMB30
L8C201MMB20
FIFO Products
16
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C202 — ORDERING INFORMATION
28-pin — 0.3" wide
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
Plastic DIP
(P10)
O
Speed
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
TE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LE
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
28-pin — 0.6" wide
Plastic DIP
(P9)
0°C to +70°C — COMMERCIAL SCREENING
ns
ns
ns
ns
L8C202PC25
L8C202PC15
L8C202PC12
L8C202PC10
BS
25
15
12
10
L8C202NC25
L8C202NC15
L8C202NC12
L8C202NC10
–40°C to +85°C — COMMERCIAL SCREENING
ns
ns
ns
ns
L8C202PI25
L8C202PI15
L8C202PI12
L8C202PI10
L8C202NI25
L8C202NI15
L8C202NI12
L8C202NI10
O
25
15
12
10
FIFO Products
17
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C202 — ORDERING INFORMATION
28-pin
4 3
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
5
2 1 32 31 30
29
6
28
7
27
8
9
10
26
Top
View
25
24
11
23
12
22
D6
D7
NC
FL/RT
RS
EF
XO/HF
Q7
Q6
Plastic J-Lead Chip Carrier
(J6)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
Ceramic Flatpack
(M2)
O
Speed
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LE
Q3
Q8
GND
NC
R
Q4
Q5
13
21
14 15 16 17 18 19 20
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
TE
D3
D8
W
NC
VCC
D4
D5
32-pin — 0.490" x 0.590"
0°C to +70°C — COMMERCIAL SCREENING
ns
ns
ns
ns
L8C202JC25
L8C202JC15
L8C202JC12
L8C202JC10
BS
25
15
12
10
–40°C to +85°C — COMMERCIAL SCREENING
25
15
12
10
ns
ns
ns
ns
L8C202JI25
L8C202JI15
L8C202JI12
L8C202JI10
–55°C to +125°C — COMMERCIAL SCREENING
L8C202MM40
L8C202MM30
L8C202MM20
O
40 ns
30 ns
20 ns
–55°C to +125°C — MIL-STD-883 COMPLIANT
40 ns
30 ns
20 ns
L8C202MMB40
L8C202MMB30
L8C202MMB20
FIFO Products
18
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C203 — ORDERING INFORMATION
28-pin — 0.3" wide
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
Plastic DIP
(P10)
O
Speed
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
TE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LE
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
28-pin — 0.6" wide
Plastic DIP
(P9)
0°C to +70°C — COMMERCIAL SCREENING
ns
ns
ns
ns
L8C203PC25
L8C203PC15
L8C203PC12
L8C203PC10
BS
25
15
12
10
L8C203NC25
L8C203NC15
L8C203NC12
L8C203NC10
–40°C to +85°C — COMMERCIAL SCREENING
ns
ns
ns
ns
L8C203PI25
L8C203PI15
L8C203PI12
L8C203PI10
L8C203NI25
L8C203NI15
L8C203NI12
L8C203NI10
O
25
15
12
10
FIFO Products
19
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C203 — ORDERING INFORMATION
28-pin
4 3
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
5
2 1 32 31 30
29
6
28
7
27
8
9
10
26
Top
View
25
24
11
23
12
22
D6
D7
NC
FL/RT
RS
EF
XO/HF
Q7
Q6
Plastic J-Lead Chip Carrier
(J6)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
Ceramic Flatpack
(M2)
O
Speed
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LE
Q3
Q8
GND
NC
R
Q4
Q5
13
21
14 15 16 17 18 19 20
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
TE
D3
D8
W
NC
VCC
D4
D5
32-pin — 0.490" x 0.590"
0°C to +70°C — COMMERCIAL SCREENING
ns
ns
ns
ns
L8C203JC25
L8C203JC15
L8C203JC12
L8C203JC10
BS
25
15
12
10
–40°C to +85°C — COMMERCIAL SCREENING
25
15
12
10
ns
ns
ns
ns
L8C203JI25
L8C203JI15
L8C203JI12
L8C203JI10
–55°C to +125°C — COMMERCIAL SCREENING
L8C203MM40
L8C203MM30
L8C203MM20
O
40 ns
30 ns
20 ns
–55°C to +125°C — MIL-STD-883 COMPLIANT
40 ns
30 ns
20 ns
L8C203MMB40
L8C203MMB30
L8C203MMB20
FIFO Products
20
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C204 — ORDERING INFORMATION
28-pin — 0.3" wide
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
Plastic DIP
(P10)
O
Speed
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
TE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LE
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
28-pin — 0.6" wide
Plastic DIP
(P9)
0°C to +70°C — COMMERCIAL SCREENING
ns
ns
ns
ns
L8C204PC25
L8C204PC15
L8C204PC12
L8C204PC10
BS
25
15
12
10
L8C204NC25
L8C204NC15
L8C204NC12
L8C204NC10
–40°C to +85°C — COMMERCIAL SCREENING
ns
ns
ns
ns
L8C204PI25
L8C204PI15
L8C204PI12
L8C204PI10
L8C204NI25
L8C204NI15
L8C204NI12
L8C204NI10
O
25
15
12
10
FIFO Products
21
03/04/99–LDS.8C201/2/3/4-H
L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
L8C204 — ORDERING INFORMATION
28-pin
4 3
5
2 1 32 31 30
29
6
28
7
27
8
9
10
Top
View
26
25
24
11
23
12
22
13
21
14 15 16 17 18 19 20
D6
D7
NC
FL/RT
RS
EF
XO/HF
Q7
Q6
Plastic J-Lead Chip Carrier
(J6)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
Ceramic Flatpack
(M2)
O
Speed
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LE
Q3
Q8
GND
NC
R
Q4
Q5
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
TE
D3
D8
W
NC
VCC
D4
D5
32-pin — 0.490" x 0.590"
0°C to +70°C — COMMERCIAL SCREENING
ns
ns
ns
ns
L8C204JC25
L8C204JC15
L8C204JC12
L8C204JC10
BS
25
15
12
10
–40°C to +85°C — COMMERCIAL SCREENING
25
15
12
10
ns
ns
ns
ns
L8C204JI25
L8C204JI15
L8C204JI12
L8C204JI10
–55°C to +125°C — COMMERCIAL SCREENING
L8C204MM40
L8C204MM30
L8C204MM20
O
40 ns
30 ns
20 ns
–55°C to +125°C — MIL-STD-883 COMPLIANT
40 ns
30 ns
20 ns
L8C204MMB40
L8C204MMB30
L8C204MMB20
FIFO Products
22
03/04/99–LDS.8C201/2/3/4-H