Fujitsu MB91470 32-bit microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16901-2E
32-bit Microcontrollers
CMOS
FR60 MB91470/480 Series
MB91482/F475/F478/F479/F487/
MB91FV470
■ DESCRIPTION
The MB91470/480 series is Fujitsu's general-purpose 32-bit RISC microcontroller, which is designed for
embedded control applications that require high-speed processing performance.
This series uses the FR60 CPU, which is compatible with the FR* family of CPUs.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
■ FEATURES
• FR60 CPU
• 32-bit RISC, load/store architecture, five-stage pipeline
• Operating frequency of 80 MHz (PLL clock multiplied)
• 16-bit fixed-length instructions (basic instructions)
• Instruction execution speed : one instruction per cycle
• Memory-to-memory transfer, bit processing, barrel shift instructions, etc. :
instructions suitable for embedded applications
• Function entry and exit instructions, multi load/store instructions of register contents :
instructions compatible with C language.
• Register interlock function to facilitate assembly-language coding
• Built-in multiplier/instruction-level support
• Signed 32-bit multiplication : 5 cycles
• Signed 16-bit multiplication : 3 cycles
• Interrupts (save PC and PS) : 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instructions compatible with the FR family
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006-2007 FUJITSU LIMITED All rights reserved
MB91470/480 Series
• Built-in Peripheral functions
• Combinations of built-in Flash/ROM and RAM capacities
MB91470 series
MB91480 series
144 pins
Flash memory
product
MASK ROM
product
Flash memory
product
MASK ROM
product
256 Kbytes/16 Kbytes
MB91F475
⎯
⎯
MB91482
384 Kbytes/24 Kbytes
MB91F478
⎯
⎯
⎯
512 Kbytes/32 Kbytes
MB91F479
⎯
MB91F487
⎯
•
•
•
•
•
•
•
•
•
•
•
•
2
100 pins
I/O ports
NMI (Non Maskable Interrupt)
External interrupts
Bit search module (for REALOS)
Function to search for the position of the first bit that has changed from 1 to 0 in a word starting from the MSB
16-bit reload timers
Timing generator
8/16-bit PPG timers
Multi-function timer
• 16-bit free-run Timer
• Input capture (Linked to free-run timer)
• Output compare (Linked to free-run timer)
• A/D start up compare (Linked to free-run timer)
• Wave form generator
Various wave forms are generated by using output compare output, 16-bit PPG timer and 16-bit dead timer.
Base timer
Only one timer function can be selected from the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload timer,
and 16/32-bit PWC timer.
8/16-bit up/down counter
Multi-function serial interface
• Full-duplex double buffer
• With 16-byte FIFO
• Asynchronous (start-stop synchronization) communication, clock synchronous communication, I2C*
standard mode (Max 100 kbps), I2C high-speed mode (selectable various modes at maximum of 400 kbps)
• Selectable parity On/Off
• Each channel has built-in baud rate generator
• Error detection function for parity, frame and overrun errors
• External clock can be used as transfer clock
• With I2C function
8/10-bit A/D Converter (Successive comparison type)
• Resolution
: 8-bit or 10-bit resolution selectable
• Conversion Time : 1.2 µs (minimum conversion time for 33 MHz system clock)
1.2 µs (minimum conversion time for 40 MHz system clock)
(Continued)
MB91470/480 Series
(Continued)
• 12-bit A/D Converter (successive approximation type)
• Resolution
: 12 bits
• Conversion Time : 2.0 µs (minimum conversion time for 33 MHz system clock)
2.2 µs (minimum conversion time for 40 MHz system clock)
• Differential input mode is available.
• Clock monitor
• Peripheral clock (CLKP) divided by 2/4/8/16/32/64/128/256 can be output.
• Multiplication and Addition Calculator
• RAM : Instruction RAM (I-RAM)
256 × 16-bit
Factor RAM (X-RAM)
64 × 32-bit
Variable RAM (Y-RAM)
64 × 32-bit
• High-speed multiplication and addition (seven-stage pipeline processing)
• Product addition (32-bit × 32-bit + 72-bit)
• Operation result is extracted rounded from 72 bits to 32 bits or 72-bit result data reading.
• DMAC (DMA Controller)
• Transfers can be started by software or by interrupts from the built-in peripherals.
• Wild register
• Instructions or data located at a target address can be replaced (in the built-in Flash/ROM area only) .
• External bus interface
• Maximum operating frequency of 40 MHz
• 16-bit address full output (64 Kbytes space) capability
• 8/16-bit data output
• Use of unused data/address pins as general-purpose I/O ports
• Totally independent 3-area chip select outputs that can be set at minimum of 64 Kbytes.
• Support of interface for various memory (SRAM, ROM/Flash)
• Basic bus cycle : 2 cycles
• Automatic wait cycle generator that can be programmed for each area and can insert waits
• External wait cycle using RDY input
• Other Features
• Watchdog timer
• Low-power consumption modes
• Sleep/stop function
• CMOS technologies : 0.18 µm
• Power supply : Single power supply (VCC = 4.0 V to 5.5 V)
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined
by Philips.
3
MB91470/480 Series
■ PRODUCT LINEUP
Characteristics
MB91470/480 series
common EVA
MB91FV470
Pin number
MB91F475 MB91F478
224 pins
MB91F479
144 pins
MB91480 series
MB91F487
MB91482
100 pins
Built-in Flash/ROM
capacity
512 Kbytes
(Flash)
256 Kbytes 384 Kbytes
(Flash)
(Flash)
512 Kbytes
(Flash)
512 Kbytes
(Flash)
256 Kbytes
(ROM)
Built-in RAM
capacity
40 Kbytes
16 Kbytes
32 Kbytes
32 Kbytes
16 Kbytes
External bus
Yes
Yes
⎯
I/O ports
160
113
77
External interrupts
NMI
16 channels
NMI
10 channels
NMI
10 channels
Reload timer
2 channels
2 channels
2 channels
2 units
1 unit
2 units
8-bit × 16 channels
16-bit × 8 channels
8-bit × 8 channels
16-bit × 4 channels
8-bit × 16 channels
16-bit × 8 channels
2 units
1 unit
2 units
Free-run timer
6 channels
3 channels
6 channels
OCU
12 channels
6 channels
12 channels
ICU
8 channels
4 channels
8 channels
A/D activation
compare
6 channels
3 channels
6 channels
Wave form generator
12 channels
6 channels
12 channels
Base timer
6 channels
4 channels
4 channels
Up/down counter
2 channels
1 channel
⎯
6 units
6 units
3 units
8/10-bit
A/D converter
4 channels × 2 units
16 channels × 1 unit
12 channels × 1 unit
4 channels × 2 units
10 channels × 1 unit
12-bit
A/D converter
4 channels × 2 units
4 channels × 2 units
⎯
Clock monitor
1 unit
⎯
1 unit
Multiplication and
addition calculator
1 unit
1 unit
1 unit
DMAC
5 channels
5 channels
5 channels
Wild register
16 channels
16 channels
16 channels
DSU4
⎯
⎯
Timing generator
PPG
Multi-function timer
Multi-function serial
interface
Debug function
4
MB91470 series
24 Kbytes
MB91470/480 Series
■ PACKAGE AND CORRESPONDING PRODUCTS
Series name
MB91470 series
MB91F475
MB91F478
MB91F479
MB91480 series
MB91F487
MB91482
FPT-144P-M12
(LQFP-0.40 mm)
⎯
⎯
BGA-144P-M06
(PFBGA-0.80 mm)
⎯
⎯
Package
FPT-100P-M20
(LQFP-0.50 mm)
⎯
: Supported
Note : For details of each package, refer to “■ PACKAGE DIMENSIONS”.
5
MB91470/480 Series
■ PIN ASSIGNMENT
• LQFP-144 (MB91470 series)
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VSS
P50/CS0X
P37/A15
P36/A14
P35/A13
P34/A12
P33/A11
P32/A10
P31/A09
P30/A08
P27/A07
P26/A06
P25/A05
P24/A04
P23/A03
P22/A02
P21/A01
P20/A00
VCC
VSS
P17/D31
P16/D30
P15/D29
P14/D28
P13/D27
P12/D26
P11/D25
P10/D24
P07/D23
P06/D22
P05/D21
P04/D20
P03/D19
P02/D18
P01/D17
P00/D16
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VCC
PQ0/RTO0
PQ1/RTO1
PQ2/RTO2
PQ3/RTO3
PQ4/RTO4
PQ5/RTO5
VCC
VSS
PP0/IC0
PP1/IC1
PP2/IC2
PP3/IC3
MD2
MD1
MD0
X0
X1
VSS
PP4/CKI0
PP5/DTTI0
C
VSS
VCC
PM0/PPG0
PM1/PPG1
PM2/PPG2
PM3/PPG3
PA2/ADTG2
PA3/ADTG3
PA4/ADTG4
PE0/AN3-0/AN3-0P
PE1/AN3-1/AN3-0N
PE2/AN3-2/AN3-1P
PE3/AN3-3/AN3-1N
AVSS12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCC
P51/CS1X
P52/CS2X
P53/ASX
P54/RDX
P55/WR0X
P56/WR1X
P60/SYSCLK
P61/RDY
PJ0/TIN0
PJ1/TOUT0
PJ2/TIN1
PJ3/TOUT1
PJ4/TIN2
PJ5/TOUT2
PJ6/TIN3
PJ7/TOUT3
VCC
VSS
P80/INT0
P81/INT1
P82/INT2
P83/INT3
P84/INT4/PPG4
P85/INT5/PPG5
P86/INT6/PPG6
P87/INT7/PPG7
P90/INT8
P91/INT9
NMIX
PL0/AIN0
PL1/BIN0
PL2/ZIN0
INITX
VCC
VSS
(FPT-144P-M12)
6
PH5/SOT3
PH4/SIN3
PH3/SCK3
PH2/SOT2
PH1/SIN2
PH0/SCK2
PG5/SOT1
PG4/SIN1
PG3/SCK1
PG2/SOT0
PG1/SIN0
PG0/SCK0
AVSS10
AVRH2
AVCC10
PD3/AN2-11
PD2/AN2-10
PD1/AN2-9
PD0/AN2-8
PC7/AN2-7
PC6/AN2-6
PC5/AN2-5/SOT5
PC4/AN2-4/SIN5
PC3/AN2-3/SCK5
PC2/AN2-2/SOT4
PC1/AN2-1/SIN4
PC0/AN2-0/SCK4
VCC
VSS
PE7/AN4-3/AN4-1N
PE6/AN4-2/AN4-1P
PE5/AN4-1/AN4-0N
PE4/AN4-0/AN4-0P
AVRH4
AVCC12
AVRH3
MB91470/480 Series
• PFBGA-144 (MB91470 series)
(TOP VIEW)
▼ Index
1
2
3
4
5
6
7
8
9
10
11
12
13
A
1
48
47
46
45
44
43
42
41
40
39
38
37
B
2
49
88
87
86
85
84
83
82
81
80
79
36
C
3
50
89
120
119
118
117
116
115
114
113
78
35
D
4
51
90
121
144
143
142
141
140
139
112
77
34
E
5
52
91
122
138
111
76
33
F
6
53
92
123
137
110
75
32
G
7
54
93
124
136
109
74
31
H
8
55
94
125
135
108
73
30
J
9
56
95
126
134
107
72
29
K
10
57
96
127
128
129
130
131
132
133
106
71
28
L
11
58
97
98
99
100
101
102
103
104
105
70
27
M
12
59
60
61
62
63
64
65
66
67
68
69
26
N
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
10
11
12
13
(BGA-144P-M06)
7
MB91470/480 Series
• LQFP-100 (MB91480 series)
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VSS
P85/INT5/PPG5
P84INT4/PPG4
P83/INT3
P82/INT2
P81/INT1
P80/INT0
PJ7/TOUT3
PJ6/TIN3
PJ5/TOUT2
PJ4/TIN2
PJ3/TOUT1
PJ2/TIN1
PJ1/TOUT0
PJ0/TIN0
PH2/SOT2
PH1/SIN2
PH0/SCK2
PG5/SOT1
PG4/SIN1
PG3/SCK1
PG2/SOT0
PG1/SIN0
PG0/SCK0
VCC
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PS0/RTO6
PS1/RTO7
PS2/RTO8
PS3/RTO9
PS4/RTO10
PS5/RTO11
VCC
VCC
VSS
C
PR0/IC4
PR1/IC5
PR2/IC6
PR3/IC7
PR4/CKI1
PR5/DTTI1
MD2
MD1
MD0
X0
X1
VSS
INITX
PA2/ADTG2
VSS
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
P86/INT6/PPG6
P87/INT7/PPG7
P90/INT8/PPG8
P91/INT9/PPG9
NMIX
PM0/PPG0
PM1/PPG1
PM2/PPG2
PM3/PPG3
PF0/CLKPOUT
PP0/IC0
PP1/IC1
PP2/IC2
PP3/IC3
PP4/CKI0
PP5/DTTI0
VSS
VCC
PQ0/RTO0
PQ1/RTO1
PQ2/RTO2
PQ3/RTO3
PQ4/RTO4
PQ5/RTO5
(FPT-100P-M20)
8
VSS
PA1/ADTG1
PA0/ADTG0
PB7/AN1-3
PB6/AN1-2
PB5/AN1-1
PB4/AN1-0
PB3/AN0-3
PB2/AN0-2
PB1/AN0-1
PB0/AN0-0
AVSS10
AVRH2
AVCC10
PD1/AN2-9
PD0/AN2-8
PC7/AN2-7
PC6/AN2-6
PC5/AN2-5
PC4/AN2-4
PC3/AN2-3
PC2/AN2-2
PC1/AN2-1
PC0/AN2-0
VCC
MB91470/480 Series
■ PIN DESCRIPTIONS
Pin no.
MB91470
series
LQFP144
50
51
MB91480
I/O
series Pin name circuit
type*
PFBGA- LQFP144
100
M6
N6
42
43
MD2
MD1
Function
H, K
Mode pin 2
This pin sets the basic operating mode.
Connect this pin to either VCC pin or VSS pin. Use circuit
type K on the Flash memory model.
H, K
Mode pin 1
This pin sets the basic operating mode.
Connect this pin to either VCC pin or VSS pin. Use circuit
type K on the Flash memory model.
Mode pin 0
This pin sets the basic operating mode.
Connect this pin to either VCC pin or VSS pin. Use circuit
type K on the Flash memory model.
52
K5
44
MD0
H, K
53
L6
45
X0
A
Clock (oscillation) input
54
K6
46
X1
A
Clock (oscillation) output
34
L1
48
INITX
I
External reset input
30
J4
6
NMIX
H
NMI (Non Maskable Interrupt) input
109
A12
⎯
110
B12
⎯
111
A11
⎯
112
B11
⎯
113
C12
⎯
114
B10
⎯
115
A10
⎯
116
C11
⎯
117
C10
⎯
D16
P00
D17
P01
D18
P02
D19
P03
D20
P04
D21
P05
D22
P06
D23
P07
D24
P10
C
C
C
C
C
C
C
C
C
Bit 16 of external data bus I/O pin
General-purpose I/O port
Bit 17 of external data bus I/O pin
General-purpose I/O port
Bit 18 of external data bus I/O pin
General-purpose I/O port
Bit 19 of external data bus I/O pin
General-purpose I/O port
Bit 20 of external data bus I/O pin
General-purpose I/O port
Bit 21 of external data bus I/O pin
General-purpose I/O port
Bit 22 of external data bus I/O pin
General-purpose I/O port
Bit 23 of external data bus I/O pin
General-purpose I/O port
Bit 24 of external data bus I/O pin
General-purpose I/O port
(Continued)
9
MB91470/480 Series
Pin no.
MB91470
series
LQFP144
MB91480
I/O
series Pin name circuit
type*
PFBGA- LQFP144
100
118
B9
⎯
119
A9
⎯
120
D10
⎯
121
C9
⎯
122
B8
⎯
123
A8
⎯
124
D9
⎯
127
A7
⎯
128
B7
⎯
129
C7
⎯
130
D7
⎯
131
A6
⎯
132
B6
⎯
133
C6
⎯
134
D6
⎯
135
A5
⎯
D25
P11
D26
P12
D27
P13
D28
P14
D29
P15
D30
P16
D31
P17
A00
P20
A01
P21
A02
P22
A03
P23
A04
P24
A05
P25
A06
P26
A07
P27
A08
P30
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
Function
Bit 25 of external data bus I/O pin
General-purpose I/O port
Bit 26 of external data bus I/O pin
General-purpose I/O port
Bit 27 of external data bus I/O pin
General-purpose I/O port
Bit 28 of external data bus I/O pin
General-purpose I/O port
Bit 29 of external data bus I/O pin
General-purpose I/O port
Bit 30 of external data bus I/O pin
General-purpose I/O port
Bit 31 of external data bus I/O pin
General-purpose I/O port
Bit 0 of external address bus output pin
General-purpose I/O port
Bit 1 of external address bus output pin
General-purpose I/O port
Bit 2 of external address bus output pin
General-purpose I/O port
Bit 3 of external address bus output pin
General-purpose I/O port
Bit 4 of external address bus output pin
General-purpose I/O port
Bit 5 of external address bus output pin
General-purpose I/O port
Bit 6 of external address bus output pin
General-purpose I/O port
Bit 7 of external address bus output pin
General-purpose I/O port
Bit 8 of external address bus output pin
General-purpose I/O port
(Continued)
10
MB91470/480 Series
Pin no.
MB91470
series
LQFP144
MB91480
I/O
series Pin name circuit
type*
PFBGA- LQFP144
100
136
B5
⎯
137
C5
⎯
138
D5
⎯
139
A4
⎯
140
B4
⎯
141
C4
⎯
142
A3
⎯
143
A2
⎯
2
B2
⎯
3
C1
⎯
4
C2
⎯
5
B3
⎯
6
D2
⎯
A09
P31
A10
P32
A11
P33
A12
P34
A13
P35
A14
P36
A15
P37
CS0X
P50
CS1X
P51
CS2X
P52
ASX
P53
RDX
P54
WR0X
C
C
C
C
C
C
C
C
C
C
C
C
C
P55
7
D1
⎯
WR1X
C3
⎯
SYSCLK
P60
Bit 9 of external address bus output pin
General-purpose I/O port
Bit 10 of external address bus output pin
General-purpose I/O port
Bit 11 of external address bus output pin
General-purpose I/O port
Bit 12 of external address bus output pin
General-purpose I/O port
Bit 13 of external address bus output pin
General-purpose I/O port
Bit 14 of external address bus output pin
General-purpose I/O port
Bit 15 of external address bus output pin
General-purpose I/O port
External chip select 0 output
General-purpose I/O port
External chip select 1 output
General-purpose I/O port
External chip select 2 output
General-purpose I/O port
External address strobe output
General-purpose I/O port
External read strobe output
General-purpose I/O port
External write strobe output
Corresponding to bit 31 to bit 24 of external data bus I/O
General-purpose I/O port
C
P56
8
Function
External write strobe output
Corresponding to bit 23 to bit 16 of external data bus I/O
General-purpose I/O port
C
External clock output
General-purpose I/O port
(Continued)
11
MB91470/480 Series
Pin no.
MB91470
series
LQFP144
MB91480
I/O
series Pin name circuit
type*
PFBGA- LQFP144
100
9
D3
⎯
20
G2
94
21
G3
95
22
G4
96
23
H1
97
RDY
P61
INT0
P80
INT1
P81
INT2
P82
INT3
P83
C
D
D
D
D
INT4
24
25
26
27
28
29
⎯
H2
H3
H4
J1
J2
J3
⎯
98
99
2
3
4
5
⎯
PPG4
Function
External ready input
General-purpose I/O port
External interrupt 0 input
General-purpose I/O port
External interrupt 1 input
General-purpose I/O port
External interrupt 2 input
General-purpose I/O port
External interrupt 3 input
General-purpose I/O port
External interrupt 4 input
D
Output of PPG timer 4
P84
General-purpose I/O port
INT5
External interrupt 5 input
PPG5
D
Output of PPG timer 5
P85
General-purpose I/O port
INT6
External interrupt 6 input
PPG6
D
Output of PPG timer 6
P86
General-purpose I/O port
INT7
External interrupt 7 input
PPG7
D
Output of PPG timer 7
P87
General-purpose I/O port
INT8
External interrupt 8 input
PPG8
D
Output of PPG timer 8 (MB91480 series only)
P90
General-purpose I/O port
INT9
External interrupt 9 input
PPG9
D
Output of PPG timer 9 (MB91480 series only)
P91
General-purpose I/O port
INT10
External interrupt 10 input
PPG10
P92
D
Output of PPG timer 10
General-purpose I/O port
(Continued)
12
MB91470/480 Series
Pin no.
MB91470
series
LQFP144
MB91480
I/O
series Pin name circuit
type*
PFBGA- LQFP144
100
INT11
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PPG11
External interrupt 11 input
D
⎯
73
⎯
⎯
74
65
L9
49
66
K9
⎯
67
N10
⎯
⎯
⎯
65
⎯
⎯
66
⎯
⎯
67
Output of PPG timer 11
P93
General-purpose I/O port
INT12
External interrupt 12 input
PPG12
D
Output of PPG timer 12
P94
General-purpose I/O port
INT13
External interrupt 13 input
PPG13
D
Output of PPG timer 13
P95
General-purpose I/O port
INT14
External interrupt 14 input
PPG14
D
Output of PPG timer 14
P96
General-purpose I/O port
INT15
External interrupt 15 input
PPG15
D
P97
⎯
Function
ADTG0
PA0
ADTG1
PA1
ADTG2
PA2
ADTG3
PA3
ADTG4
PA4
AN0-0
PB0
AN0-1
PB1
AN0-2
PB2
Output of PPG timer 15
General-purpose I/O port
D
D
D
D
D
G
G
G
External trigger input of 8/10-bit A/D converter 0
General-purpose I/O port
External trigger input of 8/10-bit A/D converter 1
General-purpose I/O port
External trigger input of 8/10-bit A/D converter 2
General-purpose I/O port
External trigger input of 12-bit A/D converter 3
General-purpose I/O port
External trigger input of 12-bit A/D converter 4
General-purpose I/O port
Analog 0 input of 8/10-bit A/D converter 0
General-purpose I/O port
Analog 1 input of 8/10-bit A/D converter 0
General-purpose I/O port
Analog 2 input of 8/10-bit A/D converter 0
General-purpose I/O port
(Continued)
13
MB91470/480 Series
Pin no.
MB91470
series
LQFP144
MB91480
I/O
series Pin name circuit
type*
PFBGA- LQFP144
100
⎯
⎯
68
⎯
⎯
69
⎯
⎯
70
⎯
⎯
71
⎯
⎯
72
AN0-3
PB3
AN1-0
PB4
AN1-1
PB5
AN1-2
PB6
AN1-3
PB7
G
G
G
G
G
AN2-0
82
J12
52
SCK4
G
53
SIN4
G
54
SOT4
G
55
SCK5
G
56
SIN5
G
57
SOT5
J10
58
AN2-6
PC6
Clock I/O of multi-function serial interface 4 (not used in I2C
mode) (MB91470 series only)
Data input of multi-function serial interface 4 (not used in
I2C mode) (MB91470 series only)
Data output of multi-function serial interface 4
(MB91470 series only)
Clock I/O of multi-function serial interface 5
(MB91470 series only)
Data input of multi-function serial interface 5 (not used in
I2C mode) (MB91470 series only)
Analog 5 input of 8/10-bit A/D converter 2
G
PC5
88
General-purpose I/O port
General-purpose I/O port
AN2-5
H13
Analog 3 input of 8/10-bit A/D converter 1
Analog 4 input of 8/10-bit A/D converter 2
PC4
87
General-purpose I/O port
General-purpose I/O port
AN2-4
H12
Analog 2 input of 8/10-bit A/D converter 1
Analog 3 input of 8/10-bit A/D converter 2
PC3
86
General-purpose I/O port
General-purpose I/O port
AN2-3
J11
Analog 1 input of 8/10-bit A/D converter 1
Analog 2 input of 8/10-bit A/D converter 2
PC2
85
General-purpose I/O port
General-purpose I/O port
AN2-2
K10
Analog 0 input of 8/10-bit A/D converter 1
Analog 1 input of 8/10-bit A/D converter 2
PC1
84
General-purpose I/O port
General-purpose I/O port
AN2-1
J13
Analog 3 input of 8/10-bit A/D converter 0
Analog 0 input of 8/10-bit A/D converter 2
PC0
83
Function
Data output of multi-function serial interface 5
(MB91470 series only)
General-purpose I/O port
G
Analog 6 input of 8/10-bit A/D converter 2
General-purpose I/O port
(Continued)
14
MB91470/480 Series
Pin no.
MB91470
series
LQFP144
MB91480
I/O
series Pin name circuit
type*
PFBGA- LQFP144
100
89
H11
59
90
H10
60
91
G13
61
92
G12
⎯
93
G11
⎯
68
M10
⎯
AN2-7
PC7
AN2-8
PD0
AN2-9
PD1
AN2-10
PD2
AN2-11
PD3
AN3-0/
AN3-0P
G
G
G
G
G
G
PE0
69
L10
⎯
AN3-1/
AN3-0N
70
N11
⎯
G
71
N12
⎯
G
76
L12
⎯
G
77
M11
⎯
PE5
General-purpose I/O port
Analog 9 input of 8/10-bit A/D converter 2
General-purpose I/O port
Analog 10 input of 8/10-bit A/D converter 2
General-purpose I/O port
Analog 11 input of 8/10-bit A/D converter 2
General-purpose I/O port
12-bit A/D converter 3 analog 0 input (in single input mode)
12-bit A/D converter 3 analog 0 ( + ) side input (in differential
input mode)
12-bit A/D converter 3 analog 1 input (in single input mode)
12-bit A/D converter 3 analog 0 ( − ) side input (in differential
input mode)
12-bit A/D converter 3 analog 2 input (in single input mode)
12-bit A/D converter 3 analog 1 ( + ) side input (in differential
input mode)
12-bit A/D converter 3 analog 3 input (in single input mode)
12-bit A/D converter 3 analog 1 ( − ) side input (in differential
input mode)
General-purpose I/O port
G
PE4
AN4-1/
AN4-0N
Analog 8 input of 8/10-bit A/D converter 2
General-purpose I/O port
PE3
AN4-0/
AN4-0P
General-purpose I/O port
General-purpose I/O port
PE2
AN3-3/
AN3-1N
Analog 7 input of 8/10-bit A/D converter 2
General-purpose I/O port
PE1
AN3-2/
AN3-1P
Function
12-bit A/D converter 4 analog 0 input (in single input mode)
12-bit A/D converter 4 analog 0 ( + ) side input (in differential
input mode)
General-purpose I/O port
G
12-bit A/D converter 4 analog 1 input (in single input mode)
12-bit A/D converter 4 analog 0 ( − ) side input (in differential
input mode)
General-purpose I/O port
(Continued)
15
MB91470/480 Series
Pin no.
MB91470
series
LQFP144
78
MB91480
I/O
series Pin name circuit
type*
PFBGA- LQFP144
100
K12
⎯
AN4-2/
AN4-1P
G
PE6
79
K13
⎯
AN4-3/
AN4-1N
⎯
⎯
11
12-bit A/D converter 4 analog 2 input (in single input mode)
12-bit A/D converter 4 analog 1 ( + ) side input (in differential
input mode)
General-purpose I/O port
G
PE7
CLKPOUT
Function
12-bit A/D converter 4 analog 3 input (in single input mode)
12-bit A/D converter 4 analog 1 ( − ) side input (in differential
input mode)
General-purpose I/O port
D
PF0
Clock monitor output
General-purpose I/O port
⎯
⎯
⎯
PF1
D
General-purpose I/O port
⎯
⎯
⎯
PF2
D
General-purpose I/O port
⎯
⎯
⎯
PF3
D
General-purpose I/O port
⎯
⎯
⎯
PF4
D
General-purpose I/O port
⎯
⎯
⎯
PF5
D
General-purpose I/O port
⎯
⎯
⎯
PF6
D
General-purpose I/O port
⎯
⎯
⎯
PF7
D
General-purpose I/O port
97
F11
77
98
F10
78
SCK0
PG0
SIN0
D
D
PG1
99
E13
79
100
E12
80
101
E11
81
SOT0
PG2
SCK1
PG3
SIN1
E10
82
103
D13
83
SOT1
PG5
SCK2
PH0
General-purpose I/O port
Data input of multi-function serial interface 0 (not used in I2C
mode)
General-purpose I/O port
D
D
D
PG4
102
Clock I/O of multi-function serial interface 0
Data output of multi-function serial interface 0
General-purpose I/O port
Clock I/O of multi-function serial interface 1
General-purpose I/O port
Data input of multi-function serial interface 1 (not used in I2C
mode)
General-purpose I/O port
D
D
Data output of multi-function serial interface 1
General-purpose I/O port
Clock I/O of multi-function serial interface 2
General-purpose I/O port
(Continued)
16
MB91470/480 Series
Pin no.
MB91470
series
LQFP144
104
MB91480
I/O
series Pin name circuit
type*
PFBGA- LQFP144
100
D12
84
SIN2
D
PH1
105
D11
85
106
C13
⎯
107
B13
⎯
SOT2
PH2
SCK3
PH3
SIN3
A13
⎯
10
E2
86
11
E1
87
12
D4
88
13
E3
89
14
F2
90
15
F1
91
16
E4
92
17
F3
93
31
K1
⎯
32
K2
⎯
SOT3
PH5
TIN0
PJ0
TOUT0
PJ1
TIN1
PJ2
TOUT1
PJ3
TIN2
PJ4
TOUT2
PJ5
TIN3
PJ6
TOUT3
PJ7
AIN0
PL0
BIN0
PL1
Data input of multi-function serial interface 2 (not used in
I2C mode)
General-purpose I/O port
D
D
D
PH4
108
Function
Data output of multi-function serial interface 2
General-purpose I/O port
Clock I/O of multi-function serial interface 3
General-purpose I/O port
Data input of multi-function serial interface 3 (not used in
I2C mode)
General-purpose I/O port
D
D
D
D
D
D
D
D
D
D
D
Data output of multi-function serial interface 3
General-purpose I/O port
Base timer 0 input
General-purpose I/O port
Base timer 0 output
General-purpose I/O port
Base timer 1 input
General-purpose I/O port
Base timer 1 output
General-purpose I/O port
Base timer 2 input
General-purpose I/O port
Base timer 2 output
General-purpose I/O port
Base timer 3 input
General-purpose I/O port
Base timer 3 output
General-purpose I/O port
8/16-bit up count input pin for up/down counter 0
General-purpose I/O port
8/16-bit down count input pin for up/down counter 0
General-purpose I/O port
(Continued)
17
MB91470/480 Series
Pin no.
MB91470
series
LQFP144
MB91480
I/O
series Pin name circuit
type*
PFBGA- LQFP144
100
33
K3
⎯
61
L8
7
62
K8
8
63
N9
9
64
M9
10
46
M5
12
47
N5
13
48
K4
14
49
L5
15
56
M7
16
57
L7
17
ZIN0
PL2
PPG0
PM0
PPG1
PM1
PPG2
PM2
PPG3
PM3
IC0
PP0
IC1
PP1
IC2
PP2
IC3
PP3
CKI0
PP4
DTTI0
D
D
D
D
D
D
D
D
D
D
D
PP5
38
M2
20
39
N3
21
40
M3
22
41
L2
23
RTO0
PQ0
RTO1
PQ1
RTO2
PQ2
RTO3
PQ3
Function
8/16-bit reset input pin for up/down counter 0
General-purpose I/O port
Output of PPG timer 0
General-purpose I/O port
Output of PPG timer 1
General-purpose I/O port
Output of PPG timer 2
General-purpose I/O port
Output of PPG timer 3
General-purpose I/O port
Trigger input of input capture 0
General-purpose I/O port
Trigger input of input capture 1
General-purpose I/O port
Trigger input of input capture 2
General-purpose I/O port
Trigger input of input capture 3
General-purpose I/O port
External clock input pin of free-run timer ch.0 to ch.2
General-purpose I/O port
Input signal controlling wave form generator outputs RTO0
to RTO5 of multi-function timer 0
General-purpose I/O port
J
J
J
J
Wave form generator output of multi-function timer 0
General-purpose I/O port
Wave form generator output of multi-function timer 0
General-purpose I/O port
Wave form generator output of multi-function timer 0
General-purpose I/O port
Wave form generator output of multi-function timer 0
General-purpose I/O port
(Continued)
18
MB91470/480 Series
(Continued)
Pin no.
MB91470
series
LQFP144
MB91480
I/O
series Pin name circuit
type*
PFBGA- LQFP144
100
42
M4
24
43
N4
25
⎯
⎯
36
⎯
⎯
37
⎯
⎯
38
⎯
⎯
39
⎯
⎯
40
⎯
⎯
41
RTO4
PQ4
RTO5
PQ5
IC4
PR0
IC5
PR1
IC6
PR2
IC7
PR3
CKI1
PR4
DTTI1
J
J
D
D
D
D
D
D
PR5
⎯
⎯
26
⎯
⎯
27
⎯
⎯
28
⎯
⎯
29
⎯
⎯
30
⎯
⎯
31
RTO6
PS0
RTO7
PS1
RTO8
PS2
RTO9
PS3
RTO10
PS4
RTO11
PS5
Function
Wave form generator output of multi-function timer 0
General-purpose I/O port
Wave form generator output of multi-function timer 0
General-purpose I/O port
Trigger input of input capture 4
General-purpose I/O port
Trigger input of input capture 5
General-purpose I/O port
Trigger input of input capture 6
General-purpose I/O port
Trigger input of input capture 7
General-purpose I/O port
External clock input pin of free-run timer ch.3 to ch.5
General-purpose I/O port
Input signal controlling wave form generator outputs RTO6
to RTO11 of multi-function timer 1
General-purpose I/O port
J
J
J
J
J
J
Wave form generator output of multi-function timer 1
General-purpose I/O port
Wave form generator output of multi-function timer 1
General-purpose I/O port
Wave form generator output of multi-function timer 1
General-purpose I/O port
Wave form generator output of multi-function timer 1
General-purpose I/O port
Wave form generator output of multi-function timer 1
General-purpose I/O port
Wave form generator output of multi-function timer 1
General-purpose I/O port
* : Refer to “■ I/O CIRCUIT TYPE” for I/O circuit type.
19
MB91470/480 Series
Power supply pins and GND pins
Pin number
MB91470
series
20
MB91480
series Pin name
Function
LQFP144
PFBGA144
LQFP100
1
18
35
37
44
60
81
126
B1
F4
M1
N2
L3
M8
K11
D8
⎯
1
19
32
33
51
76
⎯
VCC
Power supply pins
Connect all pins to the same potential.
19
36
45
55
59
80
125
144
A1
G1
N1
L4
N7
N8
L11
C8
⎯
18
34
47
50
75
100
⎯
VSS
GND pins
Connect all pins to the same potential.
58
K7
35
C
94
G10
62
AVCC10 Analog power supply pin for 8/10-bit A/D converter 0/1/2
96
F12
64
AVSS10 Analog GND pin for 8/10-bit A/D converter
74
M12
⎯
AVCC12 Analog power supply pin for 12-bit A/D converter 3/4
72
N13
⎯
AVSS12 Analog GND pin for 12-bit A/D converter 3/4
⎯
⎯
⎯
AVRH0
Analog reference power supply pin for 8/10-bit A/D converter 0
⎯
⎯
⎯
AVRH1
Analog reference power supply pin for 8/10-bit A/D converter 1
95
F13
63
AVRH2
Analog reference power supply pin for 8/10-bit A/D converter 2
73
M13
⎯
AVRH3
Analog reference power supply pin for 12-bit A/D converter 3
75
L13
⎯
AVRH4
Analog reference power supply pin for 12-bit A/D converter 4
Capacitor coupling pin for internal regulator
MB91470/480 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1
Clock input
A
Oscillation feedback resistance for
high speed (main clock oscillation)
approx. 1 MΩ
X0
Standby control
P-ch
Pull-up control
• CMOS level output
• CMOS level input
Digital output
• With standby control
• With pull-up control
P-ch
C
Digital output
N-ch
R
Digital input
Standby control
P-ch
Pull-up control
• CMOS level output
• CMOS level hysteresis input
Digital output
• With standby control
• With pull-up control
P-ch
D
Digital output
R
N-ch
Digital input
Standby control
(Continued)
21
MB91470/480 Series
Type
Circuit
Remarks
Pull-up control
Digital output
P-ch
P-ch
G
Digital output
N-ch
R
• Analog/CMOS level hysteresis I/O pin
• CMOS level output
• CMOS level hysteresis input
(with standby control)
• Analog input
(Operates as an analog input when the
corresponding AICR register bit is “1”.)
• With pull-up control
Digital input
Standby control
Analog input
• CMOS level hysteresis input
• Without standby control
P-ch
H
N-ch
R
Digital input
• CMOS level hysteresis input
P-ch
• Without standby control
• With pull-up resistance
P-ch
I
R
N-ch
Digital input
(Continued)
22
MB91470/480 Series
(Continued)
Type
Circuit
P-ch
Remarks
Pull-up control
• CMOS level output
• CMOS level hysteresis input
Digital output
• With standby control
• With pull-up control
P-ch
Digital output
J
N-ch
R
Digital input
Standby control
Flash memory product only
• CMOS level input
• High voltage control for testing Flash
memory
N-ch
N-ch
N-ch
K
Control signal
N-ch
N-ch
R
Mode input
23
MB91470/480 Series
■ HANDLING DEVICES
• Preventing latch-up
Latch-up phenomenon may occur with CMOS IC, when a voltage higher than VCC or lower than VSS is applied
to either the input or output terminals, or when a voltage is applied between VCC pin and VSS pin that exceeds the
rated voltage. When latch-up occurs, a significant power-supply current surge results, which may damage some
elements due to the excess heat, so great care must be taken to ensure that the maximum rating is never
exceeded during use.
• Treatment of unused input pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a
pull-up or pull-down resistor.
• Power pins
In products with multiple VCC and VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to the same potential power
supply and a ground line externally to lower the electro-magnetic emission level, to prevent abnormal operation
of strobe signals caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between VCC
and VSS near this device.
• Crystal oscillator circuit
Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that X0,
X1, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the
device as possible.
It is strongly recommended to design the PC board artwork with the X0 and X1pins surrounded by ground plane
because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate the
oscillational characteristics of the crystal and this device.
• About mode pins (MD0 to MD2)
These pins should be connected directly to VCC pin or VSS pin.
To prevent the device erroneously switching to test mode due to noise, the pattern length between each mode
pins and VCC or VSS on the printed circuit board should be as short as possible, and they should be connected
at low impedance.
• Operation at start-up
Be sure to execute setting initialized reset (INIT) with INITX pin immediately after start-up.
Immediately after that, also, hold the "L"-level input to the INITX pin for the stabilization wait time required for the
oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit and the stabilization wait
time for the regulator (For INIT via the INITX pin, the oscillation stabilization wait time setting is initialized to the
minimum value).
24
MB91470/480 Series
• Notes upon power-on sequence
It requires more than 600 µs (between 0.0 V to 5.0 V) to rise voltage upon power on in order to prevent the
device malfunction caused by the overshooting in the built-in voltage step-down circuit.
After the supply voltage is stable (voltage is risen) , it takes 600 µs until internal supply is stable. Hold the input
to the INITX pin during that period.
If it takes less than 600 µs (between 0.0 V to 5.0 V) for power up, it requires 2 ms* until internal supply is stable
after voltage supply is stable (voltage is risen) . Hold the input to the INITX pin during that period.
CASE : voltage rising time is more than 600 µs (0.0 V to 5.0 V)
VCC (V)
5.0
0
600 (µs)
t
Hold for more than 600 µs
INITX
Internal power supply
waits until stable
Power-on
Start operating
CASE : voltage rising time is less than 600 µs (0.0 V to 5.0 V)
VCC (V)
5.0
0
600 (µs)
t
Hold for more than 2 ms*
INITX
Power-on
Internal power supply
waits until stable
Start operating
* : In case of which it takes less than 600 µs (between 0.0 V to 5.0 V) to rise voltage, the time to make internal
power supply stable is proportional to the capacitance value of the bypass capacitor for the pin C.
It takes 2 ms if the pin C = 4.7 µF ; 4 ms if the pin C = 9.4 µF.
25
MB91470/480 Series
• Order of power turning ON/OFF
Use the following procedure for turning the power on or off. If not using the A/D converter, connect AVCC =VCC
and AVSS = VSS. Turn on the power supply in the sequence VCC → AVCC → AVRH, and turn off the power in
the reverse sequence.
• Source oscillation input when turning on the power
When turning the power on, maintain the clock input until the device is released from the oscillation stabilization
wait state.
• Cautions for operation during PLL clock mode
Even if the oscillator comes off or the clock input stops with the PLL clock selected for MB91470/480 series,
MB91470/480 series may continue to operate at the free-run frequency of the PLL’s internal self-oscillating
oscillator circuit.
Performance of this operation, however, cannot be guaranteed.
• Using an external clock
When using an external clock, you must always input clock signals with opposite phase from X0 pin to X1 pin
simultaneously. However, as the X1 pin halts with an output at the "H" level during stop mode, insert a resistor
of approximately 1 kΩ externally to prevent a conflict between the two outputs if using stop mode (oscillation
stop mode).
The figure below shows an example of how to use an external clock.
• Example of Using an External Clock
X0
MB91470/480
series
X1
• C pin
As MB91470/480 series includes an internal regulator, always connect a bypass capacitor of approximately
4.7 µF to the C pin for use by the regulator.
MB91470/480
series
C
4.7 µF
VSS
GND
• Software reset on the synchronous mode
Be sure to meet the following two conditions before setting 0 to the SRST bit of STCR (standby control register)
when the software reset is used on the synchronous mode.
• Set the interrupt enable flag (I-Flag) to interrupts disabled (I-Flag=0).
• Not used NMI
26
MB91470/480 Series
■ BLOCK DIAGRAM
•MB91470 series (144 pins)
VCC
VSS
C
FR60 CPU core
Downconversion
circuit
Watchdog
timer
32
Bit search
Flash/ROM
(Max 512 Kbytes)
32
MAC
D-bus RAM
(Max 28 Kbytes)
F-bus RAM
(Max
4 Kbytes)
DMAC 5 channels
Bus converter
32
32
SYSCLK
MD2 to MD0
INITX
X0
X1
32 ↔ 16
adapter
3 channels
external
bus
I/F
Clock control
16
NMIX
INT0 to INT9
SCK0 to SCK5
SIN0 to SIN5
SOT0 to SOT5
1+10
channels
external interrupt
6 channels
multi-function
serial interface
AVRH2
ADTG2
AN2-0 to AN2-11
12 channels input
8/10-bit
A/D converter 2
4 channels input
12-bit A/D converter 3
AVRH4
ADTG4
AN4-0 to AN4-3
4 channels input
12-bit A/D converter 4
TOUT0 to TOUT3
CS0X to CS2X
RDX
WR0X, WR1X
RDY
Interrupt
controller
Port I/F
1 channel
up/down
counter
8 channels
PPG
GPIO
AIN0
BIN0
ZIN0
2 channels
reload timer
PPG0 to
PPG7
Multi-function timer
AVCC12
AVSS12
AVRH3
ADTG3
AN3-0 to AN3-3
TIN0 to TIN3
ASX
16
1 unit
timing generator
AVCC10
AVSS10
A15 to A00
D31 to D16
4 channels
base timer
-PWC
-Reload timer
-PWM
-PPG
3 channels
A/D activating
compare
4 channels
input capture
IC0 to IC3
3 channels
free-run timer
CKI0
6 channels
output compare
6 channels
wave form
generator
RTO0 to RTO5
DTTI0
27
MB91470/480 Series
• MB91480 series (100 pins)
VCC
VSS
C
Watchdog
timer
FR60 CPU core
Downconversion
circuit
32
Bit search
Flash/ROM
(Max
512 Kbytes)
F-bus RAM
(Max
4 Kbytes)
32
MAC
D-bus RAM
(Max 28 Kbytes)
Bus converter
DMAC 5 channels
32
32
MD2 to MD0
INITX
X0
X1
32 ↔ 16
adapter
Clock
control
16
NMIX
INT0 to INT9
SCK0 to SCK2
SIN0 to SIN2
SOT0 to SOT2
1+10 channels
external interrupt
3 channels
multi-function
serial interface
16
Clock monitor
Interrupt
controller
Port I/F
2 units
timing generator
AVCC10
AVSS10
16 channels
PPG
2 channels
reload timer
AVRH2
ADTG2
AN2-0 to AN2-9
10 channels input
8/10-bit
A/D converter 2
ADTG0
AN0-0 to AN0-3
4 channels input
8/10-bit
A/D converter 0
6 channels
A/D activating
compare
4 channels input
8/10-bit
A/D converter 1
8 channels
input capture
IC0 to IC7
6 channels
free-run timer
CKI0,CKI1
PPG0 to
PPG15
Multi-function timer
ADTG1
AN1-0 to AN1-3
TIN0 to TIN3
TOUT0 to TOUT3
4 channels
base timer
-PWC
-Reload timer
-PWM
-PPG
12 channels
output compare
12 channels
wave form
generator
28
RTO0 to RTO11
DTTI0,DTTI1
CLKPOUT
GPIO
MB91470/480 Series
■ MEMORY SPACE
1. Memory Space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct Addressing Areas
The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
by the instruction. The size of directly addressable areas depends on the length of the data being accessed as
shown below.
→ byte data access
: 000H to 0FFH
→ half word data access : 000H to 1FFH
→ word data access
: 000H to 3FFH
2. Memory Map
•MB91470 series
Single chip
mode
Internal ROM
external bus mode
External ROM
external bus mode
I/O
I/O
I/O
Direct addressing
area
I/O
I/O
I/O
Refer to “■I/O MAP”
Access prohibited
Access prohibited
Access prohibited
F-bus RAM 4 Kbytes
F-bus RAM 4 Kbytes
F-bus RAM 4 Kbytes
D-bus RAM
28 Kbytes
D-bus RAM
28 Kbytes
D-bus RAM
28 Kbytes
Access prohibited
Access prohibited
0000 0000H
0000 0400H
0001 0000H
0003 F000H
0004 0000H
0004 7000H
0005 0000H
Access prohibited
0008 0000H
512 Kbytes
Flash/ROM
512 Kbytes
Flash/ROM
0010 0000H
Access prohibited
0020 0000H
External area
Maximum value
• 12 Kbytes : 00040000H to
00042FFFH
• 20 Kbytes : 00040000H to
00044FFFH
• 28 Kbytes : 00040000H to
00046FFFH
Maximum value
• 256 Kbytes : 000C0000H to
000FFFFFH
• 384 Kbytes : 000A0000H to
000FFFFFH
• 512 Kbytes : 00080000H to
000FFFFFH
Access prohibited
External area
FFFF FFFFH
144 pins
144 pins
144 pins
29
MB91470/480 Series
•MB91480 series
Single chip
mode
0000 0000H
I/O
Direct addressing
area
I/O
Refer to “■I/O MAP”
0000 0400H
0001 0000H
Access prohibited
0003 F000H
F-bus RAM 4 Kbytes
0004 0000H
D-bus RAM
28 Kbytes
0004 7000H
0005 0000H
Maximum value
• 12 Kbytes : 00040000H to 00042FFFH
• 28 Kbytes : 00040000H to 00046FFFH
Access prohibited
0008 0000H
512 Kbytes
Flash/ROM
0010 0000H
0020 0000H
Access prohibited
FFFF FFFFH
100 pins
30
Maximum value
• 256 Kbytes : 000C0000H to 000FFFFFH
• 512 Kbytes : 00080000H to 000FFFFFH
MB91470/480 Series
■ MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and mode data to set the operation mode.
1. Mode Pins
The MD2 to MD0 pins specify how the mode vector fetch and reset vector fetch is performed.
Settings other than those shown in the following table are prohibited.
Mode Pins
Reset vector
access area
Mode name
MD2
MD1
MD0
0
0
0
Internal ROM mode vector
Internal
0
0
1
External ROM mode vector
External
Remarks
The bus width is set
by mode register.
2. Mode data
The data that is written to the internal mode register (MODR) by the mode vector fetch is called mode data.
After the mode register is set, the device runs in the operating mode specified by this register.
The mode data is set by all of the reset sources. User programs cannot set the mode register.
<Details of mode data description>
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
0
0
0
0
0
ROMA
WTH1
WTH0
Operation mode setting bits
[bit 23 to bit 19] Reserved bits
Be sure to set these bits to “00000B”.
Operation is not guaranteed if these bits are set to a value other than “00000B”.
[bit 18] ROMA (Internal Flash/ROM enable bit)
This bit configures whether the internal Flash/ROM area (8 0000H to F FFFFH) is enabled.
ROMA
Function
Remarks
0
External ROM mode
Internal Flash/ROM area (8 0000H to F FFFFH) is used as an external area.
1
Internal ROM mode
Internal Flash/ROM area (8 0000H to F FFFFH) is enabled.
31
MB91470/480 Series
[bit 17, bit 16] WTH1, WTH0 (Bus width specification bit)
These bits configure the bus width in external bus mode.
In external bus mode, this value is set to the DBW1 and DBW0 bits of AWR0 (CS0 area).
WTH1
WTH0
Function
Remarks
0
0
8-bit bus width
External bus mode
0
1
16-bit bus width
External bus mode
1
0
1
1
⎯
(Setting prohibited)
Single chip mode
Single chip mode
3. Note
The mode data set in the mode vector must be stored as byte data at 0x000FFFF8H. The data should be located
in the highest byte from bit 31 to bit 24 because the FR family uses big endian byte ordering.
bit 31
Incorrect 0x000FFFF8H
Correct
0x000FFFF8H
0x000FFFFCH
32
24 23
16 15
87
0
XXXXXXXX
XXXXXXXX
XXXXXXXX
Mode data
Mode data
XXXXXXXX
XXXXXXXX
XXXXXXXX
Reset vector
MB91470/480 Series
■ I/O MAP
[How to read the table]
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Block
T-unit
Port data register
Read/write attribute, Access unit
(B : byte, H : half word, W : word)
Initial value of register after reset
Register name (column 1 of the register is at address 4n, column 2 is
at address 4 n + 1...)
Leftmost register address (For word-length access, column 1 of the
register is the MSB of the data.)
Note : Initial values of register bits are represented as follows :
“ 1 ” : Initial Value “ 1 ”
“ 0 ” : Initial Value “ 0 ”
“ X ” : Initial Value “ undefined ”
“ - ” : No physical register at this location
Access to addresses where the data access properties have not been documented is prohibited.
33
MB91470/480 Series
Address
Register
+0
+1
+2
+3
000000H
PDR0 [R/W]
B, H, W
XXXXXXXX
PDR1 [R/W]
B, H, W
XXXXXXXX
PDR2 [R/W]
B, H, W
XXXXXXXX
PDR3 [R/W]
B, H, W
XXXXXXXX
000004H
PDR5 [R/W]
B, H, W
-XXXXXXX
PDR6 [R/W]
B, H, W
------XX
PDR8 [R/W]
B, H, W
XXXXXXXX
PDR9 [R/W]
B, H, W
XXXXXXXX
000008H
PDRA [R/W]
B, H, W
---XXXXX
PDRB [R/W]
B, H, W
XXXXXXXX
PDRC [R/W]
B, H, W
XXXXXXXX
PDRD [R/W]
B, H, W
----XXXX
00000CH
PDRE [R/W]
B, H, W
XXXXXXXX
PDRF [R/W]
B, H, W
XXXXXXXX
PDRG [R/W]
B, H, W
--XXXXXX
PDRH [R/W]
B, H, W
--XXXXXX
000010H
PDRJ [R/W]
B, H, W
XXXXXXXX
⎯
PDRL [R/W]
B, H, W
-----XXX
PDRM [R/W]
B, H, W
----XXXX
000014H
PDRP [R/W]
B, H, W
--XXXXXX
PDRQ [R/W]
B, H, W
--XXXXXX
PDRR [R/W]
B, H, W
--XXXXXX
PDRS [R/W]
B, H, W
--XXXXXX
000018H
to
00003CH
⎯
Block
Port data
register
(Reserved)
000040H
EIRR0 [R/W]
B, H, W
00000000
ENIR0 [R/W]
B, H, W
00000000
ELVR0 [R/W] B, H, W
00000000 00000000
External
interrupt
(INT0 to
INT7)
000044H
DICR [R/W] B, H, W
-------0
HCRL [R/W, R]
B, H, W
0--11111
⎯
Delay
interrupt/
hold request
TMRLR0 [W] H, W
XXXXXXXX XXXXXXXX
TMR0 [R] H, W
XXXXXXXX XXXXXXXX
00004CH
⎯
TMCSR0 [R/W, R] B, H, W
----00-- ---00000
000050H
TMRLR1 [W] H, W
XXXXXXXX XXXXXXXX
TMR1 [R] H, W
XXXXXXXX XXXXXXXX
000054H
⎯
TMCSR1 [R/W, R] B, H, W
----00-- ---00000
000048H
000058H
to
00005CH
⎯
Reload
timer 0
Reload
timer 1
(Reserved)
(Continued)
34
MB91470/480 Series
Address
Register
+0
+1
+2
+3
000060H
SSR0 [R/W, R]
B, H, W
00000011
ESCR0 [R/W]/
IBSR0 [R/W, R]
B, H, W
00000000
SCR0 [R/W] /
IBCR0 [R/W, R]
B, H, W
00000000
SMR0 [R/W]
B, H, W
000-0000
000064H
BGR01[R/W]
B, H, W
00000000
BGR00 [R/W]
B, H, W
00000000
RDR0 [R]/
TDR0 [W]H, W
-------0 00000000
RDR0 [R]/
TDR0 [W]H, W
-------0 00000000
ISMK0 [R/W]
B, H, W
01111111
ISBA0 [R/W]
B, H, W
00000000
⎯
000068H
00006CH
FBYTE02 [R/W]
B, H, W
00000000
FBYTE01 [R/W]
B, H, W
00000000
FCR01 [R/W]
B, H, W
---00100
FCR00 [R/W, R]
B, H, W
-0000000
000070H
SSR1 [R/W, R]
B, H, W
00000011
ESCR1 [R/W]/
IBSR1 [R/W, R]
B, H, W
00000000
SCR1 [R/W] /
IBCR1 [R/W, R]
B, H, W
00000000
SMR1 [R/W]
B, H, W
000-0000
000074H
BGR11 [R/W]
B, H, W
00000000
BGR10 [R/W]
B, H, W
00000000
RDR1 [R]/
TDR1 [W]H, W
-------0 00000000
RDR1 [R]/
TDR1 [W]H, W
-------0 00000000
ISMK1 [R/W]
B, H, W
01111111
ISBA1 [R/W]
B, H, W
00000000
⎯
000078H
00007CH
FBYTE21 [R/W]
B, H, W
00000000
FBYTE11 [R/W]
B, H, W
00000000
FCR11 [R/W]
B, H, W
---00100
FCR10 [R/W, R]
B, H, W
-0000000
000080H
SSR2 [R/W, R]
B, H, W
00000011
ESCR2 [R/W]/
IBSR2 [R/W, R]
B, H, W
00000000
SCR2 [R/W] /
IBCR2 [R/W, R]
B, H, W
00000000
SMR2 [R/W]
B, H, W
000-0000
000084H
BGR21 [R/W]
B, H, W
00000000
BGR20 [R/W]
B, H, W
00000000
RDR2 [R]/
TDR2 [W]H, W
-------0 00000000
RDR2 [R]/
TDR2 [W]H, W
-------0 00000000
ISMK2 [R/W]
B, H, W
01111111
ISBA2 [R/W]
B, H, W
00000000
FCR21 [R/W]
B, H, W
---00100
FCR20 [R/W, R]
B, H, W
-0000000
⎯
000088H
00008CH
FBYTE22 [R/W]
B, H, W
00000000
FBYTE21 [R/W]
B, H, W
00000000
Block
Multifunction
serial
interface 0
Multifunction
serial
interface 1
Multifunction
serial
interface 2
(Continued)
35
MB91470/480 Series
Address
Register
+0
+1
+2
+3
000090H
SSR3 [R/W, R]
B, H, W
00000011
ESCR3 [R/W]/
IBSR3 [R/W, R]
B, H, W
00000000
SCR3 [R/W] /
IBCR3 [R/W, R]
B, H, W
00000000
SMR3 [R/W]
B, H, W
000-0000
000094H
BGR31 [R/W]
B, H, W
00000000
BGR30 [R/W]
B, H, W
00000000
RDR3 [R]/
TDR3 [W]H, W
-------0 00000000
RDR3 [R]/
TDR3 [W]H, W
-------0 00000000
ISMK3 [R/W]
B, H, W
01111111
ISBA3 [R/W]
B, H, W
00000000
FCR31 [R/W]
B, H, W
---00100
FCR30 [R/W, R]
B, H, W
-0000000
⎯
000098H
00009CH
FBYTE32 [R/W]
B, H, W
00000000
FBYTE31 [R/W]
B, H, W
00000000
0000A0H
OCCPBH0, OCCPBL0 [W]/
OCCPH0, OCCPL0 [R]
H, W
00000000 00000000
OCCPBH1, OCCPBL1 [W]/
OCCPH1, OCCPL1 [R]
H, W
00000000 00000000
0000A4H
OCCPBH2, OCCPBL2 [W]/
OCCPH2, OCCPL2 [R]
H, W
00000000 00000000
OCCPBH3, OCCPBL3 [W]/
OCCPH3, OCCPL3 [R]
H, W
00000000 00000000
0000A8H
OCCPBH4, OCCPBL4 [W]/
OCCPH4, OCCPL4 [R]
H, W
00000000 00000000
OCCPBH5, OCCPBL5 [W]/
OCCPH5, OCCPL5 [R]
H, W
00000000 00000000
0000ACH
OCSH1 [R/W]
B, H, W
-1100000
OCSL0 [R/W]
B, H, W
00001100
OCSH3 [R/W]
B, H, W
-1100000
OCSL2 [R/W]
B, H, W
00001100
0000B0H
OCSH5 [R/W]
B, H, W
-1100000
OCSL4 [R/W]
B, H, W
00001100
OCMOD0 [R/W]
B, H, W
--000000
⎯
0000B4H
0000B8H
0000BCH
0000C0H
CPCLRBH0, CPCLRBL0 [W]/
CPCLRH0, CPCLRL0 [R] H, W
11111111 11111111
TCCSH0 [R/W]
B, H, W
00000000
TCCSL0 [R/W]
B, H, W
01000000
CPCLRBH1, CPCLRBL1 [W] /
CPCLRH1, CPCLRL1 [R] H, W
11111111 11111111
TCCSH1 [R/W]
B, H, W
00000000
TCCSL1 [R/W]
B, H, W
01000000
TCDTH0, TCDTL0 [R/W] H, W
00000000 00000000
TCCSM0 [R/W]
B, H, W
----0000
ADTRGC0 [R/W]
B, H, W
-000-000
TCDTH1, TCDTL1 [R/W] H, W
00000000 00000000
TCCSM1 [R/W]
B, H, W
----0000
ADTRGC1 [R/W]
B, H, W
-000-000
Block
Multifunction
serial
interface 3
OCU0
Free-run
timer 0
Free-run
timer 1
(Continued)
36
MB91470/480 Series
Address
0000C4H
Register
+0
+1
CPCLRBH2, CPCLRBL2 [W] /
CPCLRH2, CPCLRL2 [R] H, W
11111111 11111111
0000C8H
TCCSH2 [R/W]
B, H, W
00000000
0000CCH
⎯
TCCSL2 [R/W]
B, H, W
01000000
+2
+3
TCDTH2, TCDTL2 [R/W] H, W
00000000 00000000
TCCSM2 [R/W]
B, H, W
----0000
ADTRGC2 [R/W]
B, H, W
-000-000
FRS2 [R/W] B, H, W FRS1 [R/W] B, H, W FRS0 [R/W] B, H, W
-000-000
-000-000
-000-000
0000D0H
⎯
FRS4 [R/W] B, H, W FRS3 [R/W] B, H, W
-000-000
-000-000
0000D4H
IPCPH0, IPCPL0 [R] H, W
XXXXXXXX XXXXXXXX
IPCPH1, IPCPL1 [R] H, W
XXXXXXXX XXXXXXXX
0000D8H
IPCPH2, IPCPL2 [R] H, W
XXXXXXXX XXXXXXXX
IPCPH3, IPCPL3 [R] H, W
XXXXXXXX XXXXXXXX
0000DCH
PICSH01 [W, R]
B, H, W
00000000
PICSL01 [R/W]
B, H, W
00000000
ICSH23 [R] B, H, W
------00
TMRRH0, TMRRL0 [R/W] H, W
XXXXXXXX XXXXXXXX
TMRRH1, TMRRL1 [R/W] H, W
XXXXXXXX XXXXXXXX
0000E4H
TMRRH2, TMRRL2 [R/W] H, W
XXXXXXXX XXXXXXXX
⎯
0000E8H
DTCR0 [R/W]
B, H, W
00000000
DTCR1 [R/W]
B, H, W
00000000
DTCR2 [R/W]
B, H, W
00000000
⎯
0000ECH
⎯
SIGCR10 [R/W]
B, H, W
00000000
⎯
SIGCR20 [R/W]
B, H, W
000000-1
0000F0H
ADCOMP0 [W]/
ADCOMPB0 [R] H, W
00000000 00000000
ADCOMPD0 [W]/
ADCOMPDB0 [R] H, W
00000000 00000000
0000F4H
ADCOMP1 [W]/
ADCOMPB1 [R] H, W
00000000 00000000
ADCOMPD1 [W]/
ADCOMPDB1 [R] H, W
00000000 00000000
0000F8H
ADCOMP2 [W]/
ADCOMPB2 [R] H, W
00000000 00000000
ADCOMPD2 [W]/
ADCOMPDB2 [R] H, W
00000000 00000000
⎯
ADTGBUF0
[R/W] B, H, W
-000-111
ADTGSEL0
[R/W] B, H, W
--000000
Free-run
timer 2
Free-run
timer
selector 0
ICU0
ICSL23[R/W]
B, H, W
00000000
0000E0H
0000FCH
Block
Wave form
generator 0
A/D
activating
compare 0
ADTGCE0
[R/W] B, H, W
--000000
(Continued)
37
MB91470/480 Series
Address
Register
+0
+1
+2
+3
000100H
PRLH0 [R/W]
B, H, W
XXXXXXXX
PRLL0 [R/W]
B, H, W
XXXXXXXX
PRLH1 [R/W]
B, H, W
XXXXXXXX
PRLL1 [R/W]
B, H, W
XXXXXXXX
000104H
PRLH2 [R/W]
B, H, W
XXXXXXXX
PRLL2 [R/W]
B, H, W
XXXXXXXX
PRLH3 [R/W]
B, H, W
XXXXXXXX
PRLL3 [R/W]
B, H, W
XXXXXXXX
000108H
PPGC0 [R/W]
B, H, W
00000000
PPGC1 [R/W]
B, H, W
00000000
PPGC2 [R/W]
B, H, W
00000000
PPGC3 [R/W]
B, H, W
00000000
00010CH
PRLH4 [R/W]
B, H, W
XXXXXXXX
PRLL4 [R/W]
B, H, W
XXXXXXXX
PRLH5 [R/W]
B, H, W
XXXXXXXX
PRLL5 [R/W]
B, H, W
XXXXXXXX
000110H
PRLH6 [R/W]
B, H, W
XXXXXXXX
PRLL6 [R/W]
B, H, W
XXXXXXXX
PRLH7 [R/W]
B, H, W
XXXXXXXX
PRLL7 [R/W]
B, H, W
XXXXXXXX
000114H
PPGC4 [R/W]
B, H, W
00000000
PPGC5 [R/W]
B, H, W
00000000
PPGC6 [R/W]
B, H, W
00000000
PPGC7 [R/W]
B, H, W
00000000
000118H
PRLH8 [R/W]
B, H, W
XXXXXXXX
PRLL8 [R/W]
B, H, W
XXXXXXXX
PRLH9 [R/W]
B, H, W
XXXXXXXX
PRLL9 [R/W]
B, H, W
XXXXXXXX
00011CH
PRLH10 [R/W]
B, H, W
XXXXXXXX
PRLL10 [R/W]
B, H, W
XXXXXXXX
PRLH11 [R/W]
B, H, W
XXXXXXXX
PRLL11 [R/W]
B, H, W
XXXXXXXX
000120H
PPGC8 [R/W]
B, H, W
00000000
PPGC9 [R/W]
B, H, W
00000000
PPGC10 [R/W]
B, H, W
00000000
PPGC11 [R/W]
B, H, W
00000000
000124H
PRLH12 [R/W]
B, H, W
XXXXXXXX
PRLL12 [R/W]
B, H, W
XXXXXXXX
PRLH13 [R/W]
B, H, W
XXXXXXXX
PRLL13 [R/W]
B, H, W
XXXXXXXX
000128H
PRLH14 [R/W]
B, H, W
XXXXXXXX
PRLL14 [R/W]
B, H, W
XXXXXXXX
PRLH15 [R/W]
B, H, W
XXXXXXXX
PRLL15 [R/W]
B, H, W
XXXXXXXX
00012CH
PPGC12 [R/W]
B, H, W
00000000
PPGC13 [R/W]
B, H, W
00000000
PPGC14 [R/W]
B, H, W
00000000
PPGC15 [R/W]
B, H, W
00000000
000130H
TRG [R/W] B, H
00000000 00000000
⎯
GATEC0 [R/W] B
--00--00
000134H
REVC [R/W] B, H
00000000 00000000
⎯
GATEC4 [R/W] B
------00
000138H
⎯
Block
PPG
GATEC8 [R/W] B
--00--00
(Continued)
38
MB91470/480 Series
Address
Register
+0
+1
000144H
TTCR0 [R/W, W, R]
B, H, W
11110000
000148H
COMP0 [R/W]
B, H, W
00000000
00014CH
TTCR1 [R/W, W, R]
B, H, W
11110000
COMP2 [R/W]
B, H, W
00000000
COMP3 [R/W]
B, H, W
00000000
000154H
EIRR1 [R/W]
B, H, W
00000000
ENIR1 [R/W]
B, H, W
00000000
000174H
COMP4 [R/W]
B, H, W
00000000
COMP6 [R/W]
B, H, W
00000000
COMP5 [R/W]
B, H, W
00000000
COMP7 [R/W]
B, H, W
00000000
ELVR1 [R/W] B, H, W
00000000 00000000
CMCLKR [R/W] B
----0000
BT0TMR [R] B, H, W
00000000 00000000
BT0STC [R/W] B
00000000
⎯
External
interrupt
(INT8 to
INT15)
Clock monitor
Base timer 0
BT0PDUT/BT0PRLH/BT0DTBF [R/W]
H, W
XXXXXXXX XXXXXXXX
⎯
(Reserved)
AICR2 [R/W] B, H, W
----1111 11111111
⎯
Timing
generator 1
BT0TMCR [R/W] B, H, W
00000000 00000000
BT0PCSR/BT0PRLL [R/W]
H, W
XXXXXXXX XXXXXXXX
ADCS2 [R/W, W]
B, H, W
0000000-
Timing
generator 0
(Reserved)
⎯
00016CH
000170H
(Reserved)
⎯
000158H
⎯
PPG
⎯
COMP1 [R/W]
B, H, W
00000000
00015CH
Block
⎯
000150H
000168H
GATEC12 [R/W] B
------00
⎯
000140H
000164H
+3
⎯
00013CH
000160H
+2
⎯
ADCH2 [R/W]
B, H, W
00000000
ADMD2 [R/W]
B, H, W
00001111
000178H
ADCD002 [R] B, H, W
10----XX XXXXXXXX
ADCD012 [R] B, H, W
10----XX XXXXXXXX
00017CH
ADCD022 [R] B, H, W
10----XX XXXXXXXX
ADCD032 [R] B, H, W
10----XX XXXXXXXX
8/10-bit
A/D converter
2
(12 channels)
(Continued)
39
MB91470/480 Series
Address
Register
+0
+1
+2
+3
000180H
ADCD042 [R] B, H, W
10----XX XXXXXXXX
ADCD052 [R] B, H, W
10----XX XXXXXXXX
000184H
ADCD062 [R] B, H, W
10----XX XXXXXXXX
ADCD072 [R] B, H, W
10----XX XXXXXXXX
000188H
ADCD082 [R] B, H, W
10----XX XXXXXXXX
ADCD092 [R] B, H, W
10----XX XXXXXXXX
00018CH
ADCD102 [R] B, H, W
10----XX XXXXXXXX
ADCD112 [R] B, H, W
10----XX XXXXXXXX
Block
8/10-bit
A/D
converter 2
(12 channels)
000190H
⎯
(Reserved)
000194H
⎯
(Reserved)
000198H
⎯
(Reserved)
00019CH
⎯
(Reserved)
0001A0H
OCCPBH6, OCCPBL6 [W]/
OCCPH6, OCCPL6 [R]
H, W
00000000 00000000
OCCPBH7, OCCPBL7 [W]/
OCCPH7, OCCPL7 [R]
H, W
00000000 00000000
0001A4H
OCCPBH8, OCCPBL8 [W]/
OCCPH8, OCCPL8 [R]
H, W
00000000 00000000
OCCPBH9, OCCPBL9 [W]/
OCCPH9, OCCPL9 [R]
H, W
00000000 00000000
0001A8H
OCCPBH10, OCCPBL10 [W]/
OCCPH10, OCCPL10 [R]
H, W
00000000 00000000
OCCPBH11, OCCPBL11 [W]/
OCCPH11, OCCPL11 [R]
H, W
00000000 00000000
0001ACH
OCSH7 [R/W]
B, H, W
-1100000
OCSL6 [R/W]
B, H, W
00001100
OCSH9 [R/W]
B, H, W
-1100000
OCSL8 [R/W]
B, H, W
00001100
0001B0H
OCSH11 [R/W]
B, H, W
-1100000
OCSL10 [R/W]
B, H, W
00001100
OCMOD1 [R/W]
B, H, W
--000000
⎯
0001B4H
0001B8H
0001BCH
0001C0H
CPCLRBH3, CPCLRBL3 [W]/
CPCLRH3, CPCLRL3 [R] H, W
11111111 11111111
TCCSH3 [R/W]
B, H, W
00000000
TCCSL3 [R/W]
B, H, W
01000000
CPCLRBH4, CPCLRBL4 [W] /
CPCLRH4, CPCLRL4 [R] H, W
11111111 11111111
TCCSH4 [R/W]
B, H, W
00000000
TCCSL4 [R/W]
B, H, W
01000000
TCDTH3, TCDTL3 [R/W] H, W
00000000 00000000
TCCSM3 [R/W]
B, H, W
----0000
ADTRGC3 [R/W]
B, H, W
-000-000
TCDTH4, TCDTL4 [R/W] H, W
00000000 00000000
TCCSM4 [R/W]
B, H, W
----0000
ADTRGC4 [R/W]
B, H, W
-000-000
OCU1
Free-run
timer 3
Free-run
timer 4
(Continued)
40
MB91470/480 Series
Address
0001C4H
Register
+0
+1
CPCLRBH5, CPCLRBL5 [W] /
CPCLRH5, CPCLRL 5 [R] H, W
11111111 11111111
0001C8H
TCCSH5 [R/W]
B, H, W
00000000
0001CCH
⎯
TCCSL5 [R/W]
B, H, W
01000000
+2
+3
TCDTH5, TCDTL5 [R/W] H, W
00000000 00000000
TCCSM5 [R/W]
B, H, W
----0000
ADTRGC5 [R/W]
B, H, W
-000-000
FRS7 [R/W] B, H, W FRS6 [R/W] B, H, W FRS5 [R/W] B, H, W
-011-011
-011-011
-011-011
0001D0H
⎯
FRS9 [R/W] B, H, W FRS8 [R/W] B, H, W
-011-011
-011-011
0001D4H
IPCPH4, IPCPL4 [R] H, W
XXXXXXXX XXXXXXXX
IPCPH5, IPCPL5 [R] H, W
XXXXXXXX XXXXXXXX
0001D8H
IPCPH6, IPCPL6 [R] H, W
XXXXXXXX XXXXXXXX
IPCPH7, IPCPL7 [R] H, W
XXXXXXXX XXXXXXXX
0001DCH
PICSH45 [W, R]
B, H, W
00000000
PICSL45 [R/W]
B, H, W
00000000
ICSH67 [R]
B, H, W
------00
TMRRH3, TMRRL3 [R/W] H, W
XXXXXXXX XXXXXXXX
TMRRH4, TMRRL4 [R/W] H, W
XXXXXXXX XXXXXXXX
0001E4H
TMRRH5, TMRRL5 [R/W] H, W
XXXXXXXX XXXXXXXX
⎯
0001E8H
DTCR3 [R/W]
B, H, W
00000000
DTCR4 [R/W]
B, H, W
00000000
DTCR5 [R/W]
B, H, W
00000000
⎯
0001ECH
⎯
SIGCR11 [R/W]
B, H, W
00000000
⎯
SIGCR21 [R/W]
B, H, W
000000-1
0001F0H
ADCOMP3 [W]/
ADCOMPB3 [R] H, W
00000000 00000000
ADCOMPD3 [W]/
ADCOMPDB3 [R] H, W
00000000 00000000
0001F4H
ADCOMP4 [W]/
ADCOMPB4 [R] H, W
00000000 00000000
ADCOMPD4 [W]/
ADCOMPDB4 [R] H, W
00000000 00000000
0001F8H
ADCOMP5 [W]/
ADCOMPB5 [R] H, W
00000000 00000000
ADCOMPD5 [W]/
ADCOMPDB5 [R] H, W
00000000 00000000
⎯
ADTGBUF1 [R/W]
B, H, W
-000-111
ADTGSEL1 [R/W]
B, H, W
--000000
Free-run
timer 5
Free-run
timer
selector 1
ICU1
ICSL67 [R/W]
B, H, W
00000000
0001E0H
0001FCH
Block
Wave form
generator
1
A/D
activating
compare 1
ADTGCE1[R/W]
B, H, W
--000000
(Continued)
41
MB91470/480 Series
Address
Register
+0
+1
+2
+3
Block
000200H
DMACA0 [R/W] B, H, W *1
00000000 ----XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W] B, H, W *1
00000000 ----XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W] B, H, W *1
00000000 ----XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W] B, H, W *1
000000000 ----XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W] B, H, W *1
00000000 ----XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH
⎯
(Reserved)
000240H
DMACR [R/W] B, H, W
0--00000 -------- -------- --------
DMAC
000244H
to
00039CH
⎯
(Reserved)
0003A0H
DSP-PC [R/W]
B, H, W
000000-0
DSP-CSR [R/W, R,
W] B, H, W
00000000
DMAC
⎯
0003A4H
DSP-LY [R/W], W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003A8H
DSP-OT0 [R], W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003ACH
DSP-OT1 [R], W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003B0H
DSP-OT2 [R], W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003B4H
DSP-OT3 [R], W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MAC
(Continued)
42
MB91470/480 Series
Address
Register
+0
+1
+2
0003B8H
DSP-OT4 [R], W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003BCH
DSP-OT5 [R], W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003C0H
DSP-OT6 [R], W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003C4H
DSP-OT7 [R], W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003C8H
DSP-AC0 [R], W
-------- -------- -------- 00000000
0003CCH
DSP-AC1 [R], W
00000000 00000000 00000000 00000000
0003D0H
DSP-AC2 [R], W
00000000 00000000 00000000 00000000
0003D4H
to
0003ECH
⎯
0003F0H
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
Block
MAC
(Reserved)
Bit search
module
000400H
DDR0 [R/W]
B, H, W
00000000
DDR1 [R/W]
B, H, W
00000000
DDR2 [R/W]
B, H, W
00000000
DDR3 [R/W]
B, H, W
00000000
000404H
DDR5 [R/W]
B, H, W
-0000000
DDR6 [R/W]
B, H, W
------00
DDR8 [R/W]
B, H, W
00000000
DDR9 [R/W]
B, H, W
00000000
000408H
DDRA [R/W]
B, H, W
---00000
DDRB [R/W]
B, H, W
00000000
DDRC [R/W]
B, H, W
00000000
DDRD [R/W]
B, H, W
----0000
00040CH
DDRE [R/W]
B, H, W
00000000
DDRF [R/W]
B, H, W
00000000
DDRG [R/W]
B, H, W
--000000
DDRH [R/W]
B, H, W
--000000
000410H
DDRJ [R/W]
B, H, W
00000000
⎯
DDRL [R/W]
B, H, W
-----000
DDRM [R/W]
B, H, W
----0000
Port
direction
register
(Continued)
43
MB91470/480 Series
Address
000414H
Register
+0
+1
+2
+3
DDRP [R/W]
B, H, W
--000000
DDRQ [R/W]
B, H, W
--000000
DDRR [R/W]
B, H, W
--000000
DDRS [R/W]
B, H, W
--000000
000418H
⎯
00041CH
⎯
000420H
PFR0 [R/W] B, H, W PFR1 [R/W] B, H, W PFR2 [R/W] B, H, W PFR3 [R/W] B, H, W
11111111
11111111
11111111
11111111
000424H
PFR5 [R/W] B, H, W PFR6 [R/W] B, H, W PFR8 [R/W] B, H, W PFR9 [R/W] B, H, W
-1111111
------11
0000---00000000
⎯
PFRC [R/W] B, H, W
--0-00-0
⎯
00042CH
⎯
PFRF [R/W]
B, H, W
-------0
PFRG [R/W]
B, H, W
--0-00-0
PFRH [R/W]
B, H, W
--0-00-0
000430H
PFRJ [R/W]
B, H, W
0-0-0-0-
000434H
⎯
⎯
000438H
⎯
00043CH
⎯
Port
function
register
PFRM [R/W]
B, H, W
----0000
⎯
PFRQ [R/W]
B, H, W
--000000
Port
direction
register
(Reserved)
⎯
000428H
Block
PFRS [R/W]
B, H, W
--000000
(Reserved)
000440H
ICR00 [R/W, R]
B, H, W
---11111
ICR01 [R/W, R]
B, H, W
---11111
ICR02 [R/W, R]
B, H, W
---11111
ICR03 [R/W, R]
B, H, W
---11111
000444H
ICR04 [R/W, R]
B, H, W
---11111
ICR05 [R/W, R]
B, H, W
---11111
ICR06 [R/W, R]
B, H, W
---11111
ICR07 [R/W, R]
B, H, W
---11111
000448H
ICR08 [R/W, R]
B, H, W
---11111
ICR09 [R/W, R]
B, H, W
---11111
ICR10 [R/W, R]
B, H, W
---11111
ICR11 [R/W, R]
B, H, W
---11111
00044CH
ICR12 [R/W, R]
B, H, W
---11111
ICR13 [R/W, R]
B, H, W
---11111
ICR14 [R/W, R]
B, H, W
---11111
ICR15 [R/W, R]
B, H, W
---11111
000450H
ICR16 [R/W, R]
B, H, W
---11111
ICR17 [R/W, R]
B, H, W
---11111
ICR18 [R/W, R]
B, H, W
---11111
ICR19 [R/W, R]
B, H, W
---11111
000454H
ICR20 [R/W, R]
B, H, W
---11111
ICR21 [R/W, R]
B, H, W
---11111
ICR22 [R/W, R]
B, H, W
---11111
ICR23 [R/W, R]
B, H, W
---11111
Interrupt
controller
(Continued)
44
MB91470/480 Series
Address
Register
+0
+1
+2
+3
000458H
ICR24 [R/W, R]
B, H, W
---11111
ICR25 [R/W, R]
B, H, W
---11111
ICR26 [R/W, R]
B, H, W
---11111
ICR27 [R/W, R]
B, H, W
---11111
00045CH
ICR28 [R/W, R]
B, H, W
---11111
ICR29 [R/W, R]
B, H, W
---11111
ICR30 [R/W, R]
B, H, W
---11111
ICR31 [R/W, R]
B, H, W
---11111
000460H
ICR32 [R/W, R]
B, H, W
---11111
ICR33 [R/W, R]
B, H, W
---11111
ICR34 [R/W, R]
B, H, W
---11111
ICR35 [R/W, R]
B, H, W
---11111
000464H
ICR36 [R/W, R]
B, H, W
---11111
ICR37 [R/W, R]
B, H, W
---11111
ICR38 [R/W, R]
B, H, W
---11111
ICR39 [R/W, R]
B, H, W
---11111
000468H
ICR40 [R/W, R]
B, H, W
---11111
ICR41 [R/W, R]
B, H, W
---11111
ICR42 [R/W, R]
B, H, W
---11111
ICR43 [R/W, R]
B, H, W
---11111
00046CH
ICR44 [R/W, R]
B, H, W
---11111
ICR45 [R/W, R]
B, H, W
---11111
ICR46 [R/W, R]
B, H, W
---11111
ICR47 [R/W, R]
B, H, W
---11111
000470H
to
00047CH
⎯
RSRR [R/W]
B, H, W
1-0-0-00
STCR [R/W]
B, H, W
001100-1
TBCR [R/W]
B, H, W
00XXX-00
CTBR [W]
B, H, W
XXXXXXXX
000484H
CLKR [R/W]
B, H, W
-000-000
⎯
DIVR0 [R/W]
B, H, W
00000011
DIVR1 [R/W]
B, H, W
00000000
⎯
000500H
⎯
AICR0 [R/W]
B, H, W
----1111
000504H
ADCS0 [R/W, W]
B, H, W
0000000-
⎯
Interrupt
controller
(Reserved)
000480H
000488H
to
0004FCH
Block
Clock
control
block
(Reserved)
⎯
ADCH0 [R/W]
B, H, W
--00--00
ADMD0 [R/W]
B, H, W
00001111
000508H
ADCD000 [R] B, H, W
10----XX XXXXXXXX
ADCD010 [R] B, H, W
10----XX XXXXXXXX
00050CH
ADCD020 [R] B, H, W
10----XX XXXXXXXX
ADCD030 [R] B, H, W
10----XX XXXXXXXX
8/10-bit
A/D
converter 0
(4 channels)
(Continued)
45
MB91470/480 Series
Address
Register
+0
+1
000510H
⎯
AICR1 [R/W]
B, H, W
----1111
000514H
ADCS1 [R/W, W]
B, H, W
0000000-
⎯
+2
+3
⎯
ADCH1 [R/W]
B, H, W
--00--00
ADMD1 [R/W]
B, H, W
00001111
000518H
ADCD001 [R] B, H, W
10----XX XXXXXXXX
ADCD011 [R] B, H, W
10----XX XXXXXXXX
00051CH
ADCD021 [R] B, H, W
10----XX XXXXXXXX
ADCD031 [R] B, H, W
10----XX XXXXXXXX
000520H
⎯
AICR3 [R/W]
B, H, W
----1111
000524H
ADCS3 [R/W, W]
B, H, W
0000000-
⎯
ADCH3 [R/W]
B, H, W
--00--00
ADMD3 [R/W]
B, H, W
00001111
ADCD003 [R] B, H, W
10--XXXX XXXXXXXX
ADCD013 [R] B, H, W
10--XXXX XXXXXXXX
00052CH
ADCD023 [R] B, H, W
10--XXXX XXXXXXXX
ADCD033 [R] B, H, W
10--XXXX XXXXXXXX
000530H
⎯
AICR4 [R/W]
B, H, W
----1111
000534H
ADCS4 [R/W, W]
B, H, W
0000000-
⎯
ADCH4 [R/W]
B, H, W
--00--00
ADMD4 [R/W]
B, H, W
00001111
ADCD004 [R] B, H, W
10--XXXX XXXXXXXX
ADCD014 [R] B, H, W
10--XXXX XXXXXXXX
00053CH
ADCD024 [R] B, H, W
10--XXXX XXXXXXXX
ADCD034 [R] B, H, W
10--XXXX XXXXXXXX
000540H
RCR10 [W] B, H, W RCR00 [W] B, H, W
XXXXXXXX
XXXXXXXX
000548H
to
00055CH
12-bit
A/D
converter 3
(4 channels)
⎯
000538H
CCRH0 [R/W]
B, H, W
00000000
8/10-bit
A/D
converter 1
(4 channels)
⎯
000528H
000544H
Block
CCRL0 [R/W, R]
B, H, W
-0001000
⎯
UDCR10 [R]
B, H, W
00000000
UDCR00 [R]
B, H, W
00000000
⎯
CSR0 [R/W, R]
B, H, W
00000000
12-bit
A/D
converter 4
(4 channels)
Up/down
counter 0
(Reserved)
(Continued)
46
MB91470/480 Series
Address
Register
+0
+1
+2
+3
000560H
SSR4 [R/W, R]
B, H, W
00000011
ESCR4 [R/W]/
IBSR4 [R/W, R]
B, H, W
00000000
SCR4 [R/W] /
IBCR4 [R/W, R]
B, H, W
00000000
SMR4 [R/W]
B, H, W
000-0000
000564H
BGR41 [R/W]
B, H, W
00000000
BGR40 [R/W]
B, H, W
00000000
RDR4 [R]/TDR4 [W]H, W
-------0 00000000
⎯
000568H
ISMK4 [R/W]
B, H, W
01111111
ISBA4 [R/W]
B, H, W
00000000
00056CH
FBYTE42 [R/W]
B, H, W
00000000
FBYTE41 [R/W]
B, H, W
00000000
FCR41 [R/W]
B, H, W
---00100
FCR40 [R/W, R]
B, H, W
-0000000
000570H
SSR5 [R/W, R]
B, H, W
00000011
ESCR5 [R/W]/
IBSR5 [R/W, R]
B, H, W
00000000
SCR5 [R/W] /
IBCR5 [R/W, R]
B, H, W
00000000
SMR5 [R/W]
B, H, W
000-0000
000574H
BGR51 [R/W]
B, H, W
00000000
BGR50 [R/W]
B, H, W
00000000
⎯
000578H
00057CH
000580H
000584H
000588H
FBYTE52 [R/W]
B, H, W
00000000
FBYTE51 [R/W]
B, H, W
00000000
BT1TMR [R] B, H, W
00000000 00000000
⎯
000594H
000598H
00059CH
ISMK5 [R/W]
B, H, W
01111111
ISBA5 [R/W]
B, H, W
00000000
FCR51 [R/W]
B, H, W
---00100
FCR50 [R/W, R]
B, H, W
-0000000
⎯
BT1PCSR/BT1PRLL [R/W]
H, W
XXXXXXXX XXXXXXXX
Multifunction
serial
interface 5
Base timer 1
BT1PDUT/BT1PRLH/BT1DTBF [R/W]
H, W
XXXXXXXX XXXXXXXX
⎯
BT2TMR [R] B, H, W
00000000 00000000
⎯
Multifunction
serial
interface 4
BT1TMCR [R/W] B, H, W
00000000 00000000
BT1STC [R/W] B
00000000
00058CH
000590H
RDR5 [R]/TDR5 [W]H, W
-------0 00000000
Block
(Reserved)
BT2TMCR [R/W] B, H, W
00000000 00000000
BT2STC [R/W] B
00000000
⎯
BT2PCSR/BT2PRLL [R/W]
H, W
XXXXXXXX XXXXXXXX
Base timer 2
BT2PDUT/BT2PRLH/BT2DTBF [R/W]
H, W
XXXXXXXX XXXXXXXX
⎯
(Reserved)
(Continued)
47
MB91470/480 Series
Address
0005A0H
0005A4H
0005A8H
Register
+0
+1
+2
BT3TMR [R] B, H, W
00000000 00000000
⎯
+3
Block
BT3TMCR [R/W] B, H, W
00000000 00000000
BT3STC [R/W] B
00000000
⎯
BT3PCSR/BT3PRLL [R/W]
H, W
XXXXXXXX XXXXXXXX
Base timer 3
BT3PDUT/BT3PRLH/BT3DTBF [R/W]
H, W
XXXXXXXX XXXXXXXX
0005ACH
⎯
(Reserved)
0005B0H
to
0005FCH
⎯
(Reserved)
000600H
PCR0 [R/W]
B, H, W
00000000
PCR1 [R/W]
B, H, W
00000000
PCR2 [R/W]
B, H, W
00000000
PCR3 [R/W]
B, H, W
00000000
000604H
PCR5 [R/W]
B, H, W
-0000000
PCR6 [R/W]
B, H, W
------00
PCR8 [R/W]
B, H, W
00000000
PCR9 [R/W]
B, H, W
00000000
000608H
PCRA [R/W]
B, H, W
---00000
PCRB [R/W]
B, H, W
00000000
PCRC [R/W]
B, H, W
00000000
PCRD [R/W]
B, H, W
----0000
00060CH
PCRE [R/W]
B, H, W
00000000
PCRF [R/W]
B, H, W
00000000
PCRG [R/W]
B, H, W
--000000
PCRH [R/W]
B, H, W
--000000
000610H
PCRJ [R/W]
B, H, W
00000000
⎯
PCRL [R/W]
B, H, W
-----000
PCRM [R/W]
B, H, W
----0000
000614H
PCRP [R/W]
B, H, W
--000000
PCRQ [R/W]
B, H, W
--000000
PCRR [R/W]
B, H, W
--000000
PCRS [R/W]
B, H, W
--000000
000618H
to
00063CH
⎯
(Reserved)
000640H
ASR0 [R/W] H, W
00000000 00000000 *2
ACR0 [R/W] H, W
1111XX-- --000000 *2
000644H
ASR1 [R/W] H, W
XXXXXXXX XXXXXXXX *2
ACR1 [R/W] H, W
XXXXXX-- --XXXXXX *2
000648H
ASR2 [R/W] H, W
XXXXXXXX XXXXXXXX *2
ACR2 [R/W] H, W
XXXXXX-- --XXXXXX *2
00064CH
Pull-up
resistor
control
register
External bus
interface
⎯
(Continued)
48
MB91470/480 Series
Address
Register
+0
+1
+2
000650H
⎯
000654H
⎯
000658H
⎯
00065CH
⎯
+3
000660H
AWR0 [R/W] H, W
0111---- 1111-111 *2
AWR1 [R/W] H, W
XXXX---- XXXX-XXX *2
000664H
AWR2 [R/W] H, W
XXXX---- XXXX-XXX *2
⎯
000668H
⎯
00066CH
⎯
000670H
⎯
000674H
⎯
000678H
⎯
00067CH
⎯
000680H
CSER [R/W] B, H
-----001
External bus
interface
⎯
000684H
to
0007F8H
0007FCH
⎯
⎯
Block
MODR [W]
XXXXXXXX
(Reserved)
⎯
000800H
to
000FFCH
⎯
001000H
DMASA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Mode
register
(Reserved)
DMAC
(Continued)
49
MB91470/480 Series
Address
Register
+0
+1
+2
+3
00101CH
DMADA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
006FFCH
⎯
FLCR [R/W, R] B
----X-0-
⎯
007004H
FLWC [R/W] B
--11-011
⎯
⎯
00700CH
⎯
007010H
⎯
007014H
to
00701CH
⎯
007020H
DMAC
(Reserved)
007000H
007008H
Block
WREN [R/W] H
00000000 00000000
Flash
memory
(Reserved)
⎯
007024H
⎯
007028H
⎯
00702CH
⎯
007030H
WA00 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
007034H
WD00 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007038H
WA01 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
00703CH
WD01 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007040H
WA02 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
007044H
WD02 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007048H
WA03 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
00704CH
WD03 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Wild
register
control
block
(Continued)
50
MB91470/480 Series
Address
Register
+0
+1
+2
007050H
WA04 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
007054H
WD04 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007058H
WA05 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
00705CH
WD05 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007060H
WA06 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
007064H
WD06 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007068H
WA07 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
00706CH
WD07 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007070H
WA08 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
007074H
WD08 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007078H
WA09 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
00707CH
WD09 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007080H
WA10 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
007084H
WD10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007088H
WA11 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
00708CH
WD11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007090H
WA12 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
007094H
WD12 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
007098H
WA13 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
00709CH
WD13 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
Block
Wild
register
control
block
(Continued)
51
MB91470/480 Series
(Continued)
Address
Register
+0
+1
+2
+3
Block
0070A0H
WA14 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
0070A4H
WD14 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0070A8H
WA15 [R/W] W
-------- ----XXXX XXXXXXXX XXXXXX--
0070ACH
WD15 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0070B0H
to
00BFFCH
⎯
00C000H
to
00C0FCH
X-RAM (coefficient RAM) [R/W]
64 × 32-bit
00C100H
to
00C1FCH
Y-RAM (variable RAM) [R/W]
64 × 32-bit
00C200H
to
00C3FCH
I-RAM (instruction RAM) [R/W]
128 × 32-bit
00C400H
to
00FFFCH
⎯
(Reserved)
010000H
to
0FFFFCH
⎯
(Reserved)
Wild
register
control
block
(Reserved)
MAC
*1 : The lower 16 bits (DTC15 to DTC0) of DMACA0 to DMACA4 cannot be accessed as bytes.
*2 : Register whose initial value depends on the reset level. The initial values shown are for INITX = “L”.
Notes : • Data is undefined in reserved or (⎯) area.
• Do not execute read modify write (RMW) instruction on registers having a write-only bit.
• The initial values are varied depending on the product series. Please refer to the hardware manual of
MB91470/480 for more details.
52
MB91470/480 Series
■ INTERRUPT VECTOR
Interrupt number
Interrupt source
Interrupt
level
Offset
TBR default
address
Decimal
Hexadecimal
Reset
0
00
⎯
3FCH
000FFFFCH
Mode vector
1
01
⎯
3F8H
000FFFF8H
System reserved
2
02
⎯
3F4H
000FFFF4H
System reserved
3
03
⎯
3F0H
000FFFF0H
System reserved
4
04
⎯
3ECH
000FFFECH
System reserved
5
05
⎯
3E8H
000FFFE8H
System reserved
6
06
⎯
3E4H
000FFFE4H
Coprocessor absent trap
7
07
⎯
3E0H
000FFFE0H
Coprocessor error trap
8
08
⎯
3DCH
000FFFDCH
INTE instruction
9
09
⎯
3D8H
000FFFD8H
System reserved
10
0A
⎯
3D4H
000FFFD4H
System reserved
11
0B
⎯
3D0H
000FFFD0H
Step trace trap
12
0C
⎯
3CCH
000FFFCCH
NMI request (tool)
13
0D
⎯
3C8H
000FFFC8H
Undefined instruction exception
14
0E
⎯
3C4H
000FFFC4H
NMI request
15
0F
⎯
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
Reload timer 1
25
19
ICR09
398H
000FFF98H
Base timer 0 (source 0/source 1)
26
1A
ICR10
394H
000FFF94H
Multi-function serial interface 0
(UART transmission completed/reception
completed/I2C status)
27
1B
ICR11
390H
000FFF90H
Multi-function serial interface 1
(UART transmission completed/reception
completed/I2C status)
28
1C
ICR12
38CH
000FFF8CH
Base timer 1 (source 0/source 1)
29
1D
ICR13
388H
000FFF88H
(Continued)
53
MB91470/480 Series
Interrupt number
Interrupt source
Interrupt
level
Offset
TBR default
address
Decimal
Hexadecimal
Base timer 2/3 (source 0/source 1)
Up/down counter 0
30
1E
ICR14
384H
000FFF84H
DTTI0/DTTI1
31
1F
ICR15
380H
000FFF80H
DMAC0 (end/error)
32
20
ICR16
37CH
000FFF7CH
DMAC1 (end/error)
33
21
ICR17
378H
000FFF78H
DMAC2/3/4 (end/error)
34
22
ICR18
374H
000FFF74H
Multi-function serial interface 2
(UART transmission completed/reception
completed/I2C status)
35
23
ICR19
370H
000FFF70H
Multi-function serial interface 3
(UART transmission completed/reception
completed/I2C status)
36
24
ICR20
36CH
000FFF6CH
Multi-function serial interface 4
(UART transmission completed/reception
completed/I2C status)
37
25
ICR21
368H
000FFF68H
Multi-function serial interface 5
(UART transmission completed/reception
completed/I2C status)
38
26
ICR22
364H
000FFF64H
MAC
39
27
ICR23
360H
000FFF60H
PPG0/PPG1
40
28
ICR24
35CH
000FFF5CH
PPG2/PPG3/PPG8/PPG9
41
29
ICR25
358H
000FFF58H
PPG4/PPG5/PPG10/PPG11
42
2A
ICR26
354H
000FFF54H
PPG6/PPG7/PPG12/PPG13/PPG14/PPG15
43
2B
ICR27
350H
000FFF50H
Wave form generator 0/3 (underflow)
44
2C
ICR28
34CH
000FFF4CH
Wave form generator 1/4 (underflow)
45
2D
ICR29
348H
000FFF48H
Wave form generator 2/5 (underflow)
46
2E
ICR30
344H
000FFF44H
Timebase timer overflow
47
2F
ICR31
340H
000FFF40H
External interrupt 8/9/10/11/12/13/14/15
48
30
ICR32
33CH
000FFF3CH
Free-run timer 0/3 (compare clear)
49
31
ICR33
338H
000FFF38H
Free-run timer 0/3 (zero detection)
50
32
ICR34
334H
000FFF34H
Free-run timer 1/4 (compare clear)
51
33
ICR35
330H
000FFF30H
Free-run timer 1/4 (zero detection)
52
34
ICR36
32CH
000FFF2CH
Free-run timer 2/5 (compare clear)
53
35
ICR37
328H
000FFF28H
Free-run timer 2/5 (zero detection)
54
36
ICR38
324H
000FFF24H
8/10-bit A/D converter 2
55
37
ICR39
320H
000FFF20H
8/10-bit A/D converter 0/
12-bit A/D converter 3
56
38
ICR40
31CH
000FFF1CH
(Continued)
54
MB91470/480 Series
(Continued)
Interrupt number
Interrupt source
Interrupt
level
Offset
TBR default
address
Decimal
Hexadecimal
8/10-bit A/D converter 1/
12-bit A/D converter 4
57
39
ICR41
318H
000FFF18H
ICU0/ICU1/ICU4/ICU5 (capture)
58
3A
ICR42
314H
000FFF14H
ICU2/ICU3/ICU6/ICU7 (capture)
59
3B
ICR43
310H
000FFF10H
OCU0/OCU1/OCU6/OCU7 (match)
60
3C
ICR44
30CH
000FFF0CH
OCU2/OCU3/OCU8/OCU9 (match)
61
3D
ICR45
308H
000FFF08H
OCU4/OCU5/OCU10/OCU11 (match)
62
3E
ICR46
304H
000FFF04H
Interrupt delay source bit
63
3F
ICR47
300H
000FFF00H
System reserved (Used by REALOS)
64
40
⎯
2FCH
000FFEFCH
System reserved (Used by REALOS)
65
41
⎯
2F8H
000FFEF8H
System reserved
66
42
⎯
2F4H
000FFEF4H
System reserved
67
43
⎯
2F0H
000FFEF0H
System reserved
68
44
⎯
2ECH
000FFEECH
System reserved
69
45
⎯
2E8H
000FFEE8H
System reserved
70
46
⎯
2E4H
000FFEE4H
System reserved
71
47
⎯
2E0H
000FFEE0H
System reserved
72
48
⎯
2DCH
000FFEDCH
System reserved
73
49
⎯
2D8H
000FFED8H
System reserved
74
4A
⎯
2D4H
000FFED4H
System reserved
75
4B
⎯
2D0H
000FFED0H
System reserved
76
4C
⎯
2CCH
000FFECCH
System reserved
77
4D
⎯
2C8H
000FFEC8H
System reserved
78
4E
⎯
2C4H
000FFEC4H
System reserved
79
4F
⎯
2C0H
000FFEC0H
Used by INT instruction
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
55
MB91470/480 Series
■ PIN STATUS IN EACH CPU STATE
Terms used as the status of pins mean as follows.
• Input enabled
Means that the input function can be used.
• Input fixed to “0”
A state of a pin, in which "0" is transmitted to internal circuitry, with the external input shut off by the input gate
adjacent to the pin.
• Output Hi-Z
Means to place a pin in a high impedance state by disabling the pin driving transistor from driving.
• Output storage
Means to output the state existing immediately prior to entering this mode.
That is, to output according to an internal resource with an output when it is operating or to preserve an output
when the output is provided, for example, as a port.
• Preserving the previous state
Means to be able to output or input the state existing immediately prior to entering this mode.
56
MB91470/480 Series
• List of pin status
Pin name
Function
P00 to P07
D16 to D23
P10 to P17
D24 to D31
P20 to P27
A00 to A07
P30 to P37
A08 to A15
P50 to P52
CS0X to CS2X
P53
ASX
P54
RDX
P55, P56
WR0X, WR1X
P60
SYSCLK
P61
RDY
NMIX
NMIX
P80 to P83
INT0 to INT3
P84
INT4/PPG4
P85
INT5/PPG5
P86
INT6/PPG6
P87
INT7/PPG7
P90
INT8/PPG8
P91
INT9/PPG9
P92
INT10/PPG10
P93
INT11/PPG11
P94
INT12/PPG12
P95
INT13/PPG13
P96
INT14/PPG14
P97
INT15/PPG15
PA0 to PA4
ADTG0 to
ADTG4
During initialization
INITX = “L”*
1
INITX = “H”*
2
Output Hi-Z/ Output Hi-Z/
Input disabled Input disabled
Input enabled Input enabled
In sleep mode
In stop mode
HIZ = 0
Retention of the Retention of the
immediately
immediately
prior state
prior state
Output Hi-Z/
Input “0” fixed
Input enabled
Input enabled
Input enabled
Input enabled
(only when
external
interrupt is
enabled)
Output Hi-Z/ Output Hi-Z/
Input disabled Input disabled
Retention of the Retention of the
immediately
immediately
prior state
prior state
Output Hi-Z/
Input “0” fixed
Output Hi-Z/ Output Hi-Z/
Input disabled Input disabled
Retention of the Retention of the
immediately
immediately
prior state
prior state
Output Hi-Z/
Input “0” fixed
Output Hi-Z/ Output Hi-Z/
Input disabled Input enabled
Input enabled
HIZ = 1
Input enabled
PB0 to PB3 AN0-0 to AN0-3
PB4 to PB7 AN1-0 to AN1-3
PC0
AN2-0/SCK4
PC1
AN2-1/SIN4
PC2
AN2-2/SOT4
PC3
AN2-3/SCK5
PC4
AN2-4/SIN5
PC5
AN2-5/SOT5
PC6, PC7
AN2-6, AN2-7
(Continued)
57
MB91470/480 Series
(Continued)
Pin name
Function
During initialization
1
INITX = “L”*
2
INITX = “H”*
PD0 to PD3 AN2-8 to AN2-11
PE0 to PE3
AN3-0 to AN3-3
PE4 to PE7
AN4-0 to AN4-3
PF0
CLKPOUT
PF1 to PF6
GPIO
PG0, PG3
SCK0, SCK1
PG1, PG4
SIN0, SIN1
PG2, PG5
SOT0, SOT1
PH0, PH3
SCK2, SCK3
PH1, PH4
SIN2, SIN3
PH2, PH5
SOT2, SOT3
PJ0, PJ2,
PJ4, PJ6
TIN0 to TIN3
PJ1, PJ3,
PJ5, PJ7
TOUT0 to
TOUT3
PL0
AIN0
PL1
BIN0
PL2
ZIN0
PM0 to PM3 PPG0 to PPG3
PP0 to PP3
IC0 to IC3
PP4
CKI0
PP5
DTTI0
PQ0 to PQ5
RTO0 to RTO5
PR0 to PR3
IC4 to IC7
PR4
CKI1
PR5
DTTI1
PS0 to PS5
RTO6 to RTO11
In sleep mode
In stop mode
HIZ = 0
HIZ = 1
Output Hi-Z/ Output Hi-Z/
Input disabled Input disabled
Retention of the Retention of the
Output Hi-Z/
immediately
immediately
Input “0” fixed
prior state
prior state
Output Hi-Z/ Output Hi-Z/
Input disabled Input disabled
Retention of the Retention of the
Output Hi-Z/
immediately
immediately
Input “0” fixed
prior state
prior state
Output Hi-Z/ Output Hi-Z/
Input disabled Input disabled
Retention of the Retention of the
Output Hi-Z/
immediately
immediately
Input “0” fixed
prior state
prior state
Output Hi-Z/ Output Hi-Z/
Input disabled Input disabled
Retention of the Retention of the
Output Hi-Z/
immediately
immediately
Input “0” fixed
prior state
prior state
Output Hi-Z/ Output Hi-Z/
Input disabled Input disabled
Retention of the Retention of the
Output Hi-Z/
immediately
immediately
Input “0” fixed
prior state
prior state
Output Hi-Z/ Output Hi-Z/
Input disabled Input disabled
Retention of the Retention of the
Output Hi-Z/
immediately
immediately
Input “0” fixed
prior state
prior state
Output Hi-Z/ Output Hi-Z/
Input disabled Input disabled
Retention of the Retention of the
Output Hi-Z/
immediately
immediately
Input “0” fixed
prior state
prior state
Output Hi-Z/ Output Hi-Z/
Input disabled Input disabled
Retention of the Retention of the
Output Hi-Z/
immediately
immediately
Input “0” fixed
prior state
prior state
*1 : INITX = “L” : Indicates the pin status with INITX remaining at the “L” level.
*2 : INITX = “H” : Indicates the pin status existing immediately after INITX transition from “L” to “H” level.
58
MB91470/480 Series
• List of pin status (external bus mode)
Pin name
Function
P00 to P07
D16 to D23
P10 to P17
D24 to D31
P20 to P27
A00 to A07
P30 to P37
A08 to A15
P50 to P52
CS0X to CS2X
P53
ASX
P54
RDX
P55, P56
WR0X, WR1X
P60
SYSCLK
P61
RDY
During initialization
INITX = “L”*
Output Hi-Z
1
2
INITX = “H”*
Output Hi-Z
In sleep mode
In Stop mode
HIZ = 0
HIZ = 1
Retention of the Retention of the Output Hi-Z
immediately
immediately
prior state
prior state
Input disabled Input disabled
Input “0”
fixed
*1 : INITX = “L” : Indicates the pin status with INITX remaining at the “L” level.
*2 : INITX = “H” : Indicates the pin status existing immediately after INITX transition from “L” to “H” level.
59
MB91470/480 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.5
VSS + 6.0
V
Analog power supply
voltage*1,*2,*6
AVCC10
AVCC12
VSS − 0.5
VSS + 6.0
V
Analog reference voltage*7
AVRHn
VSS − 0.5
VSS + 6.0
V
VI
VSS − 0.3
VCC + 0.3
V
Analog pin input voltage*1
VIA
VSS − 0.3
AVCC + 0.3
V
Output voltage*1
VO
VSS − 0.3
VCC + 0.3
V
“L” level maximum output
current*3
IOL
⎯
10
mA
“L” level average output
current*4
IOLAV
⎯
4
mA
Except port Q0 to Q5 and S0 to S5
12
mA
Port Q0 to Q5 and S0 to S5
“L” level total maximum
output current
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
IOH
⎯
−10
mA
“H” level average output
current *4
IOHAV
⎯
−4
mA
Except port Q0 to Q5 and S0 to S5
−12
mA
Port Q0 to Q5 and S0 to S5
“H” level total maximum
output current
ΣIOH
⎯
−100
mA
ΣIOHAV
⎯
−50
mA
Power consumption
PD
⎯
800
mW
Storage temperature
TSTG
−55
+125
°C
Power supply voltage*1
Input voltage*
1
“L” level total average output
current*5
“H” level maximum output
current*3
“H” level total average
output current*5
*1 : The parameter is based on VSS = AVSS10 = AVSS12 = 0 V.
*2 : Be careful not to exceed VCC + 0.3 V, for example, when the power is turned on.
Be careful to set AVCC10, AVCC12 equal VCC, for example, when the power is turned on.
*3 : The maximum output current is the peak value for a single pin.
*4 : The average output is the average current for a single pin over a period of 100 ms.
*5 : The total average output current is the average current for all pins over a period of 100 ms.
*6 : AVCC10 is the analog supply voltage for the 8/10-bit A/D converter, and AVCC12 is the analog supply voltage
for the 12-bit A/D converter.
*7 : AVRHn=AVRH0/AVRH1/AVRH2 are the analog reference voltage for the 8/10-bit A/D converter, and AVRH3/
AVRH4 are the analog reference voltage for the 12-bit A/D converter.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
60
MB91470/480 Series
2. Recommended Operating Conditions
(VSS = AVSS10 = AVSS12 = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min
Max
VCC
4.0
5.5
V
AVCC10
VSS + 4.0
VSS + 5.5
V
For all 8/10-bit A/D converter
(common use)
AVCC12
VSS + 4.0
VSS + 5.5
V
For all 12-bit A/D converter
(common use)
AVRH0
AVSS10
AVCC10
V
For 8/10-bit A/D converter 0
AVRH1
AVSS10
AVCC10
V
For 8/10-bit A/D converter 1
AVRH2
AVSS10
AVCC10
V
For 8/10-bit A/D converter 2
AVRH3
AVSS12
AVCC12
V
For 12-bit A/D converter 3
AVRH4
AVSS12
AVCC12
V
For 12-bit A/D converter 4
(-) Analog input signal voltage
range
ANINN
AVSS12
AVCC12/2
V
(+) Analog input signal
voltage range
ANINP
AVSS12
AVCC12
V
ANINN-ANINP voltage
difference
ANINN−
ANINP
⎯
AVCC12/4
V
Power supply voltage
Analog power supply voltage
Analog reference voltage
+ 70
Operating temperature
TA
− 40
°C
+ 85
For all 12-bit A/D converters
(common use)
(under differential mode)
When mounted on single-layer
PCB*
When mounted on four-layer
PCB*
* : The remaining rating values assume four-layer PCB.
Note : During power-on, it takes approximately 600 µs for the internal power supply to stabilize after the VCC power
supply has stabilized. Continue to assert the INITX pin during this period.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
61
MB91470/480 Series
3. DC Characteristics
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V)
Parameter
Symbol
Pin
Conditions
Value
Min
Typ
Max
Unit
Remarks
VIH
CMOS
input pin
⎯
VCC × 0.7
⎯
VCC
V
VIHS
CMOS
hysteresis
input pin
⎯
VCC × 0.8
⎯
VCC
V
VIL
CMOS
input pin
⎯
VSS
⎯
VCC × 0.3
V
VILS
CMOS
hysteresis
input pin
⎯
VSS
⎯
VCC × 0.2
V
VOH1
Except port
VCC = 5.0 V,
Q0 to Q5 and
IOH = 4 mA
port S0 to S5
VCC − 0.5
⎯
⎯
V
VOH2
Port Q0 to
Q5 and port
S0 to S5
VCC − 0.5
⎯
⎯
V
VOL1
Except port
VCC = 5.0 V,
Q0 to Q5 and
IOL = 4 mA
port S0 to S5
⎯
⎯
VSS + 0.4
V
VOL2
Port Q0 to
Q5 and port
S0 to S5
VCC = 5.0 V,
IOL = 12 mA
⎯
⎯
VSS + 0.4
V
Input leak
current
ILI
⎯
VCC = 5.0 V,
VSS < VI < VCC
−5
⎯
⎯
µA
Pull-up
resistance
RPULL
⎯
50
⎯
kΩ
⎯
When the
multiply and
mA accumulate
unit is not
used.
⎯
When the
multiply and
mA
accumulate
unit is used.
“H” level input
voltage
“L” level input
voltage
“H” level
output voltage
“L” level output
voltage
Power
supply
current
ICC
INITX,
pull-up pin
VCC
VCC = 5.0 V,
IOH = 12 mA
⎯
Flash memory
VCC = 5.0 V,
fC = 20 MHz,
PLL × 4,
CLKB = 80 MHz
CLKP = 40 MHz
CLKT = 40 MHz
⎯
⎯
100
140
(Continued)
62
MB91470/480 Series
(Continued)
Parameter
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V)
Symbol
ICC
Pin
VCC
MASK ROM
VCC = 5.0 V,
fC = 20 MHz,
PLL × 4,
CLKB = 80 MHz
CLKP = 40 MHz
CLKT = 40 MHz
Value
Min
⎯
⎯
⎯
Power
supply
current
ICCS
ICCH
Input
capacitance
Conditions
CIN
VCC
VCC
Other than
VCC, VSS,
AVSS12, AVSS10,
AVCC12, AVCC10,
AVRH0, AVRH1,
AVRH2, AVRH3,
AVRH4
Typ
65
105
50
Max
Unit
Remarks
⎯
When the
multiply and
mA accumulate
unit is not
used.
⎯
When the
multiply and
mA
accumulate
unit is used.
⎯
In sleep
mode
(When
multiplication
mA
and addition
calculator
circuit is not
used.)
VCC = 5.0 V,
fC = 20 MHz,
PLL × 4,
CLKB = 80 MHz
CLKP = 40 MHz
CLKT = 40 MHz
⎯
80
⎯
In sleep
mode
(When
multiplication
mA
and addition
calculator
circuit is
used.)
VCC = 5.0 V,
TA = + 25 °C
⎯
350
⎯
µA
In stop mode
VCC = 5.0 V,
TA = + 85 °C
⎯
1500
⎯
µA
In stop mode
⎯
5
15
pF
⎯
63
MB91470/480 Series
4. Flash Memory Write/Erase Characteristics
Parameter
64
Conditions
Value
Min
Typ
Max
Unit
Remarks
Sector erase time
(8 Kbytes sectors)
VCC = 5.0 V,
TA = + 25 °C
⎯
0.5
2.0
s
Not including time for internal
writing before deletion.
Word write time
VCC = 5.0 V,
TA = + 25 °C
⎯
6
100
µs
Not including system-level
overhead time.
Chip write time
VCC = 5.0 V,
TA = + 25 °C
⎯
1.8
29.5
s
Not including system-level
overhead time.
Erase/write cycle
⎯
10000
⎯
⎯
cycle
Flash memory data
hold time
⎯
10
⎯
⎯
year
MB91470/480 Series
5. AC Characteristics
(1) Clock Timing
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V)
Parameter
Sym- Pin
bol Name
Clock frequency
fC
Condition
X0
X1
Value
Min
Typ
Unit
Max
When using the
PLL within the
MHz self-oscillating
range, set the
multiplier so that
the internal clock
does not exceed
ns the internal operating clock frequency.
10*2
⎯
20
100
⎯
50*2
5*1
⎯
80
MHz CPU
5*1
⎯
40
MHz Peripheral
5*1
⎯
40
MHz External bus
12.5
⎯
200
ns
CPU
25
⎯
200
ns
Peripheral
25
⎯
200
ns
External bus
⎯
Clock cycle time
tC
X0
X1
fCP
Internal operating
clock frequency
fCPP
⎯
fCPT
tCP
Internal operating
clock cycle time
tCPP
⎯
When 20 MHz is
input as the X0
clock frequency and
the oscillator circuit
PLL system is set to
× 4 multiplication
tCPT
Remarks
*1 : The values assume a gear cycle of 1/16.
*2 : When the PLL is used, the PLL multiplication rate varies depending on the frequency of the clock input
to the X0 and X1 pins. Set the PLL multiplication rate so that the PLL output clock frequency is in the
range between 40 MHz and 80 MHz.
PLL Multiplication Rate
PLL output clock frequency
when X0 = 10 MHz
PLL output clock frequency
when X0 = 20 MHz
1
2
3
(Setting not allowed)
(Setting
not
allowed)
40 MHz
60 MHz
4
5
6
7
8
40 MHz
50 MHz
60 MHz
70 MHz
80 MHz
80 MHz
(Setting not allowed)
• Conditions for measuring the clock timing ratings
tC
Output pin
0.8 VCC
C = 50 pF
65
MB91470/480 Series
• Operation assurance range
Power supply voltage
VCC (V)
5.5
4.0
fCP (MHz)
0 0.31
80
but the upper limit of fCPT/fCPP is 40 MHz.
Internal clock
• Internal clock setting range
(MHz)
80
Internal clock
CPU (CLKB) :
Peripheral (CLKP)
External bus (CLKT) :
40
Oscillation input clock fC = 20 MHz
(PLL multiplied by 4)
5
16 :16
2:2
1:2
CPU : Divided ratio for
peripherals/external bus.
Notes : • When the PLL is used, the external clock input should be in the range of 10 MHz to 20 MHz.
• Treat the PLL oscillation stabilization time as > 600 µs
• Set the internal clock gear setting to within the values shown in the clock timing ratings table.
66
MB91470/480 Series
(2) Clock Output Timing
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol Pin Name
Cycle time
tCYC
SYSCLK↑→ SYCSCLK↓
tCHCL
SYSCLK↓→ SYCSCLK↑
tCLCH
Value
Condition
⎯
SYSCLK
Unit Remarks
Min
Max
tCPT
⎯
ns
*1
tCYC/2 − 5
tCYC/2 + 5
ns
*2
tCYC/2 − 5
tCYC/2 + 5
ns
*1 : tCYC is the frequency of one clock cycle including the gear cycle.
*2 : The following ratings are for the gear ratio set to × 2. For the ratings when the gear ratio is set to 1/4 and 1/8,
can be calculated by substituting 1/4 or 1/8 for n respectively in the following equation.
(1/2 × 1/n) × tCYC-5
Note : For tCPT (internal clock cycle time) , refer to “(1) Clock Timing”.
tCYC
tCHCL
tCLCH
VOH
VOH
SYSCLK
VOL
(3) PLL Oscillation stabilization time (LOCK UP TIME)
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
PLL Oscillation stabilization wait time
(LOCK UP TIME)
Symbol
Pin Name
Condition
tLOCK*
⎯
⎯
Value
Min
Max
600
⎯
Unit
µs
* : The length of time to wait for the PLL oscillations to stabilize.
67
MB91470/480 Series
(4) Reset Input Ratings
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
INITX input time
(at power-on and stop mode)
Symbol
tINTL
Pin Name
INITX
Condition
⎯
INITX input time
(other than the above)
Value
Unit
Min
Max
Oscillation time of
oscillator
tc × 10
⎯
ns
tc × 10
⎯
ns
Notes : • It takes approximately 600 µs for the internal power to stabilize after the power supply has stabilized.
Continue to input “L” level to the INITX pin during this period.
• For tCPT (internal clock cycle time) , refer to “(1) Clock Timing”.
tINTL
INITX
0.2 VCC
68
MB91470/480 Series
(5) Normal Bus Access Read/Write Operation
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C)
Value
CondiParameter
Symbol
Pin Name
Unit Remarks
tion
Min
Max
ASX setup
tASLCH
ASX hold
tCHASH
CS0X to CS2X setup
tCSLCH
CS0X to CS2X hold
tCHCSH
Address setup
Address hold
Valid address →
Valid data input time
RDX delay time
SYSCLK
ASX
⎯
SYSCLK
CS0X to CS2X
⎯
⎯
ns
3
1/2 × tCYC + 10
ns
3
⎯
ns
3
1/2 × tCYC + 10
ns
3
⎯
ns
3
⎯
ns
tASCH
SYSCLK
A15 to A00
tASRL
RDX
A15 to A00
tASWL
WR0X, WR1X
A15 to A00
3
⎯
ns
tCHAX
SYSCLK
A15 to A00
3
1/2 × tCYC + 10
ns
tRHAX
RDX
A15 to A00
3
⎯
ns
tWHAX
WR0X, WR1X
A15 to A00
3
⎯
ns
tAVDV
A15 to A00
D31 to D16
⎯
⎯
3/2 × tCYC − 7
ns
SYSCLK
RDX
⎯
⎯
10
ns
⎯
⎯
10
ns
⎯
tCYC − 5
ns
18
⎯
ns
0
⎯
ns
tCYC − 5
⎯
ns
⎯
10
ns
⎯
10
ns
tCYC
⎯
ns
3
⎯
ns
tCYC − 5
⎯
ns
tCHRL
tCHRH
⎯
⎯
RDX ↓ →
Valid data input time
tRLDV
Data setup →
RDX ↑ time
tDSRH
RDX ↑ →
Data hold time
tRHDX
RDX minimum pulse width
tRLRH
RDX
⎯
tCHWL
SYSCLK
RDX
⎯
WR0X, WR1X delay time
3
tCHWH
Data setup →
WR0X, WR1X ↑ time
tDSWH
WR0X, WR1X ↑ →
Data hold time
tWHDX
WR0X, WR1X minimum pulse
width
tWLWH
RDX
D31 to D16
⎯
WR0X, WR1X
D31 to D16
⎯
WR0X, WR1X
⎯
*1
*2
*1
(Continued)
69
MB91470/480 Series
(Continued)
*1 : When the bus timing is delayed by an automatic wait instruction or RDY input, add the time (tCYC × the number
of delay cycles added) to this rating.
*2 : The following ratings are for the gear ratio set to × 2. For the ratings when the gear ratio is set to between 1/3
and 1/16, substitute the value between 1/3 and 1/16 for n in the following equation.
Formula : 3/ (2n) × tCYC−15
Note : Load capacitance C = 50 pF
tCYC
SYSCLK
VOH
VOH
tCHASH
tASLCH
ASX
VOH
VOL
tCSLCH
CS0X to CS2X
tCHCSH
VOH
VOL
tASCH
A15 to A00
tCHAX
VOH
VOL
VOH
VOL
tCHRL
tCHRH
tRLRH
RDX
VOH
VOL
tASRL
tRHAX
tRLDV
tDSRH
tRHDX
tAVDV
VOH
VOL
D31 to D16
(Read)
tCHWL
VOH
VOL
tCHWH
tWLWH
VOH
WR0X, WR1X
tASWL
tWHAX
tDSWH
D31 to D16
(Write)
70
VOH
VOL
tWHDX
VOH
VOL
MB91470/480 Series
(6) Multiplex Bus Access Read/Write Operation
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
A15 to A00 address
setup time → SYSCLK ↑
tASCH
SYSCLK ↑ → A15 to A00 address
Hold Time
tCHAX
A15 to A00 address
setup time → ASX ↑
tASASH
ASX ↑ → A15 to A00 address
hold time
tASHAX
Pin Name
Value
Condition
Unit
Min
Max
3
⎯
ns
3
1/2 × tCYC + 10
ns
12
⎯
ns
tCYC − 5
tCYC + 5
ns
SYSCLK,
D31 to D16
⎯
ASX,
D31 to D16
Notes : • This rating is not guaranteed when the CSX → RDX/WRX Setup Delay setting by AWR : bit1 is “0”.
• Normal bus interface ratings are applicable except this rating.
• For tCYC (cycle time), refer to “(2) Clock Output Timing”.
tCYC
SYSCLK
AS
VOH
VOH
VOH
VOL
tASASH
tASCH
D31 to D16
(A15 to A00)
tASHAX
tCHAX
VOH
VOL
71
MB91470/480 Series
(7) Ready Input Timing
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
RDY setup time →
SYSCLK ↑
tRDYS
SYSCLK ↑ →
RDY hold time
tRDYH
Pin Name
Value
Condition
SYSCLK,
RDY
Max
18
⎯
ns
0
⎯
ns
⎯
tCYC
VOH
SYSCLK
VOH
VOL
VOL
tRDYS
tRDYS
tRDYH
tRDYH
RDY
(When WAIT is used)
VOH
VOL
VOH
VOL
RDY
(When WAIT is not used)
VOH
VOH
VOL
72
Unit
Min
VOL
MB91470/480 Series
(8) UART Timing
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin
Serial clock cycle time
tSCYC
SCK↓→SOT delay time
Conditions
Value
Unit
Min
Max
SCK0 to SCK5
8 × tCYCP
⎯
ns
tSLOV
SCK0 to SCK5
SOT0 to SOT5
−50
+50
ns
Valid SIN→SCK↑
tIVSH
SCK0 to SCK5
SIN0 to SIN5
50
⎯
ns
SCK↑→
Valid SIN hold time
tSHIX
SCK0 to SCK5
SIN0 to SIN5
0
⎯
ns
Serial clock “H” pulse width
tSHSL
SCK0 to SCK5
4 × tCYCP
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK5
4 × tCYCP
⎯
ns
SCK↓→SOT delay time
tSLOV
SCK0 to SCK5
SOT0 to SOT5
⎯
50
ns
Valid SIN→SCK↑
tIVSH
SCK0 to SCK5
SIN0 to SIN5
50
⎯
ns
SCK↑→ Valid SIN hold time
tSHIX
SCK0 to SCK5
SIN0 to SIN5
50
⎯
ns
Internal shift
clock mode
External shift
clock mode
Notes : • The above ratings are the AC characteristics for CLK synchronous mode.
• tCYCP indicates the peripheral clock cycle time.
73
MB91470/480 Series
• Internal shift clock mode
tSCYC
SCK0 to SCK5
VOH
VOL
VOL
tSLOV
VOH
VOL
SOT0 to SOT5
tIVSH
tSHIX
VOH
VOL
SIN0 to SIN5
VOH
VOL
• External shift clock mode
tSLSH
tSHSL
VOH
SCK0 to SCK5
VOL
VOL
VOL
tSLOV
SOT0 to SOT5
VOH
VOL
tIVSH
SIN0 to SIN5
74
VOH
VOL
tSHIX
VOH
VOL
MB91470/480 Series
(9) Free-run Timer Clock, Up/Down Counter, Base Timer, and External Interrupt Input Timing
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Free-run timer
input clock pulse width
Up-down counter
input pulse width
Base timer
input pulse width
Pin Name
Unit
Min
Max
CKI0, CKI1
4 × tCYCP
⎯
ns
AIN0
BIN0
ZIN0
4 × tCYCP
⎯
ns
4 × tCYCP
⎯
ns
4 × tCYCP
⎯
ns
1.0
⎯
µs
tTIWH
tTIWL
⎯
TIN0 to TIN3
External interrupt
input pulse width
Value
Condition
INT0 to INT15
Note : tCYCP indicates the peripheral clock cycle time.
tTIWH
VOH
CKI0, CKI1
AIN0, BIN0, ZIN0
TIN0 to TIN3
INT0 to INT15
tTIWL
VOH
VOL
VOL
75
MB91470/480 Series
(10) Trigger Input Timing
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin Name
tICWH
tICWL
IC0 to IC7
Base timer trigger input
tTGINWH
tTGINWL
TIN0 to TIN3
A/D activation trigger input
tADTGWH
tADTGWL
ADTG0 to ADTG4
Input Capture trigger input
Condition
⎯
Note : tCYCP indicates the peripheral clock cycle time.
tICWH
tTGINWH
tADTGWH
VOH
IC0 to IC7
TIN0 to TIN3
ADTG0 to ADTG4
tICWL
tTGINWL
tADTGWL
VOH
VOL
76
VOL
Value
Unit
Min
Max
5 × tCYCP
⎯
ns
4 × tCYCP
⎯
ns
5 × tCYCP
⎯
ns
MB91470/480 Series
(11) I2C Timing
a. Master Mode
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Standard Mode
Symbol Condition
Fast Mode *3
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
“L” width of the SCL clock
tLOW
4.7
⎯
1.3
⎯
ms
“H” width of the SCL
clock
tHIGH
4.0
⎯
0.6
⎯
ms
Bus free time between
STOP and START
conditions
tBUS
4.7
⎯
1.3
⎯
ms
SCL↓→
SDA output delay time
tDLDAT
⎯
5 × tCYCP *1
⎯
5 × tCYCP *1
ns
Setup time for a repeated
START condition
SCL↑→SDA↓
tSUSTA
4.7
⎯
0.6
⎯
ms
R=1 kΩ,
C=50 pF*4
Hold time for a repeated
START condition
SDA↓→SCL↓
tHDSTA
4.0
⎯
0.6
⎯
ms
Setup time for STOP
condition
SCL↑→SDA↑
tSUSTO
4.0
⎯
0.6
⎯
ms
SDA Data input hold time
(vs. SCL↓)
tHDDAT
2 × tCYCP *1
⎯
2 × tCYCP *1
⎯
ms
SDA Data input setup
time (vs. SCL↑)
tSUDAT
250
⎯
100 *2
⎯
ns
Remarks
The first
clock pulse
is generated
after this.
*1 : tCYCP indicates the peripheral clock cycle time.
*2 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
If a device does not extend the “L” period of the SCL signal, it is necessary to output the next piece of data to
the SDA line 1250 ns (SDA and SCL rising Max time + tSUDAT) before the SCL line is released.
*3 : For use at over 100 kHz, set the resource clock to at least 6 MHz.
*4 : R and C are the pull-up resistance and load capacitance of the SCL and SDA lines.
77
MB91470/480 Series
b. Slave Mode
(VCC = 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol Condition
Standard Mode
Fast Mode *3
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
“L” width of the SCL
clock
tLOW
4.7
⎯
1.3
⎯
µs
“H” width of the SCL
clock
tHIGH
4.0
⎯
0.6
⎯
µs
Bus free time between
STOP and START
conditions
tBUS
4.7
⎯
1.3
⎯
µs
SCL ↓ → SDA output
delay time
tDLDAT
⎯
5 × tCYCP *1
⎯
5 × tCYCP *1
ns
Setup time for a
repeated START
condition
SCL ↑ → SDA ↓
tSUSTA
4.7
⎯
0.6
⎯
µs
R=1 kΩ,
C=50 pF*4
Hold time for a repeated
START condition
SDA ↓ → SCL ↓
tHDSTA
4.0
⎯
0.6
⎯
µs
Setup time for STOP
condition
SCL ↑ → SDA ↑
tSUSTO
4.0
⎯
0.6
⎯
µs
SDA Data input hold
time
(vs. SCL ↓)
tHDDAT
2 × tCYCP *1
⎯
2 × tCYCP *1
⎯
µs
SDA Data input setup
time
(vs. SCL ↑)
tSUDAT
250
⎯
100 *2
⎯
ns
Remarks
The first
clock pulse
is generated
after this.
*1 : tCYCP indicates the peripheral clock cycle time.
*2 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
If a device does not extend the “L” period of the SCL signal, it is necessary to output the next piece of data to
the SDA line 1250 ns (SDA and SCL rising Max time + tSUDAT) before the SCL line is released.
*3 : For use at over 100 kHz, set the resource clock to at least 6 MHz.
*4 : R and C are pull-up resistance and load capacitance of the SCL and SDA lines.
78
MB91470/480 Series
6. Electrical Characteristics for the A/D Converter
(1) 8/10-bit A/D Converter
(VCC = 4.0 V to 5.5 V, AVRHn = 4.0 V to 5.5 V, VSS = AVSS10 = 0 V, TA = − 40 °C to + 85 °C)
Symbol
Pin Name
Resolution
⎯
Total error
Parameter
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
−4
⎯
+4
LSB
Linearity error
⎯
⎯
− 3.5
⎯
+ 3.5
LSB
Differential
linearity error
⎯
⎯
−3
⎯
+3
LSB
Remarks
Zero transition
voltage
VOT
When AVRHn =
AN0-0 to AN0-3
5.0 V
AN1-0 to AN1-3 AVSS10−3.5 AVSS10+0.5 AVSS10+4.5 LSB
AN2-0 to AN2-11
Full-scale
transition voltage
VFST
AN0-0 to AN0-3
AN1-0 to AN1-3 AVRHn−5.5
AN2-0 to AN2-11
Conversion time*1
⎯
⎯
1.2
⎯
⎯
µs
Analog port input
current
IAIN
AN0-0 to AN0-3
AN1-0 to AN1-3
AN2-0 to AN2-11
⎯
⎯
10
µA
Analog input
voltage
VAIN
AN0-0 to AN0-3
AN1-0 to AN1-3
AN2-0 to AN2-11
AVSS10
⎯
AVRHn
V
Reference voltage
⎯
AVRHn
AVSS10
⎯
AVCC10
V
Power supply
current
(Analog + digital)
IA
AVCC10
⎯
2
⎯
mA
IAH*2
AVCC10
⎯
⎯
5
µA
IR
AVRHn
⎯
1
⎯
For each 1 unit,
mA at AVRHn = 5.0 V
AVSS10 = 0 V
IRH*2
AVRHn
⎯
⎯
5
µA
Analog input
capacitance
⎯
⎯
⎯
⎯
12.5
pF
Interchannel
disparity
⎯
AN0-0 to AN0-3
AN1-0 to AN1-3
AN2-0 to AN2-11
⎯
⎯
4
LSB
Reference voltage
supply current
(between AVRH
and AVSS)
AVRHn−1.5
AVRHn+2.5 LSB
For each 1 unit
For each 1 unit,
at stop mode
*1 : When VCC = AVCC10 = 5.0 V and Machine clock = 33 MHz
*2 : The current when the CPU is in stop mode and the A/D converter is not operating (at VCC = AVCC10 =
AVRHn = 5.0 V) .
Notes : • The above figures do not guarantee the accuracy between each unit.
• Output impedance of the external circuit ≤ 2 kΩ.
• AVRHn = AVRH0, AVRH1, and AVRH2
79
MB91470/480 Series
(2) 12-bit A/D Converter
(VCC = 4.0 V to 5.5 V, AVRHn = 4.0 V to 5.5 V, VSS = AVSS12 = 0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin Name
Resolution
⎯
Linearity error
Differential
linearity error
Value
Unit
Remarks
Min
Typ
Max
⎯
⎯
⎯
12
bit
⎯
⎯
−3.6
⎯
+ 3.6
LSB
⎯
⎯
−3
⎯
+3
LSB
Zero transition
voltage
VOT
AN3-0 to AN3-3
AN4-0 to AN4-3
Typ −
20 mV
AVSS12 +
0.5 LSB
Typ +
20 mV
⎯
Full-scale
transition voltage
VFST
AN3-0 to AN3-3
AN4-0 to AN4-3
Typ −
20 mV
AVRHn −
1.5 LSB
Typ +
20 mV
⎯
2.0
⎯
⎯
µs
When machine
clock = 33 MHz
2.2
⎯
⎯
µs
When machine
clock = 40 MHz
Conversion time
⎯
⎯
Analog port
input current
IAIN
AN3-0 to AN3-3
AN4-0 to AN4-3
⎯
⎯
10
µA
Analog input
voltage
VAIN
AN3-0 to AN3-3
AN4-0 to AN4-3
AVSS12
⎯
AVRHn
V
Reference
voltage
⎯
AVRHn
AVSS12
⎯
AVCC12
V
Analog supply
current
(analog + digital)
IA
AVCC12
⎯
2
⎯
mA
IAH*
AVCC12
⎯
⎯
5
µA
When AVRHn =
5.0 V
For each unit
Reference
voltage supply
current
(between AVRH
and AVSS)
IR
AVRHn
⎯
1
⎯
For each unit,
mA at AVRHn = 5.0 V,
AVSS12 = 0 V
IRH*
AVRHn
⎯
⎯
5
µA
Analog input
capacitance
⎯
⎯
⎯
⎯
18
pF
Interchannel
disparity
⎯
AN3-0 to AN3-3
AN4-0 to AN4-3
⎯
⎯
4
LSB
For each unit,
at stop mode
* : The current when the CPU is in stop mode and the A/D converter is not operating (at VCC = AVCC10 =
AVRHn = 5.0 V) .
Notes : • The above figures do not guarantee the accuracy between each unit.
• Output impedance of the external circuit ≤ 2 kΩ
• AVRHn = AVRH3, AVRH4
80
MB91470/480 Series
• External impedance and sampling time of analog inputs
• The A/D converter is fitted with a sample and hold circuit. If the external impedance is so high that there is not
sufficient time for sampling, the internal sample and hold capacitor will not fully charge to the analog voltage,
and the precision of the A/D conversion will be adversely affected. Therefore, in order to satisfy the A/D
conversion precision specifications, either adjust the register values and operating frequency or reduce the
external impedance so that the sampling time is greater than the minimum value as given by the relationship
between external impedance and minimum sampling time. If you are still unable to hold enough sampling time,
connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input circuit schematic
R
Analog input
Comparator
C
During sampling : ON
8/10-bit A/D converter
12-bit A/D converter
R
4.6 kΩ
1.0 kΩ
C
12.5 pF
18.0 pF
Note : The values are reference values.
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
8/10-bit A/D converter
100
90
80
70
60
50
40
30
20
10
0
12-bit A/D converter
0
2
4
6
8
10
12
Minimum sampling time [µs]
14
8/10-bit A/D converter
20
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
18
16
14
12
10
8
6
4
2
0
12-bit A/D converter
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
Minimum sampling time [µs]
• About errors
• The relative error increases as the value of |AVRH − AVSS| decreases.
81
MB91470/480 Series
• Definition of 8/10-bit A/D Converter Terms
• Resolution
• Linearity error
: Analog variation that is recognized by the A/D converter.
: Deviation between the line connecting zero transition point
(0000000000←→0000000001) and full-scale transition point
(1111111110←→1111111111) and actual conversion characteristics.
• Differential linear error : Deviation from the ideal value of input voltage necessary to change the output code
by ILSB.
• Total Error
: This error is the difference between actual and ideal values, including the zero
transition error/full-scale transition error/linearity error.
Linearity error
FFFH
Differential linear error
Actual conversion
characteristic
Actual conversion
characteristic
(N + 1)H
FFEH
Digital output
VFST
(Measurement
value)
VNT
004H
(Measurement
value)
003H
Digital output
{1 LSB (N − 1) + V OT}
FFDH
Ideal characteristic
NH
V(N+1)T
(N − 1)H
(Measurement
value)
Actual conversion
characteristic
Ideal characteristic
002H
VNT
(Measurement value)
(N − 2)H
001H
VOT
AVSS
Actual conversion
characteristic
(Measurement value)
Analog input
AVRH
AVSS
Analog input
AVRH
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
1 LSB
V (N+1) T − VNT
Differential linear error in digital output N =
− 1 [LSB]
1 LSB
VFST − VOT
1 LSB =
1022
N
: A/D converter digital output value
VOT : Voltage at which digital output changes from 000H to 001H.
VFST : Voltage at which digital output changes from 3FEH to 3FFH.
VNT : Voltage at which digital output changes from (N − 1) H to NH.
Linear error in digital output N =
(Continued)
82
MB91470/480 Series
(Continued)
Total error
3FFH
1.5 LSB'
Actual conversion
characteristic
3FEH
Digital output
3FDH
{1 LSB' (N − 1) + 0.5 LSB'}
004H
VNT
003H
(Measurement value)
Actual conversion
characteristic
002H
Ideal characteristic
001H
0.5 LSB'
AVSS
Analog input
AVRH
AVRH − AVSS
[V]
1024
VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
Total error of digital output N =
1 LSB’
N : A/D converter digital output value
VNT : Voltage at which digital output changes from (N + 1) H to NH.
VOT’ (ideal value) = AVSS + 0.5 LSB’ [V]
VFST’ (ideal value) = AVRH − 1.5 LSB’ [V]
1 LSB’ (ideal value) =
83
MB91470/480 Series
• Definition of 12-bit A/D Converter Terms
• Resolution
• Linearity error
: Analog variation that is recognized by the A/D converter.
: Deviation between the line connecting zero transition point
(000000000000←→000000000001) and full-scale transition point
(111111111110←→111111111111) and actual conversion characteristics.
• Differential linear error : Deviation from the ideal value of input voltage necessary to the output code by ILSB.
Linearity error
FFFH
Differential linear error
Actual conversion
characteristic
Actual conversion
characteristic
(N + 1)H
FFEH
Digital output
VFST
(Measurement
value)
VNT
004H
(Measurement
value)
003H
Digital output
{1 LSB (N − 1) + V OT}
FFDH
Ideal characteristic
NH
V(N+1)T
(N − 1)H
(Measurement
value)
Actual conversion
characteristic
Ideal characteristic
002H
VNT
(Measurement value)
(N − 2)H
001H
VOT
AVSS
Actual conversion
characteristic
(Measurement value)
Analog input
AVRH
AVSS
Analog input
VNT − {1 LSB’ × (N − 1) + VOT}
[LSB]
1 LSB’
V (N+1) T − VNT
Differential linear error in digital output N =
− 1 [LSB]
1 LSB’
VFST − VOT
1 LSB =
4094
N
: A/D converter digital output value
VOT : Voltage at which digital output changes from 000H to 001H.
VFST : Voltage at which digital output changes from FFEH to FFFH.
VNT : Voltage at which digital output changes from (N − 1)H to NH.
Linear error in digital output N =
84
AVRH
MB91470/480 Series
■ ORDERING INFORMATION
Part No.
Package
MB91F475PMC1-GE1
FPT-144P-M12
MB91F475BGL-GE1
BGA-144P-M06
MB91F478PMC1-GE1
FPT-144P-M12
MB91F478BGL-GE1
BGA-144P-M06
MB91F479PMC1-GE1
FPT-144P-M12
MB91F479BGL-GE1
BGA-144P-M06
MB91F487PMC-GE1
FPT-100P-M20
MB91482PMC-GE1
FPT-100P-M20
85
MB91470/480 Series
■ PACKAGE DIMENSIONS
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
26
100
1
C
0.08(.003)
(0.50(.020))
0.25(.010)
0.60±0.15
(.024±.006)
25
0.20±0.05
(.008±.002)
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
M
0.145±0.055
(.0057±.0022)
2005 FUJITSU LIMITED F100031S-c-2-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
86
MB91470/480 Series
144-pin plastic LQFP
Lead pitch
0.40 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP144-16×16-0.40
(FPT-144P-M12)
144-pin plastic LQFP
(FPT-144P-M12)
Note 1) * : These dimensions include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
+.016
*16.00 –0.10 .630 –.004 SQ
73
108
72
109
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8˚
37
144
LEAD No.
1
0.60±0.15
(.024±.006)
36
0.40(.016)
C
"A"
0.18±0.035
.007±.001
+0.05
0.07(.003)
M
2003 FUJITSU LIMITED F144024S-c-3-3
0.145 –0.03
.006
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
+.002
–.001
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
87
MB91470/480 Series
(Continued)
144-ball plastic PFBGA
Ball pitch
0.80 mm
Package width ×
package length
12.00 × 12.00 mm
Lead shape
Soldering ball
Sealing method
Plastic mold
Ball size
∅0.45 mm
Mounting height
1.45 mm Max.
Weight
0.32 g
(BGA-144P-M06)
144-ball plastic PFBGA
(BGA-144P-M06)
B
12.00±0.10(.472±.004)
0.20(.008) S B
0.80(.031)
REF
13
12
11
10
9
8
7
6
5
4
3
2
1
0.80(.031)
REF
A
12.00±0.10
(.472±.004)
(INDEX AREA)
0.20(.008) S A
1.25±0.20
0.35±0.10
(.014±.004)
(Stand off)
(.049±.008)
(Seated height)
N M L K J H G F E D C B A
INDEX
144-ø0.45±0.10
(144-ø.018±.004)
ø0.08(.003)
M
S A B
S
0.10(.004) S
C
2003 FUJITSU LIMITED B144006S-c-1-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
88
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB91470/480 Series
■ MAIN CHANGES IN THIS EDITION
Page
6
Section
■ PIN ASSIGNMENT
• LQFP-144 (MB91470 series)
12
■ PIN DESCRIPTIONS
14
25
27, 28
Changed the pin name as follows :
PE0/AN3-0 → PE0/AN3-0/AN3-0P
PE1/AN3-1 → PE1/AN3-1/AN3-0N
PE2/AN3-2 → PE2/AN3-2/AN3-1P
PE3/AN3-3 → PE3/AN3-3/AN3-1N
PE7/AN4-3 → PE7/AN4-3/AN4-1N
PE6/AN4-2 → PE6/AN4-2/AN4-1P
PE5/AN4-1 → PE5/AN4-1/AN4-0N
PE4/AN4-0 → PE4/AN4-0/AN4-0P
Added the following description in the Function of PPG8,
PPG9;
(MB91480 series only)
Added the following description in the Function of SCK4,
SIN4, SOT4, SCK5, SIN5, SOT5;
(MB91470 series only)
■ HANDLING DEVICES
Added the “• Notes upon power-on sequence”
■ BLOCK DIAGRAM
Changed in the figure
65
66
Change Results
■ ELECTRICAL CHARACTERISTICS
5. AC Characteristics
(1) Clock Timing
In the figure of “Conditions for measuring the clock timing
ratings”, deleted tCF, tCR and PWH, PWL and its range lines.
Changed as follows in the “Operation assurance range”
fCPS → fCP
but the upper limit of fCPT/fCPP is 40 MHz. → but the upper limit
of fCPT/fCPP is 40 MHz.
71
■ ELECTRICAL CHARACTERISTICS
5. AC Characteristics
(6) Multiplex Bus Access Read/Write
Operation
Changed in the figure as follows :
tCHAH → tCHAX
83
■ ELECTRICAL CHARACTERISTICS
6. Electrical Characteristics for the
A/D converter
Changed in the figure of “Total error”
85
■ ORDERING INFORMATION
Changed the part number
MB91F487PMC1-GE1 → MB91F487PMC-GE1
The vertical lines marked in the left side of the page show the changes.
89
MB91470/480 Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
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Edited
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