LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 LM111QML Voltage Comparator Check for Samples: LM111QML FEATURES DESCRIPTION • The LM111 is a voltage comparator that has input currents nearly a thousand times lower than devices such as the LM106 or LM710. It is also designed to operate over a wider range of supply voltages: from standard ±15V op amp supplies down to the single 5V supply used for IC logic. The output is compatible with RTL, DTL and TTL as well as MOS circuits. Further, it can drive lamps or relays, switching voltages up to 50V at currents as high as 50 mA. 1 2 • • • • • • • • Available with radiation ensured – High Dose Rate 50 krad(Si) – Low Dose and ELDRS Free 100 krad(Si) Operates from single 5V supply Input current: 200 nA max. over temperature Offset current: 20 nA max. over temperature Differential input voltage range: ±30V Power consumption: 135 mW at ±15V Power supply voltage, single 5V to ±15V Offset voltage null capability Strobe capability Both the inputs and the output of the LM111 can be isolated from system ground, and the output can drive loads referred to ground, the positive supply or the negative supply. Offset balancing and strobe capability are provided and outputs can be wire OR'ed. Although slower than the LM106 and LM710 (200 ns response time vs 40 ns) the device is also much less prone to spurious oscillations. The LM111 has the same pin configuration as the LM106 and LM710. Connection Diagrams TO-99 Package Note: Pin 4 connected to case Figure 1. Top View Package Number LMC0008C 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com CDIP Package CDIP Package Figure 2. Top View Package Number NAB008A Figure 3. Top View Package Number J0014A Figure 4. Top View Package Number NAC0010A, NAD0010A 2 N/C GND N/C V+ N/C 3 2 1 20 19 N/C 4 18 N/C IN+ 5 17 OUTPUT N/C 6 16 N/C IN- 7 15 BALANCE/ STROBE N/C 8 14 N/C 9 10 11 12 13 N/C V- N/C BALANCE N/C Figure 5. Top View Package Number NAJ0020A Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 Schematic Diagram Pin connections shown on schematic diagram are for LMC0008C package. Figure 6. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 3 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 Absolute Maximum Ratings www.ti.com (1) Positive Supply Voltage +30.0V Negative Supply Voltage -30.0V Total Supply Voltage 36V Output to Negative Supply Voltage 50V GND to Negative Supply Voltage 30V Differential Input Voltage ±30V Sink Current 50mA Input Voltage (2) Power Dissipation ±15V (3) 8 LD CDIP 400mW at 25°C 8 LD TO-99 330mW at 25°C 10 LD CLGA 330mW at 25°C 10 LD CLGA 330mW at 25°C 20 LD LCCC 500mW at 25°C Output Short Circuit Duration 10 seconds Maximum Strobe Current 10mA -55°C ≤ TA ≤ 125°C Operating Temperature Range Thermal Resistance θJA 8 LD CDIP (Still Air at 0.5W) 134°C/W 8 LD CDIP (500LF/Min Air flow at 0.5W) 76°C/W 8 LD TO-99 (Still Air at 0.5W) 162°C/W 8 LD TO-99 (500LF/Min Air flow at 0.5W) 92°C/W 10 LD CLGA (Still Air at 0.5W) 231°C/W 10 LD CLGA (500LF/Min Air flow at 0.5W) 153°C/W 10 LD CLGA (Still Air at 0.5W) 231°C/W 10 LD CLGA (500LF/Min Air flow at 0.5W) 153°C/W 14 LD CDIP(Still Air at 0.5W) 97°C/W 14 LD CDIP (500LF/Min Air flow at 0.5W) 65°C/W 20 LD LCCC (Still Air at 0.5W) 90°C/W 20 LD LCCC (500LF/Min Air flow at 0.5W) 65°C/W θJC (1) (2) (3) 4 8 LD CDIP 21°C/W 8 LD TO-99 50°C/W 10 LD CLGA 24°C/W 10 LD CLGA 24°C/W 14 LD CDIP 20°C/W 20 LD LCCC 21°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For specifications and test conditions, see the Electrical Characteristics tables. The specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. This rating applies for ±15V supplies. The positive input voltage limits is 30 V above the negative supply. The negative input voltage limits is equal to the negative supply voltage or 30V below the positive supply, whichever is less. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (continued) -65°C ≤ TA ≤ 150°C Storage Temperature Range Maximum Junction Temperature 175°C Lead Temperature (Soldering, 60 seconds) 300°C V+ = -5V Voltage at Strobe Pin Package Weight (Typical) 8 LD TO-99 965mg 8 LD CDIP 1100mg 10 LD CLGA 250mg 10 LD CLGA 225mg 14 LD CDIP TBD 20 LD LCCC ESD Rating (4) TBD (4) 300V Human body model, 1.5 kΩ in series with 100 pF. Recommended Operating Conditions Supply Voltage VCC = ±15VDC -55°C ≤ TA ≤ 125°C Operating Temperature Range Quality Conformance Inspection Table 1. Mil-Std-883, Method 5005 - Group A Subgroup Description Temperature (°C) 1 Static tests at +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 5 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com LM111/883 Electrical Characteristics DC Parameters (1) The following conditions apply, unless otherwise specified. V56 = 0, RS = 0 Ω, VCC = ±15V, VCM = 0, VO = 1.4V WRT −VCC The pin assignments are based on the 8 pin package configuration. (2) Symbol Parameter Conditions IIO Input Offset Current VCM = 13.5V, RS = 50KΩ VCM = 13.5V, V85 = V86 = 0V, RS = 50KΩ Notes (2) VCM = -14.5V, RS= 50KΩ VCM = -14.5V, V85 = V86 = 0V, RS= 50KΩ (2) RS = 50KΩ V85 = V86 = 0V, RS = 50KΩ IIB Input Bias Current (2) Max -10 10 nA 1 -20 20 nA 2, 3 -30 30 nA 1 -10 10 nA 1 -20 20 nA 2, 3 -30 30 nA 1 -10 10 nA 1 -20 20 nA 2, 3 -30 30 nA 1 100 nA 1 150 nA 2, 3 100 nA 1 150 nA 2, 3 100 nA 1 150 nA 2, 3 VCM = 13.5V, RS = 50KΩ VCM = -14.5V, RS = 50KΩ RS = 50KΩ IOL Output Leakage Current IGL Ground Leakage Current VSat Saturation Voltage Subgroups Min Unit VCC = ± 18V, I5 + I6 = 5mA, VO = 35V WRT -VCC (2) 10 nA 1 (2) 500 nA 2, 3 VCC = ± 18V, I5 + I6 = 5mA, VO = 50V WRT -VCC (2) 25 nA 1 (2) 500 nA 2 VI = -5mV, I7 = 50mA (2) 1.5 V 1, 2, 3 VI = -6mV, I7 = 8mA (2) 0.4 V 1, 2, 3 1, 2 -ICC Negative Supply Current 5.0 mA 15 mA 3 +ICC Positive Supply Current 6.0 mA 1, 2 IL1 Input Leakage Current IL2 Input Leakage Current VOSt 15 mA 3 VCC = ± 18V, V28 = 1V, V38 = 30V, I5 + I6 = 5mA VO = 50V WRT -VCC (2) 10 nA 1 (2) 30 nA 2 VCC = ± 18V, V38 = 1V, V28 = 30V, I5 + I6 = 5mA VO = 50V WRT -VCC (2) 10 nA 1 (2) 30 nA 2 14 V 1 14 V 1 Collector Output Voltage (Strobe) ISt = 3mA (1) (2) 6 Calculated parameter. Pin names based on an 8 pin package configuration. When using higher pin count packages then: Pin 2 & 3 are Inputs, Pin 5 is Balance, Pin 6 is Balance /Strobe, Pin 7 is Output, and Pin 8 is V+. For example: V56 is the Voltage between the Balance and Balance / Strobe pins. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 LM111/883 Electrical Characteristics DC Parameters(1) (continued) The following conditions apply, unless otherwise specified. V56 = 0, RS = 0 Ω, VCC = ±15V, VCM = 0, VO = 1.4V WRT −VCC The pin assignments are based on the 8 pin package configuration. (2) Symbol Parameter Conditions Notes VIO Input Offset Voltage VCM = 13.5V Subgroups 3.0 mV 1 4.0 mV 2, 3 -3.0 3.0 mV 1 -3.0 3.0 mV 1 -4.0 4.0 mV 2, 3 -3.0 3.0 mV 1 -3.0 3.0 mV 1 -4.0 4.0 mV 2, 3 -3.0 3.0 mV 1 VO = 0.4V, +VCC = 4.5V, -VCC = 0V, VCM = 3V -5.0 5.0 mV 1 -6.0 6.0 mV 2, 3 VO = 4.5V, +VCC = 4.5V, -VCC = 0V, VCM = 3V -3.0 3.0 mV 1 -4.0 4.0 mV 2, 3 VO = 0.4V, +VCC = 4.5V, -VCC = 0V, VCM = 0.5V -5.0 5.0 mV 1 -6.0 6.0 mV 2, 3 VO = 4.5V, +VCC = 4.5V, -VCC = 0V, VCM = 0.5V -3.0 3.0 mV 1 -4.0 4.0 mV 2, 3 (2) (2) VCM = -14.5V, V85 = V86 = 0V (2) V85 = V86 = 0V (3) Unit -4.0 VCM = -14.5V Large Signal Gain Max -3.0 VCM = 13.5V, V85 = V86= 0V AVS Min -12V ≤ VO ≤ 35V, RL = 1KΩ (3) 40 V/mV 4 (3) 30 V/mV 5, 6 Datalog reading in K=V/mV. LM111/883 Electrical Characteristics AC Parameters (1) The following conditions apply, unless otherwise specified. V56 = 0, RS = 0 Ω, VCC = ±15V, VCM = 0, VO = 1.4V WRT −VCC The pin assignments are based on the 8 pin package configuration. (2) Symbol tR Parameter Conditions Notes Min Response Time (1) (2) Max Unit Subgroups 400 nS 7 Calculated parameter. Pin names based on an 8 pin package configuration. When using higher pin count packages then: Pin 2 & 3 are Inputs, Pin 5 is Balance, Pin 6 is Balance /Strobe, Pin 7 is Output, and Pin 8 is V+. For example: V56 is the Voltage between the Balance and Balance / Strobe pins. LM111-SMD Electrical Characteristics SMD 5962-8687701 DC Parameters (1) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Symbol VIO (1) Parameter Input Offset Voltage Conditions VI = 0V, RS = 50Ω Notes Min Max Unit Subgroups -3.0 +3.0 mV 1 -4.0 +4.0 mV 2, 3 +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50Ω -3.0 +3.0 mV 1 -4.0 +4.0 mV 2, 3 +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50Ω -3.0 +3.0 mV 1 -4.0 +4.0 mV 2, 3 +VCC = +2.5V, -VCC = -2.5V, VI = 0V, RS = 50Ω -3.0 +3.0 mV 1 -4.0 +4.0 mV 2, 3 Calculated parameter. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 7 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com LM111-SMD Electrical Characteristics SMD 5962-8687701 DC Parameters(1) (continued) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Symbol VIO R Parameter Raised Input Offset Voltage Min Max Unit Subgroups -3.0 +3.0 mV 1 -4.5 +4.5 mV 2, 3 -3 +3 mV 1 -4.5 +4.5 mV 2, 3 -3.0 +3.0 mV 1 -4.5 +4.5 mV 2, 3 -10 +10 nA 1, 2 -20 +20 nA 3 +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50KΩ -10 +10 nA 1, 2 -20 +20 nA 3 +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50KΩ -10 +10 nA 1, 2 -20 +20 nA 3 -25 +25 nA 1, 2 -50 +50 nA 3 -100 0.1 nA 1, 2 -150 0.1 nA 3 +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50KΩ -150 0.1 nA 1, 2 -200 0.1 nA 3 +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50KΩ -150 0.1 nA 1, 2 -200 0.1 nA 3 +VI = Gnd, -VI = 15V, ISt = -3mA, RS = 50Ω (3) (4) 14 V 1, 2, 3 -28V ≤ -VCC ≤ -0.5V, RS = 50Ω, 2V ≤ +VCC ≤ 29.5V, RS = 50Ω, -14.5V ≤ VCM ≤ 13V, RS = 50Ω 80 dB 1, 2, 3 Conditions VI = 0V, RS = 50Ω +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50Ω +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50Ω IIO Input Offset Current IIOR Raised Input Offset Current ±IIB Input Bias Current VOSt CMRR VOL Output Leakage Current IL Input Leakage Current +ICC 8 Common Mode Rejection Ratio Low Level Output Voltage ICEX (2) (3) (4) (5) Collector Output Voltage (Strobe) Notes (2) (2) (2) VI = 0V, RS = 50KΩ VI = 0V, RS = 50KΩ (2) VI = 0V, RS = 50KΩ +VCC = 4.5V, -VCC = Gnd, IO = 8mA, ±VI = 0.71V, VID = -6mV 0.4 V 1, 2, 3 +VCC = 4.5V, -VCC = Gnd, IO = 8mA, ±VI = −1.75V, VID = -6mV 0.4 V 1, 2, 3 IO = 50mA, ±VI = 13V, VID = -5mV 1.5 V 1, 2, 3 IO = 50mA, ±Vl= -14V, VID = -5mV 1.5 V 1, 2, 3 -1.0 10 nA 1 -1.0 500 nA 2 +VCC = 18V, -VCC = -18V, VO = 32V +VCC = 18V, -VCC = -18V, +VI = +12V, -VI = -17V (5) -5.0 500 nA 1, 2, 3 +VCC = 18V, -VCC = -18V, +VI = -17V, -VI = +12V (5) -5.0 500 nA 1, 2, 3 6.0 mA 1, 2 7.0 mA 3 Power Supply Current Subscript (R) indicates tests which are performed with input stage current raised by connecting BAL and BAL/STB terminals to +VCC. IST = −2mA at −55°C Group A sample ONLY VID is voltage difference between inputs. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 LM111-SMD Electrical Characteristics SMD 5962-8687701 DC Parameters(1) (continued) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Symbol -ICC Parameter Conditions Power Supply Current Δ VIO / ΔT Δ IIO / ΔT IOS Unit Subgroups -5.0 mA 1, 2 -6.0 mA 3 Min Max Temperature Coefficient Input Offset Voltage 25°C ≤ T ≤ 125°C (5) (4) -25 25 µV/°C 2 -55°C ≤ T ≤ 25°C (5) (4) -25 25 µV/°C 3 Temperature Coefficient Input Offset Current 25°C ≤ T ≤ 125°C (5) (4) -100 100 pA/°C 2 -55°C ≤ T ≤ 25°C (5) (4) -200 200 pA/°C 3 (6) 200 mA 1 (6) 150 mA 2 (6) 250 mA 3 mV 1 Short Circuit Current VO = 5V, t ≤ 10mS, -VI = 0.1V, +VI = 0V +VIO adj. Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω -VIO adj. Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω ±AVE Voltage Gain (Emitter) RL = 600Ω (6) (7) Notes 5.0 mV 1 (7) 10 -5.0 V/mV 4 (7) 8.0 V/mV 5, 6 Actual min. limit used is 5mA due to test setup. Datalog reading in K=V/mV. LM111-SMD Electrical Characteristics SMD 5962-8687701 AC Parameters (1) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Symbol tRLHC tRHLC (1) (2) Parameter Conditions Notes Min Max Unit Subgroups Response Time (Collector Output) VOD(Overdrive) = -5mV, CL = 50pF, VI = -100mV (2) 300 nS 7, 8B (2) 640 nS 8A Response Time (Collector Output) VOD(Overdrive) = 5mV, CL = 50pF, VI = 100mV (2) 300 nS 7, 8B (2) 500 nS 8A Calculated parameter. Group A sample ONLY LM111 RADIATION Electrical Characteristics SMD 5962L0052401 DC Parameters (1) (2) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Symbol VIO (1) (2) Parameter Input Offset Voltage Min Max Unit Subgroups -3.0 +3.0 mV 1 -4.0 +4.0 mV 2, 3 +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50Ω -3.0 +3.0 mV 1 -4.0 +4.0 mV 2, 3 +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50Ω -3.0 +3.0 mV 1 -4.0 +4.0 mV 2, 3 +VCC = +2.5V, -VCC = -2.5V, VI = 0V, RS = 50Ω -3.0 +3.0 mV 1 -4.0 +4.0 mV 2, 3 Conditions VI = 0V, RS = 50Ω Notes Calculated parameter. Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are ensured only for the conditions as specified in Mil-Std-883, Method 1019, Condition A. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 9 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com LM111 RADIATION Electrical Characteristics SMD 5962L0052401 DC Parameters(1)(2) (continued) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Symbol VIO R Parameter Raised Input Offset Voltage Min Max Unit Subgroups -3.0 +3.0 mV 1 -4.5 +4.5 mV 2, 3 -3.0 +3.0 mV 1 -4.5 +4.5 mV 2, 3 -3.0 +3.0 mV 1 -4.5 +4.5 mV 2, 3 -10 +10 nA 1, 2 -20 +20 nA 3 +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50KΩ -10 +10 nA 1, 2 -20 +20 nA 3 +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50KΩ -10 +10 nA 1, 2 -20 +20 nA 3 -25 +25 nA 1, 2 -50 +50 nA 3 -100 0.1 nA 1, 2 -150 0.1 nA 3 +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50KΩ -150 0.1 nA 1, 2 -200 0.1 nA 3 +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50KΩ -150 0.1 nA 1, 2 -200 0.1 nA 3 +VI = Gnd, -VI = 15V, ISt = -3mA, RS = 50Ω (4) (5) 14 V 1, 2, 3 -28V ≤ -VCC ≤ -0.5V, RS = 50Ω, 2V ≤ +VCC ≤ 29.5V, RS = 50Ω, -14.5V ≤ VCM ≤ 13V, RS = 50Ω 80 dB 1, 2, 3 Conditions VI = 0V, RS = 50Ω +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50Ω +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50Ω IIO Input Offset Current IIOR Raised Input Offset Current ±IIB Input Bias Current VOSt CMRR VOL Output Leakage Current IL Input Leakage Current +ICC 10 Common Mode Rejection Ratio Low Level Output Voltage ICEX (3) (4) (5) (6) Collector Output Voltage (Strobe) Notes (3) (3) (3) VI = 0V, RS = 50KΩ VI = 0V, RS = 50KΩ (3) VI = 0V, RS = 50KΩ +VCC = 4.5V, -VCC = Gnd, IO = 8mA, ±VI = 0.5V, VID = -6mV 0.4 V 1, 2, 3 +VCC = 4.5V, -VCC = Gnd, IO = 8mA, ±VI = 3V, VID = -6mV 0.4 V 1, 2, 3 IO = 50mA, ±VI = 13V, VID = -5mV 1.5 V 1, 2, 3 IO = 50mA, ±VI = -14V, VID = -5mV 1.5 V 1, 2, 3 -1.0 10 nA 1 -1.0 500 nA 2 +VCC = 18V, -VCC = -18V, VO = 32V +VCC = 18V, -VCC = -18V, +VI = +12V, -VI = -17V (6) -5.0 500 nA 1, 2, 3 +VCC = 18V, -VCC = -18V, +VI = -17V, -VI = +12V (6) -5.0 500 nA 1, 2, 3 6.0 mA 1, 2 7.0 mA 3 Power Supply Current Subscript (R) indicates tests which are performed with input stage current raised by connecting BAL and BAL/STB terminals to +VCC. IST = −2mA at −55°C Group A sample ONLY VID is voltage difference between inputs. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 LM111 RADIATION Electrical Characteristics SMD 5962L0052401 DC Parameters(1)(2) (continued) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Symbol -ICC Parameter Conditions Notes Power Supply Current Unit Subgroups -5.0 mA 1, 2 -6.0 mA 3 Min Max ΔVIO / ΔT Temperature Coefficient Input Offset Voltage 25°C ≤ T ≤ 125°C -25 25 µV/°C 2 -55°C ≤ T ≤ 25°C -25 25 µV/°C 3 Δ IIO / ΔT Temperature Coefficient Input Offset Current 25°C ≤ T ≤ 125°C -100 100 pA/°C 2 -55°C ≤ T ≤ 25°C -200 200 pA/°C 3 (7) 200 mA 1 (7) 150 mA 2 (7) 250 mA 3 mV 1 IOS Short Circuit Current VO = 5V, t ≤ 10mS, -VI = 0.1V, +VI = 0V +VIO adj. Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω -VIO adj. Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω ±AVE Voltage Gain (Emitter) RL = 600Ω (7) (8) 5.0 mV 1 (8) 10 -5.0 V/mV 4 (8) 8.0 V/mV 5, 6 Actual min. limit used is 5mA due to test setup. Datalog reading in K=V/mV. LM111 RADIATION Electrical Characteristics SMD 5962L0052401 AC Parameters (1) (2) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Symbol tRLHC tRHLC (1) (2) Parameter Conditions Notes Response Time (Collector Output) VOD(Overdrive) = -5mV, CL = 50pF, VI = -100mV (3) Response Time (Collector Output) VOD(Overdrive) = 5mV, CL = 50pF, VI = 100mV (3) Min Max Unit Subgroups 300 nS 7, 8B 640 nS 8A 300 nS 7, 8B 500 nS 8A Calculated parameter. Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are ensured only for the conditions as specified in Mil-Std-883, Method 1019, Condition A. Group A sample ONLY (3) LM111 RADIATION Electrical Characteristics SMD 5962L0052401 DC DELTA Parameters (1) (2) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Delta calculations performed on QMLV devices at group B , subgroup 5. Symbol VIO (1) (2) Parameter Input Offset Voltage Min Max Unit Subgroups VI = 0V, RS = 50Ω -0.5 0.5 mV 1 +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50Ω -0.5 0.5 mV 1 +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50Ω -0.5 0.5 mV 1 Conditions Notes Calculated parameter. Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are ensured only for the conditions as specified in Mil-Std-883, Method 1019, Condition A. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 11 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com LM111 RADIATION Electrical Characteristics SMD 5962L0052401 DC DELTA Parameters(1)(2) (continued) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Delta calculations performed on QMLV devices at group B , subgroup 5. Symbol ±IIB Parameter Input Bias Current ICEX Output Leakage Current Min Max Unit Subgroups VI = 0V, RS = 50KΩ -12.5 12.5 nA 1 +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50KΩ -12.5 12.5 nA 1 +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50KΩ -12.5 12.5 nA 1 +VCC = 18V, -VCC = -18V, VO = 32V -5.0 5.0 nA 1 Conditions Notes LM111 RADIATION Electrical Characteristics SMD 5962L0052401 Post Radiation Parameters (1) (2) The following conditions apply, unless otherwise specified Symbol IIO Input Offset Current ±IIB Input Bias Current ICEX (1) (2) Parameter Output Leakage Current Min Max Unit Subgroups +VCC = 29.5V, −VCC = −0.5V, VI = 0V, VCM = −14.5V, RS = 50KΩ −50 +50 nA 1 +VCC = 2V, −VCC = −28V, VI = 0V, VCM = +13V, RS = 50KΩ −50 +50 nA 1 VI = 0V, RS = 50KΩ −150 0.1 nA 1 +VCC = 29.5V, −VCC = −0.5V, VI = 0V, VCM = −14.5V, RS = 50KΩ −175 0.1 nA 1 +VCC = 18V, −VCC = −18V, VO = 32V −25 +25 nA 1 Conditions Notes Calculated parameter. Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are ensured only for the conditions as specified in Mil-Std-883, Method 1019, Condition A. LM111 RADIATION Electrical Characteristics SMD 5962R0052402 DC Parameters (1) (2) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Symbol VIO (1) (2) 12 Parameter Input Offset Voltage Min Max Unit Subgroups -3.0 +3.0 mV 1 -4.0 +4.0 mV 2, 3 +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50Ω -3.0 +3.0 mV 1 -4.0 +4.0 mV 2, 3 +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50Ω -3.0 +3.0 mV 1 -4.0 +4.0 mV 2, 3 +VCC = +2.5V, -VCC = -2.5V, VI = 0V, RS = 50Ω -3.0 +3.0 mV 1 -4.0 +4.0 mV 2, 3 Conditions VI = 0V, RS = 50Ω Notes Calculated parameter. Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table. These parts may be sensitive in a high dose environment. Low dose rate testing has been performed on a wafer-by-wafer basis, per test method 1019 condition D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS) effect. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 LM111 RADIATION Electrical Characteristics SMD 5962R0052402 DC Parameters(1)(2) (continued) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Symbol VIO R Parameter Raised Input Offset Voltage Min Max Unit Subgroups -3.0 +3.0 mV 1 -4.5 +4.5 mV 2, 3 -3.0 +3.0 mV 1 -4.5 +4.5 mV 2, 3 -3.0 +3.0 mV 1 -4.5 +4.5 mV 2, 3 -10 +10 nA 1, 2 -20 +20 nA 3 +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50KΩ -10 +10 nA 1, 2 -20 +20 nA 3 +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50KΩ -10 +10 nA 1, 2 -20 +20 nA 3 -25 +25 nA 1, 2 -50 +50 nA 3 -100 0.1 nA 1, 2 -150 0.1 nA 3 +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50KΩ -150 0.1 nA 1, 2 -200 0.1 nA 3 +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50KΩ -150 0.1 nA 1, 2 -200 0.1 nA 3 +VI = Gnd, -VI = 15V, ISt = -3mA, RS = 50Ω (3) (4) 14 V 1, 2, 3 -28V ≤ -VCC ≤ -0.5V, RS = 50Ω, 2V ≤ +VCC ≤ 29.5V, RS = 50Ω, -14.5V ≤ VCM ≤ 13V, RS = 50Ω 80 dB 1, 2, 3 Conditions VI = 0V, RS = 50Ω +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50Ω +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50Ω IIO Input Offset Current IIOR Raised Input Offset Current ±IIB Input Bias Current VOSt CMRR VOL Output Leakage Current IL Input Leakage Current +ICC (3) (4) (5) Common Mode Rejection Ratio Low Level Output Voltage ICEX -ICC Collector Output Voltage (Strobe) Notes (2) (2) (2) VI = 0V, RS = 50KΩ VI = 0V, RS = 50KΩ (2) VI = 0V, RS = 50KΩ +VCC = 4.5V, -VCC = Gnd, IO = 8mA, ±VI = 0.5V, VID = -6mV 0.4 V 1, 2, 3 +VCC = 4.5V, -VCC = Gnd, IO = 8mA, ±VI = 3V, VID = -6mV 0.4 V 1, 2, 3 IO = 50mA, ±VI = 13V, VID = -5mV 1.5 V 1, 2, 3 IO = 50mA, ±VI = -14V, VID = -5mV 1.5 V 1, 2, 3 -1.0 10 nA 1 -1.0 500 nA 2 +VCC = 18V, -VCC = -18V, VO = 32V +VCC = 18V, -VCC = -18V, +VI = +12V, -VI = -17V (5) -5.0 500 nA 1, 2, 3 +VCC = 18V, -VCC = -18V, +VI = -17V, -VI = +12V (5) -5.0 500 nA 1, 2, 3 6.0 mA 1, 2 7.0 mA 3 -5.0 mA 1, 2 -6.0 mA 3 Power Supply Current Power Supply Current IST = −2mA at −55°C Group A sample ONLY VID is voltage difference between inputs. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 13 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com LM111 RADIATION Electrical Characteristics SMD 5962R0052402 DC Parameters(1)(2) (continued) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Symbol ΔVIO / ΔT Parameter Conditions Notes Min Max Unit Subgroups Temperature Coefficient Input Offset Voltage 25°C ≤ T ≤ 125°C -25 25 µV/°C 2 -55°C ≤ T ≤ 25°C -25 25 µV/°C 3 Δ IIO / ΔT Temperature Coefficient Input Offset Current 25°C ≤ T ≤ 125°C -100 100 pA/°C 2 -200 IOS Short Circuit Current VO = 5V, t ≤ 10mS, -VI = 0.1V, +VI = 0V -55°C ≤ T ≤ 25°C 200 pA/°C 3 (6) 200 mA 1 (5) 150 mA 2 250 mA 3 mV 1 mV 1 (5) +VIO adj. Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω -VIO adj. Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω ±AVE Voltage Gain (Emitter) RL = 600Ω (6) (7) 5.0 -5.0 (7) 10 V/mV 4 (7) 8.0 V/mV 5, 6 Actual min. limit used is 5mA due to test setup. Pin names based on an 8 pin package configuration. When using higher pin count packages then: Pin 2 & 3 are Inputs, Pin 5 is Balance, Pin 6 is Balance /Strobe, Pin 7 is Output, and Pin 8 is V+. For example: V56 is the Voltage between the Balance and Balance / Strobe pins. LM111 RADIATION Electrical Characteristics SMD 5962R0052402 AC Parameters (1) (2) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Symbol tRLHC tRHLC (1) (2) Parameter Conditions Notes Response Time (Collector Output) VOD(Overdrive) = -5mV, CL = 50pF, VI = -100mV (3) Response Time (Collector Output) VOD(Overdrive) = 5mV, CL = 50pF, VI = 100mV (3) Min Max Unit Subgroups 300 nS 7, 8B 640 nS 8A 300 nS 7, 8B 500 nS 8A Calculated parameter. Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table. These parts may be sensitive in a high dose environment. Low dose rate testing has been performed on a wafer-by-wafer basis, per test method 1019 condition D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS) effect. Group A sample ONLY (3) LM111 RADIATION Electrical Characteristics SMD 5962R0052402 DC DELTA Parameters (1) (2) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Delta calculations performed on QMLV devices at group B , subgroup 5. Symbol VIO (1) (2) 14 Parameter Input Offset Voltage Min Max Unit Subgroups VI = 0V, RS = 50Ω -0.5 0.5 mV 1 +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50Ω -0.5 0.5 mV 1 +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50Ω -0.5 0.5 mV 1 Conditions Notes Calculated parameter. Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table. These parts may be sensitive in a high dose environment. Low dose rate testing has been performed on a wafer-by-wafer basis, per test method 1019 condition D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS) effect. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 LM111 RADIATION Electrical Characteristics SMD 5962R0052402 DC DELTA Parameters(1)(2) (continued) The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0 Delta calculations performed on QMLV devices at group B , subgroup 5. Symbol ±IIB Parameter Input Bias Current ICEX Output Leakage Current Min Max Unit Subgroups VI = 0V, RS = 50KΩ -12.5 12.5 nA 1 +VCC = 29.5V, -VCC = -0.5V, VI = 0V, VCM = -14.5V, RS = 50KΩ -12.5 12.5 nA 1 +VCC = 2V, -VCC = -28V, VI = 0V, VCM = +13V, RS = 50KΩ -12.5 12.5 nA 1 +VCC = 18V, -VCC = -18V, VO = 32V -5.0 5.0 nA 1 Conditions Notes LM111 RADIATION Electrical Characteristics SMD 5962R0052402 Post Radiation Parameters (1) (2) The following conditions apply, unless otherwise specified Symbol Parameter Conditions Notes (3) Min Max Unit Subgroups IIOR Raised Input Offset Current VI = 0V, RS = 50KΩ −100 +100 nA 1 ±IIB Input Bias Current VI = 0V, RS = 50KΩ −180 0.1 nA 1 +VCC = 29.5V, −VCC = −0.5V, VI = 0V, VCM = −14.5V, RS = 50KΩ −225 0.1 nA 1 +VCC = 18V, −VCC = −18V, VO = 32V −1.0 +25 nA 1 ICEX (1) (2) (3) Output Leakage Current Calculated parameter. Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table. These parts may be sensitive in a high dose environment. Low dose rate testing has been performed on a wafer-by-wafer basis, per test method 1019 condition D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS) effect. Subscript (R) indicates tests which are performed with input stage current raised by connecting BAL and BAL/STB terminals to +VCC. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 15 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com LM111 Typical Performance Characteristics 16 Input Bias Current Input Bias Current Figure 7. Figure 8. Input Bias Current Input Bias Current Figure 9. Figure 10. Input Bias Current Input Bias Current Figure 11. Figure 12. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 LM111 Typical Performance Characteristics (continued) Input Bias Current Input Overdrives Input Bias Current Input Overdrives Figure 13. Figure 14. Input Bias Current Response Time for Various Input Overdrives Figure 15. Figure 16. Response Time for Various Input Overdrives Output Limiting Characteristics Figure 17. Figure 18. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 17 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com LM111 Typical Performance Characteristics (continued) Supply Current Supply Current Figure 19. Figure 20. Leakage Currents Figure 21. 18 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 APPLICATION HINTS CIRCUIT TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR APPLICATIONS When a high-speed comparator such as the LM111 is used with fast input signals and low source impedances, the output response will normally be fast and stable, assuming that the power supplies have been bypassed (with 0.1 μF disc capacitors), and that the output signal is routed well away from the inputs (pins 2 and 3) and also away from pins 5 and 6. However, when the input signal is a voltage ramp or a slow sine wave, or if the signal source impedance is high (1 kΩ to 100 kΩ), the comparator may burst into oscillation near the crossing-point. This is due to the high gain and wide bandwidth of comparators like the LM111. To avoid oscillation or instability in such a usage, several precautions are recommended, as shown in Figure 22 below. 1. The trim pins (pins 5 and 6) act as unwanted auxiliary inputs. If these pins are not connected to a trim-pot, they should be shorted together. If they are connected to a trim-pot, a 0.01 μF capacitor C1 between pins 5 and 6 will minimize the susceptibility to AC coupling. A smaller capacitor is used if pin 5 is used for positive feedback as in Figure 22. 2. Certain sources will produce a cleaner comparator output waveform if a 100 pF to 1000 pF capacitor C2 is connected directly across the input pins. 3. When the signal source is applied through a resistive network, RS, it is usually advantageous to choose an RS′ of substantially the same value, both for DC and for dynamic (AC) considerations. Carbon, tin-oxide, and metal-film resistors have all been used successfully in comparator input circuitry. Inductive wire wound resistors are not suitable. 4. When comparator circuits use input resistors (e.g. summing resistors), their value and placement are particularly important. In all cases the body of the resistor should be close to the device or socket. In other words there should be very little lead length or printed-circuit foil run between comparator and resistor to radiate or pick up signals. The same applies to capacitors, pots, etc. For example, if RS=10 kΩ, as little as 5 inches of lead between the resistors and the input pins can result in oscillations that are very hard to damp. Twisting these input leads tightly is the only (second best) alternative to placing resistors close to the comparator. 5. Since feedback to almost any pin of a comparator can result in oscillation, the printed-circuit layout should be engineered thoughtfully. Preferably there should be a ground plane under the LM111 circuitry, for example, one side of a double-layer circuit card. Ground foil (or, positive supply or negative supply foil) should extend between the output and the inputs, to act as a guard. The foil connections for the inputs should be as small and compact as possible, and should be essentially surrounded by ground foil on all sides, to guard against capacitive coupling from any high-level signals (such as the output). If pins 5 and 6 are not used, they should be shorted together. If they are connected to a trim-pot, the trim-pot should be located, at most, a few inches away from the LM111, and the 0.01 μF capacitor should be installed. If this capacitor cannot be used, a shielding printed-circuit foil may be advisable between pins 6 and 7. The power supply bypass capacitors should be located within a couple inches of the LM111. (Some other comparators require the power-supply bypass to be located immediately adjacent to the comparator.) 6. It is a standard procedure to use hysteresis (positive feedback) around a comparator, to prevent oscillation, and to avoid excessive noise on the output because the comparator is a good amplifier for its own noise. In the circuit of Figure 23, the feedback from the output to the positive input will cause about 3 mV of hysteresis. However, if RS is larger than 100Ω, such as 50 kΩ, it would not be reasonable to simply increase the value of the positive feedback resistor above 510 kΩ. The circuit of Figure 24 could be used, but it is rather awkward. See the notes in paragraph 7 below. 7. When both inputs of the LM111 are connected to active signals, or if a high-impedance signal is driving the positive input of the LM111 so that positive feedback would be disruptive, the circuit of Figure 22 is ideal. The positive feedback is to pin 5 (one of the offset adjustment pins). It is sufficient to cause 1 to 2 mV hysteresis and sharp transitions with input triangle waves from a few Hz to hundreds of kHz. The positivefeedback signal across the 82Ω resistor swings 240 mV below the positive supply. This signal is centered around the nominal voltage at pin 5, so this feedback does not add to the VOS of the comparator. As much as 8 mV of VOS can be trimmed out, using the 5 kΩ pot and 3 kΩ resistor as shown. 8. These application notes apply specifically to the LM111 and are applicable to all high-speed comparators in general, (with the exception that not all comparators have trim pins). Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 19 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com Pin connections shown are for LM111H in the LMC0008C package Figure 22. Improved Positive Feedback Pin connections shown are for LM111H in the LMC0008C package Figure 23. Conventional Positive Feedback Figure 24. Positive Feedback with High Source Resistance 20 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 TYPICAL APPLICATIONS Figure 25. Offset Balancing Note: Do Not Ground Strobe Pin. Output is turned off when current is pulled from Strobe Pin. Figure 26. Strobing Increases typical common mode slew from 7.0V/μs to 18V/μs. Figure 27. Increasing Input Stage Current Figure 28. Detector for Magnetic Transducer Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 21 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com Figure 29. Digital Transmission Isolator *Absorbs inductive kickback of relay and protects IC from severe voltage transients on V++ line. Note: Do Not Ground Strobe Pin. Figure 30. Relay Driver with Strobe Note: Do Not Ground Strobe Pin. (1) Typical input current is 50 pA with inputs strobed off. (2) Pin connections shown on schematic diagram and typical applications are for LMC0008C package. Figure 31. Strobing off Both Input and Output Stages 22 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 *Solid tantalum Figure 32. Positive Peak Detector Figure 33. Zero Crossing Detector Driving MOS Logic Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 23 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com TYPICAL APPLICATIONS FOR METAL CYLINDER PACKAGE (Pin numbers refer to LMC0008C package) Figure 34. Zero Crossing Detector Driving MOS Switch *TTL or DTL fanout of two Figure 35. 100 kHz Free Running Multivibrator 24 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 *Adjust for symmetrical square wave time when VIN = 5 mV †Minimum capacitance 20 pF Maximum frequency 50 kH Figure 36. 10 Hz to 10 kHz Voltage Controlled Oscillator *Input polarity is reversed when using pin 1 as output. Figure 37. Driving Ground-Referred Load Figure 38. Using Clamp Diodes to Improve Response Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 25 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com *Values shown are for a 0 to 30V logic swing and a 15V threshold. †May be added to control speed and reduce susceptibility to noise spikes. Figure 39. TTL Interface with High Level Logic Figure 40. Crystal Oscillator Figure 41. Comparator and Solenoid Driver 26 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 *Solid tantalum †Adjust to set clamp level Figure 42. Precision Squarer *Solid tantalum Figure 43. Low Voltage Adjustable Reference Supply Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 27 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com *Solid tantalum Figure 44. Positive Peak Detector Figure 45. Zero Crossing Detector Driving MOS Logic *Solid tantalum Figure 46. Negative Peak Detector 28 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 *R2 sets the comparison level. At comparison, the photodiode has less than 5 mV across it, decreasing leakages by an order of magnitude. Figure 47. Precision Photodiode Comparator Figure 48. Switching Power Amplifier Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 29 LM111QML SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 www.ti.com Figure 49. Switching Power Amplifier 30 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML LM111QML www.ti.com SNOSAJ4C – OCTOBER 2005 – REVISED MARCH 2013 Table 2. Revision History Released Revision Section Originator Changes 10/11/05 A New Release, Corporate format L. Lytle 3 MDS data sheets converted into one Corp. data sheet format. MNLM111-X Rev 0A0, MDLM111-X Rev. 0B0, and MRLM111-X-RH Rev 0E1. The drift table was eliminated from the 883 section since it did not apply; Note #3 was removed from RH & QML datasheets with SG verification that it no longer applied. Added NSID's for 50k Rad and Post Radiation Table. MDS data sheets will be archived. 12/14/05 B Ordering Information Table R. Malone Removed NSID reference LM111J-8PQMLV, 5962P0052401VPA 30k rd(Si). Reason: NSID on LTB, Inventory exhausted. Added following NSID's: LM111HPQMLV, LM111WPQMLV and LM111WGPQMLV. Reason: Still have Inventory. LM111QML, Revision A will be archived. 06/26/08 C Features, Ordering Information Table, Electrical section Notes. Larry McGee Added Radiation reference, ELDRS NSID's and Note 14 and 15, Low Dose Electrical Table. Deleted 30k rd(Si) NSID's: LM111HPQMLV, LM111WPQMLV and LM111WGPQMLV. Reason: EOL 9/06/05. Revision B will be archived. 03/26/2013 C All Sections Changed layout of National Data Sheet to TI format Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM111QML 31 PACKAGE OPTION ADDENDUM www.ti.com 19-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962L0052401VGA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LM111HLQMLV 5962L0052401VGA Q ACO 5962L0052401VGA Q >T 5962L0052401VHA ACTIVE CFP NAD 10 19 TBD Call TI Call TI -55 to 125 LM111W LQMLV Q 5962L00524 01VHA ACO 01VHA >T 5962L0052401VPA ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 LM111J-8LQV 5962L00524 01VPA Q ACO 01VPA Q >T 5962L0052401VZA ACTIVE CFP NAC 10 54 TBD Call TI Call TI -55 to 125 LM111W GLQMLV Q 5962L00524 01VZA ACO 01VZA >T 5962R0052402VGA ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LM111HRLQV 5962R0052402VGA Q ACO 5962R0052402VGA Q >T 5962R0052402VHA ACTIVE CFP NAD 10 19 TBD Call TI Call TI -55 to 125 LM111W RLQMLV Q 5962R00524 02VHA ACO 02VHA >T 5962R0052402VPA ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 LM111J-8RLQV 5962R00524 02VPA Q ACO 02VPA Q >T 5962R0052402VZA ACTIVE CFP NAC 10 54 TBD Call TI Call TI -55 to 125 LM111W GRLQMLV Q 5962R00524 02VZA ACO 02VZA >T Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 19-Jul-2016 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM111 MD8 ACTIVE DIESALE Y 0 300 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 LM111 MW8 ACTIVE WAFERSALE YS 0 1 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 LM111-MDE ACTIVE DIESALE Y 0 40 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 LM111H/883 ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LM111H/883 Q ACO LM111H/883 Q >T LM111HLQMLV ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LM111HLQMLV 5962L0052401VGA Q ACO 5962L0052401VGA Q >T LM111HRLQMLV ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LM111HRLQV 5962R0052402VGA Q ACO 5962R0052402VGA Q >T LM111J-8/883 ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 LM111J-8 /883 Q ACO /883 Q >T LM111J-8LQMLV ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 LM111J-8LQV 5962L00524 01VPA Q ACO 01VPA Q >T LM111J-8RLQMLV ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 LM111J-8RLQV 5962R00524 02VPA Q ACO 02VPA Q >T LM111J/883 ACTIVE CDIP J 14 25 TBD Call TI Call TI -55 to 125 LM111J/883 Q LM111WG/883 ACTIVE CFP NAC 10 54 TBD Call TI Call TI -55 to 125 LM111WG /883 Q ACO /883 Q >T LM111WGLQMLV ACTIVE CFP NAC 10 54 TBD Call TI Call TI -55 to 125 LM111W GLQMLV Q 5962L00524 01VZA ACO 01VZA >T Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 19-Jul-2016 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM111WGRLQMLV ACTIVE CFP NAC 10 54 TBD Call TI Call TI -55 to 125 LM111W GRLQMLV Q 5962R00524 02VZA ACO 02VZA >T LM111WLQMLV ACTIVE CFP NAD 10 19 TBD Call TI Call TI -55 to 125 LM111W LQMLV Q 5962L00524 01VHA ACO 01VHA >T LM111WRLQMLV ACTIVE CFP NAD 10 19 TBD Call TI Call TI -55 to 125 LM111W RLQMLV Q 5962R00524 02VHA ACO 02VHA >T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com 19-Jul-2016 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF LM111QML, LM111QML-SP : • Military: LM111QML • Space: LM111QML-SP NOTE: Qualified Version Definitions: • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 4 MECHANICAL DATA NAB0008A J08A (Rev M) www.ti.com MECHANICAL DATA NAC0010A WG10A (Rev H) www.ti.com MECHANICAL DATA NAD0010A W10A (Rev H) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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