AVAGO HSDL-3603-208 Irdaâ® data compliant 4 mbit/s infrared transceiver Datasheet

HSDL-3603
IrDA® Data Compliant 4 Mbit/s Infrared Transceiver
Data Sheet
Description
The HSDL-3603 is a low profile infrared transceiver
module that provides interface between logic and IR
signals for through-air, serial, half-duplex IR data-link.
The module is fully compliant to IrDA Date Physical
Layer Specifications v1.4 and IEC825-Class I Eye
Safe.
The HSDL-3603 can be shut down completely to
achieve very low power consumption. In the
shutdown mode, the PIN diode will be inactive and thus
producing very little photocurrent even under very
bright ambient light. Such features are ideal for mobile
devices that require low power consumption.
Applications
• Digital imaging
– Digital still cameras
– Photo-imaging printers
• Data communication
– Notebook computers
– Desktop PCs
– WinCE handheld products
– Personal Digital Assistants
– Printers
– Auto PCs
– Dongles
– Set-top box
• Digital imaging
– Digital cameras
– Photo-imaging printers
• Telecommunication products
– Mobile phones
– Pagers
• Electronic wallet
• Small industrial and medical instrumentation
– General data collection devices
– Patient and pharmaceutical data collection devices
• IR LANs
Features
• Fully compliant to IrDA 1.4 Fast Infrared (FIR) from 9.6
kbit/s to 4 Mbit/s
• Typical link distance > 1.5 m
• Miniature package
– Height: 3.90 mm (3.75 mm without shield)
– Width: 9.80 mm (9.3 mm without shield)
– Depth: 4.65 mm (4.4 mm without shield)
• Guaranteed temperature performance, -25 to 70°C
– Critical parameters are guaranteed over
temperature and supply voltage
• Low power consumption
– Low shutdown current (10 nA typical)
– Complete shutdown of TXD, RXD, and PIN diode
• Withstands >100 mVp-p power supply ripple typically
•
•
•
•
VCC supply 2.7 to 5.25 volts
Integrated optional EMI shield
LED stuck-high protection
Designed to accommodate light loss with cosmetic
windows
• IEC 825-Class 1 eye safe
• Interface to various super I/O and controller devices
Pinout
Functional Block Diagram
REAR VIEW
VCC
CX2
VCC (6)
CX1
GND (8)
NC (7)
8
7
6
5
4
3
2
1
Figure 2a. Rear view diagram with shield.
RECEIVER
SD/MODE (5)
RXD (4)
TRANSMITTER
OPTIONAL
SHIELD
REAR VIEW
HSDL-3603
TXD (3)
LED C (2)
VCC
R1
8
LED A (1)
7
6
5
4
3
2
1
Figure 2b. Rear view diagram without shield.
Figure 1. HSDL-3603 functional block diagram.
Ordering Information
Part Number
HSDL-3603-007
HSDL-3603-208
HSDL-3603-207
Packaging Type
Tape and Reel
Tape and Reel
Tape and Reel
Marking Information
The unit is marked with
3603yyww on the shield.
3603 = Product name
yy
= year
ww = work week
2
Package
Front View
Top View
Front View
Quantity
1800
1800
1800
Application Support Information
The Application Engineering
Group is available to assist you
with the application designs
associated with the HSDL-3603
infrared transceiver module. You
can contact them through your
local sales representatives for
additional details.
I/O Pins Configuration Table
Pin
1
Symbol
LED A
Description
LED Anode
I/O Type
Input
2
3
LED C
TXD
LED Cathode
Transmit Data
Output
Input,
Active High
4
RXD
Receive Data
Output,
Active Low
5
SD/Mode Shutdown/
Mode Select
Input,
Active High
6
VCC
7
8
–
NC
GND
Shield
Supply
Voltage
No Connect
Ground
EMI Shield
Supply
Voltage
No Connect
Ground
EMI Shield
Function
This pin can be connected directly to VCC (i.e., without series resistor)
at less than 3 V. Please refer to Table 1 for VCC versus Series Resistor, R1.
Leave this pin unconnected.
This pin is used to transmit serial data when SD/Mode pin is low. If this
pin is held high longer than ~100 µs, the LED would be turned off when
used in conjunction with the SD/Mode pin. TXD is low at initialization.
This pin is capable of driving a standard CMOS or TTL load. No external
pull-up or pull-down resistor is required. It is in tri-state mode when the
transceiver is in shutdown mode and during digital serial programming
operations. RXD is high at initialization.
The transceiver is in shutdown mode if this pin is high for more than
400 µs. On the falling edge of this signal, the state of the TXD pin sampled
and used to set receiver low bandwidth (TXD=low) or high bandwidth
(TXD=high) mode. See Figure 3 and Figure 4 for bandwidth selection
timings. SD is low at initialization.
Regulated, 2.7 to 5.25 Volts.
Connect to system ground.
Connect to system ground via a low inductance trace. For best
performance, do not connect directly to the transceiver pin GND.
Recommended Application Circuit Components
Component
Recommended Value
R1
0 Ω ± 5%, 0.5 Watt, for 2.7 V
1.8 Ω ± 5%, 0.5 Watt, for 3.0 V
4.7 Ω ± 5%, 0.5 Watt, for 3.3 V
6.8 Ω ± 5%, 0.5 Watt, for 3.5 V
CX1
0.47 µF ± 20%, X7R Ceramic
CX2
6.8 µF ± 20%, Tantalum
Notes
1
2
Notes:
1. CX1 must be placed within 0.7 cm of the HSDL-3603 to obtain optimum noise immunity.
2. In environments with noisy power supplies, supply rejection performance can be enhanced
by including CX2, as shown in Figure 1: ”HSDL-3603 Functional Block Diagram“ on Page 2.
3
Bandwidth Selection Timing
The transceiver is in default SIR/
MIR mode when powered on.
User needs to apply the following
programming sequence to both
the SD and TXD inputs to enable
the transceiver to operate at FIR
mode.
VIH
VIH
50%
SD/MODE
50%
SD/MODE
VIL
VIL
tS
tS
tH
tH
VIH
TXD
50%
TXD
50%
50%
VIL
VIL
Figure 3. Bandwidth selection timing at SIR/MIR mode.
Figure 4. Bandwidth selection timing at FIR mode.
Setting the transceiver to SIR/MIR
Mode (9.6 kb/s to 1.152 Mbit/s)
1. Set SD/Mode input to logic
HIGH
2. TXD input should remain at
logic LOW
3. After waiting for tS ≥ 25 ns,
set SD/Mode to logic LOW, the
HIGH to LOW negative edge
transition will determine the
receiver bandwidth
4. Ensure that TXD input remains
low for tH ≥ 100 ns, the
receiver is now in SIR/MIR
mode
5. SD input pulse width for mode
selection should be > 50 ns.
Setting the transceiver to FIR
(4.0 Mbit/s) Mode
1. Set SD/Mode input to logic
HIGH
2. After SD/Mode input remains
HIGH at > 25ns, set TXD input
to logic HIGH, wait tS ≥ 25 ns
(from 50% of TXD rising edge
till 50% of SD falling edge)
3. Then set SD/Mode to logic
LOW, the HIGH to LOW
negative edge transition will
determine the receiver
bandwidth
4. After waiting for tH ≥ 100ns, set
the TXD input to logic LOW
5. SD input pulse width mode
selection should be > 50ns.
4
50%
Transceiver I/O Truth Table
Inputs
TXD
Light Input to Receiver
High
Don’t Care
Low
High
Low
Low
Don’t Care
Don’t Care
SD
Low
Low
Low
High
Outputs
LED
On
Off
Off
Off
RXD
Not Valid
Low
High
High
Notes
1, 2
Notes:
1. In-band IrDA signals and data rates ≤ 4Mbit/s.
2. RXD logic low is a pulsed response. The condition is maintained for a duration dependent on pattern and strength of the incident intensity.
Caution: The BiCMOS inherent to the design of this component increases the component’s susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be
taken in handling and assembly of this component to prevent damage and/or degradation, which
may be induced by ESD.
5
Absolute Maximum Ratings
For implementations where case to ambient thermal resistance is ≤ 50°C/W.
Parameter
Symbol
Min.
Max.
Storage Temperature
TS
–40
100
Operating Temperature
TA
–25
70
LED Anode Voltage
VLEDA
0
6.5
Supply Voltage
VCC
0
6.5
Input Voltage: TXD, SD/Mode
VI
0
6.5
Output Voltage: RXD
VO
0
6.5
DC LED Transmit Current
ILED (DC)
150
Average Transmit Current
ILED (PK)
650
Units
°C
°C
V
V
V
V
mA
mA
Notes
3
Note:
3. ≤ 25% duty cycle, ≤ 90 µs pulse width.
Recommended Operating Conditions
Parameter
Symbol
Operating Temperature
TA
Supply Voltage
VCC
Logic Input Voltage Logic High
VIH
for TXD, SD/Mode
Logic Low
VIL
Receiver Input
Logic High
EIH
Irradiance
Logic Low
LED (Logic High) Current
Pulse Amplitude
Receiver Data Rate
EIL
ILEDA
Min.
Typ.
–25
2.7
2/3 VCC
0
0.0036
Max.
70
5.25
VCC
1/3 VCC
500
Units
°C
V
V
V
mW/cm2
Conditions
0.0090
500
mW/cm2
400
0.3
600
µW/cm2
mA
0.576 Mbit/s ≤ in-band signals
≤ 4 Mbit/s[4]
For in-band signals ≤ 115.2 kbit/s[4]
0.0096
4.0
Mbit/s
For in-band signals ≤ 115.2 kbit/s[4]
Note:
4. An in-band optical signal is a pulse/sequence where the peak wavelength, λp, is defined as 850 ≤ λp ≤ 900 nm, and the pulse characteristics are
compliant with the IrDA Serial Infrared Physical Layer Link Specification v1.4.
6
Electrical and Optical Specifications
Specifications (Min. and Max. values) hold over the recommended operating conditions unless otherwise noted. Unspecified
test conditions may be anywhere in their operating range. All typical values (Typ.) are at 25°C with VCC set to 3.0 V unless
otherwise noted.
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
Receiver
Viewing Angle
2θ
30
°
Peak Sensitivity Wavelength
λp
880
nm
RXD Output Voltage Logic High VOH
VCC – 0.2
VCC
V
IOH = –200 µA, EI ≤ 0.3 µW/cm2
Logic Low VOL
0
0.4
V
IOL = 200 µA, EI ≥ 3.6 µW/cm2
RXD Pulse Width (SIR)
tPW (SIR) 1
4.0
µs
θ ≤ 15°, CL = 12 pF[5]
RXD Pulse Width (MIR)
tPW(MIR) 100
500
ns
θ ≤ 15°, CL = 12 pF 6]
RXD Pulse Width (FIR)
tPW(FIR)
80
165
ns
θ ≤ 15°, CL = 12 pF[7]
RXD Rise and Fall Times
tr, tf
25
ns
CL =12 pF
Receiver Latency Time
tL
10
150
µs
Receiver Wake Up Time
trw
10
150
µs
Transmitter
Radiant Intensity
IEH
100
180
mW/Sr
ILEDA = 400 mA, θ ≤ 15°, VTXD ≥ VIH
T = 25 °C
Viewing Angle
2θ
30
60
°
Peak Wavelength
λP
875
nm
Spectral Line Half Width
∆λ
35
nm
TXD Logic Levels
High
VIH
2/3 VCC
VCC
V
Low
VIL
0
1/3 VCC V
TXD Input Current
High
IH
0.02
10
µA
VI ≥ VIH
Low
IL
–10
–0.02
10
µA
0 ≤ VI ≤ VIL
LED Current
On
IVLED
400
600
mA
VI(TXD) ≥ VIH
Shutdown IVLED
20
1000
nA
VI(SD) ≥ VIH, TA = 25°C
TXD Pulse Width (SIR)
tPW (SIR) 1.5
1.6
1.8
µs
tPW (TXD) = 1.6 µs at 115.2 kbit/s
TXD Pulse Width (MIR)
tPW(MIR) 148
217
260
ns
tPW (TXD) = 217 ns at 1.152 Mbit/s
TXD Pulse Width (FIR)
tPW(FIR)
115
125
135
ns
tPW (TXD) = 125 ns at 4.0 Mbit/s
Maximum Optical PW
tPW(max.)
60
100
µs
TXD Rise and Fall Time (Optical)
tr, tf
40
ns
tPW (TXD) = 125 ns at 4.0 Mbit/s
Transceiver
Supply Current
Shutdown ICC1
10
1000
nA
VSD ≥ 2/3 VCC, TA = 25°C
Idle
ICC2
1.8
3.0
mA
VI(TXD) ≤ VIL, EI = 0
Active
ICC3
2.5
mA
EI = 10 mW/cm2
Notes:
5. For in-band signals ≤ 115.2 kbit/s where 3.6 µW/cm2 ≤ EI ≤ 500 mW/cm2.
6. For in-band signals at 1.152 Mbit/s where 9.0 µW/cm2 ≤ EI ≤ 500 mW/cm2.
7. For in-band signals of 125 ns pulse width, 4 Mbit/s, 4 PPM at recommended 400 mA drive current.
7
390
RADIANT INTENSITY (mW/Sr) vs. ILED
TA = 25°C, VCC = 3.0 V, ON-AXIS
2.80
370
2.70
350
330
310
2.60
VLED_A (V)
IEH (mW/Sr)
VLED_A vs. ILED
TA = 25°C, VCC = 3.0 V
290
270
250
230
210
190
2.50
2.40
2.30
2.20
2.10
170
150
250 300 350 400 450 500 550 600 650
2.00
250 300 350 400 450 500 550 600 650
ILED (mA)
ILED (mA)
Figure 5. IR LOP vs. ILED.
Figure 6. IR VLED vs. ILED.
tpw
tpw
VOH
VOL
LED ON
90%
90%
50%
50%
10%
10%
LED OFF
tf
tr
Figure 7. RXD output waveform.
tr
Figure 8. LED optical waveform.
TXD
LED
tpw (MAX.)
Figure 9. TXD ‘stuck on’ waveform.
SD
SD
RX
LIGHT
TXD
RXD
TX
LIGHT
tRW
Figure 10. Receiver wakeup time waveform.
8
tTW
Figure 11. TXD wakeup time waveform.
tf
HSDL-3603 Package Outline Dimensions (with shield)
4.90
MOUNTING CENTER
1.00
EMITTING
CENTER
LIGHT RECEIVING
CENTER
9.80
93° ± 1°
3.90
0.1
8
–0.10
+0.20
7
6
5
4
3
0.37
2
1
0.65
0.83
3.5
P1.0 x 7 = 7
4.10
3.85
;;;;
;;
Figure 12. Package outline dimensions.
9
5 SD/MODE
2 LEDC
6 Vcc
3 TXD
7 NC
4 RXD
8 GND
1.70
4.65
0.95
UNIT: mm
TOLERANCE: ± 0.2 mm
1 LEDA
0.75
0.25
HSDL-3603 Tape and Reel Dimensions (with shield)
4.00 ± 0.10
5°(MAX.)
1.75 ± 0.10
0.75 ± 0.10
1.55 ± 0.05
POLARITY
PIN 8: GND
+0.10
3.46 0
7.50 ± 0.10
16.00 ± 0.30
9.50 ± 0.10
+0.10
3.30 0
PIN 1: LED A
8.00
± 0.10
2.46 ± 0.10
0.30 ± 0.10
4.50 ± 0.10
5°(MAX.)
MATERIAL OF CARRIER TAPE: CONDUCTIVE POLYSTYRENE
MATERIAL OF COVER TAPE: PVC
4.65 ± 0.10
METHOD OF COVER: HEAT ACTIVATED ADHESIVE
5.15 ± 0.10
PROGRESSIVE DIRECTION
EMPTY
(40 mm MIN.)
LEADER
PARTS
MOUNTED
(40 mm MIN.)
EMPTY
(40 mm MIN.)
"B" "C"
330
QUANTITY
80
1800
UNIT: mm
DETAIL A
2.0 ± 0.5
DIA. 13.0 ± 0.5
B
C
R 1.0
LABEL
16.40
+ 2.00
0
21 ± 0.8
DETAIL A
Figure 13. Tape and reel dimensions.
10
2.00 ± 0.50
HSDL-3603 Package Outline Dimensions (without shield)
EMITTING
CENTER
LIGHT RECEIVING
CENTER
9.30
3.75
2.93
2.70
;;;
3.58
PITCH 1.00
4.40
0.75
0.83 (2 PLACES)
0.55
3.75
0.65 (8 PLACES)
9.30
Figure 14. Package outline dimensions.
11
HSDL-3603 Tape and Reel Dimensions (without shield)
;;;;; ;;;
;;
4.00 ± 0.10
5°(MAX.)
1.75 ± 0.10
0.75 ± 0.10
1.55 ± 0.05
POLARITY
PIN 8: GND
+0.10
3.46 0
7.50 ± 0.10
16.00 ± 0.30
9.50 ± 0.10
+0.10
3.30 0
PIN 1: LED A
8.00
± 0.10
2.46 ± 0.10
0.30 ± 0.10
4.50 ± 0.10
5°(MAX.)
MATERIAL OF CARRIER TAPE: CONDUCTIVE POLYSTYRENE
MATERIAL OF COVER TAPE: PVC
4.65 ± 0.10
METHOD OF COVER: HEAT ACTIVATED ADHESIVE
5.15 ± 0.10
PROGRESSIVE DIRECTION
EMPTY
(40 mm MIN.)
LEADER
PARTS
MOUNTED
(40 mm MIN.)
EMPTY
(40 mm MIN.)
"B" "C"
330
QUANTITY
80
1800
UNIT: mm
DETAIL A
2.0 ± 0.5
DIA. 13.0 ± 0.5
B
C
R 1.0
LABEL
16.40
+ 2.00
0
21 ± 0.8
DETAIL A
Figure 15. Tape and reel dimensions.
12
2.00 ± 0.50
Moisture Proof Packaging
All HSDL-3603 options are shipped in moisture proof package. Once
opened, moisture absorption begins. This part is compliant to JEDEC
level 4.
UNITS IN A SEALED
MOISTURE-PROOF
PACKAGE
PACKAGE IS
OPENED (UNSEALED)
ENVIRONMENT
LESS THAN 30°C,
AND LESS THAN
60% RH
YES
NO BAKING
IS NECESSARY
PACKAGE IS
OPENED LESS
THAN 72 HOURS
YES
NO
PERFORM RECOMMENDED
BAKING CONDITIONS
NO
Figure 16. Baking conditions.
Baking Conditions
If the parts are not stored in dry conditions, they must be baked before
reflow to prevent damage to the parts.
Package
In Reels
In Bulk
Temperature
60˚C
100˚C
125˚C
150˚C
Baking should only be done once.
13
Time
≥ 48 hours
≥ 4 hours
≥ 2 hours
≥ 1 hour
Recommended Storage Conditions
Storage
10°C to 30°C
Temperature
Relative Humidity
below 60% RH
Time from Unsealing to Soldering
After removal from the bag, the
parts should be soldered within
three days if stored at the
recommended storage conditions.
If times longer than three days
are needed, the parts must be
stored in a dry box.
In process zone P1, the PC
board and HSDL-3603
castellation I/O pins are heated
to a temperature of 125°C to
activate the flux in the solder
paste. The temperature ramp up
rate, R1, is limited to 4°C per
second to allow for even heating
of both the PC board and
HSDL-3603 castellation I/O pins.
Process zone P2 should be of
sufficient time duration (> 60
seconds) to dry the solder paste.
The temperature is raised to a
level just below the liquidus point
of the solder, usually 170°C
(338°F).
Process zone P3 is the solder
reflow zone. In zone P3, the
temperature is quickly raised
above the liquidus point of solder
to 230°C (446°F) for optimum
results. The dwell time above the
liquidus point of solder should be
between 15 and 90 seconds. It
usually takes about 15 seconds to
assure proper coalescing of the
solder balls into liquid solder and
the formation of good solder
14
MAX. 245°C
230
T – TEMPERATURE – (°C)
Reflow Profile
The reflow profile is a straightline representation of a nominal
temperature profile for a convective reflow solder process. The
temperature profile is divided
into four process zones, each
with different ∆T/∆time temperature change rates. The ∆T/∆time
rates are detailed in the following
table. The temperatures are measured at the component to
printed circuit board connections.
R3
200
183
170
150
R2
90 sec.
MAX.
ABOVE
183°C
125
R1
100
R4
R5
50
25
0
50
100
150
200
250
300
t-TIME (SECONDS)
P1
HEAT
UP
P2
SOLDER PASTE DRY
P3
SOLDER
REFLOW
P4
COOL
DOWN
Figure 17. Reflow graph.
Process Zone
Heat Up
Solder Paste Dry
Solder Reflow
Cool Down
Symbol
P1, R1
P2, R2
P3, R3
P3, R4
P4, R5
∆T
25˚C to 125˚C
125˚C to 170˚C
170˚C to 230˚C (245˚C max.)
230˚C to 170˚C
170˚C to 25˚C
connections. Beyond a dwell time
of 90 seconds, the intermetallic
growth within the solder connections becomes excessive,
resulting in the formation of weak
and unreliable connections. The
temperature is then rapidly
reduced to a point below the
solidus temperature of the solder,
usually 170°C (338°F), to allow
the solder within the connections
to freeze solid.
Maximum
∆T/∆time
4˚C/s
0.5˚C/s
4˚C/s
–4˚C/s
–3˚C/s
Process zone P4 is the cool
down after solder freeze. The
cool down rate, R5, from the
liquidus point of the solder to
25°C (77°F) should not exceed
-3°C per second maximum. This
limitation is necessary to allow
the PC board and HSDL-3603
castellation I/O pins to change
dimensions evenly, putting
minimal stresses on the
HSDL-3603 transceiver.
Appendix A: HSDL-3603 SMT Assembly Application Note
1.0. Solder Pad, Mask, and Metal Solder Stencil Aperture
METAL STENCIL
FOR SOLDER PASTE
PRINTING
STENCIL
APERTURE
LAND
PATTERN
SOLDER
MASK
PCBA
Figure 18. Stencil and PCBA.
1.1. Recommended Land Pattern for HSDL-3603
Dimension
a
b
c (pitch)
d
e
f
g
mm
2.00
0.70
1.00
2.50
1.51
3.09
2.84
RX LENS
inches
0.079
0.028
0.039
0.098
0.059
0.122
0.112
TX LENS
e
d
SHIELD'S
SOLDER
PAD
g
f
a
FIDUCIAL
b
8x SOLDER PAD
Figure 19. Top view of land pattern.
15
c
1.2. Adjacent Land Keep-out and
Solder Mask Areas
Dimension
h
j
k
l
mm
min. 0.2
10.8
5.1
3.2
inches
min. 0.008
0.425
0.201
0.126
• Adjacent land keep-out is
the maximum space occupied
by the unit relative to the land
pattern. There should be no
other SMD components within
this area.
• “h” is the minimum solder
resist strip width required to
avoid solder bridging adjacent
pads.
• It is recommended that
2 fiducial cross be placed at
mid-length of the pads for unit
alignment.
Note: Wet/Liquid photoimagineable solder resist/mask is
recommended.
16
j
Rx LENS
LAND
Tx LENS
SOLDER
MASK
h
k
Y
CENTER
l
Figure 20. PCBA – Adjacent land keep-out and solder mask.
1.3. Recommended Metal Solder
Stencil Aperture
It is recommended that only
0.152 mm (0.006 inches) or
0.127 mm (0.005 inches) thick
stencil be used for solder paste
printing. This is to ensure adequate printed solder paste volume and no shorting. The
following combination of metal
stencil aperture and metal stencil
thickness should be used:
See Figure 18
t, nominal stencil thickness
l, length of aperture
mm
inches
mm
inches
0.152
0.006
2.0 ± 0.05
0.12 ± 0.002
0.127
0.005
2.0 ± 0.05
0.15 ± 0.002
w, the width of aperture is fixed at 0.70 mm (0.027 inches)
Aperture opening for shield pad is 2.50 mm x 1.51 mm as per land dimension.
APERTURES AS PER
LAND DIMENSIONS
t (STENCIL THICKNESS)
SOLDER PASTE
METAL STENCIL
w
l
Figure 21. Solder paste stencil aperture.
17
Appendix B: HSDL-3603 SMT Assembly Application Note (No Shield)
1.0. Solder Pad, Mask, and Metal Solder Stencil Aperture
METAL STENCIL
FOR SOLDER PASTE
PRINTING
STENCIL
APERTURE
LAND
PATTERN
SOLDER
MASK
PCBA
Figure 22. Stencil and PCBA.
1.1. Recommended Land Pattern for HSDL-3603
Dimension
a
b
c (pitch)
mm
2.00
0.70
1.00
RX LENS
inches
0.079
0.028
0.039
TX LENS
a
FIDUCIAL
b
8x SOLDER PAD
Figure 23. Top view of land pattern.
18
c
1.2. Adjacent Land Keep-out and
Solder Mask Areas
j
Dimension
h
j
k
l
mm
min. 0.2
10.8
5.1
3.2
inches
min. 0.008
0.425
0.201
0.126
Rx LENS
LAND
h
Tx LENS
SOLDER
MASK
• Adjacent land keep-out is
the maximum space occupied
by the unit relative to the land
pattern. There should be no
other SMD components within
this area.
• “h” is the minimum solder
resist strip width required to
avoid solder bridging adjacent
pads.
• It is recommended that
2 fiducial cross be placed at
mid-length of the pads for unit
alignment.
Note: Wet/Liquid photoimagineable solder resist/mask is
recommended.
19
k
l
Figure 24. PCBA – Adjacent land keep-out and solder mask.
1.3. Recommended Metal Solder
Stencil Aperture
It is recommended that only
0.152 mm (0.006 inches) or
0.127 mm (0.005 inches) thick
stencil be used for solder paste
printing. This is to ensure adequate printed solder paste volume and no shorting. The
following combination of metal
stencil aperture and metal stencil
thickness should be used:
See Figure 18
t, nominal stencil thickness
l, length of aperture
mm
inches
mm
inches
0.152
0.006
2.0 ± 0.05
0.12 ± 0.002
0.127
0.005
2.0 ± 0.05
0.15 ± 0.002
w, the width of aperture is fixed at 0.70 mm (0.027 inches)
Aperture opening for shield pad is 2.50 mm x 1.51 mm as per land dimension.
APERTURES AS PER
LAND DIMENSIONS
t (STENCIL THICKNESS)
SOLDER PASTE
METAL STENCIL
w
l
Figure 25. Solder paste stencil aperture.
20
Appendix C: PCB Layout Suggestion
The following PCB layout guidelines should be followed to obtain a
good PSRR and EM immunity,
resulting in good electrical
performance. Things to note:
Refer to the diagram below for
an example of a 4-layer board.
TOP LAYER
CONNECT THE METAL SHIELD AND MODULE
GROUND PIN TO BOTTOM GROUND LAYER.
1. The AGND pin should be
connected to the ground plane.
LAYER 2
CRITICAL GROUND PLANE ZONE. DO NOT
CONNECT DIRECTLY TO THE MODULE
GROUND PIN.
2. C1 and C2 are optional supply
filter capacitors; they may be left
out if a clean power supply is
used.
3. VLED can be connected to either
unfiltered or unregulated power
supply. If VLED and VCC share
the same power supply and C1 is
used, the connection should be
before the current limiting
resistor R1. In a noisy environment, including capacitor C2 can
enhance supply rejection. C1 is
generally a ceramic capacitor of
low inductance providing a wide
frequency response while C2 is a
tantalum capacitor of big volume
and fast frequency response. The
use of a tantalum capacitor is
more critical on the VLED line,
which carries a high current.
LAYER 3
KEEP DATA BUS AWAY FROM CRITICAL
GROUND PLANE ZONE.
BOTTOM LAYER (GND)
The area underneath the module at
the second layer, and 3 cm in all
directions around the module, is
defined as the critical ground plane
zone. The ground plane should be
maximized in this zone. Refer to
application note AN1114 or the
Avago IrDA Data Link Design
Guide for details. The layout below
is based on a 2-layer PCB.
17.2 mm
4. Preferably, a multi-layered board
should be used to provide
sufficient ground plane. Use the
layer underneath and near the
transceiver module as VCC, and
sandwich that layer between
ground connected board layers.
28 mm
Top Layer
Figure 26. PCB layout suggestion.
21
Bottom Layer
Appendix D: General Application
Guide for the HSDL-3603 Infrared
IrDA® Compliant 4 Mb/s Transceiver
Description
The HSDL-3603 wide voltage
operating range infrared transceiver is a low-cost and small
form factor that is designed to
address the mobile computing
market such as notebooks, printers, and LAN access as well as
small embedded mobile products
such as digital cameras, cellular
phones, and PDAs. It is fully compliant to IrDA 1.4 specification
up to 4 Mb/s. The design of the
HSDL-3603 also includes the
following unique features:
• Low passive component count.
• Shutdown mode for low power
consumption requirement.
• Single-receive output for all
data rates.
22
Selection of Resistor R1
Resistor R1 should be selected to
provide the appropriate peak
pulse LED current over different
ranges of VCC. The recommended
selection of R1 is tabulated in the
table on page 3. The HSDL-3603
typically provides 180 mW/Sr of
intensity at the recommended
minimum peak pulse LED current
of 400 mA.
Interface to Recommended I/O chips
The HSDL-3603’s TXD data input
is buffered to allow for CMOS
drive levels. No peaking circuit or
capacitor is required.
Data rate from 9.6 kb/s up to 4
Mb/s is available at the RXD pin.
Following shows the interface of
HSDL-3603 with National
Semiconductor’s Super I/Os, and
the SMC I/O chips.
(A) National Semiconductor Super
I/O and Infrared Controller
For National Semiconductor
Super I/O and Infrared Controller
chips, IR link can be realized with
the following connections:
• Connect IRTX of the National
Super I/O or IR Controller to
TXD (pin 3) of the HSDL-3603.
• Connect IRRX1 of the National
Super I/O or IR Controller to
RXD (pin 4) of the HSDL-3603.
• Connect IRSL0 of the National
Super I/O or IR Controller to
SD/Mode (pin 5) of the HSDL3603.
Please refer to the table below for
the IR pin assignments for the
National Super I/O and IR Controllers that support IrDA 1.4 up
to 4 Mb/s:
PC87391/2/3/3F-VJG
PC97338VJG
PC87360/3/4/5/6
PC87309VLJ
PC8(9)7307
PC8(9)7317VUL
IRTX
70
63
57
44
81
81
R1
LEDC (2)
LEDA (1)
TXD (3)
SP
IRTX
IRRX1
HSDL-3603
RXD (4)
IRSL0
SD/MODE (5)
CX1
VCC (6)
GND (8)
CX2
VCC
HSDL-3603
FUNCTIONAL BLOCK DIAGRAM
Figure 27. NS Super I/O configuration circuit.
23
IRSL0
68
66
58
100
79
79
Please refer to the National Semiconductor data sheets and application notes for updated
information.
VCC
NATIONAL
SEMICONDUCTOR
SUPER I/O
or
IR CONTROLLER
IRRX1
69
65
59
43
80
80
(B) Standard Micro System Corporation (SMC) Super and Ultra I/O
Controllers
For SMC Super and Ultra I/O
Controller chips, IR link can be
realized with the following
connections:
Please refer to the table below for
the IR pin assignments for the
SMC Super or Ultra I/O Controllers that support IrDA 1.4 up to
4 Mb/s:
• Connect IRTX of the SMC Super
or Ultra I/O Controller to TXD
(pin 3) of the HSDL-3603.
• Connect IRRX of the SMC Super
or Ultra I/O Controller to RXD
(pin 4) of the HSDL-3603.
• Connect IRMODE of the Super
or Ultra I/O Controller to
SD/Mode (pin 5) of the HSDL3603.
FDC37C669FR
FDC37N769
FDC37C957/8FR
IRTX
89
87
204
VCC
R1
LEDC (2)
IRRX
STANDARD
MICROSYSTEM
CORPORATION
SUPER I/O
or
IR CONTROLLER
IRMODE
LEDA (1)
RXD (4)
SD/MODE (5)
HSDL-3603
IRTX
TXD (3)
SP
CX1
GND (8)
VCC (6)
CX2
VCC
GND
Figure 28. SMC Super I/O configuration circuit.
24
IRRX
88
86
203
IRMODE
23
21
145 or 190
(C) Mobile Phone and PDA Platform
The block diagrams below show
how the IrDA port fits into a
mobile phone and PDA platform.
MICROPHONE
AUDIO INTERFACE
SPEAKER
DSP CORE
ASIC
CONTROLLER
RF INTERFACE
TRANSCEIVER
MOD/
DE-MODULATOR
IR
MICROCONTROLLER
USER INTERFACE
Figure 29. IR layout in mobile phone platform.
LCD
PANEL
RAM
IR
CPU
FOR EMBEDDED
APPLICATION
ROM
PCMCIA
CONTROLLER
TOUCH
PANEL
RS232C
DRIVER
Figure 30. IR layout in PDA platform.
25
COM
PORT
Appendix E: Window Design
In the figure below, X is the width
of the window, Y is the height of
the window and Z is the distance
from the HSDL-3603 to the back
of the window. The distance from
the center of the LED lens to the
center of the photodiode lens, K,
is 7.08 mm. The equations for
computing the window dimensions are as follows:
Optical Port Dimensions for HSDL3603:
To ensure IrDA compliance,
some constraints on the height
and width of the window exist.
The minimum dimensions ensure
that the IrDA cone angles are met
without vignetting. The maximum
dimensions minimize the effects
of stray light. The minimum size
corresponds to a cone angle of
30° and the maximum size corresponds to a cone angle of 60º.
X = K + 2*(Z + D)*tanA
Y = 2*(Z + D)*tanA
The above equations assume that
the thickness of the window is
negligible compared to the distance of the module from the back
;;;;;;;;
;;;;;;
;;;;;;;;;
;;;;;;
;;;;;;;;
;;;;;
;; ;;
OPAQUE
MATERIAL
IR TRANSPARENT WINDOW
Y
X
IR TRANSPARENT
WINDOW
K
Z
A
D
Figure 31. Window design diagram.
26
OPAQUE
MATERIAL
of the window (Z). If they are comparable, Z' replaces Z in the above
equation. Z' is defined as
Z' = Z + t/n
where ‘t’ is the thickness of the
window and ‘n’ is the refractive
index of the window material.
The depth of the LED image inside the HSDL-3603, D, is 8 mm.
‘A’ is the required half angle for
viewing. For IrDA compliance,
the minimum is 15° and the maximum is 30°. Assuming the thickness of the window to be
negligible, the equations result in
the following tables and graphs:
APERTURE WIDTH (X) vs. MODULE DEPTH
APERTURE HEIGHT (Y) vs. MODULE DEPTH
30
25
25
20
15
10
X MAX.
X MIN.
5
0
0
1
2
3
4
5
6
7
8
9
MODULE DEPTH (Z) – mm
Figure 32. Aperture width (X) vs. module depth.
27
Aperture Height
(y, mm)
max.
min.
9.238
4.287
10.392
4.823
11.547
5.359
12.702
5.895
13.856
6.431
15.011
6.967
16.166
7.503
17.321
8.038
18.475
8.574
19.630
9.110
APERTURE HEIGHT (Y) – mm
APERTURE WIDTH (X) – mm
Module Depth, (z) mm
0
1
2
3
4
5
6
7
8
9
Aperture Width
(x, mm)
max.
min.
16.318
11.367
17.472
11.903
18.627
12.439
19.782
12.975
20.936
13.511
22.091
14.047
23.246
14.583
24.401
15.118
25.555
15.654
26.710
16.190
20
15
10
5
0
Y MAX.
Y MIN.
0
1
2
3
4
5
6
7
8
9
MODULE DEPTH (Z) – mm
Figure 33. Aperture height (Y) vs. module depth.
Window Material
Almost any plastic material will
work as a window material.
Polycarbonate is recommended.
The surface finish of the plastic
should be smooth, without any
texture. An IR filter dye may be
used in the window to make it look
black to the eye, but the total
optical loss of the window should
be 10% or less for best optical
performance. Light loss should be
measured at 875 nm.
The recommended plastic
materials for use as a cosmetic
window are available from General
Electric Plastics.
Shape of the Window
From an optics standpoint, the
window should be flat. This
ensures that the window will not
alter either the radiation pattern of
the LED, or the receive pattern of
the photodiode.
If the window must be curved for
mechanical or industrial design
reasons, place the same curve on
the back side of the window that
has an identical radius as the front
side. While this will not completely
eliminate the lens effect of the
front curved surface, it will
significantly reduce the effects.
The amount of change in the
radiation pattern is dependent
upon the material chosen for the
window, the radius of the front and
back curves, and the distance from
the back surface to the transceiver.
Once these items are known, a lens
design can be made which will
eliminate the effect of the front
surface curve.
The following drawings show the
effects of a curved window on the
radiation pattern. In all cases, the
center thickness of the window is
1.5 mm, the window is made of
polycarbonate plastic, and the
distance from the transceiver to
the back surface of the window is
3 mm.
Recommended Plastic Materials:
Material
Number
Lexan 141L
Lexan 920A
Lexan 940A
Light
Transmission
88%
85%
85%
Haze
1%
1%
1%
Refractive
Index
1.586
1.586
1.586
Note: 920A and 940A are more flame retardant than 141L.
Recommended Dye: Violet #21051 (IR transmissant above 625 nm).
Flat Window
(First Choice)
Figure 34. Window design choices.
28
Curved Front and Back
(Second Choice)
Curved Front, Flat Back
(Do Not Use)
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes 5988-7926EN
5988-8659EN May 24, 2006