Dual, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™) ISL23328 Features The ISL23328 is a volatile, low voltage, low noise, low power, 128-Tap, dual digitally controlled potentiometer (DCP) with an I2C Bus™ interface. It integrates two DCP cores, wiper switches and control logic on a monolithic CMOS integrated circuit. • Two potentiometers per package Each digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated volatile Wiper Register (WRi, i = 0, 1) that can be directly written to and read by the user. The contents of the WRi controls the position of the wiper. When powered on, the wiper of each DCP will always commence at mid-scale (64 tap position). The low voltage, low power consumption, and small package of the ISL23328 make it an ideal choice for use in battery operated equipment. In addition, the ISL23328 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the VCC value. This allows for low logic levels to be connected directly to the ISL23328 without passing through a voltage level shifter. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. • 128 resistor taps • 10kΩ, 50kΩ or 100kΩ total resistance • I2C serial interface - No additional level translator for low bus supply - Three address pins allow up to eight devices per bus • Power supply - VCC = 1.7V to 5.5V analog power supply - VLOGIC = 1.2V to 5.5V I2C bus/logic power supply • Maximum supply current without serial bus activity (standby) - 3µA @ VCC and VLOGIC = 5V - 1.7µA @ VCC and VLOGIC = 1.7V • Shutdown Mode - Forces the DCP into an end-to-end open circuit and RWi is connected to RLi internally - Reduces power consumption by disconnecting the DCP resistor from the circuit • Wiper resistance: 70Ω typical @ VCC = 3.3V • Power-on preset to mid-scale (64 tap position) Applications • Extended industrial temperature range: -40°C to +125°C • Power supply margining • 14 Ld TSSOP or 16 Ld UTQFN packages • Trimming sensor circuits • Pb-free (RoHS Compliant) • Gain adjustment in battery powered instruments • RF power amplifier bias compensation 10000 VREF RESISTANCE (Ω) 8000 6000 RH1 1 DCP OF ISL23328 4000 RW1 VREF_M + ISL28114 2000 RL1 0 0 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP POSITION, 10kΩ DCP September 29, 2015 FN7902.1 1 FIGURE 2. VREF ADJUSTMENT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2015. All Rights Reserved Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL23328 Block Diagram VLOGIC VCC SCL SDA A0 POWER UP INTERFACE, CONTROL AND STATUS LOGIC LEVEL SHIFTER I/O BLOCK A1 A2 RH0 WR0 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY WR1 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY RW0 GND Pin Configurations RH1 RL0 RW1 RL1 Pin Descriptions TSSOP UTQFN SYMBOL DESCRIPTION 1 6, 15 GND 2 16 VLOGIC 3 1 SDA Logic Pin - Serial bus data input/open drain output Ground pin 1 14 VCC VLOGIC 2 13 RL0 SDA 3 12 RW0 SCL 4 11 RH0 4 2 SCL Logic Pin - Serial bus clock input A0 5 10 RH1 5 3 A0 A1 6 9 RW1 A2 7 8 RL1 Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND 6 4 A1 Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND 7 5 A2 Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND RL0 I2C bus/logic supply. Range 1.2V to 5.5V GND 8 8 RL1 DCP1 “low” terminal 13 ISL23328 (14 LD TSSOP) TOP VIEW 9 9 RW1 DCP1 wiper terminal ISL23328 (16 LD UTQFN) GND VCC 14 15 16 VLOGIC TOP VIEW 10 10 RH1 DCP1 “high” terminal RH0 11 11 RH0 DCP0 “high” terminal A0 3 10 RH1 A1 4 9 RW1 12 12 RW0 DCP0 wiper terminal 13 13 RL0 DCP0 “low” terminal 14 14 VCC Analog power supply. Range 1.7V to 5.5V 7 NC Not Connected RL1 NC A2 GND 2 8 RW0 11 7 12 2 6 1 SCL 5 SDA FN7902.1 September 29, 2015 ISL23328 Ordering Information PART NUMBER (Note 4) PART MARKING RESISTANCE OPTION (kΩ) TEMP RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL23328TFVZ (Note 2) 23328 TFVZ 100 -40 to +125 14 Ld TSSOP M14.173 ISL23328TFVZ-T7A (Notes 1, 2) 23328 TFVZ 100 -40 to +125 14 Ld TSSOP M14.173 ISL23328TFVZ-TK (Notes 1, 2) 23328 TFVZ 100 -40 to +125 14 Ld TSSOP M14.173 ISL23328UFVZ (Note 2) (No longer available, recommended replacement: ISL23328TFRUZ-TK) 23328 UFVZ 50 -40 to +125 14 Ld TSSOP M14.173 ISL23328UFVZ-T7A (Notes 1, 2) (No longer available, recommended replacement: ISL23328TFRUZ-TK) 23328 UFVZ 50 -40 to +125 14 Ld TSSOP M14.173 ISL23328UFVZ-TK (Notes 1, 2) 23328 UFVZ 50 -40 to +125 14 Ld TSSOP M14.173 ISL23328WFVZ (Note 2) 23328 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173 ISL23328WFVZ-T7A (Notes 1, 2) 23328 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173 ISL23328WFVZ-TK (Notes 1, 2) 23328 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173 ISL23328TFRUZ-T7A (Notes 1, 3) GBM 100 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A ISL23328TFRUZ-TK (Notes 1, 3) GBM 100 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A ISL23328UFRUZ-T7A (Notes 1, 3) (No longer available, recommended replacement: ISL23328TFRUZ-TK) GBL 50 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A ISL23328UFRUZ-TK (Notes 1, 3) (No longer available, recommended replacement: ISL23328TFRUZ-TK) GBL 50 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A ISL23328WFRUZ-T7A (Notes 1, 3) GBK 10 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A ISL23328WFRUZ-TK (Notes 1, 3) GBK 10 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL23328. For more information on MSL please see techbrief TB363. 3 FN7902.1 September 29, 2015 ISL23328 Absolute Maximum Ratings Thermal Information Supply Voltage Range VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Wiper Current IW (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .4.5kV Charged Device Model (Tested per JESD22-A114E) . . . . . . . . . . . . . 1kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 14 Ld TSSOP Package (Notes 5, 6) . . . . . . 112 40 16 Ld UTQFN Package (Notes 5, 6) . . . . . . 110 64 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For JC, the “case temp” location is the center top of the package. Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL RTOTAL PARAMETER RH to RL Resistance TEST CONDITIONS MIN (Note 19) RW UNITS 10 kΩ U option 50 kΩ T option VRH, VRL MAX (Note 19) W option RH to RL Resistance Tolerance End-to-End Temperature Coefficient TYP (Note 7) 100 -20 W option ±2 kΩ +20 125 % ppm/°C U option 65 ppm/°C T option 45 ppm/°C DCP Terminal Voltage VRH or VRL to GND 0 VCC V Wiper Resistance RH - floating, VRL = 0V, force IW current to the wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V 70 200 Ω VCC = 1.7V 580 Ω 32/32/32 pF CH/CL/CW Terminal Capacitance See “DCP Macro Model” on page 9 ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC Noise Resistor Noise Density Wiper at middle point, W option 16 nV/√Hz Wiper at middle point, U option 49 nV/√Hz Wiper at middle point, T option 61 nV/√Hz Digital Feed-through from Bus to Wiper Wiper at middle point -65 dB Power Supply Reject Ratio Wiper output change if VCC change ±10%; wiper at middle point -75 dB Feed Thru PSRR 4 -0.4 <0.1 0.4 µA FN7902.1 September 29, 2015 ISL23328 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL MIN (Note 19) TYP (Note 7) MAX (Note 19) W option -0.5 ±0.15 +0.5 LSB (Note 8) U, T option -0.5 ±0.15 +0.5 LSB (Note 8) W option -0.5 ±0.15 +0.5 LSB (Note 8) U, T option -0.5 ±0.15 +0.5 LSB (Note 8) -3 -1.5 0 LSB (Note 8) -1.5 -0.9 0 LSB (Note 8) W option 0 1.5 3 LSB (Note 8) U, T option 0 0.9 1.5 LSB (Note 8) DCPs at same tap position, same voltage at all RH terminals, and same voltage at all RL terminals -2 ±0.5 2 LSB (Note 8) PARAMETER TEST CONDITIONS UNITS VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) INL (Note 12) DNL (Note 11) FSerror Integral Non-linearity, Guaranteed Monotonic Differential Non-linearity, Guaranteed Monotonic Full-scale Error W option U, T option ZSerror (Note 9) Vmatch (Note 21) Zero-scale Error DCP to DCP Matching TCV Ratiometric Temperature Coefficient (Notes 13) tLS_Settling Large Signal Wiper Settling Time fcutoff -3dB Cutoff Frequency W option, Wiper Register set to 40 hex 8 ppm/°C U option, Wiper Register set to 40 hex 4 ppm/°C T option, Wiper Register set to 40 hex 2.3 ppm/°C From code 0 to 7F hex, measured from 0 to 1 LSB settling of the wiper 300 ns Wiper at middle point W option 1200 kHz Wiper at middle point U option 250 kHz Wiper at middle point T option 120 kHz RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected) RINL (Note 17) Integral Non-linearity, Guaranteed Monotonic W option; VCC = 2.7V to 5.5V -1.0 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V Differential Non-linearity, Guaranteed Monotonic W option; VCC = 2.7V to 5.5V -0.5 U, T option; VCC = 1.7V 5 ±0.15 -0.5 ±0.15 +0.5 ±0.15 ±0.4 MI (Note 14) MI (Note 14) +0.5 ±0.4 -0.5 MI (Note 14) MI (Note 14) 1 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V +1.0 4 U, T option; VCC = 1.7V RDNL (Note 16) ±0.5 MI (Note 14) MI (Note 14) +0.5 MI (Note 14) MI (Note 14) FN7902.1 September 29, 2015 ISL23328 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER TEST CONDITIONS Roffset (Note 15) Offset, Wiper at 0 Position W option; VCC = 2.7V to 5.5V MIN (Note 19) TYP (Note 7) MAX (Note 19) 0 1.8 3 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V MI (Note 14) 3 0 U, T option; VCC = 1.7V 0.3 MI (Note 14) 1 MI (Note 14) 0.5 -2 UNITS MI (Note 14) Rmatch (Note 22) DCP to DCP Matching Any two DCPs at the same tap position with the same terminal voltages 2 LSB (Note 8) TCR (Note 18) Resistance Temperature Coefficient W option; Wiper register set between 19 hex and 7F hex 170 ppm/°C U option; Wiper register set between 19 hex and 7F hex 80 ppm/°C T option; Wiper register set between 19 hex and 7F hex 50 ppm/°C Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL ILOGIC ICC ILOGIC SB PARAMETER VLOGIC Supply Current (Write/Read) VCC Supply Current (Write/Read) VLOGIC Standby Current MAX (Note 19) UNITS VLOGIC = 5.5V, VCC = 5.5V, fSCL = 400kHz (for I2C active read and write) 200 µA VLOGIC = 1.2V, VCC = 1.7V, fSCL = 400kHz (for I2C active read and write) 5 µA VLOGIC = 5.5V, VCC = 5.5V 18 µA VLOGIC = 1.2V, VCC = 1.7V 10 µA VLOGIC = VCC = 5.5V, I2C interface in standby 1 µA 0.5 µA 2 µA 1.2 µA 1 µA 0.5 µA 2 µA 1.2 µA 0.4 µA TEST CONDITIONS MIN (Note 19) TYP (Note 7) VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby ICC SB VCC Standby Current VLOGIC = VCC = 5.5V, I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby ILOGIC VLOGIC Shutdown Current SHDN VLOGIC = VCC = 5.5V, I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby ICC SHDN VCC Shutdown Current VLOGIC = VCC = 5.5V, I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby ILkgDig Leakage Current, at Pins A0, A1, A2, SDA, SCL 6 Voltage at pin from GND to VLOGIC -0.4 <0.1 FN7902.1 September 29, 2015 ISL23328 Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL tDCP tShdnRec PARAMETER Wiper Response Time DCP Recall Time from Shutdown Mode VCC, VLOGIC VCC ,VLOGIC Ramp Rate Ramp (Note 20) Serial Interface Specification SYMBOL MIN (Note 19) TEST CONDITIONS TYP (Note 7) MAX (Note 19) UNITS W option; SCL rising edge of the acknowledge bit after data byte to wiper new position from 10% to 90% of the final value. 0.4 µs U option; SCL rising edge of the acknowledge bit after data byte to wiper new position from 10% to 90% of the final value. 1.5 µs T option; SCL rising edge of the acknowledge bit after data byte to wiper new position from 10% to 90% of the final value. 3.5 µs SCL rising edge of the acknowledge bit after ACR data byte to wiper recalled position and RH connection 1.5 µs Ramp monotonic at any level 0.01 50 V/ms For SCL, SDA, A0, A1, A2 unless otherwise noted. PARAMETER TEST CONDITIONS MIN (Note 19) TYP (Note 7) MAX (Note 19) UNITS VIL Input LOW Voltage -0.3 0.3 x VLOGIC V VIH Input HIGH Voltage 0.7 x VLOGIC VLOGIC + 0.3 V Hysteresis VOL SDA and SCL Input Buffer Hysteresis VLOGIC > 2V 0.05 x VLOGIC V VLOGIC < 2V 0.1 x VLOGIC V SDA Output Buffer LOW Voltage IOL = 3mA, VLOGIC > 2V 0 IOL = 1.5mA, VLOGIC < 2V Cpin SDA, SCL Pin Capacitance fSCL SCL Frequency tsp Pulse Width Suppression Time at SDA and SCL Inputs tAA 0.4 V 0.2 x VLOGIC V 10 pF 400 kHz Any pulse narrower than the max spec is suppressed 50 ns SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VLOGIC, until SDA exits the 30% to 70% of VLOGIC window 900 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VLOGIC during a STOP condition, to SDA crossing 70% of VLOGIC during the following START condition 1300 ns tLOW Clock LOW Time Measured at the 30% of VLOGIC crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VLOGIC crossing 600 ns START Condition Set-up Time SCL rising edge to SDA falling edge; both crossing 70% of VLOGIC 600 ns tSU:STA 7 FN7902.1 September 29, 2015 ISL23328 Serial Interface Specification SYMBOL For SCL, SDA, A0, A1, A2 unless otherwise noted. (Continued) PARAMETER TEST CONDITIONS MIN (Note 19) TYP (Note 7) MAX (Note 19) UNITS tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VLOGIC to SCL falling edge crossing 70% of VLOGIC 600 ns tSU:DAT Input Data Set-up Time From SDA exiting the 30% to 70% of VLOGIC window, to SCL rising edge crossing 30% of VLOGIC 100 ns tHD:DAT Input Data Hold Time From SCL falling edge crossing 70% of VLOGIC to SDA entering the 30% to 70% of VLOGIC window 0 ns tSU:STO STOP Condition Set-up Time From SCL rising edge crossing 70% of VLOGIC, to SDA rising edge crossing 30% of VLOGIC 600 ns tHD:STO STOP Condition Hold Time for Read From SDA rising edge to SCL or Write falling edge; both crossing 70% of VLOGIC 1300 ns 0 ns tDH Output Data Hold Time From SCL falling edge crossing 30% of VLOGIC, until SDA enters the 30% to 70% of VLOGIC window. IOL = 3mA, VLOGIC > 2V. IOL = 0.5mA, VLOGIC < 2V tR SDA and SCL Rise Time From 30% to 70% of VLOGIC 20 + 0.1 x Cb 250 ns tF SDA and SCL Fall Time From 70% to 30% of VLOGIC 20 + 0.1 x Cb 250 ns Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF tSU:A A2, A1, A0 Setup Time Before START condition 600 ns tHD:A A2, A1, A0 Hold Time After STOP condition 600 ns NOTES: 7. Typical values are for TA = +25°C and 3.3V supply voltages. 8. LSB = [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 9. ZS error = V(RW)0/LSB. 10. FS error = [V(RW)127 – VCC]/LSB. 11. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 12. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127 Max V RW i – Min V RW i 10 6 13. TC = ----------------------------------------------------------------------------For i = 8 to 127decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage - --------------------V V RW i +25°C +165°C and Min( ) is the minimum value of the wiper voltage over the temperature range. 14. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 15. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 16. RDNL = (RWi – RWi-1)/MI -1, for i = 8 to 127. 17. RINL = [RWi – (MI • i) – RW0]/MI, for i = 8 to 127. 18. 6 Max Ri – Min Ri 10 TC R = ------------------------------------------------------- --------------------Ri +25°C +165°C for i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the minimum value of the resistance over the temperature range. 19. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 20. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC first followed by the VCC. 21. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. 22. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. 8 FN7902.1 September 29, 2015 ISL23328 DCP Macro Model RTOTAL RH CL CH CW 32pF RL 32pF 32pF RW Timing Diagrams SDA vs SCL Timing tHIGH tF SCL tLOW tsp tR tSU:DAT tSU:STA tHD:DAT tHD:STA SDA (INPUT TIMING) tSU:STO tAA tDH tBUF SDA (OUTPUT TIMING) A0, A1, and A2 Pin Timing STOP START SCL CLK 1 SDA tSU:A tHD:A A0, A1, A2 9 FN7902.1 September 29, 2015 ISL23328 0.20 0.04 0.10 0.02 DNL (LSB) DNL (LSB) Typical Performance Curves 0.00 -0.10 0.00 -0.02 -0.20 0 32 64 96 -0.04 128 0 32 64 0.12 0.15 0.09 INL (LSB) INL (LSB) 0.30 0.00 0.06 0.03 -0.15 0 32 64 96 0.00 128 0 TAP POSITION (DECIMAL) 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 5. 10kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 6. 50kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C 0.20 0.04 0.10 0.02 RDNL (MI) RDNL (MI) 128 FIGURE 4. 50kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 3. 10kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C -0.30 96 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) 0.00 -0.10 0.00 -0.02 -0.20 -0.04 0 32 64 96 TAP POSITION (DECIMAL) FIGURE 7. 10kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C 10 128 0 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 8. 50kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C FN7902.1 September 29, 2015 ISL23328 (Continued) 0.30 0.08 0.15 0.04 RINL (MI) RINL (MI) Typical Performance Curves 0.00 -0.15 -0.30 0.00 -0.04 0 32 64 96 -0.08 128 0 32 +125°C 100 WIPER RESISTANCE () WIPER RESISTANCE () +25°C 80 60 40 -40°C 20 +125°C +25°C 80 60 -40°C 40 20 0 32 64 96 TAP POSITION (DECIMAL) 0 128 0 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 11. 10kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V FIGURE 12. 50kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V 200 40 150 30 TCv (ppm/°C) TCv (ppm/°C) 128 120 100 100 20 10 50 0 96 FIGURE 10. 50kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 9. 10kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C 0 64 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) 15 43 71 99 TAP POSITION (DECIMAL) FIGURE 13. 10kΩ TCv vs TAP POSITION, VCC = 3.3V 11 127 0 15 43 71 99 127 TAP POSITION (DECIMAL) FIGURE 14. 50kΩ TCv vs TAP POSITION, VCC = 3.3V FN7902.1 September 29, 2015 ISL23328 Typical Performance Curves (Continued) 120 500 90 TCr (ppm/°C) TCr (ppm/°C) 400 300 200 30 100 0 60 15 43 71 99 0 127 15 43 TAP POSITION (DECIMAL) 20 120 15 90 10 5 0 127 FIGURE 16. 50kΩ TCr vs TAP POSITION, VCC = 3.3V TCr (ppm/°C) TCv (ppm/°C) FIGURE 15. 10kΩ TCr vs TAP POSITION 71 99 TAP POSITION (DECIMAL) 60 30 15 43 71 99 TAP POSITION (DECIMAL) FIGURE 17. 100kΩ TCv vs TAP POSITION, VCC = 3.3V 127 0 15 43 71 99 TAP POSITION (DECIMAL) 127 FIGURE 18. 100kΩ TCr vs TAP POSITION, VCC = 3.3V SCL CLOCK WIPER SCL 9TH CLK OF THE DATA BYTE (ACK) RW PIN CH1: 20mV/DIV, 2µs/DIV CH2: 2V/DIV, 2µs/DIV CH1: 1V/DIV, 1µs/DIV CH2: 10mV/DIV, 1µs/DIV FIGURE 19. WIPER DIGITAL FEED-THROUGH 12 FIGURE 20. WIPER TRANSITION GLITCH FN7902.1 September 29, 2015 ISL23328 Typical Performance Curves (Continued) 1V/DIV 0.2µs/DIV 0.5V/DIV 20µs/DIV SCL 9TH CLOCK OF THE DATA BYTE (ACK) VCC WIPER WIPER FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE CH1: RH TERMINAL CH2: RW TERMINAL 1.8 STANDBY CURRENT ICC (µA) 1.6 1.4 1.2 1.0 VCC = 5.5V, VLOGIC = 5.5V 0.8 0.6 VCC = 1.7V, VLOGIC = 1.2V 0.4 0.2 0 -40 0.5V/DIV, 0.2µs/DIV -3dB FREQUENCY = 1.4MHz AT MIDDLE TAP Potentiometers Pins RHI AND RLI The high (RHi, i = 0, 1) and low (RLi, i = 0, 1) terminals of the ISL23328 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 127 decimal, the wiper will be closest to RHi, and with the WR set to 0, the wiper is closest to RLi. RWI RWi (i = 0, 1) is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. 13 10 35 60 85 110 TEMPERATURE (°C) FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY Functional Pin Descriptions -15 FIGURE 24. STANDBY CURRENT vs TEMPERATURE VCC Power terminal for the potentiometer section analog power source. Can be any value needed to support voltage range of DCP pins, from 1.7V to 5.5V, independent of the VLOGIC voltage. Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bi-directional serial data input/output pin for I2C interface. It receives device address, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. SDA requires an external pull-up resistor, since it is an open drain input/output. FN7902.1 September 29, 2015 ISL23328 SERIAL CLOCK (SCL) This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor, since a master is an open drain output. DEVICE ADDRESS (A2, A1, A0) The address inputs are used to set the least significant 3 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the ISL23328. A maximum of eight ISL23328 devices may occupy the I2C serial bus (see Table 3). The WRi can be read or written to directly using the I2C serial interface as described in the following sections. Memory Description The ISL23328 contains three volatile 8-bit registers: Wiper Register WR0, Wiper Register WR1, and Access Control Register (ACR). Memory map of the ISL23328 is shown in Table 1. The Wiper Register WR0 at address 0, contains current wiper position of DCP0; The Wiper Register WR1 at address 1 contains current wiper position of DCP1. The Access Control Register (ACR) at address 10h contains information and control bits described in Table 2. TABLE 1. MEMORY MAP VLOGIC Digital power source for the logic control section. It supplies an internal level translator for 1.2V to 5.5V serial bus operation. Use the same supply as the I2C logic source. Principles of Operation The ISL23328 is an integrated circuit incorporating two DCPs with its associated registers and an I2C serial interface providing direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap positions. Voltage at any DCP pins, RHi, RLi or RWi, should not exceed VCC level at any conditions during power-up and normal operation. The VLOGIC pin is the terminal for the logic control digital power source. It should use the same supply as the I2C logic source which allows reliable communication with a wide range of microcontrollers and is independent from the VCC level. This is extremely important in systems where the master supply has lower levels than DCP analog supply. ADDRESS (hex) VOLATILE REGISTER NAME DEFAULT SETTING (hex) 10 ACR 40 1 WR1 40 0 WR0 40 TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # 7 6 5 4 3 2 1 0 NAME/ VALUE 0 SHDN 0 0 0 0 0 0 Shutdown Function The SHDN bit (ACR[6]) disables or enables shutdown mode for all DCP channels simultaneously. When this bit is 0, i.e., DCP is forced to end-to-end open circuit and RW is connected to RL through a 2kΩ serial resistor as shown in Figure 25. Default value of the SHDN bit is 1. RH DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi pins). The RWi pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WRi). When the WRi of a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal (RWi) is closest to its “Low” terminal (RLi). When the WRi register of a DCP contains all ones (WRi[7:0] = 7Fh), its wiper terminal (RWi) is closest to its “High” terminal (RHi). As the value of the WRi increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RLi to the position closest to RHi. At the same time, the resistance between RWi and RLi increases monotonically, while the resistance between RHi and RWi decreases monotonically. RW 2kΩ RL FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE When the device enters shutdown, all current DCP WR settings are maintained. When the device exits shutdown, the wipers will return to the previous WR settings after a short settling time (see Figure 26). In shutdown mode, if there is a glitch on the power supply which causes it to drop below 1.3V for more than 0.2 to 0.4µs, the wipers will be RESET to their mid position. This is done to avoid an undefined state at the wiper outputs. While the ISL23328 is being powered up, both WR0 and WR1 are reset to 40h (64 decimal), which positions RWi at the center between RLi and RHi. 14 FN7902.1 September 29, 2015 WIPER VOLTAGE, VRW (V) ISL23328 ISL23328 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 27). A START condition is ignored during the power-up of the device. POWER-UP MID SCALE = 40H USER PROGRAMMED AFTER SHDN SHDN ACTIVATED SHDN RELEASED WIPER RESTORE TO THE ORIGINAL POSITION SHDN MODE 0 TIME (s) FIGURE 26. SHUTDOWN MODE WIPER RESPONSE I2C Serial Interface The ISL23328 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL23328 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 27). A STOP condition at the end of a read operation or at the end of a write operation places the device in its standby mode. An ACK (Acknowledge) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 28). The ISL23328 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL23328 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 1010 as the four MSBs, and the following three bits are matching the logic values present at pins A2, A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a Read operation and “0” for a Write operation (see Table 3). TABLE 3. IDENTIFICATION BYTE FORMAT Protocol Conventions LOGIC VALUES AT PINS A2, A1 AND A0 RESPECTIVELY Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 27). On power-up of the ISL23328, the SDA pin is in the input mode. 1 0 1 0 A2 (MSB) A1 A0 R/W (LSB) All I2C interface operations must begin with a START condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS 15 FN7902.1 September 29, 2015 ISL23328 SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER S T A R T SIGNALS FROM THE MASTER SIGNAL AT SDA WRITE IDENTIFICATION BYTE ADDRESS BYTE 1 0 1 0 A2A1 A0 0 SIGNALS FROM THE SLAVE S T O P DATA BYTE 0 0 0 A C K A C K A C K FIGURE 29. BYTE WRITE SEQUENCE SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA IDENTIFICATION BYTE WITH R/W = 0 ADDRESS BYTE 1 0 1 0 A2A1 A0 0 A C K S A T C O K P A C K 1 0 1 0 A2A1 A0 1 0 0 0 A C K SIGNALS FROM THE SLAVE S READ T A IDENTIFICATION R BYTE WITH T R/W = 1 A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 30. READ SEQUENCE Write Operation Read Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL23328 responds with an ACK. The data is transferred from I2C block to the corresponding register at the 9th clock of the data byte and the device enters its standby state (see Figures 28 and 29). A Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 30). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL23328 responds with an ACK; then the ISL23328 transmits Data Byte. The master terminates the read operation issuing a NACK (ACK) and a STOP condition following the last bit of the last Data Byte (see Figure 30). It is possible to perform a sequential Write to all DCP channels via a single Write operation. The command is initiated by sending an additional Data Byte after the first Data byte instead of sending a STOP condition. 16 FN7902.1 September 29, 2015 ISL23328 Applications Information VLOGIC Requirements VLOGIC should be powered continuously during normal operation. In a case where turning VLOGIC OFF is necessary, it is recommended to ground the VLOGIC pin of the ISL23328. Grounding the VLOGIC pin or both VLOGIC and VCC does not affect other devices on the same bus. It is good practice to put a 1µF cap in parallel to 0.1µF as close to the VLOGIC pin as possible. VCC Requirements and Placement It is recommended to put a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to the VCC pin. Wiper Transition When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break” within a short period of time (<1µs). There are several code transitions such as 0Fh to 10h, 1Fh to 20h,..., 6Fh to 7Fh, which have higher transient glitch. Note, that all switching transients will settle well within the settling time as stated in the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients. However, that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery. 17 FN7902.1 September 29, 2015 ISL23328 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE September 29, 2015 FN7902.1 Updated Ordering Information Table on page 3. Updated “Product“ section to “About Intersil”. Updated POD L16.2.6x1.8A from rev 5 go rev 6. Change since rev 5: Changed in Note 5 0.30 to 0.25 August 19, 2011 FN7902.0 Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN7902.1 September 29, 2015 ISL23328 Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 ±0.10 SEE DETAIL "X" 8 14 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 1 0.20 C B A 7 B 0.65 0.09-0.20 TOP VIEW END VIEW 1.00 REF 0.05 H C 0.90 +0.15/-0.10 1.20 MAX SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 GAUGE PLANE 0.25 5 0°-8° 0.05 MIN 0.15 MAX CBA SIDE VIEW 0.60 ±0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN 19 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. FN7902.1 September 29, 2015 ISL23328 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) D L16.2.6x1.8A B 16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS 6 INDEX AREA 2X A N SYMBOL E 0.10 C 1 2 2X 0.10 C 0.10 C C A A1 SIDE VIEW e PIN #1 ID K 1 2 NX L L1 (DATUM B) (DATUM A) BOTTOM VIEW NOTES 0.45 0.50 0.55 - - - 0.05 - 0.127 REF - b 0.15 0.20 0.25 5 D 2.55 2.60 2.65 - E 1.75 1.80 1.85 - 0.40 BSC - K 0.15 - - - L 0.35 0.40 0.45 - L1 0.45 0.50 0.55 - N 16 2 Nd 4 3 Ne 4 3 NX b 5 16X 0.10 M C A B 0.05 M C MAX A e SEATING PLANE NOMINAL A1 A3 TOP VIEW 0.05 C MIN 0 - 12 4 Rev. 6 1/14 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.25mm from the terminal tip. CL (A1) NX (b) L 5 e SECTION "C-C" 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. TERMINAL TIP C C 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 3.00 1.80 1.40 1.40 2.20 0.90 0.40 0.20 0.50 0.20 0.40 10 LAND PATTERN 20 FN7902.1 September 29, 2015