TI OPA2131 General-purpose fet-input operational amplifier Datasheet

O PA
OPA1
OPA
131
OPA2
31
2131
O PA
OPA131
OPA2131
OPA4131
4131
OP
A41
31
131
OPA4
131
SBOS040A – NOVEMBER 1994 – REVISED DECEMBER 2002
General-Purpose
FET-INPUT OPERATIONAL AMPLIFIERS
FEATURES
● FET INPUT: IB = 50pA max
● LOW OFFSET VOLTAGE: 750µV max
OPA131
● WIDE SUPPLY RANGE: ±4.5V to ±18V
● SLEW RATE: 10V/µs
Offset Trim
1
8
NC
–In
2
7
V+
+In
3
6
Output
V–
4
5
Offset Trim
8
V+
7
Out B
6
–In B
5
+In B
● WIDE BANDWIDTH: 4MHz
● EXCELLENT CAPACITIVE LOAD DRIVE
● SINGLE, DUAL, QUAD VERSIONS
DIP-8, SO-8
DESCRIPTION
The OPA131 series of FET-input op amps provides high
performance at low cost. Single, dual, and quad versions in
industry-standard pinouts allow cost-effective design options.
OPA2131
Out A
The OPA131 series offers excellent general-purpose performance, including low offset voltage, drift, and good dynamic
characteristics.
1
–In A
2
+In A
3
V–
4
A
B
Single, dual, and quad versions are available in DIP and SO
packages. Performance grades include commercial and industrial temperature ranges.
DIP-8, SO-8
OPA4131
OPA4131
Out A
1
–In A
2
A
14
Out D
Out A
1
13
–In D
–In A
2
A
D
+In A
3
12
+In D
V+
4
11
V–
+In B
5
10
+In C
B
16
Out D
15
–In D
D
+In A
3
14
+In D
V+
4
13
V–
+In B
5
12
+In C
B
C
C
–In B
6
9
–In C
–In B
6
11
–In C
Out B
7
8
Out C
Out B
7
10
Out C
NC
8
9
NC
DIP-14, SO-14
NC = No Connection
SOL-16
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage, V+ to V– .................................................................... 36V
Input Voltage .................................................. (V–) – 0.7V to (V+) + 0.7V
Output Short-Circuit(2) .............................................................. Continuous
Operating Temperature .................................................. –55°C to +125°C
Storage Temperature ..................................................... –55°C to +125°C
Junction Temperature ...................................................................... 150°C
Lead Temperature (soldering, 10s) ................................................. 300°C
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. (2) Short-circuit to ground, one amplifier per package.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
Single
OPA131
"
OPA131
"
OPA131
"
SO-8
"
SO-8
"
SO-8
"
D
"
D
"
D
"
–40°C to +85°C
"
–40°C to +85°C
"
–40°C to +85°C
"
OPA131UJ
"
OPA131UA
"
OPA131U
"
OPA131UJ
OPA131UJ/2K5
OPA131UA
OPA131UA/2K5
OPA131U
OPA131U/2K5
Rails, 100
Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
Dual
OPA2131
"
OPA2131
"
SO-8
"
SO-8
"
D
"
D
"
–40°C to +85°C
"
–40°C to +85°C
"
OPA2131UJ
"
OPA2131UA
"
OPA2131UJ
OPA2131UJ/2K5
OPA2131UA
OPA2131UA/2K5
Rails, 100
Tape and Reel, 2500
Rails, 100
Tape and Reel, 2500
Quad
OPA4131
"
OPA4131
"
OPA4131
"
DIP-14
"
SOL-16
"
SOL-14
"
N
"
DW
"
D
"
–40°C to +85°C
"
–40°C to +85°C
"
–40°C to +85°C
"
OPA4131PJ
OPA4131PA
OPA4131UA
"
OPA4131NJ
OPA4131NA
OPA4131PJ
OPA4131PA
OPA4131UA
OPA4131UA/1K
OPA4131NJ
OPA4131NA
Rails, 25
Rails, 25
Rails, 48
Tape and Reel, 1000
Rails, 58
Rails, 58
PRODUCT
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
2
OPA131, 2131, 4131
www.ti.com
SBOS040A
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = ±15V, and RL = 2kΩ, unless otherwise noted.
OPA131UA
OPA2131UA
OPA4131PA, UA, NA
PARAMETER
OFFSET VOLTAGE
Input Offset Voltage
OPA131U model only
vs Temperature(1)
vs Power Supply
OPA131U model only
INPUT BIAS CURRENT(2)
Input Bias Current
vs Temperature
Input Offset Current
CONDITION
MIN
TYP
MAX
UNITS
✻
±1.5
✻
✻
✻
✻
mV
mV
µV/°C
µV/V
µV/V
+5
±50
See Typical Characteristic
±1
±50
✻
✻
✻
✻
pA
✻
pA
21
16
15
15
3
✻
✻
✻
✻
✻
Operating Temperature Range
VS = ±4.5V to ±18V
VCM = 0V
VCM = 0V
NOISE
Input Voltage Noise
Noise Density, f = 10Hz
f = 100Hz
f = 1kHz
f = 10kHz
Current Noise Density, f = 1kHz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection
OPA131U model only
INPUT IMPEDANCE
Differential
Common-Mode
OPEN-LOOP GAIN
Open-Loop Voltage Gain
OPA131U model only
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
Settling Time 0.1%
0.01%
Total Harmonic Distortion + Noise
VCM = –12V to +14V
VO = –12V to +12V
MAX
±0.2
±0.2
±2
50
50
±1
0.75
±10
200
100
(V+) – 1
80
86
94
100
✻
✻
✻
110
110
4
10
1.5
2
0.0008
G = –1, 10V Step, CL = 100pF
G = –1, 10V Step, CL = 100pF
1kHz, G = 1, VO = 3.5Vrms
✻
✻
(V+) – 3 (V+) – 2.5
(V–) + 3 (V–) + 2.5
±25
±4.5
IO = 0
TEMPERATURE RANGE
Operating Range
Storage
Thermal Resistance, θJA
DIP-8
SO-8
DIP-14
SO-14, SOL-16
MIN
1010 || 1
1012 || 3
VCM = 0V
OUTPUT
Voltage Output, Positive
Negative
Short-Circuit Current
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current (per amplifier)
(V–) + 3
70
80
TYP
OPA131UJ
OPA2131UJ
OPA4131PJ, NJ
±15
±1.5
–55
–55
100
150
80
110
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
✻
✻
V
dB
dB
✻
✻
Ω || pF
Ω || pF
✻
dB
dB
✻
✻
✻
✻
✻
MHz
V/µs
µs
µs
%
✻
✻
✻
V
V
mA
✻
±18
±1.75
✻
+125
+125
–55
✻
✻
✻
✻
✻
✻
✻
±2
V
V
mA
+125
✻
°C
°C
°C/W
°C/W
°C/W
°C/W
✻ Specifications same as OPA131UA.
NOTES: (1) Ensured by wafer test. (2) High-speed test at TJ = 25°C.
OPA131, 2131, 4131
SBOS040A
www.ti.com
3
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±15V, and RL = 2kΩ, unless otherwise noted.
POWER SUPPLY AND COMMON-MODE REJECTION
vs FREQUENCY
OPEN-LOOP GAIN/PHASE vs FREQUENCY
100
80
∅
–90
60
40
–135
20
Phase Shift (°)
Voltage Gain (dB)
–45
G
–180
0
Power Supply Rejection (dB)
120
–20
120
100
80
80
–PSR
60
CMR
40
40
20
20
10
100
1k
10k
100k
1M
0
10
10M
100
1k
Frequency (Hz)
10
10
Channel Separation (dB)
Voltage Noise
RL = ∞
140
120
Dual and quad devices.
G = 1, all channels.
Quad measured channel
A to D or B to C—other
combinations yield improved
rejection.
100
Current Noise
1
1
100
1k
1M
160
Current Noise (fA/√Hz)
Voltage Noise (nV/√Hz)
100
100
10
100k
CHANNEL SEPARATION vs FREQUENCY
1k
1k
1
10k
Frequency (Hz)
INPUT VOLTAGE AND CURRENT NOISE
SPECTRAL DENSITY vs FREQUENCY
10k
100k
RL = 2kΩ
80
10
1M
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
INPUT BIAS AND INPUT OFFSET CURRENT
vs TEMPERATURE
INPUT BIAS CURRENT
vs INPUT COMMON-MODE VOLTAGE
1k
10k
Input bias current is a
function of the voltage
between the V– supply
and the inputs.
1k
Input Bias Current (pA)
Input Bias and Input Offset Current (pA)
60
0
1
VCM = 0V
100
IB
IOS
10
1
100
VS = ±15V
10
0.1
VS = ±5V
0.01
–75
–50
–25
0
25
50
75
100
125
1
–15
–10
–5
0
5
10
15
Common-Mode Voltage (V)
Ambient Temperature (°C)
4
100
+PSR
OPA131, 2131, 4131
www.ti.com
SBOS040A
Common-Mode Rejection (dB)
0
120
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = ±15V, and RL = 2kΩ, unless otherwise noted.
QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT
vs TEMPERATURE
1.8
120
40
IQ
VS = ±15V
Quiescent Current (mA)
Voltage Gain (dB)
ISC–
115
110
105
30
ISC+
1.4
20
IQ
VS = ±5V
1.2
10
1
100
–75
–50
–25
0
25
50
75
100
0
–75
125
–50
–25
0
25
50
75
Ambient Temperature (°C)
Temperature (°C)
OFFSET VOLTAGE
PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
100
125
35
20
Typical production distribution
of packaged units. Single,
Typical production distribution
of packaged units. Single,
30
dual and quad units included.
15
dual and quad units included.
25
Units (%)
Units (%)
1.6
10
20
15
10
5
5
0
1400
1200
800
1000
600
400
0
200
–200
–400
–600
–800
–1000
–1200
–1400
0
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
Offset Voltage Drift (µV/°C)
Offset Voltage (µV)
MAXIMUM OUTPUT VOLTAGE
vs FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
30
1
Output Voltage (Vp-p)
VO = 3.5Vrms
0.1
THD + Noise (%)
VS = ±15V
BandwidthLimited
G = 100V/V
0.01
G = 10V/V
0.001
Maximum output voltage
without slew-rate induced
distortion.
20
10
VS = ±5V
G = 1V/V
0
0.0001
10
100
1k
10k
100k
OPA131, 2131, 4131
SBOS040A
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
www.ti.com
5
Short-Circuit Current (mA)
OPEN-LOOP GAIN vs TEMPERATURE
TYPICAL CHARACTERISTICS (Cont.)
At TCASE = +25°C, VS = ±15V, and RL = 2kΩ, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE
G = 1, CL = 300pF
5V/div
50mV/div
SMALL-SIGNAL STEP RESPONSE
G =1, CL = 300pF
1µs/div
200ns/div
SMALL-SIGNAL OVERSHOOT
vs LOAD CAPACITANCE
SETTLING TIME vs CLOSED-LOOP GAIN
100
50
40
Overshoot (%)
Settling Time (µs)
VO = 10V Step
RL = 2kΩ
CL = 100pF
10
0.01%
0.1%
G = +2
G = –1
30
G = ±10
20
G=1
10
1
–1
RL = 2kΩ
Higher RL value
generally reduces
overshoot.
–10
–100
0
100pF
–1000
1nF
Closed-Loop Gain (V/V)
10nF
Load Capacitance
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
15
VIN = 15V
Output Voltage Swing (V)
14
13
25°C
–55°C
12
11
125°C
10
–10
25°C
125°C
–11
–12
–55°C
–13
–14
VIN = –15V
–15
0
5
10
15
20
25
30
Output Current (mA)
6
OPA131, 2131, 4131
www.ti.com
SBOS040A
APPLICATIONS INFORMATION
V+
The OPA131 series op amps are unity-gain stable and
suitable for a wide range of general-purpose applications.
Power-supply pins should be bypassed with 10nF ceramic
capacitors or larger.
OPA131
(Single op amp only)
7
2
6
3
OPA131
5
The OPA131 series op amps are free from unexpected
output phase-reversal common with FET op amps. Many
FET-input op amps exhibit phase-reversal of the output when
the input common-mode voltage range is exceeded. This can
occur in voltage-follower circuits, causing serious problems
in control-loop applications. All circuitry is completely independent in dual and quad versions, assuring normal behavior
when one amplifier in a package is overdriven or shortcircuited.
FIGURE 1. OPA131 Offset Voltage Trim Circuit.
OFFSET VOLTAGE TRIM
INPUT BIAS CURRENT
The OPA131 (single op amp version) provides offset voltage trim connections on pins 1 and 5. Offset voltage can be
adjusted by connecting a potentiometer as shown in Figure
1. This adjustment should be used only to null the offset of
the op amp, not system offset or offset produced by the
signal source.
1
4
Trim Range: ±20mV typ
V–
The input bias current is approximately 5pA at room temperature and increases with temperature as shown in the
typical characteristic “Input Bias Current vs Temperature.”
Input bias current also varies with common-mode voltage
and power supply voltage. This variation is dependent on the
voltage between the negative power supply and the common-mode input voltage. The effect is shown in the typical
curve “Input Bias Current vs Common-Mode Voltage.”
OPA131, 2131, 4131
SBOS040A
100kΩ
www.ti.com
7
PACKAGE DRAWINGS
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES: A.
B.
C.
D.
8
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
OPA131, 2131, 4131
www.ti.com
SBOS040A
PACKAGE DRAWINGS (Cont.)
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
16
0.010 (0,25) M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0° – 8°
A
0.050 (1,27)
0.016 (0,40)
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
PINS **
0.004 (0,10)
16
18
20
24
28
A MAX
0.410
(10,41)
0.462
(11,73)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
A MIN
0.400
(10,16)
0.453
(11,51)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
DIM
4040000 / E 08/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
OPA131, 2131, 4131
SBOS040A
www.ti.com
9
PACKAGE DRAWINGS (Cont.)
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
A MAX
0.775
(19,69)
0.775
(19,69)
0.920
(23,37)
0.975
(24,77)
A MIN
0.745
(18,92)
0.745
(18,92)
0.850
(21,59)
0.940
(23,88)
DIM
A
16
9
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.035 (0,89) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gauge Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92) MAX
0.010 (0,25) M
14/18 PIN ONLY
4040049/D 02/00
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001).
10
OPA131, 2131, 4131
www.ti.com
SBOS040A
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
OPA131P
OBSOLETE
PDIP
P
8
None
Call TI
Call TI
OPA131PA
OBSOLETE
PDIP
P
8
None
Call TI
Call TI
OPA131PJ
OBSOLETE
PDIP
P
8
None
Call TI
Call TI
OPA131U
ACTIVE
SOIC
D
8
100
None
CU SNPB
Level-2-220C-1 YEAR
OPA131U/2K5
ACTIVE
SOIC
D
8
2500
None
CU SNPB
Level-2-220C-1 YEAR
OPA131UA
ACTIVE
SOIC
D
8
100
None
CU SNPB
Level-2-220C-1 YEAR
OPA131UA/2K5
ACTIVE
SOIC
D
8
2500
None
CU SNPB
Level-3-235C-168 HR
OPA131UJ
ACTIVE
SOIC
D
8
100
None
CU SNPB
Level-3-235C-168 HR
OPA131UJ/2K5
ACTIVE
SOIC
D
8
2500
None
CU SNPB
Level-3-235C-168 HR
OPA2131PA
OBSOLETE
PDIP
P
8
None
Call TI
Call TI
OPA2131PJ
OBSOLETE
PDIP
P
8
None
Call TI
Call TI
OPA2131UA
ACTIVE
SOIC
D
8
100
None
CU SNPB
Level-3-220C-168 HR
OPA2131UA/2K5
ACTIVE
SOIC
D
8
2500
None
CU SNPB
Level-3-220C-168 HR
OPA2131UJ
ACTIVE
SOIC
D
8
100
None
CU SNPB
Level-3-220C-168 HR
OPA2131UJ/2K5
ACTIVE
SOIC
D
8
2500
None
CU SNPB
Level-3-220C-168 HR
OPA4131NA
ACTIVE
SOIC
D
14
58
None
CU SNPB
Level-3-220C-168 HR
OPA4131NJ
ACTIVE
SOIC
D
14
58
None
CU SNPB
Level-3-235C-168 HR
OPA4131PA
ACTIVE
PDIP
N
14
25
None
Call TI
Level-NA-NA-NA
Level-NA-NA-NA
OPA4131PJ
ACTIVE
PDIP
N
14
25
None
Call TI
OPA4131UA
ACTIVE
SOIC
DW
16
48
None
CU SNPB
Level-3-260C-168 HR
OPA4131UA/1K
ACTIVE
SOIC
DW
16
1000
None
CU SNPB
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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