Cypress CY2XF32FLXCT High performance cmos oscillator with frequency margining - pin control Datasheet

PRELIMINARY
CY2XF32
High Performance CMOS Oscillator with
Frequency Margining - Pin Control
Features
Functional Description
■
Crystal Oscillator with CMOS Output
■
Output Frequency from 8 MHz to 200 MHz
■
Two Frequency Margining Control Pins (FS0, FS1)
■
Output Enable or Power Down Function
■
Factory Configured or Field Programmable
■
Integrated Phase-Locked Loop (PLL)
■
Supply Voltage: 3.3V or 2.5V
■
Pb-free Package: 5.0 x 3.2 mm LCC
■
Commercial and Industrial Temperature Ranges
The CY2XF32 is a high performance and high frequency Crystal
Oscillator (XO). It uses a Cypress proprietary low noise PLL to
synthesize the frequency from an integrated crystal. The output
frequency can be changed via two select pins, allowing easy
frequency margin testing in applications.
The CY2XF32 is available as a factory configured device or as
a field programmable device.
Logic Block Diagram
CRYSTAL
OSCILLATOR
FS1
LOW -NOISE
PLL
OUTPU T
DIVIDER
4
CLK
2
FREQUENCY
SELECT DECODE
FS0
5
OE/PD#
1
Pinouts
Figure 1. Pin Diagram - 6 Pin Ceramic LCC
Cypress Semiconductor Corporation
Document Number: 001-53147 Rev. *B
•
OE/PD# 1
6 VDD
FS1 2
5 FS0
VSS 3
4 CLK
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 18, 2009
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CY2XF32
PRELIMINARY
Table 1. Pin Definitions - 6 Pin Ceramic LCC
Pin
Name
I/O Type
Description
1
OE/PD#
CMOS Input
Output Enable or Power Down: Functionality is a programming option; see Table 3 and
Table 4 for details.
2, 5
FS1, FS0
CMOS Input
Frequency Select.
4
CLK
CMOS Output
Clock Output.
6
VDD
Power
Supply Voltage: 2.5V or 3.3V.
3
VSS
Power
Ground.
Functional Description
Table 4. Power Down Operation
The FS0 and FS1 pins select between four different output
frequencies, as shown in Table 2. Frequency margining is a
common application for this feature. One frequency is used for
the standard operating mode of the device, while the other
frequencies are available for margin testing, either during
product development or in system manufacturing test.
Table 2. Frequency Select
FS1
FS0
Output Frequency
0
0
Frequency 0
0
1
Frequency 1
1
0
Frequency 2
1
1
Frequency 3
PLL & Xtal Oscillator
Output Buffer
0
Off
Off
1
Active
On
Programming Description
The CY2XF32 is a programmable device. Before being used in
an application, it must be programmed with the output
frequencies and other variables described in a later section. Two
different device types are available, each with its own
programming flow. They are described below.
Field Programmable CY2XF32F
When changing the output frequency, the frequency transition is
not guaranteed to be smooth. There can be frequency excursions beyond the start frequency and the new frequency.
Glitches and runt pulses are possible, and time must be allowed
for the PLL to relock.
Pin 1 is programmed to function as either OE (output enable) or
PD# (power down, active low). The OE function is used to enable
or disable the CLK output very quickly, but it does not reduce
core power consumption. The PD# function puts the device into
a low power state, but the wake up takes longer because the PLL
must reacquire lock. Details are shown in Table 3 and Table 4.
Table 3. Output Enable Operation
Field programmable devices are shipped unprogrammed and
must be programmed before being installed on a printed circuit
board (PCB). Customers use CyberClocks™ Online Software to
specify the device configuration and generate a JEDEC
(extension .jed) programming file. Programming of samples and
prototype quantities is available using a Cypress programmer.
Third party vendors manufacture programmers for small to large
volume applications. Cypress’s value added distribution partners
also provide programming services. Field programmable
devices are designated with an “F” in the part number. They are
intended for quick prototyping and inventory reduction. The
CY2XF32 is one time programmable (OTP).
The software is located at www.cyberclocksonline.com.
Factory Configured CY2XF32
OE
PLL & Xtal Oscillator
Output Buffer
0
Active
Off
1
Active
On
Document Number: 001-53147 Rev. *B
PD#
For ready-to-use devices, the CY2XF32 is available with no field
programming required. All requests are submitted to the local
Cypress Field Application Engineer (FAE) or sales representative. After the request is processed, the user receives a new
part number, samples, and data sheet with the programmed
values. This part number is used for additional sample requests
and production orders.
Page 2 of 8
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CY2XF32
PRELIMINARY
Programming Variables
Output Frequencies
The CY2XF32 is programmed with up to four independent output
frequencies, which are then selected using the FS0 and FS1
pins. The device can synthesize frequencies to a resolution of
one part per million (ppm), but the actual accuracy of the output
frequency is limited by the accuracy of the integrated reference
crystal.
Industrial versus Commercial Device Performance
Industrial and commercial devices have different internal
crystals. This has a potentially significant impact on performance
levels for applications requiring the lowest possible phase noise.
CyberClocks Online Software displays expected performance
for both options.
Table 5. Device Programming Variables
Variable
Pin 1: Output Enable or Power Down (OE/PD#)
Output Frequency 0 (Power on default)
Pin 1 is programmed as either Output Enable (OE) or Power
Down (PD#).
Output Frequency 2
Supply Voltage
A programming option optimizes the CY2XF32 for either 2.5V or
3.3V supply voltage. A device programmed for a particular
supply voltage is not guaranteed to meet specifications when
operated at the other voltage.
Document Number: 001-53147 Rev. *B
Output Frequency 1
Output Frequency 3
Pin 1 Functionality (OE or PD#)
Supply Voltage (2.5V or 3.3V)
Temperature Range (Commercial or Industrial)
Page 3 of 8
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CY2XF32
PRELIMINARY
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply Voltage
–0.5
4.4
V
VIN[1]
Input Voltage, DC
Relative to VSS
–0.5
VDD+0.5
V
TS
Temperature, Storage
Non operating
–55
135
°C
TJ
Temperature, Junction
–40
135
°C
ESDHBM
ESD Protection (Human Body Model)
JEDEC STD 22-A114-B
ΘJA[2]
Thermal Resistance, Junction to Ambient
0 m/s airflow
2000
–
V
°C/W
64
Operating Conditions
Parameter
VDD
Min
Typ
Max
Unit
3.3V Supply Voltage Range
Description
3.135
3.3
3.465
V
2.5V Supply Voltage Range
2.375
2.5
2.625
V
TPU
Power Up Time for VDD to Reach Minimum Specified Voltage (Power Ramp
is Monotonic)
0.05
–
500
ms
TA
Ambient Temperature, Commercial
0
–
70
°C
–40
–
85
°C
Load Capacitance at CLK (>100 MHz)
–
–
10
pF
Load Capacitance at CLK (≤100 MHz)
–
–
15
pF
Min
Typ
Max
Unit
–
–
110
mA
–
–
200
μA
0.9*VDD
–
–
V
Ambient Temperature, Industrial
CLOAD
DC Electrical Characteristics
Parameter
Description
IDD
Operating Supply Current
Condition
VDD = 3.465V, OE/PD# = VDD, output
unloaded
ISB
Standby Supply Current
PD# = VSS
VOH
Output High Voltage
VDD = min, IOH = –4 mA
VOL
Output Low Voltage
VDD = max, IOL = 4 mA
IOZ
Output Leakage Current
OE/PD# = VSS
VIH
VIL
–
–
0.1*VDD
V
–35
–
35
μA
Input High Voltage
0.7*VDD
–
–
V
Input Low Voltage
–
–
0.3*VDD
V
IIH0
Input High Current, OE/PD# Pin
Input = VDD
–
–
115
μA
IIH1
Input High Current, FS0 & FS1 Pins Input = VDD
–
–
10
μA
IIL0
Input Low Current, OE/PD# Pin
Input = VSS
–50
–
–
μA
IIL1
Input Low Current, FS0 & FS1 Pin
Input = VSS
–20
–
–
μA
CIN0[3]
CIN1[3]
Input Capacitance, OE/PD# Pin
–
15
–
pF
Input Capacitance, FS0 & FS1 Pin
–
4
–
pF
Notes
1. The voltage on any input or I/O pin cannot exceed the power pin during power up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has four layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3. Not 100% tested, guaranteed by design and characterization.
Document Number: 001-53147 Rev. *B
Page 4 of 8
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CY2XF32
PRELIMINARY
AC Electrical Characteristics[3]
Parameter
Description
Min
Typ
Max
Unit
8
–
200
MHz
TA = 0°C to 70°C
–
–
±35
ppm
TA = –40°C to 85°C
–
–
±55
ppm
–
–
±15
ppm
Output Duty Cycle
Measured at VDD/2; see Figure 2
45
50
55
%
FOUT
Output Frequency[5]
FSC
Frequency Stability, Commercial
Devices[4]
FSI
Frequency Stability, Industrial
Devices[4]
AG
Aging, 10 Years
TDC
Condition
TR
Output Rise Time
20% to 80% of VDD, CLOAD = 15 pF
–
0.7
1.5
ns
TF
Output Fall Time
80% to 20% of VDD, CLOAD = 15 pF
–
0.8
1.5
ns
TOHZ
Output Disable Time
Time from falling edge on OE to stopped
outputs (Asynchronous)
–
–
100
ns
TOE
Output Enable Time
Time from rising edge on OE to outputs at
a valid frequency (Asynchronous)
–
–
100
ns
TLOCK
Startup Time
Time for CLK to reach valid frequency
measured from the time
VDD = VDD(min.) or from PD# rising edge
–
–
5
ms
TLFS
Relock Time
Time for CLK to reach valid frequency from
FS0 or FS1 pin change
–
–
1
ms
Notes
4. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage.
5. This parameter is specified in CyberClocks Online software.
Document Number: 001-53147 Rev. *B
Page 5 of 8
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CY2XF32
PRELIMINARY
Switching Waveforms
Figure 2. Duty Cycle Timing
CLK
TDC =
TPW
TPW
TPERIOD
TPERIOD
Figure 3. Output Rise and Fall Time
80%
CLK
VDD
80%
20%
20%
0V
TF
TR
Figure 4. Output Enable and Disable Timing
OE
V IL
TOH Z
CLK
Document Number: 001-53147 Rev. *B
V IH
TOE
High Impedance
Page 6 of 8
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CY2XF32
PRELIMINARY
Ordering Information
Part Number[6]
Configuration
Package Description
Product Flow
Pb-Free
CY2XF32FLXCT
Field Programmable
6-Pin Ceramic LCC SMD - Tape and Reel
Commercial, 0° to 70°C
CY2XF32FLXIT
Field Programmable
6-Pin Ceramic LCC SMD - Tape and Reel
Industrial, –40° to 85°C
CY2XF32LXCxxxT
Factory Configured
6-Pin Ceramic LCC SMD - Tape and Reel
Commercial, 0° to 70°C
CY2XF32LXIxxxT
Factory Configured
6-Pin Ceramic LCC SMD - Tape and Reel
Industrial, –40° to 85°C
Package Diagram
Figure 5. 6-Pin 3.2x5.0 mm Ceramic LCC
0.50
1.30 Max
2.54 TYP.
SIDE VIEW
0.64 TYP.
TYP.
0.20 R REF.
5
4
0.32 R
INDEX
6
10
7
9
8
TYP.
1.2 TYP.
3
2
0.45 REF.
TOP VIEW
1
0.10 REF.
3.2
TYP.
1.27
5.0
0.10 R REF.
BOTTOM VIEW
Dimensions in mm
General Tolerance: ± 0.15MM
Kyocera dwg ref KD-VA6432-A
001-10044-**
Package Weight ~ 0.12 grams
.
Note
6. “xxx” is a factory assigned code that identifies the programming option.
Document Number: 001-53147 Rev. *B
Page 7 of 8
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PRELIMINARY
CY2XF32
Document History Page
Document Title: CY2XF32 High Performance CMOS Oscillator with Frequency Margining - Pin Control
Document Number: 001-53147
Rev.
ECN No.
Orig. of
Change
Submission
Date
05/13/09
Description of Change
**
2705753
KVM/PYRS
*A
2734005
WWZ
07/09/2009 Post to external web
New data sheet
*B
2764787
KVM
09/19/2009 Change ISB max from 250 μA to 200 μA
Add max limit for TR, TF: 1.5 ns
Change TLOCK max from 10 ms to 5 ms
Change TLFS max from 10 ms to 1 ms
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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53147 Rev. *B
Revised September 18, 2009
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CyberClocks is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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