Holt HI-8430PQI 8-channel, ground /open, or supply / open sensor Datasheet

HI-8430, HI-8431
8-Channel, Ground /Open, or Supply / Open Sensor
4-channel 200 mA Supply / Open Driver
· Airbus ABD0100H compliant
The HI-8431 is a smaller, reduced pin version of the HI8430 and is available in a 32-pin PQFP or 5mm x 5mm
QFN. It has all the features of the HI-8430 except the
individual fault detection outputs, tri-state pin selection and
fixed internal thresholds.
Interface to the digital subsystem is simple CMOS logic
inputs and outputs. The logic pins are compatible with 5V
or 3.3V logic allowing direct connection to a wide range of
microcontrollers or FPGAs.
FEATURES
· Robust CMOS Silicon-on-Insulator (SOI) technology
· Selectable Thresholds and Hysteresis
· Sense Detection Range 3V to 20V
· Logic Operation from 3.0V to 5.5V
· Lightning Protected Sense Inputs
(DS8430 Rev. C)
· Max Power Dissipation Automatically Limited by Fault
Protection
· Diode Clamps for Discharging Inductive Loads
APPLICATIONS
· Avionics Discrete to Digital Sensing
· Relay Driver
· Lamp driver
· Discrete Signaling
PIN CONFIGURATIONS
VWET - 1
SENSE0 - 2
SENSE1 - 3
SENSE2 - 4
SENSE3 - 5
SENSE4 - 6
SENSE5 - 7
SENSE6 - 8
SENSE7 - 9
OE - 10
HI-8430PCI
HI-8430PCT
30 29 - FAULT_0
28 - DRV_0
27 - DRV_1
26 - FAULT_1
25 - VDRV
24 - FAULT_2
23 - DRV_2
22 - DRV_3
21 - FAULT_3
40 Pin Plastic 6mm x 6mm
Chip-scale package
SENSE0 - 1
SENSE1 - 2
SENSE2 - 3
SENSE3 - 4
SENSE4 - 5
SENSE5 - 6
SENSE6 - 7
SENSE7 - 8
HI-8431PCI
HI-8431PCT
24 - DSEL_3
23 - DRV0
22 - DRV1
21 - VDRV
20 - DRV_2
19 - DRV_3
18 - FAULT_OR
17 - GND
SO_0
SO_1
SO_2
SO_3
SO_4
SO_5
SO_6
SO_7
· 8-channel Selectable Sense Operation, GND/Open
or Supply/Open
· Over-Current Fault Detection Signaled by Logic Output
40 - VLOGIC
39 - THS_SEL
38 - HI_SET
37 - LO_SET
36 - SNSE_SEL
35 - FAULT_OR
34 - DSEL_0
33 - DSEL_1
32 - DSEL_2
31 - DSEL_3
The HI-8430 also offers four high side switches each
capable of sourcing 200 mA of current. Each switch
transistor is controlled by its own digital input pin and is fully
fault protected. Over-current conditions, such as a short
circuit, are detected and inhibited while signaling the fault
condition at the corresponding logic output. These four
FAULT outputs are also available in a combined OR output.
The outputs are fully protected from transients when
driving relays.
· 4.5 Ohm On Resistance VLOGIC Inputs Control 5V to
28V High Side Drivers
SO_0 - 11
SO_1 - 12
SO_2 - 13
SO_3 - 14
SO_4 - 15
SO_5 - 16
SO_6 - 17
SO_7 - 18
GND - 19
- 20
All sense inputs are internally lightning protected to
DO160G, Section 22, Cat AZ, BZ and ZZ without external
components.
· 4 High-Side 200 mA Drivers
32 - VWET
31 - VLOGIC
30 - HI_SET
29 - LO_SET
28 - SNSE_SEL
27 - DSEL_0
26 - DSEL_1
25 - DSEL_2
The HI-8430 is a combined 8-channel discrete-to-digital
sensor and quad high side driver fabricated with Siliconon-Insulator (SOI) technology for robust latch-up free
operation. Sense detection can either be GND/Open or
Supply/Open as configured by the SNSE_SEL pin.
Supply/Open sensing is also referred to as 28V/Open
sensing. The sensing circuit window comparator
thresholds can be fixed at the internal programmed values
or can be set externally at the HI_SET and LO_SET pins,
as selected by the THS_SEL pin. The digital SENSE
outputs can be tri-stated by taking the OE pin high.
9
10
11
12
13
14
15
16
GENERAL DESCRIPTION
-
August 2013
32 Pin Plastic 5mm x 5mm
Chip-scale package
(See page 14 for leaded QFP package options)
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/13
HI-8430, HI-8431
BLOCK DIAGRAM
VLOGIC
VWET
VLOGIC
THS_SEL
VREF_HI
VOLTAGE
REFERENCE
VREF_LO
VTHI/10
SNSE_SEL
VTLO/10
HI_SET
LO_SET
VWET
VLOGIC
SNSE_SEL
+
23.8K
SENSE_0
SENSE_1
SENSE_2
SENSE_3
SENSE_4
SENSE_5
SENSE_6
SENSE_7
-
3.3K
LIGHTNING
PROTECTION
29K
+
-
360K
SNSE_SEL
40K
SO_0
SO_1
SO_2
SO_3
SO_4
SO_5
SO_6
SO_7
OE
VDRV
Current
Sense
DSEL_0
DSEL_1
DSEL_2
DSEL_3
Drive
Control
DRV_0
DRV_1
DRV_2
DRV_3
FAULT_0
FAULT_1
FAULT_2
FAULT_3
FAULT_OR
GND
Figure 2
HOLT INTEGRATED CIRCUITS
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HI-8430, HI-8431
PIN DESCRIPTIONS
SYMBOL
FUNCTION
DESCRIPTION
Optional input to supply relay wetting current to sense lines in GND/Open operation
VWET
Supply
SENSE_0
Discrete Input
Discrete input 0. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
50KΩ To GND
SENSE_1
Discrete Input
Discrete input 1. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
SENSE_2
Discrete Input
Discrete input 2. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
SENSE_3
Discrete Input
Discrete input 3. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
SENSE_4
Discrete Input
Discrete input 4. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
SENSE_5
Discrete Input
Discrete input 5. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
SENSE_6
Discrete Input
Discrete input 6. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
SENSE_7
Discrete Input
Discrete input 7. If SNSE_SEL = 0 pin senses GND/Open. If SNSE_SEL = 1, senses SUPPLY/Open
OE
Digital Input
If High, SO_n outputs are high-impedance. OE has internal 30KΩ pull-down resistor
SO_0
Digital output
High if SNSE_SEL=0 and SENSE_0 < VLO, or Low if SNSE_SEL=1 and SENSE_0 > VHI
SO_1
Digital output
High if SNSE_SEL=0 and SENSE_1 < VLO, or Low if SNSE_SEL=1 and SENSE_1 > VHI
SO_2
Digital output
High if SNSE_SEL=0 and SENSE_2 < VLO, or Low if SNSE_SEL=1 and SENSE_2 > VHI
SO_3
Digital output
High if SNSE_SEL=0 and SENSE_3 < VLO, or Low if SNSE_SEL=1 and SENSE_3 > VHI
SO_4
Digital output
High if SNSE_SEL=0 and SENSE_4 < VLO, or Low if SNSE_SEL=1 and SENSE_4 > VHI
SO_5
Digital output
High if SNSE_SEL=0 and SENSE_5 < VLO, or Low if SNSE_SEL=1 and SENSE_5 > VHI
SO_6
Digital output
High if SNSE_SEL=0 and SENSE_6 < VLO, or Low if SNSE_SEL=1 and SENSE_6 > VHI
SO_7
GND
Digital output
Supply
High if SNSE_SEL=0 and SENSE_7 < VLO, or Low if SNSE_SEL=1 and SENSE_7 > VHI
Reference, 0V
FAULT_3
Digital output
High if Driver 3 is attempting to source excess current
DRV_3
Switch Output
VDRV
Supply
DRV_2
Switch Output
Drain node of high switch driver 2
FAULT_2
Digital output
High if Driver 2 is attempting to source excess current
FAULT_1
Digital output
High if Driver 1 is attempting to source excess current
DRV_1
Switch Output
Drain node of high switch driver 1
Drain node of high switch driver 3
Supply for DRV_0-3. The VDRV pin and the isolated backside pad should be connected for optimum
performance and power dissipation.
DRV_0
Switch Output
Drain node of high switch driver 0
FAULT_0
Digital output
High if Driver 0 is attempting to source excess current
DSEL_3
Digital Input
When high, turns on Driver 3. DSEL_3 has an internal 30KΩ pull-down resistor
DSEL_2
Digital Input
When high, turns on Driver 2. DSEL_2 has an internal 30KΩ pull-down resistor
DSEL_1
Digital Input
When high, turns on Driver 1. DSEL_1 has an internal 30KΩ pull-down resistor
DSEL_0
Digital Input
When high, turns on Driver 0. DSEL_0 has an internal 30KΩ pull-down resistor
FAULT_OR Digital Output
High if any Driver is attempting to source excess current
SNSE_SEL
Digital Input
If Low, SENSE pins are sensing Open/Gnd. If High, SENSE pins are sensing SUPPLY/Open
LO_SET
Analog input
If THS_SEL is High, this pin sets the lower window comparator threshold
HI_SET
Analog input
If THS_SEL is High, this pin sets the upper window comparator threshold
THS_SEL
Digital Input
If THS_SEL is Low, comparator thresholds are set internally. THS_SEL has an internal 30KΩ pull-up
VLOGIC
Supply
Logic supply. (3.0V - 5.5V)
HOLT INTEGRATED CIRCUITS
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HI-8430, HI-8431
FUNCTIONAL DESCRIPTION
SENSING
WETTING CURRENT
The 8 Sense Channels can be configured to meet the
requirements of a variety of conditions and applications.
Table 1 summarizes basic function selection and Table 2
gives more details on possible threshold values.
For GND/Open applications with VWET open, the wetting
current with the input voltage at GND is simply (VLOGIC 0.75)/3.3K. When applying a voltage at the VWET pin the
wetting current is (VLOGIC - 0.75)/3.3K + (VWET 4.2)/127K. Additional wetting current can be achieved by
placing an external resistor and a diode between VWET
and the individual sense inputs.
GND/OPEN SENSING
For GND/Open sensing, the SNS_SEL pin is connected to
GND. Referring to the Block Diagram, Figure 2, this selection
will connect a 3.3KΩ pull-up resistor through a diode to
VLOGIC and a 23.8KΩ resistor through 3 diodes to VWET.
These resistors give extra noise immunity for detecting the
open state while providing relay wetting current. Configuring
THS_SEL, HI_SET/LO_SET and VWET as described below
sets the window comparator thresholds, VTHI and VTLO, the
input voltage when open, and the input current.
HI-8430 (40 pin version) - THRESHOLD SELECT
The HI-8430 offers a choice between internally fixed
thresholds or external thresholds provided by the user.
With THS_SEL set to GND, the window comparator
thresholds are fixed based on an internal reference. The high
threshold, VTHI, and the low threshold, VTLO levels may be
found in Table 2. When the internal references are used the
HI_SET and LO_SET pins should be connected to GND.
For applications with either large GND offsets or thresholds
higher than VLOGIC - 0.75V, THS_SEL is set high and the
thresholds are set externally, for example by a simple
resistor divider off the VLOGIC supply. In this case VTHI is
equal to 10X the voltage on the HI_SET pin. VTLO is equal to
10X the voltage on the LO_SET pin. This mode allows the
user complete flexibility to define the thresholds and
hysteresis levels.
HI-8431 (32 pin version) THRESHOLD SELECT
For applications that can take advantage of the very small 32
pin chip scale package of the HI-8431, THS_SEL is not
available and an internal pull-up makes it mandatory to
supply HI_SET and LO_SET externally.
SUPPLY/OPEN SENSING
The 8 Sense Channels can be configured to sense
Supply/Open by connecting the SNSE_SEL pin to
VLOGIC. Refering to Figure 2, a 32KΩ resistor is switched
in series to provide a pull down in addition to the 400KΩ of
the comparator input divider to GND. Similar to the
GND/Open case configuring THS_SEL, HI_SET/LO_SET
and VWET as described below sets the window comparator thresholds, the open input voltage when open and the
wetting current.
THRESHOLD SELECT
The threshold selections are handled in the same way as
stated above for the GND/OPEN case.
For THS_SEL set low, the internal reference nominally
sets the window comparator. See table 2 for the VTHI and
VTLO threshold levels.
For THS_SEL set high, the final thresholds are 10X the
voltage set on the HI_SET and LO_SET pins. The VWET
pin must be left open in the Supply/Open sensing case.
WETTING CURRENT
For the Supply/Open case the wetting current into the
sense input is the current sunk by the effective 28KΩ to
GND. For VSENSE_n = 28V, IWET is 1ma. See Figure 12.
Table 1. Function Table
SENSE_n
SNSE_SEL
OE
SO_n
OPEN INPUT VOLTAGE
For correct operation, the VSENSE_n when open, must be
higher than VTHI so SO_n will be low.
NOTE 1: In the case of 3.3V VLOGIC operation, VWET must
be connected to a supply greater than (1.3 x VTHI + 2.25V)
to fulfill the above condition. In the case of 5V operation, the
above condition may be satisfied with VWET left open (see
table 2). In this case, the input floats to VSENSE_n = VLOGIC 0.75V.
NOTE 2: Various ARINC standards such as ARINC 763
define the standard “Open” signal as characterized by a
resistance of 100KΩ or more with respect to signal common.
The user should consider this 100KΩ to ground case when
setting the thresholds.
Open or > VTHI
L
(GND/OPEN)
L
L
< VTLO
L
(GND/OPEN)
L
H
X
L
(GND/OPEN)
H
Z
Open or < VTLO
H
(V+/OPEN)
L
H
> VTHI
H
(V+/OPEN)
L
L
X
H
(V+/OPEN)
H
Z
H = VLOGIC, L = GND, Z = Hi-Z, X = Don’t Care, V+ = VSUPPLY
See Table 2 for values of VTHI/VTLO
HOLT INTEGRATED CIRCUITS
4
HI-8430, HI-8431
FUNCTIONAL DESCRIPTION
Table 2. Configuration options and allowed threshold values -55C to 125C.
Operation
Threshold
Selected
Maximum
HI_SET
(VTHI =
HI_SETx10)
Minimum
LO_SET
(VTLO =
LO_SETx10)
Guaranteed
High
Threshold
Guaranteed
Low
Threshold
L
GND/OPEN
Internal
-
-
3.0V
1.0V
L
L
GND/OPEN
Internal
-
-
3.25V
1.0V
28V
L
L
GND/OPEN
Internal
-
-
3.0V
1.0V
3.0V to 3.6V
8V
L
H
GND/OPEN
External
0.4V (4.0V)
0.3V (3.0V)
VTHI + 25%
VTLO - 25%
3.0V to 3.6V
28V
L
H
GND/OPEN
External
2.0V (20V)
0.3V (3.0V)
VTHI + 25%
VTLO - 25%
3.0V to 3.6V
OPEN
H
L
V+/OPEN
Internal
-
-
18.0V
9.0V
3.0V to 3.6V
OPEN
H
H
V+/OPEN
Exernal
2.2V (22V)
0.3V (3.0V)
VTHI + 25%
VTLO - 25%
4.5V
OPEN
L
L
GND/OPEN
Internal
-
-
3.5V
1.0V
5.5V
OPEN
L
L
GND/OPEN
Internal
-
-
4.0V
1.0V
5.0V
28V
L
L
GND/OPEN
Internal
-
-
4.0V
1.0V
4.5V to 5.5V
7V
L
H
GND/OPEN
External
0.4V (4.0V)
0.3V (3.0V)
VTHI + 25%
VTLO - 25%
4.5V to 5.5V
28V
L
H
GND/OPEN
External
2.0V (20V)
0.3V (3.0V)
VTHI + 25%
VTLO - 25%
4.5V to 5.5V
OPEN
H
L
V+/OPEN
Internal
-
-
18.0V
9.0V
4.5V to 5.5V
OPEN
H
H
V+/OPEN
External
2.2V (22V)
0.3V (3.0V)
VTHI + 25%
VTLO - 25%
SNSE_ THS_
SEL
SEL
VLOGIC
VWET
Pin
3.0V
8V
L
3.6V
8V
3.3V
NOTE: VTHI = Sense pin high threshold (HI_SET x 10), VTLO = Sense pin low threshold (LO_SET x 10)
OUTPUT ENABLE
OVER-CURRENT SHUTDOWN
The output enable pin, OE, available on the HI-8430, tristates all Sense Outputs and High Side Driver Fault Outputs
to allow connecting the tri-state outputs in parallel with other
tri-stated chips. The OE pin has a pull-down and when left
open will cause these digital outputs to be driven to their logic
levels. If the OE pin is High, these digital outputs are high
impedance.
Maximum DC power dissipation per driver is
approximately 0.5W at room temperature. Conditions that
would cause the power to exceed this amount will result in
a shut down of the driver. Over-current shutdown is
initiated when the driver pin voltage is more than
approximately 1.5V from the VDRV rail. However there is a
delay of approximately 11μsec before the shutdown
actually occurs giving the driver an opportunity to charge
capacitive loads and thereby avoid shutdown. Similarly, if
the driver is on and a high load is suddenly switched on,
the over-current shutdown will be delayed in activation.
Note that even when the over-current fault condition is
present, the driver pin is still sourcing a few milliamps. This
low current condition continues until the input is taken low
or the load is removed.
OUTPUT DRIVERS
HIGH SIDE DRIVERS
Both product versions offer four High Side Drivers. Each
driver (PMOS switch) is capable of sourcing a minimum of
200mA while exhibiting a Ron of 4.5Ω typical. VDRV, the high
side rail, may range from 5V to 28V independent of VLOGIC,
which may range from 3V to 5.5V. Each output has diode
clamps for protection during inductive kick-back for relay
applications. Off-state leakage is typically less than 10nA at
room temperature. The inputs, DSEL0 through DSEL3, have
internal pull-downs which hold off the drivers until logic highs
are presented.
FAULT CONDITIONS
Each driver has a converter that translates an over-current
detection into a logic high output at its FAULT output. The
FAULT_OR output goes high if one or more FAULT outputs
are high. These outputs can be tri-stated by setting OE
high.
HOLT INTEGRATED CIRCUITS
5
HI-8430, HI-8431
FUNCTIONAL DESCRIPTION
LIGHTNING PROTECTION
All SENSE_n inputs are protected to RTCA/DO-160G, Section 22, Categories AZ and BZ, Waveforms 3, 4, 5A, with no external
components. In addition, all inputs are also protected to ZZ, Waveforms 3 and 5B, to provide more robustness in composite
airframe applications. Table 3 and Figure 3 give values and waveforms.
Waveforms
3/3
4/1
5A/5A
5B/5B
Voc (V) / Isc (A)
Voc (V) / Isc (A)
Voc (V) / Isc (A)
Voc (V) / Isc (A)
2
250/10
125/25
125/125
125/125
Z
500/20
300/60
300/300
300/300
3
600/24
300/60
300/300
300/300
Level
Table 3. Waveform Peak Amplitudes
Voltage/Current Waveform 3
V/I (%)
Peak
1.0
V (%)
50%
0.5
0.8
0.0
0.5
-0.5
0.3
-1.0
I/V (%)
1.0
t
Peak
1us/div.
Current/Voltage Waveform 5A
0.0
50%
T1
I/V (%)
1.0
Peak
t
T2
T1 = 6.4µs +/-20%
T2 = 69µs +/-20%
Current/Voltage Waveform 5B
0.8
0.8
50%
0.5
50%
0.5
0.3
0.0
Voltage Waveform 4
Peak
1.0
0.3
T1
t
T2
T1 = 40µs +/-20%
T2 = 120µs +/-20%
0.0
T1
Figure 3. Lightning Waveforms
HOLT INTEGRATED CIRCUITS
6
t
T2
T1 = 50µs +/-20%
T2 = 500µs +/-20%
HI-8430, HI-8431
APPLICATION EXAMPLES
VWET
Open
VLOGIC
VLOGIC = 5.0V
HI_SET
For GND/Open SNSE_SEL = GND
Low to High Threshold = 4.0V
High to Low Threshold = 1.0V
LO_SET
GND
SNSE_SEL
For 28V/Open SNSE_SEL = VLOGIC
Low to High Threshold = 18.0V
High to Low Threshold = 9.0V
GND
SENSE0
SENSE1
SENSE2
SENSE3
SENSE4
SENSE5
SENSE6
SENSE7
From SENSORS
THS_SEL
HI-8430
SO_0
SO_1
SO_2
SO_3
SO_4
SO_5
SO_6
SO_7
OE
Figure 4 Input Sensing with Internal Thresholds
VWET
VLOGIC
OPEN
VLOGIC = 3.3V
10μF
10V
0.1μF
10V
68K
HI_SET = 1.12V
GND
15K
3.3μF
10V
LO_SET = 0.64V
Low to High Threshold = 11.2V
High to Low Threshold = 6.4V
LO_SET
20K
GND
VLOGIC = 3.3V
VLOGIC = 3.3V
From SENSORS
HI_SET
SENSE0
SENSE1
SENSE2
SENSE3
SENSE4
SENSE5
SENSE6
SENSE7
3.3μF
10V
SNSE_SEL
THS_SEL
HI-8430
OE
Figure 5 Input Sensing, 28V/OPEN, Typical ABD0100H Thresholds
HOLT INTEGRATED CIRCUITS
7
SO_0
SO_1
SO_2
SO_3
SO_4
SO_5
SO_6
SO_7
HI-8430, HI-8431
APPLICATION EXAMPLES
VWET
VLOGIC
28V
VLOGIC = 3.3V
10μF
10V
0.1μF
10V
75K
HI_SET = 0.97V
GND
HI_SET
3.3μF
10V
13K
LO_SET = 0.56V
LO_SET
18K
Low to High Threshold = 9.7V
High to Low Threshold = 5.6V
3.3μF
10V
GND
GND
VLOGIC = 3.3V
From SENSORS
SNSE_SEL
THS_SEL
SENSE0
SENSE1
SENSE2
SENSE3
SENSE4
SENSE5
SENSE6
SENSE7
SO_0
SO_1
SO_2
SO_3
SO_4
SO_5
SO_6
SO_7
HI-8430
OE
Figure 6 Input Sensing, GND/OPEN Typical ABD0100H Thresholds, 1ma wetting current
V+
V+
FAULT_n
Current
Sense
DSEL_n
FAULT_n
Current
Sense
VDRV
DSEL_n
Drive
Control
VDRV
Drive
Control
DRV_n
DRV_n
HI-8430
HI-8430
Figure 7 Highside Output Driving Relay
Figure 8 Highside Output Driving LED
V+
V+
FAULT_n
Current
Sense
DSEL_n
FAULT_n
Current
Sense
VDRV
DSEL_n
Drive
Control
VDRV
Drive
Control
DRV_n
DRV_n
HI-8430
HI-8430
Figure 9 Highside Output Driving Lamp
Figure 10 Highside Output Driving Resistive Load
HOLT INTEGRATED CIRCUITS
8
HI-8430, HI-8431
APPLICATION EXAMPLES
V+
FAULT_n
Current
Sense
DSEL_n
VDRV
SENSE_n
Drive
Control
SENSE_n
SENSE_n
DRV_n
HI-8430
HI-8425
HI-8430
Figure 11 Highside Output Used for Discrete Signaling with three separate users
Figure 12 Input Current Vs. Input Voltage
HOLT INTEGRATED CIRCUITS
9
HI-8425
HI-8430, HI-8431
RECOMMENDED
OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to Ground
Supply Voltage (VLOGIC)
.........................
-0.3V to +7V
VDRV
.........................
50V
VWET
.........................
-0.3V to +50V
DC Driver Current per pin
.........................
Logic Input Voltage Range
................ -0.3V to VLOGIC+0.3V
Discrete Input Voltage Range
Supply Voltage
VLOGIC
VDRV
VWET
Operating Temperature Range
Industrial Screening ............. -40°C to +85°C
Hi-Temp Screening ............. -55°C to +125°C
300mA
..................
................................. 3.0V to 5.5V
................................ 7.0V to 36V
.................................. 8.0V to 36V
-80V to +80V
Continuous Power Dissipation (TA=+70°C)
QFN (derate 21.3mW/°C above +70°C) ........
QFP (derate 10.0mW/°C above +70°C) ........
1.7W
1.5W
Solder Temperature (reflow)
260°C
...........................
Junction Temperature
.............................
175°C
Storage Temperature
............................
-65°C to -150°C
NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to
the device. These are stress ratings only. Operation at the limits is not recommended.
D.C. ELECTRICAL CHARACTERISTICS
VDD = 3.3V or 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
DISCRETE INPUTS
SENSE V+/OPEN
Resistance to Ground
SEN_SEL = High, VWET open
RIN
Case 1: THS_SEL = GND
Internal Threshold Mode
Open State Input Voltage
VOS
Input voltage to give High output
V+ State Input Voltage
VV+
Input voltage to give Low output
Input Current at 28V
IIN28
VIN = 28V
Hysteresis
KΩ
30
VHY
Case 2: THS_SEL = Open or VLOGIC
9.0
18.0
V
V
0.95
mA
1.5
V
HI_SET/LO_SET pin set Thresholds
HI_SET Threshold Range
VHR
HI Threshold is set to HI_SET X 10
0.4
2.2
V
LO_SET Threshold Range
VLR
LO Threshold is set to LO_SET X 10
0.3
2.1
V
HI_SET > LO_SET
0.1
Min Threshold Window
10:1 Division Accuracy
VTHW
As measured by Sense Output Change
HOLT INTEGRATED CIRCUITS
10
VLR - 25%
V
VHR + 25%
V
HI-8430, HI-8431
D.C. ELECTRICAL CHARACTERISTICS (cont)
VDD = 3.3V or 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
DISCRETE INPUTS
SENSE GND/OPEN
Resistance in series with diode to VLOGIC
RIN
3.3
KΩ
Resistance in series with diode to VWET
RW
23.8
KΩ
Case 1: THS_SEL = GND
Internal Threshold Mode
Ground State Input Voltage
VGS
Input voltage to give High output
Open State Input Voltage
VOS
Input voltage to give Low output
VDD = 5.5V
VDD = 3.0V
Input Current at 0V
IIN28
Hysteresis
VHY
1.0
4.0
3.0
V
-0.65
-1.65
VIN = 0V, VDD = 3.0V
VIN = 0V, VDD = 5.5V
V
mA
mA
0.15
V
HI_SET/LO_SET pins set Thresholds
Case 2: THS_SEL = Open or VLOGIC
HI_SET Threshold Range
VHR
HI Threshold is set to HI_SET X 10
0.4
2.0
V
LO_SET Threshold Range
VLR
LO Threshod is set to LO_SET X 10
0.3
1.9
V
HI_SET > LO_SET
0.1
Min Threshold Window
VTHW
10:1 Division Accuracy
As measured by Sense Output Change
V
VHR + 25%
VLR - 25%
V
LOGIC INPUTS
Input Voltage
Input Current, OE, DSEL_n
VIH
Input Voltage HI
VIL
Input Votage LO
ISINK
ISOURCE
Input Current, THS_SEL
ISINK
ISOURCE
Input Current, SNSE_SEL
ISINK
ISOURCE
80%
VLOGIC
20%
VIN = VLOGIC, 30KΩ pull down
125
VIN = VLOGIC
μA
0.1
VIN = GND
0.1
VIN = GND , 30KΩ pull up
VLOGIC
μA
μA
125
μA
VIN = VLOGIC
0.1
μA
VIN = GND,
0.1
μA
HOLT INTEGRATED CIRCUITS
11
HI-8430, HI-8431
D.C. ELECTRICAL CHARACTERISTICS (cont)
VDD = 3.3V or 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LOGIC OUTPUTS
Output Voltage
Output Current
VOH
IOH = -100μA
VOL
IOL = 100μA
IOL
VOUT= 0.4V
IOH
VOUT = VLOGIC - 0.4V
Tri-State Leakage Current
ITSL
Output Capacitance
CO
PARAMETER
SYMBOL
90%
VLOGIC
10%
1.6
VLOGIC > Vout > GND
mA
-1.0
-1.0
mA
1.0
μA
15
CONDITION
MIN
VLOGIC
TYP
pF
MAX
UNITS
1.0
μA
8
Ω
ANALOG INPUTS
HI_SET/LO_SET Leakage Current
IL
Max leakage for VLOGIC > Vinput > GND
-0.1
HIGH SIDE DRIVERS
On Resistance
Over Current Threshold
Over Current Delay
RON
VDSMAX
TOC
ISOURCE = 200mA See Figure 16
Maximum VDS before current limiting.
VDRV = 28V See Figure 17
Period that Driver sinks max current.
VDRV = 28V See Figure 17
4.5
1.5
5
V
11
μs
SUPPLY
VLOGIC
3.0
5.5
V
Operating VDRV range
VDRV
0
28
V
Operation VWET range
VWET
0
28
V
Operating VLOGIC range
VLOGIC Current
IDD1
All Sense Pins Open
10
mA
VDRV Current
IVDRV
All Drivers off, VDRV = 28V
3
mA
VWET Current
IVWET
All Sense Inputs = 0V, VWET = 28V
20
mA
HOLT INTEGRATED CIRCUITS
12
HI-8430, HI-8431
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V or 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
SENSE V+/OPEN
Delay, Output going High
tH1
See Figure 13, THS_SEL = GND, 25°C
1.0
μs
Delay, Output going Low
tL1
See Figure 13, THS_SEL = GND, 25°C
1.0
μs
Delay, Output going High
tH2
See Figure 14, THS_SEL = GND, 25°C
1.0
μs
Delay, Output going Low
tL2
See Figure 14, THS_SEL = GND, 25°C
1.0
μs
Tri-state Delay, On
tTSON
See Figure 15, THS_SEL = GND, 25°C
40
ns
Tri-state Delay, Off
tTSOFF
See Figure 15, THS_SEL = GND, 25°C
40
ns
SENSE GND/OPEN
TRI-STATE DELAY
HIGH SIDE DRIVERS
Turn On Delay, DSEL_N
tSON
See Figure 16, VLOGIC = 3.3V, 25°C
Turn Off Delay, DSEL_N
tSOFF
See Figure 16, VLOGIC = 3.3V, 25°C
900
ns
Fault Output Delay, On
tFON
See Figure 17, VLOGIC = 3.3V, 25°C
15
μs
Fault Output Delay, Off
tFOFF
See Figure 17, VLOGIC = 3.3V, 25°C
15
μs
HOLT INTEGRATED CIRCUITS
13
400
ns
HI-8430, HI-8431
TEST CIRCUIT AND TIMING DIAGRAMS
28V
SENSE_n
tR = tF = 1μs
12V
SENSE_n
GND
SO_n
tH1
tL1
15pf
3.3V
HI-8430
SO_n
Figure 13 28V/Open Output Delay
VLOGIC
SO_n
5K
15pf
SO_n
5K
2.5V
SENSE_n
3.3V
OE
1.8V
tR = tF = 1μs
50%
tR = tF = 10ns
GND
tH2
tTSON
tL2
90%
SO_n
SO_n
Figure 14 GND/Open Output Delay
Figure 15 Sense Enable Output Delay
DRV_n
100pf
134Ω
3.3V
DSEL_n
tR = tF = 10ns
Short to GND
DSEL_n
3.3V
tR = tF = 10ns
50%
tTSON
90%
1.65V
10%
VDRV = 28V
DRV_n
50%
90%
28V
tFON
DRV_n
tTSOFF
3.3V
3.3V
tTSOFF
FAULT_n
Figure 16 High Side Driver Output Delay
3.3V
tFOFF
50%
Figure 17 High Side Driver Short Circuit Fault Delay
HOLT INTEGRATED CIRCUITS
14
HI-8430, HI-8431
ORDERING INFORMATION
HI - 843xxx x x
LEAD
FINISH
PART
NUMBER
Blank
Tin / Lead (Sn /Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
F
TEMPERATURE
RANGE
PART
NUMBER
FLOW
BURN
IN
I
-40°C TO +85°C
I
NO
T
-55°C TO +125°C
T
NO
PART
NUMBER
PACKAGE
DESCRIPTION
40 PIN PLASTIC CHIP SCALE (40PCS)
8430PQ
44 PIN PLASTIC QUAD FLAT PACK (44PMQS)
8431PC
32 PIN PLASTIC CHIP SCALE (32PCS)
8431PQ
32 PIN PLASTIC QUAD FLAT PACK (32PQS)
32
31
30
29
28
27
26
25
44
43
42
41
40
39
38
37
36
35
34
- VWET
- VLOGIC
- HI_SET
- LO_SET
- SNSE_SEL
- DSEL_0
- DSEL_1
- DSEL_2
- N/C
- VLOGIC
- THS_SEL
- HI_SET
- LO_SET
- SNSE_SEL
- FAULT_OR
- DSEL_0
- DSEL_1
- DSEL_2
- DSEL_3
8430PC
-1
-2
-3
-4
-5
-6
-7
-8
HI-8431PQI
HI-8431PQT
24 - DSEL_3
23 - DRV0
22 - DRV1
21 - VDRV
20 - DRV_2
19 - DRV_3
18 - FAULT_OR
17 - GND
N/C - 1
VWET - 2
SENSE0 - 3
SENSE1 - 4
SENSE2 - 5
SENSE3 - 6
SENSE4 - 7
SENSE5 - 8
SENSE6 - 9
SENSE7-10
N/C -11
HI-8430PQI
HI-8430PQT
33 - NC
32 - FAULT_0
31 - DRV_0
30 - DRV_1
29 - FAULT_1
28 - VDRV
27 - FAULT_2
26 - DRV_2
25 - DRV_3
24 - FAULT_3
23 - N/C
OE - 12
SO_0 - 13
SO_1 - 14
SO_2 - 15
SO_3 - 16
SO_4 - 17
SO_5 - 18
SO_6 - 19
SO_7 - 20
GND - 21
N/C - 22
SO_0 - 9
SO_1 - 10
SO_2 - 11
SO_3 - 12
SO_4 - 13
SO_5 - 14
SO_6 - 15
SO_7 - 16
SENSE0
SENSE1
SENSE2
SENSE3
SENSE4
SENSE5
SENSE6
SENSE7
32 - Pin Plastic Quad Flat Pack (PTQFP)
7mm x 7mm body
44 - Pin Plastic Quad Flat Pack (PQFP)
10mm x 10mm body
HOLT INTEGRATED CIRCUITS
15
HI-8430, HI-8431
REVISION HISTORY
P/N
Rev
DS8430 New
A
Date
10/4/12
06/6/13
B
6/12/13
C
08/20/13
Description of Change
Initial Release
Correct schematic for sense inputs. Correct reference to pull-up resistor on inputs from 3.5K
to 3.3K.
Update VWET estimation formulas.
Clarify function of OE pin (tri-states all sense outputs).
Update Figure 12 Input Current vs. Input Voltage charts.
Delete Sensing Application Table. Add more detailed Table 2 instead. Update limits.
Correct threshold ranges in DC Electrical Characteristics Table.
Update QFN-40 and QFN-32 package drawings.
Clarified VWET open status for 5V VLOGIC operation. Corrected numerous typos.
Corrected waveform 5B chart.
Updated Discrete Input Voltage Range from +/-60V to +/-80V.
HOLT INTEGRATED CIRCUITS
16
HI-8430, HI-8431
PACKAGE DIMENSIONS
millimeters
40-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
6.00 ± .10
Electrically isolated pad on
bottom of package. Connect
to any ground or power plane
for optimum thermal
dissipation.
Package Type: 40PCS
4.1 ± .05
0.50 BSC
6.00 ± .10
4.1 ± .05
0.25 typ.
0.40 ± .05
See Detail A
0.90 ± .10
0.2 typ
0.90 ± .10
0.02 typ.
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
Detail A
millimeters (inches)
32-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
5.00 ± .05
(0.197 ± .002)
Electrically isolated pad on
bottom of package. Connect
to any ground or power plane
for optimum thermal
dissipation.
Package Type: 32PCS
3.40 ± .05
(0.134 ± .002)
.50
BSC
(.020)
5.00 ± .05
(.197 ± .002)
3.40 ± .05
(0.134 ± .002)
.25 typ.
(.01 typ.)
.40 ± .05
(.016 ± .002)
.90 ± .10
(.035 ± .004)
See Detail A
.90 ± .10
(.035 ± .004)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
Detail A
HOLT INTEGRATED CIRCUITS
17
.02 typ.
(.001 typ.)
HI-8430, HI-8431
PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC QUAD FLAT PACK (PQFP)
Package Type:
44PMQS
.009 MAX.
(.23)
.0315
BSC
(.80)
.394 ± .004
(10.0 ± .10)
SQ.
.520 ± .010
(13.20 ± .25)
SQ.
.014 ± .003
(.37 ± .08)
.035 ± .006
(.88 ± .15)
.012
R MAX.
(.30)
See Detail A
.079 ± .008
(2.0 ± .20)
.096
MAX.
(2.45)
0° £ Q £ 7°
.005
R MIN. Detail A
(.13)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
inches (millimeters)
32 PIN PLASTIC QUAD FLAT PACK (PQFP)
Package Type: 32PQS
.0057 ± .002
(0.145 ± .06)
.354 BSC SQ
(9.00)
.0315
BSC
(0.80)
.276 BSC SQ
(7.00)
.015 ± .003
(0.375 ± .075)
.024 ± .006
(0.60 ± .15)
.039 ± .002
(1.0 ± .05)
.006 ± .002
(0.14 ± .06) R
See Detail A
0° £ Q £ 7°
.047
max
(1.20)
.004 ± .002
(0.10 ± .05)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
18
.003
R min
(.08)
Detail A
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