IRF IRS2104PBF Half-bridge driver Datasheet

Data Sheet No.PD60267
IRS2104(S)PbF
HALF-BRIDGE DRIVER
Features
• Floating channel designed for bootstrap operation
• Fully operational to +600 V
• Tolerant to negative transient voltage, dV/dt
immune
• Gate drive supply range from 10 V to 20 V
• Undervoltage lockout
• 3.3 V, 5 V, and 15 V input logic compatible
• Cross-conduction prevention logic
• Internally set deadtime
• High-side output in phase with input
• Shutdown input turns off both channels
• Matched propagation delay for both channels
• RoHS compliant
Product Summary
VOFFSET
600 V max.
IO+/-
130 mA/270 mA
VOUT
10 V - 20 V
ton/off (typ.)
680 ns/150 ns
Deadtime (typ.)
520 ns
Packages
Description
The IRS2104 is a high voltage, high speed power
MOSFET and IGBT driver with dependent high- and lowside referenced output channels. Proprietary HVIC and
8 Lead SOIC
8 Lead PDIP
latch immune CMOS technologies enable ruggedized
IRS2104S
IRS2104
monolithic construction. The logic input is compatible
with standard CMOS or LSTTL output, down to 3.3 V
logic. The output drivers feature a high pulse current buffer stage designed for minimum driver crossconduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side
configuration which operates from 10 V to 600 V.
Typical Connection
up to 600 V
VCC
VCC
VB
IN
IN
HO
SD
SD
VS
COM
LO
TO
LOAD
(Refer to Lead Assignment for correct pin configuration). This diagram shows electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
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1
IRS2104(S) PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
VB
High-side floating absolute voltage
-0.3
625
VS
High-side floating supply offset voltage
VB - 25
VB + 0.3
VHO
High-side floating output voltage
VS - 0.3
VB + 0.3
VCC
Low-side and logic fixed supply voltage
-0.3
25
VLO
Low-side output voltage
-0.3
VCC + 0.3
Logic input voltage (IN & SD )
-0.3
VCC + 0.3
—
50
VIN
dVs/dt
PD
RthJA
Allowable offset supply voltage transient
Package power dissipation @ TA ≤ +25 °C
Thermal resistance, junction to ambient
(8 lead PDIP)
—
1.0
(8 lead SOIC)
—
0.625
(8 lead PDIP)
—
125
(8 lead SOIC)
—
200
TJ
Junction temperature
—
150
TS
Storage temperature
-55
150
TL
Lead temperature (soldering, 10 seconds)
—
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at a 15 V differential.
Symbol
Min.
Max.
VB
High-side floating supply absolute voltage
Definition
VS + 10
VS + 20
VS
High-side floating supply offset voltage
Note 1
600
VHO
High-side floating output voltage
VS
VB
VCC
Low-side and logic fixed supply voltage
10
20
VLO
Low-side output voltage
0
VCC
VIN
Logic input voltage (IN & SD )
0
VCC
TA
Ambient temperature
-40
125
Units
V
°C
Note 1: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
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2
IRS2104(S) PbF
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, CL = 1000 pF and TA = 25 °C unless otherwise specified.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
ton
Turn-on propagation delay
—
680
820
VS = 0 V
toff
Turn-off propagation delay
—
150
220
VS = 600 V
tsd
tr
Shutdown propagation delay
—
160
220
tf
Turn-on rise time
—
70
170
Turn-off fall time
—
35
90
DT
Deadtime, LS turn-off to HS turn-on &
HS turn-on to LS turn-off
400
520
650
MT
Delay matching, HS & LS turn-on/off
—
—
60
ns
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15 V and TA = 25 °C unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to
COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
VIH
Logic “1” (HO) & Logic “0” (LO) input voltage
2.5
—
—
VIL
Logic “0” (HO) & Logic “1” (LO) input voltage
—
—
0.8
VSD,TH+
SD input positive going threshold
2.5
—
—
VSD,TH-
SD input negative going threshold
—
—
0.8
VOH
High level output voltage, VBIAS - VO
—
0.05
0.2
VOL
Low level output voltage, VO
—
0.02
0.1
ILK
Offset supply leakage current
—
—
50
IQBS
Quiescent VBS supply current
—
30
55
IQCC
Quiescent VCC supply current
—
150
270
IIN+
Logic “1” input bias current
—
3
10
VIN = 5 V
IIN-
Logic “0” input bias current
—
—
5
VIN = 0 V
VCCUV+
VCC supply undervoltage positive going
threshold
8
8.9
9.8
VCCUV-
VCC supply undervoltage negative going
threshold
7.4
8.2
9
IO+
Output high short circuit pulsed current
130
290
—
IO-
Output low short circuit pulsed current
270
600
—
VCC = 10 V to 20 V
V
IO = 2 mA
VB = VS = 600 V
µA
V
mA
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VIN = 0 V or 5 V
VO = 0 V
PW ≤ 10 µs
VO = 15 V
PW ≤ 10 µs
3
IRS2104(S) PbF
Functional Block Diagram
VB
HV
LEVEL
SHIFT
Q
PULSE
FILTER
HO
R
S
VS
IN
PULSE
GEN
UV
DETECT
DEAD TIME &
SHOOT-THROUGH
PREVENTION
VCC
LO
SD
COM
Lead Definitions
Symbol Description
IN
Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO
SD
VB
Logic input for shutdown
HO
High-side gate drive output
VS
High-side floating supply return
VCC
Low-side and logic fixed supply
High-side floating supply
LO
Low-side gate drive output
COM
Low-side return
Lead Assignments
VCC
VB
2
IN
HO
3
SD
VS
6
4
COM
LO
5
1
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8
7
VCC
VB
8
IN
HO
7
3
SD
VS
6
4
COM
LO
5
1
2
8 Lead PDIP
8 Lead SOIC
IRS2104PbF
IRS2104SPbF
4
IRS2104(S) PbF
IN(LO)
IN
50%
50%
SD
IN(HO)
ton
toff
tr
90%
HO
LO
HO
LO
Figure 1. Input/Output Timing Diagram
90%
10%
10%
Figure 2. Switching Time Waveform Definitions
50%
SD
tf
50%
IN
50%
90%
tsd
HO
LO
90%
HO
10%
DT
LO
DT
90%
Figure 3. Shutdown Waveform Definitions
10%
Figure 4. Deadtime Waveform Definitions
IN (LO)
50%
50%
IN (HO)
LO
HO
10%
MT
MT
90%
LO
HO
Figure 5. Delay Matching Waveform Definitions
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5
IRS2104(S) PbF
1400
( )
Turn-On Delayy Time (ns)
Turn-On Delay Time (ns)
1400
1200
1000
Max.
800
600
Typ.
400
200
1200
Max.
1000
800
Typ.
600
400
200
0
0
-50
-25
0
25
50
75
100
10
125
12
Temperature (°C)
14
16
18
20
VBIAS Supply Voltage (V)
Figure 6A. Turn-On Time vs. Temperature
Figure 6B. Turn-On Time vs. Supply Voltage
1000
500
800
Turn-Off Delay Time (ns)
Turn-On Delay Time (ns)
Max.
600
Typ.
400
200
400
300
200
100
2
4
6
8
10
12
14
16
18
Typ.
0
-50
0
0
Max.
20
-25
0
Input Voltage (V)
50
75
100
125
Figure 7A. Turn-Off Time vs. Temperature
Figure 6C. Turn-On Time vs. Input Voltage
1000
Turn-Off Delay Time (ns)
500
Turn-Off Delay Time (ns)
25
Temperature (°C)
400
Max.
300
200
Typ.
100
0
800
600
Ma x .
400
200
Typ
0
10
12
14
16
18
20
VBIAS Supply Voltage (V)
Figure 7B. Turn-Off Time vs. Supply Voltage
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0
2
4
6
8
10
12 14
16 18
20
Input Voltage (V)
Figure 7C. Turn-Off Time vs. Input Voltage
6
IRS2104(S) PbF
500
Shutdown Delay Time (ns)
Shutdown Delay Time (ns)
500
400
300
M ax.
200
100
T y p.
0
-5 0
-2 5
0
25
50
75
100
400
Max.
300
200
Typ.
100
0
125
10
12
Temperature (°C)
Figure 8A. Shutdown Time vs. Temperature
18
20
500
Turn-On Rise Time (ns)
(
Turn-On Rise Time (ns)
16
Figure 8B. Shutdown Time vs. Voltage
500
400
300
200
14
VBIAS Supply Voltage (V)
Max.
100
400
300
Max.
200
100
Typ.
Typ.
0
-50
0
-25
0
25
50
75
100
125
10
12
14
16
18
20
VBIAS Supply Voltage (V)
Temperature (°C)
MAX
V BIAS Supply Voltage (V)
Figure 9A. Turn-On Rise Time
vs. Temperature
Figure 9B. Turn-On Rise Time vs. Voltage
200
Turn-Off Fall Time (ns)
Turn-Off Fall Time (ns)
200
150
100
Max.
50
150
Max.
100
50
Typ.
Typ.
0
-50
0
-25
0
25
50
75
100
Temperature (°C)
Figure 10A. Turn-Off Fall Time
vs. Temperature
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125
10
12
14
16
18
20
Input Voltage
Figure 10B. Turn-Off Fall Time
vs. Input Voltage
7
1400
1400
1200
1200
Deadtime (ns)
Deadtime (ns)
IRS2104(S) PbF
1000
800
M ax.
600
Typ.
400
M ax.
800
600
Typ.
400
M in .
M in .
200
1000
200
0
0
-5 0
-2 5
0
25
50
75
100
10
125
12
Temperature (°C)
8
8
7
7
6
6
5
4
Min.
2
1
18
20
5
4
Min.
3
2
1
0
0
-50
-25
0
25
50
75
100
125
10
12
Temperature (oC)
Min
14
16
18
20
V BAIS Supply Voltage (V)
Figure12A. Logic "1" Input Voltage
vs. Temperature
Figure 12B. Logic "1" Input Voltage
vs. Supply Voltage
Min.
4
4
Input Voltage (V)
Input Voltage (V)
16
Figure 11B. Deadtime vs. Voltage
Input Voltage (V)
Input Voltage (V)
Figure 11A. Deadtime vs. Temperature
3
14
VBIAS Supply Voltage (V)
3.2
2.4
1.6
Max.
0.8
0
-50
3 .2
2 .4
1 .6
M ax.
0 .8
0
-25
0
25
50
75
100
125
Temperature (°C)
Figure 13A. Logic "0" (HO) & Logic “1” (LO)
& Active SD Input Voltage
vs. Temperature
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10
12
14
16
18
20
Vcc Supply Voltage (V)
Figure 13B. Logic "0" (HO) & Logic “1” (LO)
& Active SD Input Voltage
vs. Voltage
8
IRS2104(S) PbF
High Level Output Voltage (V)
High Level Output Voltage (V)
0.5
0.4
0.3
0.2
Max.
0.1
Typ.
0.0
-50
-25
0
25
50
75
100
0.5
0.4
0.3
Max.
0.2
0.1
Typ.
0.0
125
10
12
Temperature ( oC)
Low Level Output Voltage (V)
Low Level Output Voltage (V)
0.5
0.4
0.3
0.2
Max.
Typ.
0.0
20
0.5
0.4
0.3
0.2
Max.
0.1
Typ.
-25
0
25
50
75
100
125
10
12
o
Temperature ( C)
300
200
Max.
0
25
50
75
100
Temperature (°C)
Figure 16A. Offset Supply Current
vs. Temperature
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125
Offset Supply Leakage Current (µA)
400
-25
16
18
20
Figure 15B. Low Level Output Voltage
vs. Supply Voltage
500
0
-50
14
V BIAS Supply Voltage (V)
Figure 15A. Low Level Output Voltage
vs. Temperature
Offset Supply Leakage Current (µA)
18
0
-50
100
16
Figure 14B. High Level Output Voltage
vs. Supply Voltage
Figure 14A. High Level Output Voltage
vs. Temperature
0.1
14
VBIAS Supply Voltage (V)
500
400
300
200
100
Max.
0
0
100
200
300
400
500
600
VB Boost Voltage (V)
Figure 16B. Offset Supply Current
vs. Voltage
9
IRS2104(S) PbF
150
VBS Supply Current (µA)
VBS Supply Current (µA)
150
120
90
60
Max.
30
Typ.
0
-50
120
90
60
Max .
30
Ty p.
0
-25
0
25
50
75
100
125
10
12
Temperature (°C)
Figure 17A. VBS Supply Current
vs. Temperature
Vcc Supply Current (µA)
Vcc Supply Current (µA)
500
400
Max.
200
Typ.
0
-50
500
400
300
Max.
200
100
Typ.
0
-25
0
25
50
75
100
125
10
12
16
18
20
Figure 18B. Vcc Supply Current vs. Voltage
30
30
Logic 1” Input Current (µA)
Logic 1” Input Current (µA)
14
Vcc Supply Voltage (V)
Figure 18A. Vcc Supply Current
vs. Temperature
25
20
15
Max.
5
Typ.
0
-50
20
600
Temperature (°C)
10
18
700
600
100
16
Figure 17B. VBS Supply Current
vs. Voltage
700
300
14
VBS Floating Supply Voltage (V)
25
20
15
10
Max.
5
Typ.
0
-25
0
25
50
75
100
Temperature (°C)
Figure 19A. Logic"1" Input Current
vs. Temperature
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125
10
12
14
16
18
20
Vcc Supply Voltage (V)
Figure 19B. Logic"1" Input Current
vs. Voltage
10
Logic "0" Input Bias C ur r ent ( µA)
Logic “0” Input Bias Current (µA)
IRS2104(S) PbF
6
5
Max
4
3
2
1
0
- 50
- 25
0
25
50
75
100
6
Max
5
4
3
2
1
0
125
10
12
(°C)
TempTemperature
er atur e ( °C)
Figure 20A. Logic "0" Input Bias Current
vs. Temperature
V CC UVLO T hreshold - (V)
VCC UVLO T hreshold +(V)
18
20
11
Max.
10
Typ.
Min.
8
7
6
-50
-25
0
25
50
75
100
10
Max.
9
Typ.
8
7
Min.
6
-50
125
-25
0
Temperature (°C)
25
50
75
100
125
Temperature (°C)
Figure 21A. Vcc Undervoltage Threshold(+)
vs. Temperature
Figure 21B. Vcc Undervoltage Threshold(-)
vs. Temperature
500
400
Output Source Current (mA)
500
Output Source Current (mA)
16
Figure 20B. Logic "0" Input Bias Current
vs. Voltage
11
9
14
Supply
Voltage (V
(V))
Supply
V oltage
Typ.
300
200
Min.
100
400
300
200
Typ.
100
Min.
0
0
-50
-25
0
25
50
75
100
Temperature (°C)
Figure 22A. Output Source Current
vs. Temperature
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125
10
12
14
16
18
20
VBIAS Supply Voltage (V)
Figure 22B. Output Source Current
vs. Voltage
11
IRS2104(S) PbF
1000
Output Sink Current (mA)
Output Sink Current (mA)
1000
800
Typ.
600
400
Min.
200
800
600
400
Typ.
200
Min.
0
-50
0
-25
0
25
50
75
100
10
125
12
Figure 23A. Output Sink Current
vs. Temperature
18
20
Figure 23B. Output Sink Current
vs. Supply Voltage
6
6
SD Input Threshold (+) (V)
SD Input Threshold (+) (V)
16
VBIAS Supply Voltage (V)
Temperature (°C)
5
4
3
14
Max.
2
1
-50
5
4
3
Max.
2
1
-25
0
25
50
75
100
125
Temperature (°C)
Figure 24A. SD Input Positive Going Threshold (+)
vs. Temperature
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10
12
14
16
18
20
Vcc Supply Voltage (V)
Figure 24B. SD Input Positive Going Threshold (+)
vs. Supply Voltage
12
IRS2104(S) PbF
Case Outline
D
DIM
B
5
A
FOOTPRINT
8
7
6
5
6
H
E
0.25 [.010]
1
2
3
A
4
6.46 [.255]
6X e
3X 1.27 [.050]
8X 1.78 [.070]
MILLIMETERS
MAX
MIN
.0532
.0688
1.35
1.75
A1 .0040
.0098
0.10
0.25
b
.013
.020
0.33
0.51
c
.0075
.0098
0.19
0.25
D
.189
.1968
4.80
5.00
.1574
3.80
4.00
A
8X 0.72 [.028]
INCHES
MIN
E
.1497
e
.050 BASIC
e1
MAX
1.27 BASIC
.025 BASIC
0.635 BASIC
H
.2284
.2440
5.80
6.20
K
.0099
.0196
0.25
0.50
L
.016
.050
0.40
1.27
y
0°
8°
0°
8°
K x 45°
e1
A
C
y
0.10 [.004]
8X b
0.25 [.010]
8X L
A1
7
C A B
NOTES:
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
8 Lead SOIC
8 Lead PDIP
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8X c
01-6027
01-0021 11 (MS-012AA)
01-6014
01-3003 01 (MS-001AB)
13
IRS2104(S) PbF
Tape & Reel
8-lead SOIC
LOAD ED TA PE FEED DIRECTION
A
B
H
D
F
C
N OT E : CO NTROLLING
D IMENSION IN MM
E
G
C A R R I E R T A P E D IM E N S I O N F O R 8 S O I C N
M e tr ic
Im p e ri a l
Co d e
M in
M ax
M in
M ax
A
7 .9 0
8.1 0
0. 31 1
0 .3 18
B
3 .9 0
4.1 0
0. 15 3
0 .1 61
C
11 .7 0
1 2 . 30
0 .4 6
0 .4 84
D
5 .4 5
5.5 5
0. 21 4
0 .2 18
E
6 .3 0
6.5 0
0. 24 8
0 .2 55
F
5 .1 0
5.3 0
0. 20 0
0 .2 08
G
1 .5 0
n/ a
0. 05 9
n/ a
H
1 .5 0
1.6 0
0. 05 9
0 .0 62
F
D
C
B
A
E
G
H
R E E L D IM E N S I O N S F O R 8 S O IC N
M e tr ic
Im p e ri a l
Co d e
M in
M ax
M in
M ax
A
3 2 9 . 60
3 30 .2 5
1 2 .9 76
1 3 .0 0 1
B
20 .9 5
2 1 . 45
0. 82 4
0 .8 44
C
12 .8 0
1 3 . 20
0. 50 3
0 .5 19
D
1 .9 5
2.4 5
0. 76 7
0 .0 96
E
98 .0 0
1 02 .0 0
3. 85 8
4 .0 15
F
n /a
1 8 . 40
n /a
0 .7 24
G
14 .5 0
1 7 . 10
0. 57 0
0 .6 73
H
12 .4 0
1 4 . 40
0. 48 8
0 .5 66
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14
IRS2104(S) PbF
LEADFREE PART MARKING INFORMATION
Part number
Date code
S
IRxxxxxx
YWW?
?XXXX
Pin 1
Identifier
?
P
IR logo
MARKING CODE
Lead Free Released
Non-Lead Free
Released
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
ORDER INFORMATION
8-Lead PDIP IRS2104PbF
8-Lead SOIC IRS2104SPbF
8-Lead SOIC Tape & Reel IRS2104STRPbF
The SOIC-8 is MSL2 qualified.
This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 11/27/2006
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15
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