NSC CD4724BCJ Dual 4-bit, 8-bit addressable latch Datasheet

CD4723BM/CD4723BC Dual 4-Bit Addressable Latch
CD4724BM/CD4724BC 8-Bit Addressable Latch
General Description
The CD4723B is a dual 4-bit addressable latch with common control inputs, including two address inputs (A0, A1),
an active low enable input (E), and an active high clear input
(CL). Each latch has a data input (D) and four outputs (Q0 –
Q3). The CD4724B is an 8-bit addressable latch with three
address inputs (A0–A2), an active low enable input (E), active high clear input (CL), a data input (D) and eight outputs
(Q0 – Q7).
Data is entered into a particular bit in the latch when that is
addressed by the address inputs and the enable (E) is low.
Data entry is inhibited when enable (E) is high.
When clear (CL) and enable (E) are high, all outputs are low.
When clear (CL) is high and enable (E) is low, the channel
demultiplexing occurs. The bit that is addressed has an active output which follows the data input while all unaddressed bits are held low. When operating in the address-
able latch mode (E e CL e low), changing more than one
bit of the address could impose a transient wrong address.
Therefore, this should only be done while in the memory
mode (E e high, CL e low).
Features
Y
Y
Y
Y
Y
Y
Y
Y
Wide supply voltage range
3.0V to 15V
High noise immunity
0.45 VDD (typ.)
Low power TTL
fan out of 2 driving 74L
compatibility
or 1 driving 74LS
Serial to parallel capability
Storage register capability
Random (addressable) data entry
Active high demultiplexing capability
Common active high clear
Connection Diagrams
CD4724B
Dual-In-Line Package
CD4723B
Dual-In-Line Package
Order Number CD4723B or
CD4724B
TL/F/6003–1
TL/F/6003 – 2
Top View
Top View
Truth Table
Mode Selection
E
CL
Addressed
Latch
L
H
L
H
L
L
H
H
Follows Data
Hold Previous Data
Follows Data
Reset to ‘0’’
C1995 National Semiconductor Corporation
TL/F/6003
Unaddressed
Latch
Mode
Holds Previous Data
Holds Previous Data
Reset to ‘‘0’’
Reset to ‘‘0’’
Addressable Latch
Memory
Demultiplexer
Clear
RRD-B30M105/Printed in U. S. A.
CD4723BM/CD4723BC Dual 4-Bit Addressable Latch
CD4724BM/CD4724BC 8-Bit Addressable Latch
February 1988
Absolute Maximum Ratings (Notes 1 & 2)
Recommended Operating
Conditions (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Supply Voltage (VDD)
Input Voltage (VIN)
Storage Temperature (TS)
Power Dissipation (PD)
Dual-In-Line
Small Outline
Lead Temperature (TL)
(Soldering, 10 seconds)
DC Supply Voltage (VDD)
Input Voltage (VIN)
Operating Temperature Range (TA)
CD4723BM/CD4724BM
CD4723BC/CD4724BC
b 0.5V to a 18 VDC
b 0.5V to VDD a 0.5 VDC
b 65§ C to a 150§ C
3.0V to 15 VDC
0V to VDD VDC
b 55§ C to a 125§ C
b 40§ C to a 85§ C
700 mW
500 mW
260§ C
DC Electrical Characteristics CD4723BM/CD4724BM (Note 2)
Symbol
Parameter
b 55§ C
Conditions
Min
Max
a 25§ C
Min
a 125§ C
Typ
Max
Min
Units
Max
IDD
Quiescent Device
Current
VDD e 5V
VDD e 10V
VDD e 15V
5.0
10
20
0.02
0.02
0.02
5.0
10
20
150
300
600
mA
mA
mA
VOL
Low Level
Output Voltage
lIOl s 1 mA
VDD e 5V
VDD e 10V
VDD e 15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
High Level
Output Voltage
lIOl s 1 mA
VDD e 5V
VDD e 10V
VDD e 15V
VIL
Low Level
Input Voltage
VDD e 5V, VO e 0.5V or 4.5V
VDD e 10V, VO e 1V or 9V
VDD e 15V, VO e 1.5V or 13.5V
VIH
High Level
Input Voltage
VDD e 5V, VO e 0.5V or 4.5V
VDD e 10V, VO e 1V or 9V
VDD e 15V, VO e 1.5V or 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.5
8.25
3.5
7.0
11.0
V
V
V
IOL
Low Level Output
Current
(Note 3)
VDD e 5V, VO e 0.4V
VDD e 10V, VO e 0.5V
VDD e 15V, VO e 1.5V
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
IOH
High Level Output
Current
(Note 3)
VDD e 5V, VO e 4.6V
VDD e 10V, VO e 9.5V
VDD e 15V, VO e 13.5V
b 0.64
b 1.6
b 4.2
b 0.51
b 1.3
b 3.4
b 0.88
b 2.25
b 8.8
b 0.36
b 0.9
b 2.4
mA
mA
mA
IIN
Input Current
VDD e 15V, VIN e 0V
VDD e 15V, VIN e 15V
VOH
4.95
9.95
14.95
4.95
9.95
14.95
1.5
3.0
4.0
5.0
10
15
2.25
4.5
6.75
4.95
9.95
14.95
1.5
3.0
4.0
V
V
V
1.5
3.0
4.0
b 0.1
b 10 b 5
b 0.1
b 1.0
0.1
10b5
0.1
1.0
V
V
V
mA
mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device
operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOL and IOH are tested one output at a time.
2
DC Electrical Characteristics CD4723BC/CD4724BC (Note 2)
Symbol
Parameter
b 40§ C
Conditions
Min
Max
a 25§ C
Min
a 85§ C
Typ
Max
Min
Units
Max
IDD
Quiescent Device
Current
VDD e 5V
VDD e 10V
VDD e 15V
20
40
80
0.02
0.02
0.02
20
40
80
150
300
600
mA
mA
mA
VOL
Low Level
Output Voltage
lIOl s 1 mA
VDD e 5V
VDD e 10V
VDD e 15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
High Level
Output Voltage
lIOl s 1 mA
VDD e 5V
VDD e 10V
VDD e 15V
VIL
Low Level
Input Voltage
VDD e 5V, VO e 0.5V or 4.5V
VDD e 10V, VO e 1V or 9V
VDD e 15V, VO e 1.5V or 13.5V
VIH
High Level
Input Voltage
VDD e 5V, VO e 0.5V or 4.5V
VDD e 10V, VO e 1V or 9V
VDD e 15V, VO e 1.5V or 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.5
8.25
3.5
7.0
11.0
V
V
V
IOL
Low Level Output
Current
(Note 3)
VDD e 5V, VO e 0.4V
VDD e 10V, VO e 0.5V
VDD e 15V, VO e 1.5V
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
IOH
High Level Output VDD e 5V, VO e 4.6V
Current
VDD e 10V, VO e 9.5V
(Note 3)
VDD e 15V, VO e 13.5V
b 0.52
b 1.3
b 3.6
b 0.44
b 1.1
b 3.0
b 0.88
b 2.25
b 8.8
b 0.36
b 0.9
b 2.4
mA
mA
mA
IIN
Input Current
VOH
4.95
9.95
14.95
4.95
9.95
14.95
1.5
3.0
4.0
VDD e 15V, VIN e 0V
VDD e 15V, VIN e 15V
5.0
10
15
2.25
4.5
6.75
4.95
9.95
14.95
1.5
3.0
4.0
V
V
V
1.5
3.0
4.0
b 0.30
b 10 b 5
b 0.30
b 1.0
0.30
10b5
0.30
1.0
V
V
V
mA
mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device
operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOL and IOH are tested one output at a time.
3
AC Electrical Characteristics*
TA e 25§ C, CL e 50 pF, RL e 200k, Input tr e tf e 20 ns, unless otherwise noted
Typ
Max
Units
tPHL, tPLH
Symbol
Propagation Delay
Data to Output
Parameter
VDD e 5V
VDD e 10V
VDD e 15V
Conditions
Min
200
75
50
400
150
100
ns
ns
ns
tPLH, tPHL
Propagation Delay
Enable to Output
VDD e 5V
VDD e 10V
VDD e 15V
200
80
60
400
160
120
ns
ns
ns
tPHL
Propagation Delay
Clear to Output
VDD e 5V
VDD e 10V
VDD e 15V
175
80
65
350
160
130
ns
ns
ns
tPLH, tPHL
Propagation Delay
Address to Output
VDD e 5V
VDD e 10V
VDD e 15V
225
100
75
450
200
150
ns
ns
ns
tTHL, tTLH
Transition Time
(Any Output)
VDD e 5V
VDD e 10V
VDD e 15V
100
50
40
200
100
80
ns
ns
ns
TWH, TWL
Minimum Data
Pulse Width
VDD e 5V
VDD e 10V
VDD e 15V
100
50
40
200
100
80
ns
ns
ns
tWH, tWL
Minimum Address
Pulse Width
VDD e 5V
VDD e 10V
VDD e 15V
200
100
65
400
200
125
ns
ns
ns
tWH
Minimum Clear
Pulse Width
VDD e 5V
VDD e 10V
VDD e 15V
75
40
25
150
75
50
ns
ns
ns
tSU
Minimum Setup Time
Data to E
VDD e 5V
VDD e 10V
VDD e 15V
40
20
15
80
40
30
ns
ns
ns
tH
Minimum Hold Time
Data to E
VDD e 5V
VDD e 10V
VDD e 15V
60
30
25
120
60
50
ns
ns
ns
tSU
Minimum Setup Time
Address to E
VDD e 5V
VDD e 10V
VDD e 15V
b 15
0
0
50
30
20
ns
ns
ns
tH
Minimum Hold Time
Address to E
VDD e 5V
VDD e 10V
VDD e 15V
b 50
b 20
b 15
15
10
5
ns
ns
ns
CPD
Power Dissipation
Capacitance
Per Package
(Note 4)
100
CIN
Input Capacitance
Any Input
5.0
pF
7.5
pF
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device
operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOL and IOH are tested one output at a time.
Note 4: Dynamic power dissipation (PD) is given by: PD e (CPD a CL) VCC2f a PQ; where CL e load capacitance; f e frequency of operation; for further details,
see Application Note AN-90, ‘‘54C/74C Family Characteristics’’.
4
Logic Diagrams
CD4723B
TL/F/6003 – 3
5
Logic Diagrams (Continued)
CD4724B
TL/F/6003 – 4
6
TL/F/6003 – 5
Switching Time Waveforms
7
CD4723BM/CD4723BC Dual 4-Bit Addressable Latch
CD4724BM/CD4724BC 8-Bit Addressable Latch
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4723BMJ, CD4723BCJ, CD4724BMJ or CD4724BCJ
NS Package Number J16A
Molded Dual-In-Line Package (N)
Order Number CD4723BMN, CD4723BCN, CD4724BMN or CD4724BCN
NS Package Number N16E
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