Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5602D Rev. 3.1, 02/2011 MPC5602D 100 LQFP 14 mm x 14 mm 64 LQFP 10 mm x 10 mm MPC5602D Microcontroller Data Sheet • • • • • • • • • • • • • • Single issue, 32-bit CPU core complex (e200z0) — Compliant with the Power Architecture® embedded category — Includes an instruction set enhancement allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. Up to 256 KB on-chip Code Flash supported with Flash controller and ECC 64 KB on-chip Data Flash with ECC Up to 16 KB on-chip SRAM with ECC Interrupt controller (INTC) with multiple interrupt vectors, including 20 external interrupt sources and 18 external interrupt/wakeup sources Frequency modulated phase-locked loop (FMPLL) Crossbar switch architecture for concurrent access to peripherals, Flash, or SRAM from multiple bus masters Boot assist module (BAM) supports internal Flash programming via a serial link (CAN or SCI) Timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS-lite) Up to 33 channel 12-bit analog-to-digital converter (ADC) 2 serial peripheral interface (DSPI) modules 3 serial communication interface (LINFlex) modules 1 enhanced full CAN (FlexCAN) module with configurable buffers Up to 79 configurable general purpose pins supporting input and output operations (package dependent) • • • • • • Real Time Counter (RTC) with clock source from 128 kHz or 16 MHz internal RC oscillator supporting autonomous wakeup with 1 ms resolution with max timeout of 2 seconds Up to 4 periodic interrupt timers (PIT) with 32-bit counter resolution 1 System Module Timer (STM) Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class 1 standard Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) On-chip voltage regulator (VREG) for regulation of input supply for all internal levels This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2009, 2010. All rights reserved. Preliminary—Subject to Change Without Notice Table of Contents 1 2 3 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .7 3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .20 4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.3.1 NVUSRO[PAD3V5V] field description . . . . . . . .20 4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .21 4.5 Recommended operating conditions . . . . . . . . . . . . . .22 4.6 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .24 4.6.1 Package thermal characteristics . . . . . . . . . . . .24 4.6.2 Power considerations. . . . . . . . . . . . . . . . . . . . .25 4.7 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .25 4.7.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.7.2 I/O input DC characteristics . . . . . . . . . . . . . . . .26 4.7.3 I/O output DC characteristics. . . . . . . . . . . . . . .26 4.7.4 Output pin transition times . . . . . . . . . . . . . . . . .29 4.7.5 I/O pad current specification . . . . . . . . . . . . . . .29 4.8 RESET electrical characteristics. . . . . . . . . . . . . . . . . .34 4.9 Power management electrical characteristics. . . . . . . .36 4.9.1 Voltage regulator electrical characteristics . . . .36 4.9.2 Voltage monitor electrical characteristics. . . . . .38 4.10 Low voltage domain power consumption . . . . . . . . . . .39 5 6 4.11 Flash memory electrical characteristics . . . . . . . . . . . 40 4.11.1 Program/Erase characteristics . . . . . . . . . . . . . 40 4.11.2 Flash power supply DC characteristics . . . . . . 42 4.11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 43 4.12 Electromagnetic compatibility (EMC) characteristics. . 43 4.12.1 Designing hardened software to avoid noise problems. . . . . . . . . . . . . . . . . . . . . . . . 44 4.12.2 Electromagnetic interference (EMI) . . . . . . . . . 44 4.12.3 Absolute maximum ratings (electrical sensitivity)44 4.13 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 49 4.15 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.16 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 52 4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.17.2 Input impedance and ADC accuracy . . . . . . . . 52 4.17.3 ADC electrical characteristics . . . . . . . . . . . . . 57 4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 60 4.18.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 62 4.18.3 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 68 Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 69 5.1.1 100 LQFP mechanical outline drawing. . . . . . . 69 5.1.2 64 LQFP mechanical outline drawing. . . . . . . . 73 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 MPC5602D Microcontroller Data Sheet, Rev. 3.1 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor Introduction 1 Introduction 1.1 Document overview This document describes the device features and highlights the important electrical and physical characteristics. 1.2 Description These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices designed to be central to the development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control and seat control applications. This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology and designed specifically for embedded applications. The advanced and cost-efficient e200z0 host processor core of this automotive controller family complies with the Power Architecture technology and only implements the VLE (variable-length encoding) APU (auxiliary processing unit), providing improved code density. It operates at speeds of up to 48 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with the user’s implementations. The device platform has a single level of memory hierarchy and can support a wide range of on-chip static random access memory (SRAM) and internal flash memory. Table 1. MPC5602D device comparison Device Feature MPC5601DxLH MPC5601DxLL CPU MPC5602DxLH MPC5602DxLL e200z0 Execution speed Static – up to 48 MHz Code Flash 128 KB 256 KB Data Flash 64 KB (4 × 16 KB) SRAM 12 KB 16 KB eDMA 16 ch ADC 16 ch, 12-bit 33 ch, 12-bit CTU 16 ch, 12-bit 33 ch, 12-bit 16 ch 1 13 ch, 16-bit 28 ch, 16-bit 13 ch, 16-bit 28 ch, 16-bit 2 ch 5 ch 2 ch 5 ch — 9 ch — 9 ch • Type G4 7 ch 7 ch 7 ch 7 ch 5 4 ch 7 ch 4 ch 7 ch 45 79 Total timer I/O eMIOS • Type X2 • Type Y 3 • Type H SCI (LINFlex) 3 SPI (DSPI) 2 CAN (FlexCAN) 1 GPIO6 45 79 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 3 Introduction Table 1. MPC5602D device comparison (continued) Device Feature MPC5601DxLH MPC5601DxLL Debug Package 1 2 3 4 5 6 MPC5602DxLH MPC5602DxLL 64 LQFP 100 LQFP JTAG 64 LQFP 100 LQFP Refer to eMIOS section of device reference manual for information on the channel configuration and functions. Type X = MC + MCB + OPWMT + OPWMB + OPWFMB + SAIC + SAOC Type Y = OPWMT + OPWMB + SAIC + SAOC Type G = MCB + IPWM + IPM + DAOC + OPWMT + OPWMB + OPWFMB + OPWMCB + SAIC + SAOC Type H = IPWM + IPM + DAOC + OPWMT + OPWMB + SAIC + SAOC I/O count based on multiplexing with peripherals MPC5602D Microcontroller Data Sheet, Rev. 3.1 4 Preliminary—Subject to Change Without Notice Freescale Semiconductor Block diagram 2 Block diagram Figure 1 shows a top-level block diagram of the MPC5602D device series. Figure 1. MPC5602D series block diagram SRAM 16 KB JTAG Code Flash 256 KB Data Flash 64 KB 64-bit 3 x 3 Crossbar Switch JTAG Port Instructions (Master) Nexus 1 e200z0h Data NMI (Master) SIUL Voltage Regulator Interrupt requests from peripheral blocks NMI Flash Controller (Slave) (Slave) (Slave) (Master) INTC Clocks SRAM Controller eDMA CMU FMPLL RTC STM SWT MC_RGM MC_CGM PIT ECSM MC_ME MC_PCU BAM SSCM Peripheral Bridge Interrupt Request SIUL Reset Control 33 ch. ADC CTU 1x eMIOS 3x LINFlex 2x DSPI 1x FlexCAN WKPU External Interrupt Request IMUX Interrupt Request GPIO & Pad Control I/O ... ... ... ... Legend: ADC BAM CMU CTU DSPI ECSM eDMA eMIOS Flash FlexCAN FMPLL IMUX INTC JTAG LINFlex Analog-to-Digital Converter Boot Assist Module Clock Monitor Unit Cross Triggering Unit Deserial Serial Peripheral Interface Error Correction Status Module Enhanced Direct Memory Access Enhanced Modular Input Output System Flash memory Controller Area Network (FlexCAN) Frequency-Modulated Phase-Locked Loop Internal Multiplexer Interrupt Controller JTAG controller Serial Communication Interface (LIN support) MC_CGM MC_ME MC_PCU MC_RGM NMI PIT RTC SIUL SRAM SSCM STM SWT WKPU XBAR Clock Generation Module Mode Entry Module Power Control Unit Reset Generation Module Non-Maskable Interrupt Periodic Interrupt Timer Real-Time Clock System Integration Unit Lite Static Random-Access Memory System Status Configuration Module System Timer Module Software Watchdog Timer Wakeup Unit Crossbar switch MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 5 Block diagram Table 2 summarizes the functions of all blocks present in the MPC5602D series of microcontrollers. Please note that the presence and number of blocks varies by device and package. Table 2. MPC5602D series block summary Block Function Analog-to-digital converter (ADC) Multi-channel, 12-bit analog-to digital-converter Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according to the boot mode of the device Clock monitor unit (CMU) Monitors clock source (internal and external) integrity Cross triggering unit (CTU) Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT Crossbar switch (XBAR) Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices (DSPI) Error Correction Status Module (ECSM) Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host processor (eDMA) via “n” programmable channels. Enhanced modular input output system (eMIOS) Provides the functionality to generate or measure events Flash memory Provides non-volatile storage for program code, constants and variables FlexCAN (controller area network) Supports the standard CAN communications protocol Frequency-modulated phase-locked loop (FMPLL) Generates high-speed system clocks and supports programmable frequency modulation Internal multiplexer (IMUX) SIU subblock Allows flexible mapping of peripheral interface on the different pins of the device Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests JTAG controller Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode LINFlex controller Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Clock generation module (MC_CGM) Provides logic and control required for the generation of system and peripheral clocks Mode entry module (MC_ME) Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Power control unit (MC_PCU) Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called “power domains” which are controlled by the PCU MPC5602D Microcontroller Data Sheet, Rev. 3.1 6 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions Table 2. MPC5602D series block summary (continued) Block Function Reset generation module (MC_RGM) Centralizes reset sources and manages the device reset sequence of the device Non-Maskable Interrupt (NMI) Handles external events that must produce an immediate response, such as power down detection Periodic interrupt timer (PIT) Produces periodic interrupts and triggers Real-time counter (RTC) Provides a free-running counter and interrupt generation capability that can be used for timekeeping applications System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration Static random-access memory (SRAM) Provides storage for program code, constants, and variables System status and configuration module (SSCM) Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable System timer module (STM) Provides a set of output compare events to support AUTOSAR and operating system tasks System watchdog timer (SWT) Provides protection from runaway code Wakeup Unit (WKPU) Supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. 3 Package pinouts and signal descriptions 3.1 Package pinouts The available LQFP pinouts are provided in the following figures. For pin signal descriptions, please refer to Table 3. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 7 Package pinouts and signal descriptions Figure 2 shows the MPC5602D in the 100 LQFP package. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PE[12] Figure 2. 100 LQFP pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 LQFP 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PA[11] PA[10] PA[9] PA[8] PA[7] VDD_HV VSS_HV PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PB[3] PC[9] PC[14] PC[15] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[11] PC[10] PB[0] PB[1] PC[6] MPC5602D Microcontroller Data Sheet, Rev. 3.1 8 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions Figure 3 shows the MPC5602D in the 64 LQFP package. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PB[2] PC[8] PC[4] PC[5] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] Figure 3. 64 LQFP pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 LQFP PA[11] PA[10] PA[9] PA[8] PA[7] PA[3] PB[15] PB[14] PB[13] PB[12] PB[11] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PB[4] 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PB[3] PC[9] PA[2] PA[1] PA[0] VPP_TEST VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[10] PB[0] PB[1] PC[6] 3.2 Pin muxing Table 3 defines the pin list and muxing for this device. Each entry of Table 3 shows all the possible configurations for each pin, via the alternate functions. The default function assigned to each pin after reset is indicated by AF0. Table 3. Functional port pin descriptions Pin No. Port pin PCR register Alternate function1 Function Pad RESET I/O Peripheral direction2 type config. 64 LQFP 100 LQFP Port A PA[0] PCR[0] AF0 AF1 AF2 AF3 — GPIO[0] E0UC[0] CLKOUT E0UC[13] WKUP[19]3 SIUL eMIOS_0 CGL eMIOS_0 WKPU I/O I/O O I/O I M Tristate 5 12 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 9 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PCR register Alternate function1 Function Pad RESET I/O Peripheral direction2 type config. 64 LQFP 100 LQFP PA[1] PCR[1] AF0 AF1 AF2 AF3 — — GPIO[1] E0UC[1] — — NMI4 WKUP[2]3 SIUL eMIOS_0 — — WKPU WKPU I/O I/O — — I I S Tristate 4 7 PA[2] PCR[2] AF0 AF1 AF2 AF3 — GPIO[2] E0UC[2] — — WKUP[3]3 SIUL eMIOS_0 — — WKPU I/O I/O — — I S Tristate 3 5 PA[3] PCR[3] AF0 AF1 AF2 AF3 — —‘ GPIO[3] E0UC[3] — — EIRQ[0] ADC1_S[0] SIUL eMIOS_0 — — SIUL ADC I/O I/O — — I I S Tristate 43 68 PA[4] PCR[4] AF0 AF1 AF2 AF3 — GPIO[4] E0UC[4] — — WKUP[9]3 SIUL eMIOS_0 — — WKPU I/O I/O — — I S Tristate 20 29 PA[5] PCR[5] AF0 AF1 AF2 AF3 GPIO[5] E0UC[5] — — SIUL eMIOS_0 — — I/O I/O — — M Tristate 51 79 PA[6] PCR[6] AF0 AF1 AF2 AF3 — GPIO[6] E0UC[6] — — EIRQ[1] SIUL eMIOS_0 — — SIUL I/O I/O — — I S Tristate 52 80 PA[7] PCR[7] AF0 AF1 AF2 AF3 — — GPIO[7] E0UC[7] — — EIRQ[2] ADC1_S[1] SIUL eMIOS_0 — — SIUL ADC I/O I/O — — I I S Tristate 44 71 PA[8] PCR[8] AF0 AF1 AF2 AF3 — N/A5 GPIO[8] E0UC[8] E0UC[14] — EIRQ[3] ABS[0] SIUL eMIOS_0 eMIOS_0 — SIUL BAM I/O I/O — — I I S Input, weak pull-up 72 45 MPC5602D Microcontroller Data Sheet, Rev. 3.1 10 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PCR register Alternate function1 Function Pad RESET I/O Peripheral direction2 type config. 64 LQFP 100 LQFP PA[9] PCR[9] AF0 AF1 AF2 AF3 N/A5 GPIO[9] E0UC[9] — — FAB SIUL eMIOS_0 — — BAM I/O I/O — — I S Pulldown 46 73 PA[10] PCR[10] AF0 AF1 AF2 AF3 — GPIO[10] E0UC[10] — LIN1TX ADC1_S[2] SIUL eMIOS_0 — LINFlex_1 ADC I/O I/O — O I S Tristate 47 74 PA[11] PCR[11] AF0 AF1 AF2 AF3 — — — GPIO[11] E0UC[11] — — EIRQ[16] ADC1_S[3] LIN2RX SIUL eMIOS_0 — — SIUL ADC LINFlex_2 I/O I/O — — I I I S Tristate 48 75 PA[12] PCR[12] AF0 AF1 AF2 AF3 — — GPIO[12] — — — EIRQ[17] SIN_0 SIUL — — — SIUL DSPI_0 I/O — — — I I S Tristate 22 31 PA[13] PCR[13] AF0 AF1 AF2 AF3 GPIO[13] SOUT_0 — — SIUL DSPI_0 — — I/O O — — M Tristate 21 30 PA[14] PCR[14] AF0 AF1 AF2 AF3 — GPIO[14] SCK_0 CS0_0 E0UC[0] EIRQ[4] SIUL DSPI_0 DSPI_0 eMIOS_0 SIUL I/O I/O I/O I/O I M Tristate 19 28 PA[15] PCR[15] AF0 AF1 AF2 AF3 — GPIO[15] CS0_0 SCK_0 E0UC[1] WKUP[10]3 SIUL DSPI_0 DSPI_0 eMIOS_0 WKPU I/O I/O I/O I/O I M Tristate 18 27 PCR[16] AF0 AF1 AF2 AF3 GPIO[16] CAN0TX — — SIUL FlexCAN_0 — — I/O O — — M Tristate 14 23 Port B PB[0] MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 11 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PCR register Alternate function1 Function Pad RESET I/O Peripheral direction2 type config. 64 LQFP 100 LQFP PB[1] PCR[17] AF0 AF1 AF2 AF3 — — GPIO[17] — — — WKUP[4]3 CAN0RX SIUL — — — WKPU FlexCAN_0 I/O — — — I I S Tristate 15 24 PB[2] PCR[18] AF0 AF1 AF2 AF3 GPIO[18] LIN0TX — — SIUL LINFlex_0 — — I/O O — — M Tristate 64 100 PB[3] PCR[19] AF0 AF1 AF2 AF3 — — GPIO[19] — — — WKUP[11]3 LIN0RX SIUL — — — WKPU LINFlex_0 I/O — — — I I S Tristate 1 1 PB[4] PCR[20] AF0 AF1 AF2 AF3 — GPIO[20] — — — ADC1_P[0] SIUL — — — ADC I — — — I I Tristate 32 50 PB[5] PCR[21] AF0 AF1 AF2 AF3 — GPIO[21] — — — ADC1_P[1] SIUL — — — ADC I — — — I I Tristate 35 53 PB[6] PCR[22] AF0 AF1 AF2 AF3 — GPIO[22] — — — ADC1_P[2] SIUL — — — ADC I — — — I I Tristate 36 54 PB[7] PCR[23] AF0 AF1 AF2 AF3 — GPIO[23] — — — ADC1_P[3] SIUL — — — ADC I — — — I I Tristate 37 55 PB[8] PCR[24] AF0 AF1 AF2 AF3 — — GPIO[24] — — — ADC1_S[4] WKUP[25]3 SIUL — — — ADC WKPU I — — — I I I Tristate 30 39 MPC5602D Microcontroller Data Sheet, Rev. 3.1 12 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PCR register Alternate function1 Function Pad RESET I/O Peripheral direction2 type config. 64 LQFP 100 LQFP PB[9] PCR[25] AF0 AF1 AF2 AF3 — — GPIO[25] — — — ADC1_S[5] WKUP[26]3 SIUL — — — ADC WKPU I — — — I I I Tristate 29 38 PB[10] PCR[26] AF0 AF1 AF2 AF3 — — GPIO[26] — — — ADC1_S[6] WKUP[8]3 SIUL — — — ADC WKPU I/O — — — I I J Tristate 31 40 PB[11] PCR[27] AF0 AF1 AF2 AF3 — GPIO[27] E0UC[3] — CS0_0 ADC1_S[12] SIUL eMIOS_0 — DSPI_0 ADC I/O I/O — I/O I J Tristate 38 59 PB[12] PCR[28] AF0 AF1 AF2 AF3 — GPIO[28] E0UC[4] — CS1_0 ADC1_X[0] SIUL eMIOS_0 — DSPI_0 ADC I/O I/O — O I J Tristate 39 61 PB[13] PCR[29] AF0 AF1 AF2 AF3 — GPIO[29] E0UC[5] — CS2_0 ADC1_X[1] SIUL eMIOS_0 — DSPI_0 ADC I/O I/O — O I J Tristate 40 63 PB[14] PCR[30] AF0 AF1 AF2 AF3 — GPIO[30] E0UC[6] — CS3_0 ADC1_X[2] SIUL eMIOS_0 — DSPI_0 ADC I/O I/O — O I J Tristate 41 65 PB[15] PCR[31] AF0 AF1 AF2 AF3 — GPIO[31] E0UC[7] — CS4_0 ADC1_X[3] SIUL eMIOS_0 — DSPI_0 ADC I/O I/O — O I J Tristate 42 67 PC[0]6 PCR[32] AF0 AF1 AF2 AF3 GPIO[32] — TDI — SIUL — JTAGC — I/O — I — M Input, weak pull-up 59 87 PC[1]6 PCR[33] AF0 AF1 AF2 AF3 GPIO[33] — TDO — SIUL — JTAGC — I/O — O — F Tristate 54 82 Port C MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 13 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PCR register Alternate function1 Function Pad RESET I/O Peripheral direction2 type config. 64 LQFP 100 LQFP PC[2] PCR[34] AF0 AF1 AF2 AF3 — GPIO[34] SCK_1 — — EIRQ[5] SIUL DSPI_1 — — SIUL I/O I/O — — I M Tristate 50 78 PC[3] PCR[35] AF0 AF1 AF2 AF3 — GPIO[35] CS0_1 MA[0] — EIRQ[6] SIUL DSPI_1 ADC — SIUL I/O I/O O — I S Tristate 49 77 PC[4] PCR[36] AF0 AF1 AF2 AF3 — — GPIO[36] — — — SIN_1 EIRQ[18] SIUL — — — DSPI_1 SIUL I/O — — — I I M Tristate 62 92 PC[5] PCR[37] AF0 AF1 AF2 AF3 — GPIO[37] SOUT_1 — — EIRQ[7] SIUL DSPI_1 — — SIUL I/O O — — I M Tristate 61 91 PC[6] PCR[38] AF0 AF1 AF2 AF3 GPIO[38] LIN1TX — — SIUL LINFlex_1 — — I/O O — — S Tristate 16 25 PC[7] PCR[39] AF0 AF1 AF2 AF3 — — GPIO[39] — — — LIN1RX WKUP[12]3 SIUL — — — LINFlex_1 WKPU I/O — — — I I S Tristate 17 26 PC[8] PCR[40] AF0 AF1 AF2 AF3 GPIO[40] LIN2TX — — SIUL LINFlex_2 — — I/O O — — S Tristate 63 99 PC[9] PCR[41] AF0 AF1 AF2 AF3 — — GPIO[41] — — — LIN2RX WKUP[13]3 SIUL — — — LINFlex_2 WKPU I/O — — — I I S Tristate 2 2 PC[10] PCR[42] AF0 AF1 AF2 AF3 GPIO[42] — — MA[1] SIUL — — ADC I/O — — O M Tristate 13 22 MPC5602D Microcontroller Data Sheet, Rev. 3.1 14 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PCR register Alternate function1 Function Pad RESET I/O Peripheral direction2 type config. 64 LQFP 100 LQFP PC[11] PCR[43] AF0 AF1 AF2 AF3 — GPIO[43] — — MA[2] WKUP[5]3 SIUL — — ADC WKPU I/O — — O I S Tristate — 21 PC[12] PCR[44] AF0 AF1 AF2 AF3 — GPIO[44] E0UC[12] — — EIRQ[19] SIUL eMIOS_0 — — SIUL I/O I/O — — I M Tristate — 97 PC[13] PCR[45] AF0 AF1 AF2 AF3 GPIO[45] E0UC[13] — — SIUL eMIOS_0 — — I/O I/O — — S Tristate — 98 PC[14] PCR[46] AF0 AF1 AF2 AF3 — GPIO[46] E0UC[14] — — EIRQ[8] SIUL eMIOS_0 — — SIUL I/O I/O — — I S Tristate — 3 PC[15] PCR[47] AF0 AF1 AF2 AF3 — GPIO[47] E0UC[15] — — EIRQ[20] SIUL eMIOS_0 — — SIUL I/O I/O — — I M Tristate — 4 PD[0] PCR[48] AF0 AF1 AF2 AF3 — — GPIO[48] — — — WKUP[27]3 ADC1_P[4] SIUL — — — WKPU ADC I — — — I I I Tristate — 41 PD[1] PCR[49] AF0 AF1 AF2 AF3 — — GPIO[49] — — — WKUP[28]3 ADC1_P[5] SIUL — — — WKPU ADC I — — — I I I Tristate — 42 PD[2] PCR[50] AF0 AF1 AF2 AF3 — GPIO[50] — — — ADC1_P[6] SIUL — — — ADC I — — — I I Tristate — 43 Port D MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 15 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PCR register Alternate function1 Function Pad RESET I/O Peripheral direction2 type config. 64 LQFP 100 LQFP PD[3] PCR[51] AF0 AF1 AF2 AF3 — GPIO[51] — — — ADC1_P[7] SIUL — — — ADC I — — — I I Tristate — 44 PD[4] PCR[52] AF0 AF1 AF2 AF3 — GPIO[52] — — — ADC1_P[8] SIUL — — — ADC I — — — I I Tristate — 45 PD[5] PCR[53] AF0 AF1 AF2 AF3 — GPIO[53] — — — ADC1_P[9] SIUL — — — ADC I — — — I I Tristate — 46 PD[6] PCR[54] AF0 AF1 AF2 AF3 — GPIO[54] — — — ADC1_P[10] SIUL — — — ADC I — — — I I Tristate — 47 PD[7] PCR[55] AF0 AF1 AF2 AF3 — GPIO[55] — — — ADC1_P[11] SIUL — — — ADC I — — — I I Tristate — 48 PD[8] PCR[56] AF0 AF1 AF2 AF3 — GPIO[56] — — — ADC1_P[12] SIUL — — — ADC I — — — I I Tristate — 49 PD[9] PCR[57] AF0 AF1 AF2 AF3 — GPIO[57] — — — ADC1_P[13] SIUL — — — ADC I — — — I I Tristate — 56 PD[10] PCR[58] AF0 AF1 AF2 AF3 — GPIO[58] — — — ADC1_P[14] SIUL — — — ADC I — — — I I Tristate — 57 PD[11] PCR[59] AF0 AF1 AF2 AF3 — GPIO[59] — — — ADC1_P[15] SIUL — — — ADC I — — — I I Tristate — 58 MPC5602D Microcontroller Data Sheet, Rev. 3.1 16 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PCR register Alternate function1 Function Pad RESET I/O Peripheral direction2 type config. 64 LQFP 100 LQFP PD[12] PCR[60] AF0 AF1 AF2 AF3 — GPIO[60] CS5_0 E0UC[24] — ADC1_S[8] SIUL DSPI_0 eMIOS_0 — ADC I/O O I/O — I J Tristate — 60 PD[13] PCR[61] AF0 AF1 AF2 AF3 — GPIO[61] CS0_1 E0UC[25] — ADC1_S[9] SIUL DSPI_1 eMIOS_0 — ADC I/O I/O I/O — I J Tristate — 62 PD[14] PCR[62] AF0 AF1 AF2 AF3 — GPIO[62] CS1_1 E0UC[26] — ADC1_S[10] SIUL DSPI_1 eMIOS_0 — ADC I/O O I/O — I J Tristate — 64 PD[15] PCR[63] AF0 AF1 AF2 AF3 — GPIO[63] CS2_1 E0UC[27] — ADC1_S[11] SIUL DSPI_1 eMIOS_0 — ADC I/O O I/O — I J Tristate — 66 PE[0] PCR[64] AF0 AF1 AF2 AF3 — GPIO[64] E0UC[16] — — WKUP[6]3 SIUL eMIOS_0 — — WKPU I/O I/O — — I S Tristate — 6 PE[1] PCR[65] AF0 AF1 AF2 AF3 GPIO[65] E0UC[17] — — SIUL eMIOS_0 — — I/O I/O — — M Tristate — 8 PE[2] PCR[66] AF0 AF1 AF2 AF3 — — GPIO[66] E0UC[18] — — EIRQ[21] SIN_1 SIUL eMIOS_0 — — SIUL DSPI_1 I/O I/O — — I I M Tristate — 89 PE[3] PCR[67] AF0 AF1 AF2 AF3 GPIO[67] E0UC[19] SOUT_1 — SIUL eMIOS_0 DSPI_1 — I/O I/O O — M Tristate — 90 PE[4] PCR[68] AF0 AF1 AF2 AF3 — GPIO[68] E0UC[20] SCK_1 — EIRQ[9] SIUL eMIOS_0 DSPI_1 — SIUL I/O I/O I/O — I M Tristate — 93 Port E MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 17 Package pinouts and signal descriptions Table 3. Functional port pin descriptions (continued) Pin No. Port pin PCR register Alternate function1 Function Pad RESET I/O Peripheral direction2 type config. 64 LQFP 100 LQFP PE[5] PCR[69] AF0 AF1 AF2 AF3 GPIO[69] E0UC[21] CS0_1 MA[2] SIUL eMIOS_0 DSPI_1 ADC I/O I/O I/O O M Tristate — 94 PE[6] PCR[70] AF0 AF1 AF2 AF3 — GPIO[70] E0UC[22] CS3_0 MA[1] EIRQ[21] SIUL eMIOS_0 DSPI_0 ADC SIUL I/O I/O O O I M Tristate — 95 PE[7] PCR[71] AF0 AF1 AF2 AF3 — GPIO[71] E0UC[23] CS2_0 MA[0] EIRQ[21] SIUL eMIOS_0 DSPI_0 ADC SIUL I/O I/O O O I M Tristate — 96 PE[8] PCR[72] AF0 AF1 AF2 AF3 GPIO[72] — E0UC[22] — SIUL — eMIOS_0 — I/O — I/O — M Tristate — 9 PE[9] PCR[73] AF0 AF1 AF2 AF3 — GPIO[73] — E0UC[23] — WKUP[7]3 SIUL — eMIOS_0 — WKPU I/O — I/O — I S Tristate — 10 PE[10] PCR[74] AF0 AF1 AF2 AF3 — GPIO[74] — CS3_1 — EIRQ[10] SIUL — DSPI_1 — SIUL I/O — O — I S Tristate — 11 PE[11] PCR[75] AF0 AF1 AF2 AF3 — GPIO[75] E0UC[24] CS4_1 — WKUP[14]3 SIUL eMIOS_0 DSPI_1 — WKPU I/O I/O O — I S Tristate — 13 PE[12] PCR[76] AF0 AF1 AF2 AF3 — — GPIO[76] — — — ADC1_S[7] EIRQ[11] SIUL — — — ADC SIUL I/O — — — I I S Tristate — 76 PCR[121] AF0 AF1 AF2 AF3 GPIO[121] — TCK — SIUL — JTAGC — I/O — I — S Input, weak pull-up 88 Port H PH[9]6 60 MPC5602D Microcontroller Data Sheet, Rev. 3.1 18 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 3. Functional port pin descriptions (continued) Pin No. Port pin PCR register Alternate function1 PH[10]6 PCR[122] AF0 AF1 AF2 AF3 1 2 3 4 5 6 Function GPIO[122] — TMS — Pad RESET I/O Peripheral direction2 type config. SIUL — JTAGC — I/O — I — S Input, weak pull-up 64 LQFP 53 100 LQFP 81 Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00 AF0; PCR.PA = 01 AF1; PCR.PA = 10 AF2; PCR.PA = 11 AF3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “—”. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside the SIUL module. All WKUP pins also support external interrupt capability. See “wakeup unit” chapter for further details. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored. “Not applicable” because these functions are available only while the device is booting. Refer to “BAM” chapter of the device reference manual for details. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO. PC[0:1] are available as JTAG pins (TDI and TDO respectively). PH[9:10] are available as JTAG pins (TCK and TMS respectively). It is up to the user to configure these pins as GPIO when needed. 4 Electrical characteristics 4.1 Introduction This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This can be done by the internal pull-up or pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column. CAUTION All of the following parameter values can vary depending on the application and must be confirmed during silicon validation, silicon characterization or silicon reliability trial. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 19 Electrical characteristics 4.2 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 4 are used and the parameters are tagged accordingly in the tables where appropriate. Table 4. Parameter classifications Classification tag Tag description P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 4.3 NVUSRO register Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are controlled via bit values in the non-volatile user options register (NVUSRO) register. For a detailed description of the NVUSRO register, please refer to the MPC5602D reference manual. 4.3.1 NVUSRO[PAD3V5V] field description Table 5 shows how NVUSRO[PAD3V5V] controls the device configuration. Table 5. PAD3V5V field description1 Value2 1 2 Description 0 High voltage supply is 5.0 V 1 High voltage supply is 3.3 V See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer. The DC electrical characteristics are dependent on the PAD3V5V bit value. 4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description Table 6 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration. MPC5602D Microcontroller Data Sheet, Rev. 3.1 20 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 6. OSCILLATOR_MARGIN field description1 Value2 1 2 Description 0 Low consumption configuration (4 MHz/8 MHz) 1 High margin configuration (4 MHz/16 MHz) See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer. The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. 4.4 Absolute maximum ratings Table 7. Absolute maximum ratings Value Symbol C Parameter Unit Min Max VSS SR — Digital ground on VSS_HV pins — 0 0 V VDD SR — Voltage on VDD_HV pins with respect to ground (VSS) — 0.3 6.0 V VSS_LV SR — Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) — VDD_BV SR — Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) — Relative to VDD VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) — VDD_ADC SR — Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) — VIN SR — Voltage on any GPIO pin with respect to ground (VSS) Relative to VDD — Relative to VDD VSS 0.1 VSS + 0.1 0.3 6.0 V V VDD 0.3 VDD + 0.3 VSS 0.1 VSS + 0.1 0.3 6.0 V V VDD 0.3 VDD + 0.3 0.3 6.0 V VDD 0.3 VDD + 0.3 IINJPAD SR — Injected input current on any pin during overload condition — 10 10 mA IINJSUM SR — Absolute sum of all injected input currents during overload condition — 50 50 mA VDD = 5.0 V ± 10%, PAD3V5V = 0 — 70 mA VDD = 3.3 V ± 10%, PAD3V5V = 1 — 64 — — 150 mA — 55 150 °C IAVGSEG SR — Sum of all the static I/O current within a supply segment1 ICORELV SR — Low voltage static current sink through VDD_BV TSTORAGE SR — Storage temperature 1 Conditions Supply segments are described in Section 4.7.5, “I/O pad current specification. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 21 Electrical characteristics NOTE Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values. 4.5 Recommended operating conditions Table 8. Recommended operating conditions (3.3 V) Value Symbol C Parameter Conditions SR — Digital ground on VSS_HV pins — 0 0 V VDD1 SR — Voltage on VDD_HV pins with respect to ground (VSS) — 3.0 3.6 V SR — Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) — VDD_BV3 SR — Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) — — VDD_ADC4 SR — Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) — VIN 4 5 6 3.0 3.6 V V VSS 0.1 VSS + 0.1 3.05 3.6 V V Relative to VDD VDD 0.1 VDD + 0.1 — VSS 0.1 — Relative to VDD — VDD + 0.1 V IINJPAD SR — Injected input current on any pin during overload condition — 5 5 mA IINJSUM SR — Absolute sum of all injected input currents during overload condition — 50 50 mA SR — VDD slope to ensure correct power up6 — TBD 0.25 V/µs 40 125 °C 40 150 TVDD 3 SR — Voltage on any GPIO pin with respect to ground (VSS) VSS 0.1 VSS + 0.1 Relative to VDD VDD 0.1 VDD + 0.1 VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) 2 Max VSS VSS_LV2 1 Unit Min TA SR — Ambient temperature under bias TJ SR — Junction temperature under bias fCPU 48 MHz — 100 nF capacitance needs to be provided between each VDD/VSS pair. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is reset. Guaranteed by device validation MPC5602D Microcontroller Data Sheet, Rev. 3.1 22 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 9. Recommended operating conditions (5.0 V) Value Symbol C Parameter Conditions Unit Min Max VSS SR — Digital ground on VSS_HV pins — 0 0 V VDD1 SR — Voltage on VDD_HV pins with respect to ground (VSS) — 4.5 5.5 V 3.0 5.5 VSS_LV3 SR — Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) VDD_BV4 SR — Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) Voltage drop2 VSS 0.1 VSS + 0.1 — — (2) Voltage drop 4.5 5.5 3.0 5.5 V V Relative to VDD VDD 0.1 VDD + 0.1 VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS — VDD_ADC5 SR — Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) — VSS 0.1 VSS + 0.1 (2) Voltage drop 4.5 5.5 3.0 5.5 V V Relative to VDD VDD 0.1 VDD + 0.1 VIN 2 3 4 5 6 — VSS 0.1 — Relative to VDD — VDD + 0.1 V IINJPAD SR — Injected input current on any pin during overload condition — 5 5 IINJSUM SR — Absolute sum of all injected input currents during overload condition — 50 50 SR — VDD slope to ensure correct power up6 — TBD 0.25 V/µs °C TVDD 1 SR — Voltage on any GPIO pin with respect to ground (VSS) TA SR — Ambient temperature under bias fCPU 48 MHz 40 125 TJ SR — Junction temperature under bias — 40 150 mA 100 nF capacitance needs to be provided between each VDD/VSS pair. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.6 V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Guaranteed by device validation NOTE SRAM data retention is guaranteed with VDD_LV not below 1.08 V. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 23 Electrical characteristics 4.6 Thermal characteristics 4.6.1 Package thermal characteristics Table 10. LQFP thermal characteristics1 Symbol C RJA CC D Parameter Thermal resistance, junction-to-ambient natural convection4 Conditions2 Single-layer board —1s Four-layer board — 2s2p RJB CC D Thermal resistance, junction-to-board5 Single-layer board — 1s Four-layer board — 2s2p RJC CC D Thermal resistance, junction-to-case6 Single-layer board — 1s Four-layer board — 2s2p JB CC D Junction-to-board thermal characterization parameter, natural convection Single-layer board — 1s Four-layer board — 2s2p JC CC D Junction-to-case thermal characterization parameter, natural convection Single-layer board — 1s Four-layer board — 2s2p 1 2 3 4 5 6 Pin count Value3 Unit 64 72.1 °C/W 100 65.2 64 57.3 100 51.8 64 45.6 100 42.6 64 44.1 100 41.3 64 26.5 100 23.9 64 26.2 100 23.7 64 41 100 41.6 64 43 100 43.4 64 11.5 100 10.4 64 11.1 100 10.2 °C/W °C/W °C/W °C/W Thermal characteristics are targets based on simulation that are subject to change per device characterization. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C All values need to be confirmed during device validation. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. When Greek letters are not available, the symbols are typed as RthJB. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. When Greek letters are not available, the symbols are typed as RthJC. MPC5602D Microcontroller Data Sheet, Rev. 3.1 24 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 4.6.2 Power considerations The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1: TJ = TA + (PD x RJA) Eqn. 1 Where: TA is the ambient temperature in °C. RJA is the package junction-to-ambient thermal resistance, in °C/W. PD is the sum of PINT and PI/O (PD = PINT + PI/O). PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power. PI/O represents the power dissipation on input and output pins; user determined. Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273 °C) Eqn. 2 K = PD x (TA + 273 °C) + RJA x PD2 Eqn. 3 Therefore, solving equations 1 and 2: Where: K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2 iteratively for any value of TA. 4.7 4.7.1 I/O pad electrical characteristics I/O pad types The device provides four main I/O pad types depending on the associated alternate functions: • • • Slow pads—These pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium pads—These pads provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. Input only pads—These pads are associated to ADC channels (ADC_P[X]) providing low input leakage. Medium pads can use slow configuration to reduce electromagnetic emission except for PC[1], that is medium only, at the cost of reducing AC performance. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 25 Electrical characteristics 4.7.2 I/O input DC characteristics Table 11 provides input DC electrical characteristics as described in Figure 4. Figure 4. I/O input DC electrical characteristics definition VIN VDD VIH VHYS VIL PDIx = ‘1’ (GPDI register of SIUL) PDIx = ‘0’ Table 11. I/O input DC electrical characteristics Symbol C Value2 Conditions1 Parameter Unit Min Typ Max VIH SR P Input high level CMOS (Schmitt Trigger) — 0.65VDD — VDD+0.4 VIL SR P Input low level CMOS (Schmitt Trigger) — 0.4 — 0.35VDD — 0.1VDD — — TA = 40 °C — 2 — TA = 25 °C — 2 — D TA = 105 °C — 12 500 P TA = 125 °C — 70 1000 — — — 40 ns — 1000 — — ns VHYS CC C Input hysteresis CMOS (Schmitt Trigger) ILKG CC P Digital input leakage P WFI 3 No injection on adjacent pin SR P Digital input filtered pulse WNFI3 SR P Digital input not filtered pulse V nA VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 3 In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage. 1 2 4.7.3 I/O output DC characteristics The following tables provide DC characteristics for bidirectional pads: MPC5602D Microcontroller Data Sheet, Rev. 3.1 26 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics • • • Table 12 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 13 provides output driver characteristics for I/O pads when in SLOW configuration. Table 14 provides output driver characteristics for I/O pads when in MEDIUM configuration. Table 12. I/O pull-up/pull-down DC electrical characteristics Symbol C Value Conditions1 Parameter Unit Min Typ Max |IWPU| CC P Weak pull-up current absolute value C P |IWPD| CC P Weak pull-down current absolute value C P 1 2 VIN = VIL, PAD3V5V = 0 VDD = 5.0 V ± 10% PAD3V5V = 12 10 — 150 10 — 250 PAD3V5V = 1 VIN = VIL, VDD = 3.3 V ± 10% 10 — 150 VIN = VIH, PAD3V5V = 0 VDD = 5.0 V ± 10% PAD3V5V = 12 10 — 150 10 — 250 VIN = VIH, PAD3V5V = 1 VDD = 3.3 V ± 10% 10 — 150 µA µA VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET are configured in input or in high impedance state. Table 13. SLOW configuration output buffer electrical characteristics Symbol C Parameter Push Pull IOH = 2 mA, VOH CC P Output high level SLOW configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) 1 Unit Min Typ Max 0.8VDD — — C IOH = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 0.8VDD — — C IOH = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) VDD 0.8 — — VOL CC P Output low level Push Pull IOL = 2 mA, SLOW configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) 2 Value Conditions1 — — 0.1VDD C IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 1(2) — — 0.1VDD C IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) — — V V 0.5 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET are configured in input or in high impedance state. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 27 Electrical characteristics Table 14. MEDIUM configuration output buffer electrical characteristics Symbol C Parameter Value Conditions1 Unit Min Typ Max Push Pull IOH = 3.8 mA, VOH CC C Output high level MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD — — P IOH = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) 0.8VDD — — C IOH = 1 mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 0.8VDD — — C IOH = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) VDD 0.8 — — C IOH = 100 µA, VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD — — VOL CC C Output low level Push Pull IOL = 3.8 mA, MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.2VDD P IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) — — 0.1VDD C IOL = 1 mA, VDD = 5.0 V ± 10%, PAD3V5V = 1(2) — — 0.1VDD C IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) — — C IOH = 100 µA, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD 1 2 V V 0.5 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET are configured in input or in high impedance state. MPC5602D Microcontroller Data Sheet, Rev. 3.1 28 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 4.7.4 Output pin transition times Table 15. Output pin transition times Symbol C Value2 Conditions1 Parameter Unit Min Typ Max Ttr CC D Output transition time output pin3 CL = 25 pF SLOW configuration T CL = 50 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 50 — — 100 — — 125 D CL = 100 pF D CL = 25 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 — T CL = 50 pF — — 100 D CL = 100 pF — — 125 Ttr CC D Output transition time output pin(3) CL = 25 pF MEDIUM configuration T CL = 50 pF D CL = 100 pF D CL = 25 pF T CL = 50 pF D CL = 100 pF — ns 50 VDD = 5.0 V ± 10%, PAD3V5V = 0 — SIUL.PCRx.SRC = 1 — — 10 — 20 — — 40 VDD = 3.3 V ± 10%, PAD3V5V = 1 — SIUL.PCRx.SRC = 1 — — 12 — 25 — — 40 ns VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 3 C includes device and package capacitances (C L PKG < 5 pF). 1 2 4.7.5 I/O pad current specification The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 16. Table 17 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. Table 16. I/O supply segment Supply segment Package 1 2 3 4 100 LQFP pin 16 – pin 35 pin 37 – pin 69 pin 70 – pin 83 pin 84 – pin 15 64 LQFP pin 8 – pin 26 pin 28 – pin 55 pin 56 – pin 7 — MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 29 Electrical characteristics Table 17. I/O consumption Symbol ISWTSLW,3 ISWTMED(3) IRMSSLW C Typ Max VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 20 VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 16 VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 29 VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 17 VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 2.3 — — 3.2 — — 6.6 — — 1.6 — — 2.3 — — 4.7 — — 6.6 — — 13.4 — — 18.3 — — 5 — — 8.5 CL = 100 pF, 13 MHz — — 11 VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 70 VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 65 CC D Dynamic I/O current for SLOW configuration CL = 25 pF CC D Dynamic I/O current for MEDIUM configuration CL = 25 pF CC D Root medium square CL = 25 pF, 2 MHz I/O current for SLOW CL = 25 pF, 4 MHz configuration CL = 100 pF, 2 MHz CL = 25 pF, 4 MHz VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100 pF, 2 MHz CC D Root medium square CL = 25 pF, 13 MHz VDD = 5.0 V ± 10%, I/O current for PAD3V5V = 0 CL = 25 pF, 40 MHz MEDIUM configuration CL = 100 pF, 13 MHz CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz IAVGSEG SR D Sum of all the static I/O current within a supply segment Unit Min CL = 25 pF, 2 MHz IRMSMED Value2 Conditions1 Parameter VDD = 3.3 V ± 10%, PAD3V5V = 1 mA mA mA mA mA VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 3 Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. 1 2 Table 18 provides the weight of concurrent switching I/Os. In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain below 100%. MPC5602D Microcontroller Data Sheet, Rev. 3.1 30 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 18. I/O weight1 100/64 LQFP PAD Weight 5V SRC = 0 Weight 5V SRC = 1 Weight 3.3V SRC = 0 Weight 3.3V SRC = 1 PB[3] 9% 9% 10% 10% PC[9] 8% 8% 10% 10% PC[14] 8% 8% 10% 10% PC[15] 8% 11% 9% 10% PA[2] 8% 8% 9% 9% PE[0] 7% 7% 9% 9% PA[1] 7% 7% 8% 8% PE[1] 7% 10% 8% 8% PE[8] 6% 9% 8% 8% PE[9] 6% 6% 7% 7% PE[10] 6% 6% 7% 7% PA[0] 5% 7% 6% 7% PE[11] 5% 5% 6% 6% PC[11] 7% 7% 9% 9% PC[10] 8% 11% 9% 10% PB[0] 8% 11% 9% 10% PB[1] 8% 8% 10% 10% PC[6] 8% 8% 10% 10% PC[7] 8% 8% 10% 10% PA[15] 8% 11% 9% 10% PA[14] 7% 11% 9% 9% PA[4] 7% 7% 8% 8% PA[13] 7% 10% 8% 9% PA[12] 7% 7% 8% 8% PB[9] 1% 1% 1% 1% PB[8] 1% 1% 1% 1% PB[10] 5% 5% 6% 6% PD[0] 1% 1% 1% 1% PD[1] 1% 1% 1% 1% PD[2] 1% 1% 1% 1% PD[3] 1% 1% 1% 1% PD[4] 1% 1% 1% 1% PD[5] 1% 1% 1% 1% MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 31 Electrical characteristics Table 18. I/O weight1 (continued) 100/64 LQFP PAD Weight 5V SRC = 0 Weight 5V SRC = 1 Weight 3.3V SRC = 0 Weight 3.3V SRC = 1 PD[6] 1% 1% 1% 1% PD[7] 1% 1% 1% 1% PD[8] 1% 1% 1% 1% PB[4] 1% 1% 1% 1% PB[5] 1% 1% 1% 1% PB[6] 1% 1% 1% 1% PB[7] 1% 1% 1% 1% PD[9] 1% 1% 1% 1% PD[10] 1% 1% 1% 1% PD[11] 1% 1% 1% 1% PB[11] 9% 9% 11% 11% PD[12] 8% 8% 10% 10% PB[12] 8% 8% 10% 10% PD[13] 8% 8% 9% 9% PB[13] 8% 8% 9% 9% PD[14] 7% 7% 9% 9% PB[14] 7% 7% 8% 8% PD[15] 7% 7% 8% 8% PB[15] 6% 6% 7% 7% PA[3] 6% 6% 7% 7% PA[7] 4% 4% 5% 5% PA[8] 4% 4% 5% 5% PA[9] 4% 4% 5% 5% PA[10] 5% 5% 6% 6% PA[11] 5% 5% 6% 6% PE[12] 5% 5% 6% 6% PC[3] 5% 5% 6% 6% PC[2] 5% 7% 6% 6% PA[5] 5% 6% 5% 6% PA[6] 4% 4% 5% 5% PC[1] 5% 17% 4% 12% PC[0] 6% 9% 7% 8% PE[2] 7% 10% 8% 9% MPC5602D Microcontroller Data Sheet, Rev. 3.1 32 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 18. I/O weight1 (continued) 100/64 LQFP PAD 1 Weight 5V SRC = 0 Weight 5V SRC = 1 Weight 3.3V SRC = 0 Weight 3.3V SRC = 1 PE[3] 7% 10% 9% 9% PC[5] 8% 11% 9% 10% PC[4] 8% 11% 9% 10% PE[4] 8% 12% 10% 10% PE[5] 8% 12% 10% 11% PE[6] 9% 12% 10% 11% PE[7] 9% 12% 10% 11% PC[12] 9% 13% 11% 11% PC[13] 9% 9% 11% 11% PC[8] 9% 9% 11% 11% PB[2] 9% 13% 11% 12% VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 33 Electrical characteristics 4.8 RESET electrical characteristics The device implements a dedicated bidirectional RESET pin. Figure 5. Start-up reset requirements VDD VDDMIN RESET VIH VIL device reset forced by RESET device start-up phase Figure 6. Noise filtering on reset signal VRESET hw_rst VDD ‘1’ VIH VIL ‘0’ filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter unknown reset state device under hardware reset WFRST WNFRST MPC5602D Microcontroller Data Sheet, Rev. 3.1 34 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 19. Reset electrical characteristics Symbol C Parameter Value2 Conditions1 Unit Min Typ Max VIH SR P Input High Level CMOS (Schmitt Trigger) — 0.65VDD — VDD + 0.4 V VIL SR P Input low Level CMOS (Schmitt Trigger) — 0.4 — 0.35VDD V VHYS CC C Input hysteresis CMOS (Schmitt Trigger) — 0.1VDD — — V Push Pull, IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) — — 0.1VDD V Push Pull, IOL = 1 mA, VDD = 5.0 V ± 10%, PAD3V5V = 13 — — 0.1VDD Push Pull, IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) — — 0.5 CL = 25 pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 10 CL = 50 pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 20 CL = 100 pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 40 CL = 25 pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 12 CL = 50 pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 25 CL = 100 pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 40 VOL Ttr CC P Output low level CC D Output transition time output pin4 MEDIUM configuration ns WFRST SR P RESET input filtered pulse — — — 40 ns WNFRST SR P RESET input not filtered pulse — 1000 — — ns VDD = 3.3 V ± 10%, PAD3V5V = 1 10 — 150 µA VDD = 5.0 V ± 10%, PAD3V5V = 0 10 — 150 VDD = 5.0 V ± 10%, PAD3V5V = 15 10 — 250 |IWPU| CC P Weak pull-up current absolute value VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 3 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the device reference manual). 4 CL includes device and package capacitance (CPKG < 5 pF). 5 The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET are configured in input or in high impedance state. 1 2 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 35 Electrical characteristics 4.9 Power management electrical characteristics 4.9.1 Voltage regulator electrical characteristics The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved: • • • HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD power pin. BV: High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV power pin. Voltage values should be aligned with VDD. LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the internal voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure noise isolation between critical LV modules within the device: — LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding. — LV_CFLA: Low voltage supply for Code Flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. — LV_DFLA: Low voltage supply for Data Flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. — LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding. Figure 7. Voltage regulator capacitance connection CREG2 (LV_COR/LV_CFLA) GND VDD VSS_LV VDD_BV Voltage Regulator I VSS_LVn VDD_BV CREG1 (LV_COR/LV_DFLA) VDD_LVn CDEC1 (Ballast decoupling) VREF VDD_LV VDD_LV DEVICE VSS_LV GND VSS_LV DEVICE GND VSS VDD_LV VDD GND CREG3 (LV_COR/LV_PLL) CDEC2 (supply/IO decoupling) The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH. MPC5602D Microcontroller Data Sheet, Rev. 3.1 36 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see Section 4.5, “Recommended operating conditions). Table 20. Voltage regulator electrical characteristics Symbol C Parameter Typ Max SR — Internal voltage regulator external capacitance — 200 — 500 nF RREG SR — Stability capacitor equivalent serial resistance — — — 0.2 CDEC1 SR — Decoupling capacitance3 ballast VDD_BV/VSS_LV pair: VDD_BV = 4.5 V to 5.5 V 1004 4705 — nF VDD_BV/VSS_LV pair: VDD_BV = 3 V to 3.6 V 400 — CDEC2 SR — Decoupling capacitance regulator supply VDD/VSS pair 10 100 — nF VMREG CC T Main regulator output voltage Before exiting from reset — 1.32 — V TBD 1.28 TBD — — 150 mA mA IMREG IMREGINT After trimming SR — Main regulator current provided to VDD_LV domain — CC D Main regulator module current consumption IMREG = 200 mA — — 2 IMREG = 0 mA — — 1 VLPREG CC P Low power regulator output voltage After trimming TBD 1.23 TBD V ILPREG SR — Low power regulator current provided to VDD_LV domain — — 15 mA — — 600 µA ILPREG = 0 mA; TA = 55 °C — 5 — After trimming TBD 1.23 TBD V — — 5 mA IULPREG = 5 mA; TA = 55 °C — — 100 µA IULPREG = 0 mA; TA = 55 °C — 2 — — — 4006 ILPREGINT VULPREG CC P Ultra low power regulator output voltage IULPREG SR — Ultra low power regulator current provided to VDD_LV domain IULPREGINT CC D Ultra low power regulator module current consumption IDD_BV — CC D Low power regulator module current ILPREG = 15 mA; consumption TA = 55 °C — 2 Unit Min CREGn P 1 Value2 Conditions1 CC D In-rush current on VDD_BV during power-up — — mA VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 37 Electrical characteristics 3 This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical value is in the range of 470 nF. 4 This value is acceptable to guarantee operation from 4.5 V to 5.5 V. 5 External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in operating range. 6 In-rush current is seen only for short time during power-up and on standby exit (max 20 µs, depending on external capacitances to be load). 4.9.2 Voltage monitor electrical characteristics The device implements a power-on reset (POR) module to ensure correct power-up initialization, as well as four low voltage detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied: • • • • • POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state LVDHV3 monitors VDD to ensure device reset below minimum functional supply LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range LVDLVCOR monitors power domain No. 1 LVDLVBKP monitors power domain No. 0 NOTE When enabled, power domain No. 2 is monitored through LVD_DIGBKP. Figure 8. Low voltage monitor vs. reset VDD VLVDHVxH VLVDHVxL RESET MPC5602D Microcontroller Data Sheet, Rev. 3.1 38 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 21. Low voltage monitor electrical characteristics Symbol C VPORUP SR P Supply for functional POR module VPORH CC P Power-on reset threshold Value2 Conditions1 Parameter Unit Min Typ Max 1.0 — 5.5 1.5 — 2.6 — 1.5 — 2.6 — TA = 25 °C, after trimming T VLVDHV3H CC T LVDHV3 low voltage detector high threshold — — — 2.9 VLVDHV3L CC P LVDHV3 low voltage detector low threshold — 2.6 — TBD — — — 4.4 — 3.8 — TBD VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold — 1.08 — — VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold — 1.08 — 1.11 VLVDHV5H3 CC T LVDHV5 low voltage detector high threshold VLVDHV5L CC P LVDHV5 low voltage detector low threshold V VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 3 Data based on characterization results, not tested in production 1 2 4.10 Low voltage domain power consumption Table 22 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application. Table 22. Low voltage power domain electrical characteristics Symbol C Typ Max — — 100 TBD3 mA fCPU = 8 MHz — TBD — fCPU = 16 MHz — TBD — T fCPU = 32 MHz — TBD — P fCPU = 48 MHz — TBD — Slow internal RC oscillator TA = 25 °C (128 kHz) running TA = 125 °C — TBD TBD — TBD TBD — 150 TBD8 D Slow internal RC oscillator TA = 25 °C (128 kHz) running TA = 55 °C — TBD — D TA = 85 °C — TBD — D TA = 105 °C — TBD — P TA = 125 °C — TBD TBD8 CC D RUN mode maximum average current IDDRUN4 CC T RUN mode typical average current5 T CC C HALT mode current6 P IDDSTOP Unit Min IDDMAX2 IDDHALT Value Conditions1 Parameter CC P STOP mode current 7 mA mA µA mA MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 39 Electrical characteristics Table 22. Low voltage power domain electrical characteristics (continued) Symbol IDDSTDBY 1 2 3 4 5 6 7 8 9 C Parameter Value Conditions1 Unit Min Typ Max CC P STANDBY mode current9 Slow internal RC oscillator TA = 25 °C (128 kHz) running D TA = 55 °C — 25 TBD — TBD — D TA = 85 °C — — D TA = 105 °C — — P TA = 125 °C — TBD µA VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified Running consumption is given on voltage regulator supply (VDDREG). It does not include consumption linked to I/Os toggling. This value is highly dependent on the application. The given value is thought to be a worst case value with all peripherals running, and code fetched from Code Flash while modify operation on-going on Data Flash. Note that this value can be significantly reduced by application: switch off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from SRAM most used functions, use low power mode when possible. Higher current may be sinked by device during power-up and standby exit. Please refer to in rush current on Table 20. RUN current measured with typical application with accesses on both Flash and SRAM. Only for the “P” classification: Code fetched from SRAM: Serial IPs CAN and LIN in loop back mode, DSPI as Master, PLL as system clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer reset enabled. Data Flash Power Down. Code Flash in Low Power. RC-OSC 128 kHz & RC-OSC 16 MHz on. 10 MHz XTAL clock. FlexCAN: 0 ON (clocked but no reception or transmission). LINFlex: instances: 0, 1, 2 ON (clocked but no reception or transmission), instance: 3 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but no conversion except 2 analog watchdogs. Only for the “P” classification: No clock, RC-OSC 16 MHz off, RC-OSC 128 kHz on, PLL off, HPVreg off, ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode. When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA. Only for the “P” classification: ULPVreg on, HP/LPVreg off, 16 KB SRAM on, device configured for minimum consumption, all possible modules switched off. 4.11 Flash memory electrical characteristics The Data Flash operation depends strongly on the Code Flash operation. If Code Flash is switched-off, the Data Flash is disabled. 4.11.1 Program/Erase characteristics Table 23 shows the program and erase characteristics. MPC5602D Microcontroller Data Sheet, Rev. 3.1 40 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 23. Program and erase specifications (Code Flash) Value Symbol Tdwprogram C Parameter CC C Double word (64 bits) program time4 Unit Min Typ1 Initial max2 Max3 — 22 50 500 µs T16KpperaseC 16 KB block preprogram and erase time — 300 500 5000 ms T32KpperaseC 32 KB block preprogram and erase time — 400 600 5000 ms T128KpperaseC 128 KB block preprogram and erase time — 800 1300 7500 ms TBD TBD TBD TBD µs Erase suspend latency Tesus 1 Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization. 2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. 3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead. Table 24. Program and erase specifications (Data Flash) Value Symbol C Parameter Tswprogram CC C Single word (32 bits) program time4 Unit Min Typ1 Initial max2 Max3 — 30 70 300 µs T16Kpperase 16 KB block preprogram and erase time — 700 800 1500 ms TBank_D 64 KB block preprogram and erase time — 1900 2300 4800 ms 1 Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization. 2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. 3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 41 Electrical characteristics Table 25. Flash module life Value Symbol C Parameter Conditions 1 Typ Max P/E CC C Number of program/erase cycles per block for 16 KB blocks over the operating temperature range (TJ) — 100 — — kcycles P/E CC C Number of program/erase cycles per block for 32 KB blocks over the operating temperature range (TJ) — 10 1001 — kcycles P/E CC C Number of program/erase cycles per block for 128 KB blocks over the operating temperature range (TJ) — 1 100(1) — kcycles Blocks with 0–1,000 P/E cycles 20 — — years Blocks with 1,001–10,000 P/E cycles 10 — — years Blocks with 10,001–100,000 P/E cycles 5 — — years Retention CC C Minimum data retention at 85 °C average ambient temperature2 2 Unit Min To be confirmed Ambient temperature averaged over application duration. It is recommended not to exceed the product operating temperature range. ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability. Table 26. Flash read access timing Symbol fREAD 1 C CC Parameter Conditions1 Max Unit MHz P Maximum frequency for Flash reading 2 wait states 48 C 1 wait state 40 C 0 wait states 20 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 4.11.2 Flash power supply DC characteristics Table 27 shows the power supply DC characteristics on external supply. NOTE Power supply for Data Flash is actually provided by Code Flash, this means that Data Flash cannot work if Code Flash is not powered. MPC5602D Microcontroller Data Sheet, Rev. 3.1 42 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 27. Flash power supply DC electrical characteristics Symbol C Parameter Value2 Conditions1 Unit Min Typ Max ICFREAD CC D Sum of the current consumption on Flash module read VDDHV and VDDBV on read access fCPU = 48 MHz IDFREAD Code Flash — — 33 Data Flash — — 4 Code Flash — ICFMOD CC D Sum of the current consumption on Program/Erase on-going while reading Flash registers, VDDHV and VDDBV on matrix IDFMOD Data Flash — modification (program/erase) fCPU = 48 MHz — 33 — 6 mA mA CC D Sum of the current consumption on VDDHV and VDDBV during Flash low-power mode — Code Flash — — 910 µA ICFPWD CC D Sum of the current consumption on VDDHV and VDDBV during IDFPWD Flash power-down mode — Code Flash — — 125 µA Data Flash — IFLPW 1 2 — 25 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 4.11.3 Start-up/Switch-off timings Table 28. Start-up time/Switch-off time Symbol TFLARSTEXIT C Parameter CC T Delay for Flash module to exit reset mode Value Conditions1 Unit Min Typ Max Code Flash — — 125 Data Flash — — 150 TFLALPEXIT CC T Delay for Flash module to exit low-power mode2 Code Flash — — 0.5 TFLAPDEXIT CC T Delay for Flash module to exit power-down mode Code Flash — — 30 TFLALPENTRY CC T Delay for Flash module to enter low-power mode Code Flash — — 0.5 TFLAPDENTRY CC T Delay for Flash module to enter power-down mode Code Flash — — 1.5 Data Flash — — 4(3) µs 303 Data Flash VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified Data Flash does not support low-power mode 3 If Code Flash is already switched-on. 1 2 4.12 Electromagnetic compatibility (EMC) characteristics Susceptibility tests are performed on a sample basis during product characterization. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 43 Electrical characteristics 4.12.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: — Corrupted program counter — Unexpected reset — Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. • • 4.12.2 Electromagnetic interference (EMI) The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1 standard, which specifies the general conditions for EMI measurements. Table 29. EMI radiated emission measurement1,2 Value Symbol C Parameter Conditions Unit Min Typ — 0.150 — fCPU SR — Operating frequency — — 48 — MHz VDD_LV SR — LV operating voltages — — 1.28 — V No PLL frequency VDD = 5 V, TA = 25 °C, modulation 100 LQFP package Test conforming to IEC 61967-2, ± 2% PLL frequency fOSC = 8 MHz/fCPU = 48 MHz modulation — — TBD dBµV — — TBD3 dBµV — SR — Scan range SEMI CC T Peak level Max 1000 MHz 1 EMI testing and I/O port waveforms per IEC 61967-1, -2, -4 For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local marketing representative. 3 All values need to be confirmed during device validation 2 4.12.3 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 4.12.3.1 Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts * (n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. MPC5602D Microcontroller Data Sheet, Rev. 3.1 44 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 30. ESD absolute maximum ratings1 2 Symbol C Ratings Conditions Class Max value Unit V VESD(HBM) CC T Electrostatic discharge voltage (Human Body Model) TA = 25 °C conforming to AEC-Q100-002 H1C 2000 VESD(MM) CC T Electrostatic discharge voltage (Machine Model) TA = 25 °C conforming to AEC-Q100-003 M2 200 VESD(CDM) CC T Electrostatic discharge voltage (Charged Device Model) TA = 25 °C conforming to AEC-Q100-011 C3A 500 750 (corners) 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 4.12.3.2 Static latch-up (LU) Two complementary static tests are required on six parts to assess the latch-up performance: • • A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with the EIA/JESD 78 IC latch-up standard. Table 31. Latch-up results Symbol LU 4.13 CC C Parameter T Static latch-up class Conditions TA = 125 °C conforming to JESD 78 Class II level A Fast external crystal oscillator (4 to 16 MHz) electrical characteristics The device provides an oscillator/resonator driver. Figure 9 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 45 Electrical characteristics Table 32 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations. Figure 9. Crystal oscillator and resonator connection scheme EXTAL C1 Crystal EXTAL XTAL C2 DEVICE VDD I R EXTAL XTAL Resonator DEVICE XTAL DEVICE Note: XTAL/EXTAL must not be directly used to drive external circuits. MPC5602D Microcontroller Data Sheet, Rev. 3.1 46 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 32. Crystal description Crystal motional capacitance (Cm) fF Crystal motional inductance (Lm) mH Load on xtalin/xtalout C1 = C2 (pF)1 Shunt capacitance between xtalout and xtalin C02 (pF) Nominal frequency (MHz) NDK crystal reference Crystal equivalent series resistance ESR 4 NX8045GB 300 2.68 591.0 21 2.93 8 NX5032GA 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 1 The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them. 2 The value of C specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, 0 package, etc.). Figure 10. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics S_MTRANS bit (ME_GS register) ‘1’ ‘0’ VXTAL 1/fFXOSC VFXOSC 90% VFXOSCOP 10% TFXOSCSU valid internal clock MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 47 Electrical characteristics Table 33. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics Symbol C Parameter Value2 Conditions1 Unit Min Typ Max fFXOSC SR — Fast external crystal oscillator frequency — 4.0 — 16.0 MHz FXOSC CC T Fast external crystal oscillator frequency duty cycle — 30 — 70 % tFXJIT CC T Fast external crystal oscillator jitter — — — TBD ns gmFXOSC CC C Fast external crystal oscillator transconductance VDD = 3.3 V ± 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 0 2.2 — 8.2 mA/V CC P VDD = 5.0 V ± 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 0 2.0 — 7.4 CC C VDD = 3.3 V ± 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 1 2.7 — 9.7 CC C VDD = 5.0 V ± 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 1 2.5 — 9.2 CC T Oscillation amplitude at EXTAL fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 1.3 — — fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 1.3 — — — — 0.95 VFXOSC VFXOSCOP CC P Oscillation operating point V V IFXOSC,3 CC T Fast external crystal oscillator consumption — — 2 3 mA TFXOSCSU CC T Fast external crystal oscillator start-up time fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 — — 6 ms fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 — — 1.8 VIH SR P Input high level CMOS (Schmitt Trigger) Oscillator bypass mode 0.65VDD — VDD+0.4 V VIL SR P Input low level CMOS (Schmitt Trigger) Oscillator bypass mode 0.4 — 0.35VDD V VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All values need to be confirmed during device validation. 3 Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals) 1 2 MPC5602D Microcontroller Data Sheet, Rev. 3.1 48 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 4.14 FMPLL electrical characteristics The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver. Table 34. FMPLL electrical characteristics Symbol C Value2 1 Parameter Conditions Unit Min Typ Max fPLLIN SR — FMPLL reference clock3 — 4 — 48 MHz PLLIN SR — FMPLL reference clock duty cycle(3) — 40 — 60 % — 16 — 48 MHz — 256 — 512 MHz — 245.76 — 532.48 fPLLOUT CC D FMPLL output clock frequency fVCO4 CC P VCO frequency without frequency modulation VCO frequency with frequency modulation fCPU SR — System clock frequency — — — 48 MHz fFREE CC P Free-running frequency — 20 — 150 MHz tLOCK CC P FMPLL lock time Stable oscillator (fPLLIN = 16 MHz) — 40 100 µs fPLLIN = 16 MHz (resonator), fPLLCLK at 48 MHz, 4,000 cycles — — 10 ns TA = 25 °C — — 4 mA tLTJIT CC — FMPLL long term jitter IPLL CC C FMPLL consumption VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN. 4 Frequency modulation is considered ±4%. 1 2 4.15 Fast internal RC oscillator (16 MHz) electrical characteristics The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up of the device. Table 35. Fast internal RC oscillator (16 MHz) electrical characteristics Symbol Parameter CC P Fast internal RC oscillator high TA = 25 °C, trimmed frequency SR — — fFIRC IFIRCRUN C 3, IFIRCPWD Value2 Conditions1 Unit Min Typ Max — 16 — 12 MHz 20 CC T Fast internal RC oscillator high TA = 25 °C, trimmed frequency current in running mode — — 200 µA CC D Fast internal RC oscillator high TA = 25 °C frequency current in power down mode — — 10 µA MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 49 Electrical characteristics Table 35. Fast internal RC oscillator (16 MHz) electrical characteristics (continued) Symbol C Parameter Conditions Unit Min Typ Max sysclk = off — 500 — sysclk = 2 MHz — 600 — sysclk = 4 MHz — 700 — sysclk = 8 MHz — 900 — sysclk = 16 MHz — 1250 — VDD = 5.0 V ± 10% — 1.1 2.0 VDD = 3.3 V ± 10% — 1.2 TBD — TA = 125 °C VDD = 5.0 V ± 10% — — 2.0 — VDD = 3.3 V ± 10% — — TBD 1 IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 °C frequency and system clock current in stop mode TFIRCSU Value2 1 CC C Fast internal RC oscillator start-up time — TA = 55 °C CC C Fast internal RC oscillator precision after software trimming of fFIRC TA = 25 °C 1 — FIRCTRIM CC C Fast internal RC oscillator trimming step TA = 25 °C — 1.6 5 — FIRCPRE FIRCVAR CC C Fast internal RC oscillator variation in temperature and supply with respect to fFIRC at TA = 55 °C in high-frequency configuration — µA µs % % 5 % VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 1 2 4.16 Slow internal RC oscillator (128 kHz) electrical characteristics The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the RTC module. Table 36. Slow internal RC oscillator (128 kHz) electrical characteristics Symbol C Parameter CC P Slow internal RC oscillator low frequency SR — TA = 25 °C, trimmed ISIRC3, CC C Slow internal RC oscillator low frequency current TA = 25 °C, trimmed TSIRCSU CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ± 10% time fSIRC Value2 Conditions1 — Unit Min Typ Max — 128 — 100 — 150 — — 5 µA — 8 12 µs kHz MPC5602D Microcontroller Data Sheet, Rev. 3.1 50 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 36. Slow internal RC oscillator (128 kHz) electrical characteristics (continued) Symbol C Parameter Value2 1 Conditions SIRCPRE CC C Slow internal RC oscillator precision TA = 25 °C after software trimming of fSIRC SIRCTRIM CC C Slow internal RC oscillator trimming step SIRCVAR CC P Slow internal RC oscillator variation High frequency configuration in temperature and supply with respect to fSIRC at TA = 55 °C in high frequency configuration — Unit Min Typ Max 2 — 2 — 2.7 — 10 — 10 % % VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 1 2 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 51 Electrical characteristics 4.17 4.17.1 ADC electrical characteristics Introduction The device provides a 12-bit Successive Approximation Register (SAR) analog-to-digital converter. Figure 11. ADC characteristic and error definitions Offset Error OSE Gain Error GE 1023 1022 1021 1020 1019 1 LSB ideal = VDD_ADC / 1024 1018 (2) code out 7 (1) 6 (1) Example of an actual transfer curve 5 (2) The ideal transfer curve (5) (3) Differential non-linearity error (DNL) 4 (4) Integral non-linearity error (INL) (4) (5) Center of a step of the actual transfer curve 3 (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal) Offset Error OSE 4.17.2 Input impedance and ADC accuracy In the following analysis, the input circuit corresponding to the precise channels is considered. To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as MPC5602D Microcontroller Data Sheet, Rev. 3.1 52 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fc*CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 4: Eqn. 4 R S + R F + R L + R SW + R AD V A --------------------------------------------------------------------------- 1 --- LSB R EQ 2 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 53 Electrical characteristics Equation 4 generates a constraint for external network design, in particular on a resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. Figure 12. Input equivalent circuit (precise channels) EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source Filter RS Current Limiter RF VA Channel Selection Sampling RSW1 RAD RL CF CP1 CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance Current Limiter Resistance RL RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 13. Input equivalent circuit (extended channels) EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source RS Filter RF RL CF VA RS RF CF RL RSW RAD CP CS Current Limiter CP1 Channel Selection Extended Switch Sampling RSW1 RSW2 RAD CP3 CP2 CS Source Impedance Filter Resistance Filter Capacitance Current Limiter Resistance Channel Selection Switch Impedance (two contributions RSW1 and RSW2) Sampling Switch Impedance Pin Capacitance (three contributions, CP1, CP2 and CP3) Sampling Capacitance MPC5602D Microcontroller Data Sheet, Rev. 3.1 54 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit in Figure 13): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close). Figure 14. Transient behavior during sampling phase Voltage transient on CS VCS VA VA2 V <0.5 LSB 1 2 1 < (RSW + RAD) CS << TS 2 = RL (CS + CP1 + CP2) VA1 TS t In particular two different transient periods can be distinguished: 1. A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is CP CS 1 = R SW + R AD --------------------CP + CS Eqn. 5 Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS is always much longer than the internal time constant: Eqn. 6 1 R SW + R AD C S « T S The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to Equation 7: Eqn. 7 V A1 C S + C P1 + C P2 = V A C P1 + C P2 2. A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is: MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 55 Electrical characteristics Eqn. 8 2 R L C S + C P1 + C P2 In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraints on RL sizing is obtained: Eqn. 9 10 2 = 10 R L C S + C P1 + C P2 TS Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge balance assuming now CS already charged at VA1): Eqn. 10 VA2 C S + C P1 + C P2 + C F = V A C F + V A1 C P1 + C P2 + C S The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing. Figure 15. Spectral representation of input signal Analog source bandwidth (VA) Noise TC < 2 RFCF (conversion rate vs. filter pole) fF = f0 (anti-aliasing filtering condition) 2 f0 < fC (Nyquist) f0 f Anti-aliasing filter (fF = RC filter pole) fF f Sampled signal spectrum (fC = conversion rate) f0 fC f Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS: MPC5602D Microcontroller Data Sheet, Rev. 3.1 56 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Eqn. 11 VA C P1 + C P2 + C F ------------ = -------------------------------------------------------V A2 C P1 + C P2 + C F + C S From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count, a constraint is evident on CF value: Eqn. 12 C F 2048 C S 4.17.3 ADC electrical characteristics Table 37. ADC input leakage current Value Symbol C Parameter Conditions Unit Min Typ Max ILKG CC C Input leakage current TA = 40 °C No current injection on adjacent pin — 1 — C TA = 25 °C — 1 — C TA = 105 °C — 8 200 P TA = 125 °C — 45 400 nA Table 38. ADC conversion characteristics Symbol C Parameter Value Conditions1 Unit Min Typ Max VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS)2 — 0.1 — 0.1 V VDD_ADC SR — Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) — VDD 0.1 — VDD + 0.1 V VAINx SR — Analog input voltage3 — VSS_ADC 0.1 — fADC SR — ADC analog frequency VDD = 5.0 V 3.33 — 32 + 4% VDD = 3.3 V ADC_SYS SR — ADC clock duty cycle ADCLKSEL = (ipg_clk) tADC_PU SR — ADC power up delay VDD_ADC + 0.1 V MHz 3.33 — 20 + 4% 14 45 — 55 % — — — 1.5 µs MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 57 Electrical characteristics Table 38. ADC conversion characteristics (continued) Symbol C Parameter Value Conditions1 Unit Min Typ Max tADC_S CC T Sample time5 VDD = 3.3 V fADC = 20 MHz, INPSAMP = 12 600 — — T Sample time5 VDD = 5.0 V fADC = 32 MHz, INPSAMP = 17 500 — — T Sample time5 VDD = 3.3 V fADC = 3.33 MHz, INPSAMP = 255 — — 76.2 T Sample time5 VDD = 5.0 V fADC = 3.33 MHz, INPSAMP = 255 — — 76.2 fADC = 20 MHz, INPCMP = 0 2.4 — — µs P Conversion time6 VDD = 5.0 V fADC = 13.33 MHz, INPCMP = 0 1.5 — — µs P Conversion time6 VDD = 3.3 V fADC = 13.33 MHz, INPCMP = 0 — — 3.6 µs P Conversion time6 VDD = 5.0 V fADC = 32 MHz, INPCMP = 0 — — 3.6 µs tADC_C CC P Conversion time6 VDD = 3.3 V ns µs CS CC D ADC input sampling capacitance — 5 pF CP1 CC D ADC input pin capacitance 1 — 3 pF CP2 CC D ADC input pin capacitance 2 — 1 pF CP3 CC D ADC input pin capacitance 3 — 1.5 pF RSW1 CC D Internal resistance of analog source — — — 1 k RSW2 CC D Internal resistance of analog source — — — 2 k RAD CC D Internal resistance of analog source — — — 0.3 k IINJ SR — Input current Injection Current injection on one ADC input, different from the converted one VDD = 3.3 V ± 10% 5 — 5 mA VDD = 5.0 V ± 10% 5 — 5 INLP CC T Absolute Integral non-linearity-precise channels No overload — 1 3 LSB INLX CC T Absolute Integral No overload non-linearity-extended channels — 1.5 5 LSB MPC5602D Microcontroller Data Sheet, Rev. 3.1 58 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 38. ADC conversion characteristics (continued) Symbol 1 2 3 4 5 6 7 C Parameter Value Conditions1 No overload Unit Min Typ Max — 0.5 1 LSB DNL CC T Absolute Differential non-linearity OFS CC T Absolute Offset error — — 2 — LSB GNE CC T Absolute Gain error — — 2 — LSB LSB TUEP7 CC P Total unadjusted error Without current injection for precise channels, T With current injection input only pins –6 6 –8 8 TUEX7 CC T Total unadjusted error Without current injection for extended channel T With current injection –10 10 –12 12 LSB VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. Analog and digital VSS must be common (to be tied together externally). VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0xFFF. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal divider by 2. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC_S depend on programming. This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the time to load the result’s register with the conversion result. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a combination of Offset, Gain and Integral Linearity errors. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 59 Electrical characteristics 4.18 On-chip peripherals 4.18.1 Current consumption Table 39. On-chip peripherals current consumption1 Value2 Symbol C Parameter Conditions Unit Typ IDD_BV(CAN) IDD_BV(eMIOS) CC T CAN (FlexCAN) supply 500 Kbps current on VDD_BV 125 Kbps CC T eMIOS supply current on VDD_BV Total (static + dynamic) consumption: • FlexCAN in loop-back mode • XTAL at 8 MHz used as CAN engine clock source • Message sending period is 580 µs Static consumption: • eMIOS channel OFF • Global prescaler enabled Dynamic consumption: • It does not change varying the frequency (0.003 mA) IDD_BV(SCI) CC T SCI (LINFlex) supply current on VDD_BV Total (static + dynamic) consumption: • LIN mode • Baudrate: 20 Kbps IDD_BV(SPI) CC T SPI (DSPI) supply current on VDD_BV Ballast static consumption (only clocked) IDD_BV(ADC) Ballast dynamic consumption (continuous communication): • Baudrate: 2 Mbit • Transmission every 8 µs • Frame: 16 bits CC T ADC supply current on VDD = 5.5 V Ballast static consumption VDD_BV (no conversion) VDD = 5.5 V Ballast dynamic consumption (continuous conversion)3 IDD_HV_ADC(ADC) CC T ADC supply current on VDD = 5.5 V Analog static consumption VDD_HV_ADC (no conversion) VDD = 5.5 V Analog dynamic consumption (continuous conversion) IDD_HV(FLASH) IDD_HV(PLL) 8 * fperiph + 85 µA 8 * fperiph + 27 29 * fperiph 3 5 * fperiph + 31 1 16 * fperiph 41 * fperiph µA 5 * fperiph 2 * fperiph 75 * fperiph + 32 CC T CFlash + DFlash supply current on VDD_HV VDD = 5.5 V — TBD CC T PLL supply current on VDD_HV VDD = 5.5 V — 30 * fperiph MPC5602D Microcontroller Data Sheet, Rev. 3.1 60 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 1 Operating conditions: TA = 25 °C, fperiph = 8 MHz to 48 MHz fperiph is in absolute value. 3 During the conversion, the total current consumption is given from the sum of the static and dynamic consumption, i.e., (41 + 5) * fperiph 2 MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 61 Electrical characteristics 4.18.2 DSPI characteristics Table 40. DSPI characteristics1 DSPI0/DSPI1 No. 1 Symbol tSCK C SR Parameter Unit Min Typ Max D SCK cycle time Master mode (MTFE = 0) 125 — — ns D Slave mode (MTFE = 0) 125 — — D Master mode (MTFE = 1) 83 — — D Slave mode (MTFE = 1) 83 — — — — fCPU MHz ns — fDSPI — tCSC CC D Internal delay between pad associated to SCK and pad associated to CSn in master mode Master mode — — 1302 — tASC CC D Internal delay between pad associated to SCK and pad associated to CSn in master mode for CSn11 Master mode — — 130(2) ns 2 tCSCext3 SR D CS to SCK delay Slave mode 32 — — ns 3 tASCext4 SR D After SCK delay Slave mode 1/fDSPI + 5 — — ns 4 tSDC CC D SCK duty cycle Master mode — tSCK/2 — ns SR D Slave mode tSCK/2 — — SR D DSPI digital controller frequency 5 tA SR D Slave access time — 1/fDSPI + 70 — — ns 6 tDI SR D Slave SOUT disable time — 7 — — ns 9 tSUI SR D Data setup time for inputs Master mode 43 — — ns Slave mode 5 — — Master mode 0 — — Slave mode 25 — — Master mode — — 32 Slave mode — — 52 Master mode 0 — — Slave mode 8 — — 10 SR tHI 6 11 tSUO 12 tHO(6) CC CC D Data hold time for inputs D Data valid after SCK edge D Data hold time for outputs ns ns ns 1 Operating conditions: COUT = 10 to 50 pF, SlewIN = 3.5 to 15 ns. Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad. 3 The t CSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tCSC to ensure positive tCSCext. 2 MPC5602D Microcontroller Data Sheet, Rev. 3.1 62 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 4 The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tASC to ensure positive tASCext. 5 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register. 6 SCK and SOUT configured as MEDIUM pad MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 63 Electrical characteristics Figure 16. DSPI classic SPI timing – master, CPHA = 0 2 3 PCSx 1 4 SCK Output (CPOL = 0) 4 SCK Output (CPOL = 1) 9 SIN 10 First Data Last Data Data 12 SOUT First Data 11 Data Last Data Note: Numbers shown reference Table 40. Figure 17. DSPI classic SPI timing – master, CPHA = 1 PCSx SCK Output (CPOL = 0) 10 SCK Output (CPOL = 1) 9 SIN Data First Data 12 SOUT First Data Last Data 11 Data Last Data Note: Numbers shown reference Table 40. MPC5602D Microcontroller Data Sheet, Rev. 3.1 64 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Figure 18. DSPI classic SPI timing – slave, CPHA = 0 3 2 SS 1 4 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 First Data SOUT 9 6 Data Last Data Data Last Data 10 First Data SIN 11 12 Note: Numbers shown reference Table 40. Figure 19. DSPI classic SPI timing – slave, CPHA = 1 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 11 5 12 SOUT First Data 9 SIN Data Last Data Data Last Data 6 10 First Data Note: Numbers shown reference Table 40. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 65 Electrical characteristics Figure 20. DSPI modified transfer format timing – master, CPHA = 0 3 PCSx 4 1 2 SCK Output (CPOL = 0) 4 SCK Output (CPOL = 1) 9 SIN 10 First Data Last Data Data 12 SOUT 11 First Data Last Data Data Note: Numbers shown reference Table 40. Figure 21. DSPI modified transfer format timing – master, CPHA = 1 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) 10 9 SIN First Data Data 12 SOUT First Data Data Last Data 11 Last Data Note: Numbers shown reference Table 40. MPC5602D Microcontroller Data Sheet, Rev. 3.1 66 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Figure 22. DSPI modified transfer format timing – slave, CPHA = 0 3 2 SS 1 SCK Input (CPOL = 0) 4 4 SCK Input (CPOL = 1) First Data SOUT Data 6 Last Data 10 9 Data First Data SIN 12 11 5 Last Data Note: Numbers shown reference Table 40. Figure 23. DSPI modified transfer format timing – slave, CPHA = 1 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 11 5 12 First Data SOUT 9 SIN Data Last Data Data Last Data 6 10 First Data Note: Numbers shown reference Table 40. MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 67 Electrical characteristics 4.18.3 JTAG characteristics Table 41. JTAG characteristics Value No. Symbol C Parameter Unit Min Typ Max 1 tJCYC CC D TCK cycle time 83.33 — — ns 2 tTDIS CC D TDI setup time 15 — — ns 3 tTDIH CC D TDI hold time 5 — — ns 4 tTMSS CC D TMS setup time 15 — — ns 5 tTMSH CC D TMS hold time 5 — — ns 6 tTDOV CC D TCK low to TDO valid — — 49 ns 7 tTDOI CC D TCK low to TDO invalid 6 — — ns Figure 24. Timing diagram – JTAG boundary scan TCK 2/4 DATA INPUTS 3/5 INPUT DATA VALID 6 DATA OUTPUTS OUTPUT DATA VALID 7 DATA OUTPUTS Note: Numbers shown reference Table 41. MPC5602D Microcontroller Data Sheet, Rev. 3.1 68 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package characteristics 5 Package characteristics 5.1 Package mechanical data 5.1.1 100 LQFP mechanical outline drawing MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 69 Package characteristics Figure 25. 100 LQFP package mechanical drawing (part 1 of 3) MPC5602D Microcontroller Data Sheet, Rev. 3.1 70 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package characteristics 2 Figure 26. 100 LQFP package mechanical drawing (part 2 of 3) MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 71 Package characteristics Figure 27. 100 LQFP package mechanical drawing (part 3 of 3) MPC5602D Microcontroller Data Sheet, Rev. 3.1 72 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package characteristics 5.1.2 64 LQFP mechanical outline drawing Figure 28. 64 LQFP package mechanical drawing (Part 1 of 3) MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 73 Package characteristics Figure 29. 64 LQFP package mechanical drawing (Part 2 of 3) MPC5602D Microcontroller Data Sheet, Rev. 3.1 74 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package characteristics Figure 30. 64 LQFP package mechanical drawing (Part 3 of 3) MPC5602D Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 75 Ordering information 6 Ordering information Figure 31. Commercial product code structure Example code: M PC 56 0 2 D E M LL R Qualification Status Power Architecture Core Automotive Platform Core Version Flash Size (core dependent) Product Fab and Mask Indicator Temperature spec. Package Code R = Tape & Reel (blank if Tray) Qualification Status M = MC status S = Auto qualified P = PC status Automotive Platform 56 = Power Architecture in 90 nm Core Version 0 = e200z0 Flash Size (z0 core) 1= 128 KB 2 = 256 KB Product D = Access family Temperature spec. C = –40 to 85 °C V = –40 to 105 °C M = –40 to 125 °C Package Code LH = 64 LQFP LL = 100 LQFP Fab and Mask Indicator E = Data Flash (blank if none) MPC5602D Microcontroller Data Sheet, Rev. 3.1 76 Preliminary—Subject to Change Without Notice Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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