ATMEL AT17LV65 Fpga configuration eeprom memory Datasheet

AT17LV65 (1), AT17LV128 (1), AT17LV256,
AT17LV512, AT17LV010, AT17LV002, AT17LV040
FPGA Configuration EEPROM Memory
3.3V and 5.0V System Support
Note 1.
AT17LV65 and AT17LV128
are Not Recommended for
New Designs (NRND) and
are Replaced by AT17LV256.
DATASHEET
Features

EE Programmable Serial Memories Designed to Store Configuration Programs
for Field Programmable Gate Arrays (FPGAs)
̶
̶
̶











̶
̶
524,288 x 1-bit
1,048,576 x 1-bit
̶
̶
2,097,152 x 1-bit
4,194,304 x 1-bit
Supports both 3.3V and 5.0V Operating Voltage Applications
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with the Atmel® AT6000, AT40K and AT94K Devices, Altera®
FLEX®, APEX™ Devices, ORCA®, Xilinx® XC3000, XC4000, XC5200,
Spartan®, Virtex® FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density
Arrays
Very Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in 6mm x 6mm x 1mm 8-lead LAP (Pin-compatible with 8-lead SOIC
Package), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC and
44-lead TQFP Packages
Emulation of the Atmel AT24CXXX Serial EEPROMs
Low-power Standby Mode
High-reliability
̶
̶

65,536 x 1-bit(1)
131,072 x 1-bit(1)
262,144 x 1-bit
Endurance: 100,000 Write Cycles
Data Retention: 90 Years for Industrial Parts (at 85C)
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
Description
The AT17LV FPGA Configuration EEPROMs (Configurators) provide an easy-touse, cost-effective configuration memory solution for Field Programmable Gate
Arrays. The AT17LV devices are packaged in the 8-lead LAP, 8-lead PDIP, 8-lead
SOIC, 20-lead PLCC, 20-lead SOIC and 44-lead TQFP options(Table 1). The
AT17LV Configurators use a simple serial-access procedure to configure one or
more FPGA devices. The user can select the polarity of the reset function during
programming. These devices also support a write protection mechanism within its
programming mode.
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
The AT17LV configurators can be programmed with industry-standard programmers, the Atmel ATDH2200E
Programming Kit, or the Atmel ATDH2225 ISP Cable.
Table 1.
AT17LV Packages
AT17LV65/128/256(4)
AT17LV512/010
AT17LV002
AT17LV040
8-lead LAP
Yes
Yes
Yes
(3)
8-lead PDIP
Yes
Yes
–
—
8-lead SOIC
Yes
Use 8-lead LAP(1)
Use 8-lead LAP(1)
(3)
20-lead PLCC
Yes
Yes
Yes
—
20-lead SOIC
Yes(2)
—
Yes(2)
—
44-lead TQFP
—
—
Yes
Yes
Package
Notes:
1.
2.
3.
4.
2
The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-lead SOIC package is not
available for the AT17LV512/010/002 devices, it is possible to use an 8-lead LAP package instead.
The pinout for the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256 is not pin-for-pin compatible with
the AT17LV512/010/002 devices.
Refer to the AT17F datasheet which is available on the Atmel website.
The AT17LV65 and AT17LV128 are not recommended for new designs (NRND).
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
1.
Pin Configuration and Descriptions
Table 1-1.
Pin Descriptions
Pin
Description
DATA
Three-state Data Output for Configuration. Open-collector bi-directional pin for
programming.
CLK
Clock Input. Used to increment the internal address and bit counter for reading and
programming.
WP1
Write Protect (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010/002 devices.
RESET/OE
RESET (Active Low) / Output Enable (Active High) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver. The logic polarity of this input is programmable as either RESET/OE or
RESET/OE. For most applications, RESET should be programmed active Low. This document
describes the pin as RESET/OE.
WP
Write Protect Input (when CE is Low) during programming only (SER_EN Low). When WP is
Low, the entire memory can be written. When WP is enabled (High), the lowest block of the
memory cannot be written. This pin is only available on the AT17LV65 (NRND),
AT17LV128 (NRND), and the AT17LV256.
WP2
Write Protect (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on the AT17LV512/010.
CE
Chip Enable Input (Active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both the
address and bit counters and forces the device into a low-power standby mode. Note that this
pin will not enable/disable the device in the Two-Wire Serial Programming mode (SER_EN
Low).
GND
Ground. A 0.2μF decoupling capacitor between VCC and GND is recommended.
CEO
Chip Enable Output (Active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17LV devices, the CEO pin of one device
must be connected to the CE input of the next device in the chain. It will stay Low as long as
CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay
High until the entire EEPROM is read again. This CEO feature is not available on the
AT17LV65 (NRND).
A2
Device Selection Input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
READY
Open Collector Reset State Indicator. Driven Low during power-up reset, released when
power-up is complete. It is recommended to use a 4.7k pull-up resistor when this pin is used.
SER_EN
Serial Enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to VCC.
VCC
Power Supply. 3.3V (±10%) and 5.0V (±10%) power supply pin.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
3
Table 1-2.
Pin Configurations
AT17LV65/128/256(2)
AT17LV002
AT17LV040
Name
I/O
8-lead
DIP/LAP/
SOIC
DATA
I/O
1
2
2
1
2
1
2
1
40
40
CLK
I
2
4
4
2
4
2
4
3
43
43
WP1
I
–
–
–
–
5
–
5
–
7
–
RESET/OE
I
3
6
6
3
6
3
6
8
13
13
WP2
I
–
–
–
–
7
–
7
–
–
–
CE
I
4
8
8
4
8
4
8
10
15
15
5
10
10
5
10
5
10
11
18
18
21
21
GND
CEO(1)
20-lead
PLCC
20-lead
SOIC
8-lead
DIP/
LAP
20-lead
PLCC
8-lead
LAP
20-lead
PLCC
20-lead
SOIC
44-lead
TQFP
44-lead
TQFP
O
13
6
14
14
6
14
6
14
A2
I
READY
O
–
–
–
–
15
–
15
–
23
23
SER_EN
I
7
17
17
7
17
7
17
18
35
35
8
20
20
8
20
8
20
20
38
38
VCC
Notes:
4
AT17LV512/010
1.
2.
–
The CEO feature is not available on the AT17LV65 (NRND).
The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
Pinouts(1)
8-lead LAP
8-lead JEDEC SOIC
8-lead PDIP
(Top View)
(Top View)
(Top View)
DATA
1
8
VCC
CLK
2
7
SER_EN
(WP(2)) RESET/OE
3
6
CEO (A2)
CE
4
5
GND
DATA
1
8
VCC
CLK
2
7
SER_EN
(WP(2)) RESET/OE
3
6
CEO (A2)
CE
4
5
GND
DATA
1
8
VCC
CLK
2
7
SER_EN
(WP(2)) RESET/OE
3
6
CEO (A2)
CE
4
5
GND
NC
VCC
NC
20
19
NC
CLK
NC
NC
DATA
NC
VCC
NC
NC
SER_EN
NC
DATA
1
NC
15
NC (READY(3))
CE
8
14
CEO(4) (A2)
NC
NC
NC
NC
NC
NC
(WP1(1)) NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO (A2)
NC
NC
9
13
16
7
NC
6
(WP2(3)) NC
12
(WP1(2)) RESET/OE
NC
SER_EN
11
NC
17
NC
18
5
10
4
GND
CLK
(WP1(3)) NC
44
43
42
41
40
39
38
37
36
35
34
NC
(Top View)
AT17LV002 Only
2
44-lead TQFP
(Top View)
3
20-lead PLCC
12
13
14
15
16
17
18
19
20
21
22
Figure 1-1.
1.
2.
3.
4.
5.
20-lead SOIC
(Top View)
AT17LV65/128/256 Only(5)
(Top View)
AT17LV002 Only
NC
1
20
VCC
DATA
1
20
VCC
DATA
2
19
NC
NC
2
19
NC
NC
3
18
NC
CLK
3
18
SER_EN
CLK
4
17
SER_EN
NC
4
17
NC
NC
5
16
NC
NC
5
16
NC
RESET/OE
6
15
NC
NC
6
15
NC
NC
7
14
CEO (A2)
NC
7
14
NC
CE
8
13
NC
RESET/OE
8
13
CEO(4)
NC
9
12
NC
NC
9
12
NC
10
11
NC
CE
10
11
GND
GND
Notes:
20-lead SOIC
Drawings are not to scale.
This pin is only available on the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.
This pin is only available on the AT17LV512/010/002.
This pin is not available on the AT17LV65 (NRND).
The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
5
2.
Block Diagram
Figure 2-1.
Block Diagram
SER_EN
WP1(2)
WP2(2)
Programming
Data Shift
Register
Programming
Mode Logic
Power On
Reset
Row Decoder
EEPROM
Cell Matrix
Column Decoder
TC
CLK READY(2)
Notes:
6
1.
2.
3.
REST/OE (WP(1))
CE
CEO(3) (A2)
DATA
This pin is only available on the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.
This pin is only available on AT17LV512, AT17LV010, and AT17LV002.
The CEO feature is not available on the AT17LV65 (NRND).
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
3.
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA
device control signals. All FPGA devices can control the entire configuration process and retrieve data from the
configuration EEPROM without requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA output pin and
enable the address counter. When RESET/OE is driven High, the configuration EEPROM resets its address
counter and tri-states its DATA pin. The CE pin also controls the output of the AT17LV configurator. If CE is held
High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is
subsequently driven Low, the counter and the DATA output pin are enabled. When RESET/OE is driven High
again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to
avoid contention with other configurators. Upon power-up, the address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document
will describe RESET/OE.
4.
FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The
program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA
mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory.
The AT17LV Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xilinx applications.
5.
Control of Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and self-explanatory.





Note:
The DATA output of the AT17LV configurator drives DIN of the FPGA devices.
The master FPGA CCLK output drives the CLK input of the AT17LV configurator.
The CEO output of any AT17LV configurator drives the CE input of the next configurator in a cascaded
chain of EEPROMs.
SER_EN must be connected to VCC (except during ISP).
The READY(1) pin is available as an open-collector indicator of the device’s reset status; it is driven Low
while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete.
1. This pin is not available for the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
7
6.
Cascading Serial Configuration EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories,
cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its CEO output
Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and
enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE
on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive
(High) level.
The AT17LV65 (NRND) devices do not have the CEO feature to perform cascaded configurations.
7.
AT17LV Reset Polarity
The AT17LV configurator allows the user to program the reset polarity as either RESET/OE or RESET/OE. This
feature is supported by industry-standard programmer algorithms.
8.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the
2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated
inside the chip.
9.
Standby Mode
The AT17LV configurators enter a low-power standby mode whenever CE is asserted High. In this mode, the
AT17LV65 (NRND), AT17LV128 (NRND), or the AT17LV256 configurator consumes less than 50μA of current
at 3.3V (100μA for the AT17LV512/010 and 200μA for the AT17LV002/040). The output remains in a highimpedance state regardless of the state of the OE input.
8
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
10.
Electrical Specifications
10.1
Absolute Maximum Ratings*
*Notice: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions beyond those
listed under operating conditions is not
implied. Exposure to Absolute Maximum
Rating conditions for extended periods of
time may affect device reliability.
Operating Temperature . . . . . . . . . . . . . . . . .-40C to +85C
Storage Temperature . . . . . . . . . . . . . . . . . .-65C to +150C
Voltage on Any Pin
with Respect to Ground . . . . . . . . . . . . . . -0.1V to VCC +0.5V
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Maximum Soldering Temp. (10s @ 1/16 in.) . . . . . . . . 260C
ESD (RZAP = 1.5K, CZAP = 100pF) . . . . . . . . . . . . . . . .2000V
10.2
Operating Conditions
Table 10-1.
Operating Conditions
3.3V
10.3
Symbol
Description
VCC
Industrial
5.0V
Min
Max
Min
Max
Units
3.0
3.6
4.5
5.5
V
Supply voltage relative to GND
-40C to +85C
DC Characteristics
Table 10-2.
DC Characteristics for VCC = 3.3V ± 10%
AT17LV65/128/256(1)
AT17LV512/010
AT17LV002/40
Symbol
Description
Min
Max
Min
Max
Min
Max
Units
VIH
High-level Input Voltage
2.0
VCC
2.0
VCC
2.0
VCC
V
VIL
Low-level Input Voltage
0
0.8
0
0.8
0
0.8
V
VOH
High-level Output Voltage
(IOH = -2mA)
VOL
Low-level Output Voltage
(IOL = +3mA)
ICCA
Supply Current, Active Mode
IL
Input or Output Leakage Current
(VIN = VCC or GND)
ICCS
Supply Current, Standby Mode
Note:
1.
2.4
-10
2.4
2.4
V
0.4
0.4
0.4
V
5
5
5
mA
10
μA
150
μA
10
-10
100
10
100
-10
The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
9
Table 10-3.
DC Characteristics for VCC = 5.0V ± 10%
AT17LV65/128/256(1)
Description
Min
Max
Min
Max
Min
Max
Units
VIH
High-level Input Voltage
2.0
VCC
2.0
VCC
2.0
VCC
V
VIL
Low-level Input Voltage
0
0.8
0
0.8
0
0.8
V
VOH
High-level Output Voltage
(IOH = -2mA)
VOL
Low-level Output Voltage
(IOL = +3mA)
ICCA
Supply Current, Active Mode
IL
Input or Output Leakage Current
(VIN = VCC or GND)
ICCS
Supply Current, Standby Mode
1.
3.60
3.76
3.76
V
0.37
0.37
0.37
V
10
10
10
mA
10
μA
350
μA
-10
10
-10
150
10
-10
200
The AT17LV65 and AT17LV128 are not recommended for new designs.
AC Characteristics
Table 10-4.
AC Characteristics for VCC = 3.3V ± 10%
AT17LV65/128/256(3)
Symbol
Description
TOE(1)
OE to Data Delay
TCE(1)
Units
55
55
ns
CE to Data Delay
60
60
ns
TCAC(1)
CLK to Data Delay
80
60
ns
TOH
Data Hold from CE, OE, or CLK
TDF(2)
CE or OE to Data Float Delay
TLC
CLK Low Time
25
25
ns
THC
CLK High Time
25
25
ns
TSCE
CE Setup Time to CLK
(to guarantee proper counting)
60
35
ns
THCE
CE Hold Time from CLK
(to guarantee proper counting)
0
0
ns
THOE
OE High Time
(guarantees counter is reset)
25
25
ns
FMAX
Maximum Clock Frequency
1.
2.
3.
Min
Max
AT17LV512/010/002/040
Max
Notes:
10
AT17LV002/040
Symbol
Note:
10.4
AT17LV512/010
0
Min
0
55
10
ns
50
10
ns
MHz
AC test lead = 50pF.
Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
Table 10-5.
AC Characteristics when Cascading for VCC = 3.3V ± 10%
AT17LV65/128/256(3)
Symbol
TCDF
(2)
Description
Min
Max
AT17LV512/010/002/040
Min
Max
Units
CLK to Data Float Delay
60
50
ns
TOCK(1)
CLK to CEO Delay
60
55
ns
TOCE(1)
CE to CEO Delay
60
40
ns
TOOE(1)
RESET/OE to CEO Delay
45
35
ns
FMAX
Maximum Clock Frequency
8
10
MHz
Notes:
1.
2.
3.
Table 10-6.
AC test lead = 50pF.
Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
The AT17LV65 and AT17LV128 are not recommended for new designs.
AC Characteristics for VCC = 5V ± 10%
AT17LV65/128/256(3)
Symbol
Description
TOE(1)
OE to Data Delay
TCE(1)
Max
Units
35
35
ns
CE to Data Delay
45
45
ns
TCAC(1)
CLK to Data Delay
55
50
ns
TOH
Data Hold from CE, OE, or CLK
TDF(2)
CE or OE to Data Float Delay
TLC
CLK Low Time
20
20
ns
THC
CLK High Time
20
20
ns
TSCE
CE Setup Time to CLK
(To Guarantee Proper Counting)
40
25
ns
THCE
CE Hold Time from CLK
(To Guarantee Proper Counting)
0
0
ns
THOE
OE High Time
(Guarantees Counter is Reset)
20
20
ns
FMAX
Maximum Clock Frequency
Notes:
1.
2.
3.
Min
Max
AT17LV512/010/002/040
0
Min
0
50
12.5
ns
50
15
ns
MHz
AC test lead = 50pF.
Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
11
Table 10-7.
AC Characteristics When Cascading for VCC = 5V ± 10%
AT17LV65/128/256(3)
Symbol
TCDF
(2)
Description
Min
Max
AT17LV512/010/002/040
Min
Max
Units
CLK to Data Float Delay
50
50
ns
TOCK(1)
CLK to CEO Delay
40
40
ns
TOCE(1)
CE to CEO Delay
35
35
ns
TOOE(1)
RESET/OE to CEO Delay
35
30
ns
FMAX
Maximum Clock Frequency
10
12.5
MHz
Notes:
1.
2.
3.
Figure 10-1.
AC test lead = 50pF.
Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
The AT17LV65 and AT17LV128 are not recommended for new designs.
AC Waveforms
CE
TSCE
TSCE
THCE
RESET/OE
THOE
THC
TLC
CLK
TOE
TOH
TCAC
TDF
TCE
DATA
TOH
Figure 10-2.
AC Waveforms when Cascading
RESET/OE
CE
CLK
TCDF
DATA
FIRST BIT
LAST BIT
TOCK
TOCE
TOOE
CEO
TOCE
12
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
10.5
Thermal Resistance Coefficients
Table 10-8.
Thermal Resistance Coefficients
AT17LV65/128/256(2)
AT17LV512/010
AT17LV002
AT17LV040
JC [C/W]
45
45
45
—
JA [C/W](1)
115.71
135.71
159.60
—
JC [C/W]
37
37
—
—
JA [C/W](1)
107
107
—
—
JC [C/W]
45
—
—
—
JA [C/W](1)
150
—
—
—
JC [C/W]
35
35
35
—
JA [C/W](1)
90
90
90
—
Package Type
8CN4
Leadless Array
Package (LAP)
8P3
Plastic Dual Inline
Package (PDIP)
8S1
Plastic Gull Wing
Small Outline (SOIC)
20J
Plastic Leaded Chip
Carrier (PLCC)
20S2
Plastic Gull Wing
Small Outline (SOIC)
44A
Thin Plastic Quad
Flat Package (TQFP)
Notes:
1.
2.
JC [C/W]
—
JA [C/W](1)
—
JC [C/W]
—
—
17
17
JA [C/W](1)
—
—
62
62
Airflow = 0ft/min.
The AT17LV65 and AT17LV128 are not recommended for new designs.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
13
11.
Ordering Information
11.1
Ordering Code Detail
AT 1 7 LV 2 5 6 A - 1 0 P U
Atmel Designator
Package Device Grade
U
Product Family
= Green, Industrial
Temperature Range
(-40°C to +85°C)
17LV = FPGA EEPROM
Configuration Memory
Package Option
Device Density
65 = 64 kilobit
128 = 128 kilobit
256 = 256 kilobit
512 = 512 kilobit
010 = 1 Mbit
002 = 2 Mbit
040 = 4 Mbit
Special Pinouts
A = Altera
Blank = Xilinx/Atmel/Other
14
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
C
P
N
J
S
TQ
=
=
=
=
=
=
8CN4, 8-lead LAP
8P3, 8-lead PDIP
8S1, 8-lead JEDEC SOIC
20J, 20-lead PLCC
20S2, 20-lead JEDEC SOIC
44A, 44-lead TQFP
Product Variation
10 = Default Value
11.2
Ordering Information
Memory Size
256-Kbit
Atmel Ordering Code
Lead Finish
Package
AT17LV256-10CU
CuNiAu
(Lead-free/Halogen-free)
8CN4
AT17LV256-10JU
20J
AT17LV256-10NU
8S1
AT17LV256-10PU
Sn
(Lead-free/Halogen-free)
AT17LV256-10SU
1-Mbit
AT17LV512-10JU
Sn
(Lead-free/Halogen-free)
20J
AT17LV010-10CU
CuNiAu
(Lead-free/Halogen-free)
8CN4
AT17LV010-10JU
AT17LV010-10PU
AT17LV002-10CU
2-Mbit
Sn
(Lead-free/Halogen-free)
CuNiAu
(Lead-free/Halogen-free)
AT17LV002-10JU
AT17LV002-10SU
AT17LV040-10TQU
20J
Industrial
(-40C to 85C)
3.0V to 5.5V
Industrial
(-40C to 85C)
3.0V to 5.5V
Industrial
(-40C to 85C)
3.0V to 5.5V
Industrial
(-40C to 85C)
3.0V to 5.5V
Industrial
(-40C to 85C)
8P3
8CN4
20J
Sn
(Lead-free/Halogen-free)
AT17LV002-10TQU
4-Mbit
3.0V to 5.5V
20S2
8CN4
512-Kbit
Operation Range
8P3
CuNiAu
(Lead-free/Halogen-free)
AT17LV512-10CU
Voltage
20S2
44A
Sn
(Lead-free/Halogen-free)
44A
Package Type
8CN4
8-lead, 6mm x 6mm x 1mm, Leadless Array Package (LAP) (Pin-compatible with 8-lead SOIC Packages)
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
20J
20-lead, Plastic J-leaded Chip Carrier (PLCC)
20S2
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
44A
44-lead, Thin (1.0mm) Plastic Quad Flat Package Carrier (TQFP)
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
15
12.
Packaging Information
12.1
8CN4 – LAP
Marked Pin1 Indentifier
E
A
A1
D
Side View
Top View
Pin1 Corner
L1
0.10 mm
TYP
8
1
COMMON DIMENSIONS
(Unit of Measure = mm)
e
7
2
3
6
b
5
4
e1
L
Bottom View
Note:
SYMBOL
MIN
NOM
MAX
A
0.94
1.04
1.14
A1
0.30
0.34
0.38
b
0.45
0.50
0.55
D
5.89
5.99
6.09
E
5.89
5.99
6.09
e
1.27 BSC
e1
1.10 REF
NOTE
1
L
0.95
1.00
1.05
1
L1
1.25
1.30
1.35
1
1. Metal Pad Dimensions.
2. All exposed metal area shall have the following finished platings.
Ni: 0.0005 to 0.015 mm
Au: 0.0005 to 0.001 mm
2/15/08
Package Drawing Contact:
[email protected]
16
TITLE
8CN4, 8-lead (6 x 6 x 1.04 mm Body),
Lead Pitch 1.27mm,
Leadless Array Package (LAP)
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
GPC
DMH
DRAWING NO.
8CN4
REV.
D
12.2
8P3 – PDIP
E
1
E1
.381
Gage Plane
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
D
e
D1
A1
b2
b3
b v
4 PLCS
MIN
NOM
MAX
A
-
-
5.334
A1
0.381
-
-
SYMBOL
A2 A
L
0.254 m C
Side View
2
A2
2.921
3.302
4.953
b
0.356
0.457
0.559
5
b2
1.143
1.524
1.778
6
b3
0.762
0.991
1.143
6
c
0.203
0.254
0.356
D
9.017
9.271
10.160
3
D1
0.127
0.000
0.000
3
E
7.620
7.874
8.255
4
E1
6.096
6.350
7.112
3
3.810
2
e
2.540 BSC
eA
L
Notes:
NOTE
7.620 BSC
2.921
3.302
4
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
07/31/14
Package Drawing Contact:
[email protected]
TITLE
GPC
DRAWING NO.
8P3, 8-lead, 0.300” Wide Body, Plastic Dual
In-line Package (PDIP)
PTC
8P3
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
REV.
E
17
12.3
8S1 – SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
SYMBOL MIN
A
1.35
MAX
NOM
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
6/22/11
Package Drawing Contact:
[email protected]
18
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
GPC
SWB
DRAWING NO.
REV.
8S1
G
12.4
20J – PLCC
PIN NO. 1
1.14(0.045) X 45°
1.14(0.045) X 45°
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
D1
A1
D
A
0.51(0.020)MAX
45° MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102mm) maximum
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
9.779
–
10.033
D1
8.890
–
9.042
E
9.779
–
10.033
E1
8.890
–
9.042
D2/E2
7.366
–
8.382
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
Package Drawing Contact:
[email protected]
TITLE
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO. REV.
20J
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
B
19
12.5
20S2 – SOIC
C
1
10
E1 E
11
E1
20
TOP VIEW
e
L
A2
b
END VIEW
A1
A
D
Notes:
1.
2.
3.
4.
5.
6.
SIDE VIEW
This drawing is for general information only. Refer to JEDEC Drawing
MS-013, Variation AC, for proper dimensions, tolerances, datums, etc.
Dimension D does not include mold flash, protrusions or gate burrs. Mold
flash, protrustions or gate burrs shall not exceed 0.15 mm per end.
Diminsion E1 does not include interlead flash or protursion. Interlead flash
or protrusion shall not exceed 0.25 mm per side.
The package top may be smaller than the package bottom. Dimensions D
and E1 are determinded at the outermost extremes of the plastic body
exclusive of mold flash, the bar burrs, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
The dimensions apply to the flat section of the lead between 0.10 to
0.25 mm from the lead tip.
Dimension ‘b’ does not include the dambar protrusion. Allowable dambar
protrusion shall be 0.10 mm total in excess of the ‘b’ dimension at maximum
material condition. The dambar may not be located on the lower radius of
the foot.
‘A1’ is defined as the vertical distance from the seating plane to the lowest
point on the package body excluding the lid or thermal enhancement on the
cavity down package configuration.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
NOTE
D
12.80 BSC
2,3
E1
7.50 BSC
2,3
E
10.30 BSC
A
-
-
2.65
A1
0.10
-
0.30
A2
2.05
-
-
e
b
6
1.27 BSC
0.31
-
0.51
L
0.40
-
1.27
C
0.20
-
0.33
4,5
4
7/1/14
TITLE
Package Drawing Contact:
[email protected]
20
20S2, 20-lead, 0.300” Wide Body, Plastic
Gull Wing Small Outline Package (SOIC)
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
GPC
DRAWING NO.
REV.
SRJ
20S2
E
12.6
44A – TQFP
D1
D
e
E
E1
b
BOTTOM VIEW
TOP VIEW
C
0°~7°
A1
L
A2
A
SIDE VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026,
Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25 mm per side. Dimensions D1
and E1 are maximum plastic body size dimensions including
mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
1/10/13
Package Drawing Contact:
[email protected]
TITLE
44A, 44-lead 10.0 x 10.0x1.0 mm Body, 0.80 mm
Lead Pitch, Thin Profile Plastic Quad Flat
Package (TQFP)
GPC
DRAWING NO.
REV.
AIX
44A
D
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
21
13.
Revision History
Rev. No.
Date
History
The AT17LV65 and AT17LV128 are not recommended for new designs.
22
Removed the commercial options.
2321J
10/2014
2321I
02/2008
Removed -10SC, 10SI, -10TQC, -10TQI, -10BJC and -10BJI devices from ordering information.
2321H
03/2006
Added last-time buy for AT17LVXXX-10CC and AT17LVXXX-10CI.
Updated the 8P3, 8S1, 20S2, and 44A package outline drawings, ordering code details,
ordering code table, document’s template, Atmel logos, disclaimer page.
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
XXXXXX
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
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© 2014 Atmel Corporation. / Rev.: Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014.
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