256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
DDR SDRAM Unbuffered Module
(DDR466 Module)
184pin Unbuffered Module based on 256Mb E-die
64/72-bit ECC/Non ECC
Revision 1.0
December, 2003
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
Revision History
Revision 0.0 (October, 2003)
- First release
Revision 1.0 (December, 2003)
- Finalized
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
184Pin Unbuffered DIMM based on 256Mb E-die (x8)
Ordering Information
Part Number
Density
Organization
M368L3223ETM-C(L)C5
256MB
32M x 64
32Mx8( K4H560838E) * 8EA
Component Composition
1,250mil
Height
M368L6423ETM-C(L)C5
512MB
64M x 64
32Mx8( K4H560838E) * 16EA
1,250mil
M381L3223ETM-C(L)C5
256MB
32M x 72
32Mx8( K4H560838E) * 9EA
1,250mil
M381L6423ETM-C(L)C5
512MB
64M x 72
32Mx8( K4H560838E) * 18EA
1,250mil
Operating Frequencies
C5(DDR466@CL=3)
Speed @CL3
233MHz
CL-tRCD-tRP
3-4-4
Feature
• Power supply : Vdd: 2.6V ± 0.1V, Vddq: 2.6V ± 0.1V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1,250 (mil), single (256MB) and double(512MB) sided
• SSTL_2 Interface
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
Pin Configuration (Front side/back side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
*/CS2
DQ48
DQ49
VSS
/CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8
A10
CB6
VDDQ
CB7
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
VSS
DQ46
DQ47
*/CS3
VDDQ
DQ52
DQ53
*A13
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
KEY
53
54
55
56
57
58
59
60
61
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
KEY
145
146
147
148
149
150
151
152
153
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
Note :
1. * : These pins are not used in this module.
2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module, and are not used on x64 module.
3. Pins 111, 158 are NC for 1 Row Module[M368(81)L3223ETM] & used for 2 Row Moduel[M368(81)L6423ETM]
Pin Description
Pin Name
Function
Pin Name
Function
A0 ~ A12
Address input (Multiplexed)
DM0 ~ 7, 8(for ECC)
Data - in mask
BA0 ~ BA1
Bank Select Address
VDD
Power supply (2.6V)
DQ0 ~ DQ63
Data input/output
VDDQ
Power Supply for DQS(2.6V)
DQS0 ~ DQS8
Data Strobe input/output
VSS
Ground
CK0,CK0 ~ CK2, CK2
Clock input
VREF
Power supply for reference
CKE0, CKE1(for double banks)
Clock enable input
VDDSPD
Serial EEPROM Power/Supply ( 2.3V to 3.6V )
CS0, CS1(for double banks)
Chip select input
SDA
Serial data I/O
RAS
Row address strobe
SCL
Serial clock
CAS
Column address strobe
SA0 ~ 2
Address in EEPROM
WE
Write enable
NC
No connection
CB0 ~ CB7 (for x72 module)
Check bit(Data-in/data-out)
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
256MB, 32M x 64 Non ECC Module (M368L3223ETM) (Populated as 1 bank of x8 DDR SDRAM Module)
Functional Block Diagram
DQS0
DM0
CS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS4
DM4
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D1
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
Serial PD
SCL
SDA
WP
CS DQS
D5
A0
A1
A2
SA0
SA1
SA2
VDDSPD
SPD
VDD/VDDQ
D0 - D7
VREF
D0 - D7
VSS
D0 - D7
D0 - D7
CS
DQS
D6
*Clock Net Wiring
D3/D0/D6
Cap/Cap/Cap
R=120Ω
DQS7
DM7
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D3
BA0-BA1 : DDR SDRAMs D0 - D7
A0-A12 : DDR SDRAMs D0 - D7
RAS
RAS : DDR SDRAMs D0 - D7
CAS
CAS : DDR SDRAMs D0 - D7
WE
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
CS
D4
DQS6
DM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CKE0
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
CS DQS
DQS2
DM2
A0 - A12
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS5
DM5
DQS1
DM1
BA0 - BA1
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS
CKE : DDR SDRAMs D0 - D7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
CK0/CK0
CK1/CK1
CK2/CK2
Card
Edge
D7
Clock Wiring
Clock
SDRAMs
Input
3 SDRAMs
3 SDRAMs
2 SDRAMs
D4/D1/D7
CK0/1/2
*If two DRAMs are loaded,
Cap will replace DRAM
Cap/Cap/Cap
D5/D2/Cap
Cap/Cap/Cap
Notes :
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms +
5%
WE : DDR SDRAMs D0 - D7
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
256MB, 32M x 72 ECC Module (M381L3223ETM) (Populated as 1 bank of x8 DDR SDRAM Module)
Functional Block Diagram
DQS0
DM0
CS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS4
DM4
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
D0
CS
DQS
Serial PD
D4
SCL
SDA
WP
A0
A1
A2
SA0
SA1
SA2
DQS5
DM5
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D1
CS DQS
D5
VDDSPD
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D0 - D8
VREF
D0 - D8
VSS
D0 - D8
D0 - D8
DQS6
DM6
DQS2
DM2
CS
DQS
D6
D3/D0/D6
DQS7
DM7
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D3
SPD
VDD/VDDQ
Cap/Cap/Cap
R=120Ω
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D7
D4/D1/D7
CK0/1/2
Card
Edge
Cap/Cap/Cap
D5/D2/D8
Cap/Cap/Cap
DQS8
DM8
BA0 - BA1
A0 - A12
CS
DQS
D8
BA0-BA1 : DDR SDRAMs D0 - D8
A0-A12 : DDR SDRAMs D0 - D8
RAS
RAS : DDR SDRAMs D0 - D8
CAS
CAS : DDR SDRAMs D0 - D8
CKE0
CKE : DDR SDRAMs D0 - D8
WE
Clock Wiring
Clock
SDRAMs
Input
CK0/CK0
CK1/CK1
CK2/CK2
3 SDRAMs
3 SDRAMs
3 SDRAMs
Notes :
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms +
5%
WE : DDR SDRAMs D0 - D8
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
512MB, 64M x 64 Non ECC Module (M368L6423ETM) (Populated as 2 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS1
CS0
DQS4
DM4
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D0
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D8
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D1
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D9
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D4
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D12
DQS
D5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D13
DQS6
DM6
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DM
DQS
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D2
CS
DQS
D10
CS
DQS
D6
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D14
DQS7
DM7
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A0 - A12
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS
DQS5
DM5
DQS1
DM1
BA0 - BA1
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D3
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D11
Serial PD
BA0-BA1 : DDR SDRAMs D0 - D15
SCL
A0-A12 : DDR SDRAMs D0 - D15
SDA
WP
RAS
RAS : DDR SDRAMs D0 - D15
CAS
CAS : DDR SDRAMs D0 - D15
CKE1
CKE : DDR SDRAMs D8 - D15
CKE0
CKE : DDR SDRAMs D0 - D7
WE
WE : DDR SDRAMs D0 - D15
A0
A1
A2
SA0
SA1
SA2
CS DQS
D7
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D15
Clock Wiring
Clock
SDRAMs
Input
CK0/CK0
CK1/CK1
CK2/CK2
4 SDRAMs
6 SDRAMs
6 SDRAMs
*Clock Net Wiring
D3/D0/D5
D4/D1/D6
VDDSPD
VDD/VDDQ
R=120Ω
SPD
D0 - D15
D0 - D15
VREF
D0 - D15
VSS
D0 - D15
*Cap/D2/D7
CK0/1/2
Card
Edge
*If four DRAMs are loaded,
Cap will replace DRAM
*Cap/D8/D13
D11/D9/D14
Notes :
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 3.0 Ohms +
5%
D12/D10/D15
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
512MB, 64M x 72 ECC Module (M381L6423ETM) (Populated as 2 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS1
CS0
DQS4
DM4
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D0
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D9
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
CS
D4
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQS
CS
D13
DQS5
DM5
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D1
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D10
CS
DQS
D5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D14
DQS6
DM6
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DM
DQS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D2
0
1
6
7
2
3
4
5
CS
DQS
D11
CS
DQS
D6
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D15
DQS7
DM7
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS8
DM8
CS
DQS
D3
CS
DQS
D8
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D12
CS
DQS
CS
D7
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D16
Serial PD
DQS
SCL
D17
SDA
WP
A0
A1
A2
SA0
SA1
SA2
D3/D0/D5
BA0 - BA1
BA0-BA1 : DDR SDRAMs D0 - D17
A0 - A12
A0-A12 : DDR SDRAMs D0 - D17
RAS
RAS : DDR SDRAMs D0 - D17
CAS
CAS : DDR SDRAMs D0 - D17
CKE1
CKE : DDR SDRAMs D9 - D17
CKE0
CKE : DDR SDRAMs D0 - D8
WE
WE : DDR SDRAMs D0 - D17
* Clock Wiring
Clock
SDRAMs
Input
CK0/CK0
CK1/CK1
CK2/CK2
6 SDRAMs
6 SDRAMs
6 SDRAMs
D4/D1/D6
R=120Ω
D8/D2/D7
CK0/1/2
Card
Edge
D17/D9/D14
D12/D10/D15
*D8, D17 is assigned for ECC Comp.
D13/D11/D16
VDDSPD
SPD
VDD/VDDQ
D0 - D17
VREF
D0 - D17
VSS
D0 - D17
D0 - D17
Notes :
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 3.0 Ohms +
5%
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
VDD, VDDQ
-1.0 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.5 * # of component
W
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal VDD of 2.5V)
Parameter
VDD
2.5
2.7
V
5
I/O Supply voltage
VDDQ
2.5
2.7
V
5
I/O Reference voltage
VREF
0.49*VDDQ
0.51*VDDQ
V
1
VTT
VREF-0.04
VREF+0.04
V
2
VIH(DC)
VREF+0.15
VDDQ+0.3
V
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
Input Voltage Level, CK and CK inputs
VIN(DC)
-0.3
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID(DC)
0.36
VDDQ+0.6
V
3
V-I Matching: Pullup to Pulldown Current Ratio
VI(Ratio)
0.71
1.4
-
4
II
-2
2
uA
5
Input leakage current
Output leakage current
IOZ
-5
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V
IOH
-16.8
mA
uA
Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V
IOL
16.8
mA
Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V
IOH
-9
mA
Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
IOL
9
mA
Note : 1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same.
Peak-to peak noise on VREF may not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the
maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the
maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
5. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20MHz. Any noise above 20MHz at the DRAM
generated from any source other than the DRAM itself may not exceed the DC voltage range of 2.6V +/-100mV.
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
DDR SDRAM IDD spec table
(VDD=2.7V, T = 10°C)
Symbol
M368L3223ETM
M381L3223ETM
C5(DDR400@CL=3)
C5(DDR400@CL=3)
Unit
IDD0
880
990
mA
IDD1
1,120
1,260
mA
IDD2P
40
45
mA
IDD2F
280
320
mA
IDD2Q
240
270
mA
IDD3P
520
590
mA
IDD3N
680
770
mA
IDD4R
1,600
1,800
mA
IDD4W
1,680
1,890
mA
IDD5
1,680
1,890
mA
28
32
mA
IDD6
Normal
Low power
IDD7A
16
18
mA
2,640
2,970
mA
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
(VDD=2.7V, T = 10°C)
M368L6423ETM
M381L6423ETM
C5(DDR400@CL=3)
C5(DDR400@CL=3)
IDD0
1,560
1,760
mA
IDD1
1,800
2,030
mA
IDD2P
80
90
mA
IDD2F
560
630
mA
IDD2Q
480
540
mA
Symbol
Unit
IDD3P
1,040
1,170
mA
IDD3N
1,360
1,530
mA
IDD4R
2,280
2,570
mA
IDD4W
2,360
2,660
mA
IDD5
2,360
2,660
mA
56
63
mA
IDD6
Normal
Low power
IDD7A
32
36
mA
3,320
3,740
mA
Notes
Optional
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
AC Operating Conditions
Parameter/Condition
Max
Symbol
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
Unit
Note
V
VREF - 0.31
V
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
VDDQ+0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output Capacitance
Parameter
(VDD=2.6V, VDDQ=2.6V, TA= 25°C, f=1MHz)
Symbol
M368L3223ETM
M381L3223ETM
Unit
Min
Max
Min
Max
CIN1
49
57
51
60
pF
Input capacitance(CKE0)
CIN2
42
50
44
53
pF
Input capacitance( CS0)
CIN3
42
50
44
53
pF
Input capacitance( CLK0, CLK1,CLK2)
CIN4
25
30
25
30
pF
Input capacitance(DM0~DM7, DM8(for ECC))
CIN5
6
7
6
7
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
6
7
6
7
pF
Data input/output capacitance (CB0~CB7)
Cout2
-
-
6
7
pF
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Parameter
Symbol
M368L6423ETM
M381L6423ETM
Min
Min
Max
Unit
Max
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
CIN1
65
81
69
87
Input capacitance(CKE0,CKE1)
CIN2
42
50
44
53
pF
pF
Input capacitance( CS0, CS1)
CIN3
42
50
44
53
pF
Input capacitance( CLK0, CLK1,CLK2)
CIN4
28
34
28
34
pF
Input capacitance(DM0~DM7, DM8(for ECC))
CIN5
10
12
10
12
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
10
12
10
12
pF
Data input/output capacitance (CB0~CB7)
Cout2
-
-
10
12
pF
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
AC Timing Parameters and Specifications
Parameter
Symbol
Row cycle time
- C5(DDR466@CL=3)
Min
Max
Unit
tRC
60
ns
Refresh row cycle time
tRFC
70
ns
Row active time
tRAS
40
RAS to CAS delay
tRCD
18
ns
tRP
18
ns
Row precharge time
70K
ns
Row active to Row active delay
tRRD
10
ns
Write recovery time
tWR
15
ns
tWTR
2
tCK
Internal write to read command delay
CL=3.0
Clock cycle time
CL=2.5
Clock high level width
tCK
tCH
Clock low level width
DQS-out access time from CK/CK
4.3
10
ns
6
12
ns
0.45
0.55
tCK
tCL
0.45
0.55
tCK
tDQSCK
-0.55
+0.55
ns
ns
Output data access time from CK/CK
tAC
-0.65
+0.65
Data strobe edge to ouput data edge
tDQSQ
-
0.4
ns
Read Preamble
tRPRE
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.72
1.28
tCK
tWPRES
0
Write preamble
tWPRE
0.25
Write postamble
tWPST
0.4
Write preamble setup time
Note
ps
16
13
5
tCK
0.6
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
tCK
DQS-in high level width
tDQSH
0.35
tCK
DQS-in low level width
tDQSL
0.35
tCK
4
Address and Control Input setup time
tIS
0.6
ns
h,7~10
Address and Control Input hold time
tIH
0.6
ns
h,7~10
Data-out high impedence time from CK/CK
tHZ
-
tAC max
ns
3
Data-out low impedence time from CK/CK
tLZ
tAC min
tAC max
ns
3
Mode register set cycle time
tMRD
2
DQ & DM setup time to DQS, slew rate 0.5V/ns
tDS
0.4
ns
i, j
DQ & DM hold time to DQS, slew rate 0.5V/ns
tDH
0.4
ns
i, j
tDIPW
1.75
ns
9
tIPW
2.2
ns
9
DQ & DM input pulse width
Control & Address input pulse width for each input
Refresh interval time
Up to 128Mb
256Mb, 512Mb, 1Gb
tREFI
tCK
7.8
us
us
6
Output DQS valid window
tQH
tHP
-tQHS
-
ns
12
Clock half period
tHP
min
tCH/tCL
-
ns
11, 12
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
Parameter
Symbol
DDR SDRAM
- C5(DDR466@CL=3)
Min
Data hold skew factor
tQHS
Auto Precharge write recovery + precharge time
tDAL
-
Exit self refresh to non-READ command
tXSNR
75
Exit self refresh to READ command
tXSRD
200
Max
Unit
Note
0.5
ns
12
-
ns
14
ns
15
-
tCK
Component Notes
1.VID is the magnitude of the difference between the input level on CK and the input level on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
3. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a
specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).
4. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys
tem performance (bus turnaround) will degrade accordingly.
5. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ
ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
6. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
7. For command/address input slew rate ≥ 0.5 V/ns
8. For CK & CK slew rate ≥ 0.5 V/ns
9. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
10. Slew Rate is measured between VOH(ac) and VOL(ac).
11. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
12. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and pchannel to n-channel variation of the output drivers.
13. tDQSQ
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given
cycle.
14. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR466(C5) at CL=3 and
tCK=4.3ns tDAL = (15 ns / 5 ns) + (15 ns/ 5ns) = {(3) + (3)}CLK
tDAL = 6 clocks
15. In all circumstances, tXSNR can be satisfied using tXSNR=tRFCmin+1*tCK
16. The only time that the clock frequency is allowed to change is during self-refresh mode.
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR466 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
DDR466
PARAMETER
SYMBOL
MIN
MAX
Units
Notes
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
DCSLEW
0.5
4.0
V/ns
a, k
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
tIS
tIH
Units
0.5 V/ns
0
0
ps
Notes
h
0.4 V/ns
+50
0
ps
h
0.3 V/ns
+100
0
ps
h
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
tDS
tDH
Units
0.5 V/ns
0
0
ps
Notes
j
0.4 V/ns
+75
+75
ps
j
0.3 V/ns
+150
+150
ps
j
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate
tDS
tDH
Units
Notes
+/- 0.0 V/ns
0
0
ps
i
+/- 0.25 V/ns
+50
+50
ps
i
+/- 0.5 V/ns
+100
+100
ps
i
Table 5 : Output Slew Rate Characteristice (X8 Devices only)
Slew Rate Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Notes
Pullup Slew Rate
1.2 ~ 2.5
1.0
4.5
a,c,d,f,g
Pulldown slew
1.2 ~ 2.5
1.0
4.5
b,c,d,f,g
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Slew Rate Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Notes
Pullup Slew Rate
1.2 ~ 2.5
0.7
5.0
a,c,d,f,g
Pulldown slew
1.2 ~ 2.5
0.7
5.0
b,c,d,f,g
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS
PARAMETER
Output Slew Rate Matching Ratio (Pullup to Pulldown)
DDR466
MIN
MAX
Notes
-
-
e,k
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
Test point
Output
50Ω
VSSQ
Figure 1 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
VDDQ
50Ω
Output
Test point
Figure 2 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
For Maximum slew rate, only one DQ is switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.6V, typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.5V, slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and
voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
i. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.
Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the
slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as:
{1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
k. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotony.
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
Command Truth Table
DDR SDRAM
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE BA0,1 A10/AP
A0 ~ A9
A11, A12
Note
Register
Extended MRS
H
X
L
L
L
L
OP CODE
1, 2
Register
Mode Register Set
H
X
L
L
L
L
OP CODE
1, 2
L
L
L
H
X
L
H
H
H
Auto Refresh
Refresh
Entry
Self
Refresh
Exit
H
H
L
L
H
H
X
X
X
Bank Active & Row Addr.
H
X
L
L
H
H
V
Read &
Column Address
Auto Precharge Disable
H
X
L
H
L
H
V
Write &
Column Address
Auto Precharge Disable
H
X
L
H
L
L
V
H
X
L
H
H
L
H
X
L
L
H
L
H
X
X
X
L
V
V
V
X
X
X
X
Auto Precharge Enable
Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
All Banks
Active Power Down
Entry
H
L
Exit
L
H
Entry
H
L
Exit
L
H
Precharge Power Down Mode
DM
No operation (NOP) : Not defined
H
X
X
X
L
H
H
H
H
X
X
X
V
V
V
L
H
H
X
X
X
X
X
L
H
H
H
3
3
X
3
Row Address
(A0~A9, A11, A12)
L
Column
Address
H
L
Column
Address
H
X
V
L
X
H
4
4
4
4, 6
7
X
5
X
X
X
H
3
X
8
9
9
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
Physical Dimensions : 32M x 64 (M368L3223ETM), 32M x 72 (M381L3223ETM)
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.25 ± 0.006
(133.350 ± 0.15)
0.118
(3.00)
5.077
(128.950)
1.25 ± 0.006
(31.75 ±0.15)
B
0.100 Min
(2.30 Min)
A
0.7
(17.80)
0.393
ECC
(for x72)
(10.00)
(2X) 0.157
(4.00)
N/A
(for x64)
N/A
(for x64)
2.500
0.10 M
ECC
(for x72)
1.95
2.55
(64.77)
C B A
0.07 Max
(1.20 Max)
(49.53)
0.157
(4.00)
0.100
0.26
(6.62)
0.250
(6.350)
(2.50 )
0.050 ± 0.0039
(1.270 ± 0.10)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
2.175
0.071
(1.80)
Detail A
0.118
(3.00)
0.0078 ±0.006
(0.20 ±0.15)
0.050
(1.270)
Detail B
0.1575
(4.00)
0.10 M C A M B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 32Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part NO : K4H560838E.
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
DDR SDRAM
Physical Dimensions : 64M x 64 (M368L6423ETM), 64M x 72 (M381L6423ETM)
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.25 ± 0.006
(133.350 ± 0.15)
0.118
(3.00)
5.077
(128.950)
1.25 ± 0.006
(31.75 ±0.15)
0.393
(10.00)
ECC
(for x72)
0.100 Min
(2.30 Min)
B
A
0.7
(17.80)
(2X) 0.157
(4.00)
N/A
(for x64)
2.500
0.10 M
0.145 Max
(3.67 Max)
1.95
2.55
(64.77)
C B A
(49.53)
N/A
(for x64)
ECC
(for x72)
0.157
(4.00)
0.100
0.26
(6.62)
0.250
(6.350)
(2.50 )
0.050 ± 0.0039
(1.270 ± 0.10)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
2.175
0.071
(1.80)
Detail A
0.118
(3.00)
0.0078 ±0.006
(0.20 ±0.15)
0.050
(1.270)
Detail B
0.1575
(4.00)
0.10 M C A M B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 32Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part NO : K4H560838E
Revision 1.0 December, 2003