ICST ICS9159C-02 Frequency generator and integrated buffer for pentiumtm Datasheet

Integrated
Circuit
Systems, Inc.
ICS9159C-02
Frequency Generator and Integrated Buffer for PENTIUMTM
General Description
Features
The ICS9159C-02 generates all clocks required for high
speed RISC or CISC microprocessor systems such as 486,
Pentium, PowerPC,™ etc. Four different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions. These multiplying factors can be
customized for specific applications. A test mode is provided
to drive all clocks directly.
•
High drive BCLK outputs provide typically greater than
1V/ns slew rate into 30pF loads. PCLK outputs provide
typically better than 1V/ns slew rate into 20pF loads while
maintaining +/−5% duty cycle.
•
•
•
•
•
Generates up to four processor and six bus clocks, plus
disk, keyboard and reference clocks
Synchronous clocks skew matched to 250ps window on
PCLKs and 500ps window on BCLKs
Test clock mode eases system design
Custom configurations available:
Output frequency ranges to 100 MHz on options
Selectable multiplying and processor/bus ratios
Stop clock control stops clock glitch-free; available as
mask option
3.0V - 5.5V supply range
28-pin SOIC package
Applications
•
Ideal for high-speed RISC or CISC systems such as
486, Pentium, PowerPC, etc.
Block Diagram
PLL
DISK
CLOCK
KEYBD
GEN
X2
X1
XTAL OSC
REF(0:1)
OEN
FS0
PLL
SYNC
PCLK(0:3)
REG
BCLK(0:5)
CLOCK
FS1
GEN
Pentium is a trademark of Intel Corporation
PowerPC is a trademark of Motorola Corporation
9159-02 Rev D 062397
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
ICS9159C-02
Functionality
Pin Configuration
FS1
FS0
*VCO
X1, REF
(MHz)
CPU
(MHz)
0
0
118/17xX1
14.318
50(49.7)
0
1
65/7xX1
14.318
66.6(66.5)
1
0
92/11xX1
14.318
60(59.9)
1
1
Test mode
TCLK
TCLK/2
*VCO range is limited from 60 - 200 MHz
PCLK(0,3)
VCO/2
TCLK/2
28-Pin SOIC
BCLK(0,5)
PCLK/2
TCLK/4
DISK
24 MHz
TCLK/4
KEYBD
12 MHz
TCLK/8
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
1, 8, 14,
20, 26
VDD
PWR
2
X1
IN
3
4, 11, 17, 23
X2
VSS
OUT
PWR
6, 7, 9, 10
PCLK(0:3)
OUT
13, 12
FS(0:1)
IN
15, 16, 18 19,
21, 22
BCLK(0:5)
OUT
5
OEN
IN
24
DISK
OUT
25
KEYBD
OUT
28, 27
REF(0:1)
OUT
DESCRIPTION
Power for logic, PCLK and fixed frequency output buffers.
XTAL or external reference frequency input. This input includes
XTAL load capacitance and feedback bias for a 12 - 16 MHz
crystal, nominally 14.31818 MHz.
XTAL output which includes XTAL load capacitance.
Ground for logic, PCLK and fixed frequency output buffers.
Processor clock outputs which are a multiple of the input reference
frequency as shown in the table above.
Frequency multiplier select pins. See table above. These inputs have
internal pull-up devices.
Bus clock outputs are fixed at one half the PCLK frequency.
OEN tristates all outputs when low. This input has an internal pullup device.
The DISK controller clock is fixed at 24 MHz
(with 14.318 MHz input).
The KEYBD clock is fixed at 12 MHz (with 14.318 MHz input).
REF is a buffered copy of the crystal oscillator or reference input
clock nominally 14.31818 MHz.
Note: BCLK buffers cannot be supplied with 5 volts (pins 14 and 20) if CPU and fixed frequencies (pins 1, 8, and 26) are being
supplied with 3.3 volts
2
ICS9159C-02
Absolute Maximum Ratings
Supply Voltage ......................................................................................... 7.0 V
Logic Inputs ..................................................... GND - 0.5 V to VDD + 0.5 V
Ambient .................................................... Operating Temperature0 to +70 C
Storage Temperature .................................................................. 65 to +150 C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stess specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics at 3.3 V
VDD = 3.0 - 3.7 V, TA = 0 - 70oC unless otherwise stated
DC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage
VIL
-
-
0.2VDD
V
Input High Voltage
VIH
0.7VDD
-
-
V
Input Low Current
IIL
VIN=0V
-28.0
-10.5
-
mA
Input High Current
IIH
VIN=VDD
-5.0
-
5.0
mA
Output Low Current1
IOL
VOL=0.8V for PCLKS & BCLKS
30.0
47.0
-
mA
Output High Current1
IOH
VOL=2.0V for PCLKS & BCLKS
-
-66.0
-42.0
mA
Output Low Current1
IOL
VOL=0.8V for fixed CLKs
25.0
38.0
-
mA
Output High Current1
IOH
VOL=2.0V for fixed CLKs
-
-47.0
-30.0
mA
Output Low Voltage1
VOL
IOL=15mA for PCLKS & BCLKS
-
0.3
0.4
V
Output High
Voltage1
VOH
IOH=-30mA for PCLKS & BCLKS
2.4
2.8
-
V
Output Low Voltage1
VOL
IOL=12.5mA for fixed CLKs
-
0.3
0.4
V
Output High
Voltage1
VOH
IOH=-20mA for fixed CLKs
2.4
2.8
-
V
Supply Current
IDD
@66.5 MHz all outputs unloaded
-
55
110
mA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
ICS9159C-02
Electrical Characteristics at 3.3 V
VDD = 3.0 - 3.7 V, TA = 0 - 70oC unless otherwise stated
AC Characteristics
PARAMETER
SYMBOL
Rise Time1
Tr1
Fall Time1
Tf1
Rise Time1
Tr2
Fall Time1
Tf2
Duty Cycle1
Dt
TEST CONDITIONS
20pF load, 0.8 to 2.0V
PCLK & BCLK
20pF load, 2.0 to 0.8V
PCLK & BCLK
20pF load, 20% to 80%
PCLK & BCLK
20pF load, 80% to 20%
PCLK & BCLK
20pF load @ VOUT=1.4V
PCLK & BCLK Clocks;
Load=20pF, FOUT>25 MHz
Jitter, One Sigma1
Tj1s1
Jitter, Absolute1
Tjab1
Jitter, One Sigma1
Tj1s2
PCLK & BCLK Clocks;
Load=20pF, FOUT >25 MHz
Fixed CLK; Load=20pF
Tjab2
Fixed CLK; Load=20pF
1
Jitter, Absolute
1
Input Frequency
Logic Input
Capacitance1
Crystal Oscillator1
Capacitance1
Fi
MIN
TYP
MAX
UNITS
-
0.9
1.5
ns
-
0.8
1.4
ns
-
1.5
2.5
ns
-
1.4
2.4
ns
45
50
55
%
-
50
150
ps
-250
-
250
ps
-
1
3
%
-5
2
5
%
12.0
14.318
16.0
MHz
CIN
Logic input pins
-
5
-
pF
CINX
X1, X2 pins
-
18
-
pF
Power-on Time1
ton
From VDD=1.6V to 1st
crossing of 66.5 MHz VDD
supply ramp<40ms
-
2.5
4.5
ms
Frequency Settling
Time1
ts
From 1st crossing of
acquisition to <1% settling
-
2.0
4.0
ms
Clock Skew
Window1
Tsk1
PCLK to PCLK;
Load=20pF; @1.4V
-
150
250
ps
Clock Skew
Window
Tsk2
BCLK to BCLK;
Load=20pF; @1.4V
-
300
500
ps
Clock Skew
Window1
Tsk3
PCLK to BCLK;
Load=20pF; @1.4V
1
2.6
5
ns
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
ICS9159C-02
Electrical Characteristics at 5.0 V
VDD = 4.5 - 5.5 V, TA = 0 - 70oC unless otherwise stated
D C Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage
V IL
-
-
0.8
V
Input High Voltage
V IH
2.4
-
-
V
Input Low Current
I IL
V IN =0V
-45
-15
-
mA
Input High Current
I IH
V IN =V DD
-5.0
-
5.0
mA
Output Low Current 1
IOL
V OL =0.8V; for PCLKS & BCLKS
36.0
62.0
-
mA
Output High Current1
IOH
V OH =2.0V; for PCLKS & BCLKS
-
-152
-90.0
mA
Output Low Current 1
IOL
V OL =0.8V; for fixed CLKs
30.0
50.0
-
mA
Output High Current1
IOH
VOL=2.0V; for fixed CLKs
-
-110.0
-65.0
mA
Output Low Voltage 1
V OL
IOL =20mA; for PCLKS & BCLKS
-
0.25
0.4
V
Output High Voltage 1
V OH
IOH =-70mA; for PCLKS & BCLKS
2.4
4.0
-
V
Output Low Voltage 1
V OL
IOL =15mA; for fixed CLKs
-
0.2
0.4
V
Output High Voltage 1
V OH
2.4
4.7
-
V
Supply Current
IDD
-
80.0
160.0
mA
IOH =-50mA; for fixed CLKs
@66.5 MHz; all outputs unloaded
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
5
ICS9159C-02
Electrical Characteristics at 5.0 V
VDD = 4.5 - 5.5 V, TA = 0 - 70oC unless otherwise stated
AC Characteristics
PARAMETER
SYMBOL
1
Rise Time
Tr1
Fall Time1
Tf1
Rise Time1
Tr2
Fall Time1
Tf2
Duty Cycle1
Duty Cycle1
Dt
Dt2
Jitter, One Sigma1
Tj1s1
Jitter, Absolute1
Tjab1
Jitter, One Sigma1
Jitter, Absolute1
Input Frequency1
Logic Input
Capacitance1
Crystal Oscillator
Capacitance1
Tj1s2
Tjab2
Fi
Power-on Time1
Frequency Settling
Time1
Clock Skew
Window1
Clock Skew
Window1
Clock Skew
Window1
TEST CONDITIONS
20pF load, 0.8 to 2.0V
PCLK & BCLK
20pF load, 2.0 to 0.8V
PCLK & BCLK
20pF load, 20% to 80%
PCLK & BCLK
20pF load, 80% to 20%
PCLK & BCLK
20pF load @ VOUT=50%
20pF load @ VOUT=1.4V
PCLK & BCLK Clocks;
Load=20pF, RS=33
FOUT>25 MHz
PCLK & BCLK Clocks;
Load=20pF, RS=33
FOUT>25 MHz
Fixed CLK; Load=20pF RS=33
Fixed CLK; Load=20pF RS=33
MIN
TYP
MAX
UNITS
-
0.55
0.95
ns
-
0.52
0.90
ns
-
1.2
2.1
ns
-
1.1
2.0
ns
45
50
55
%
%
-
50
150
ps
-250
-
250
ps
-5
12.0
1
2
14.318
3
5
16.0
%
%
MHz
CIN
Logic input pins
-
5
-
pF
CINX
X1, X2 pins
-
18
-
pF
From VDD=1.6V to 1st crossing of
66.5 MHz VDD supply ramp<40ms
-
2.5
4.5
ms
-
2.0
4.0
ms
-
150
250
ps
-
300
500
ps
1
2.6
5
ns
ton
ts
Tsk1
Tsk2
Tsk3
From 1st crossing of acquisition to
<1% settling
PCLK to PCLK;
Load=20pF; @1.4V
BCLK to BCLK;
Load=20pF; @1.4V
PCLK to BCLK;
Load=20pF; @1.4V
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
6
ICS9159C-02
SOIC Package
Ordering Information
ICS9159C-02CW28
Example:
ICS XXXX - PPP XX ##
Lead Count
Lead Count=1,2 or 3 digits
Package Type
CW = 0.3" Body SOIC, CS = 0.15 Body SOIC
Pattern Number(2 or 3 digit number for parts with ROM code patterns)
DeviceType
(consists of 3 or 4 digit numbers and one alpha code on some parts.)
Prefix
ICS, AV=Standard Device; GSP=Genlock device
7
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
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