Maxim DS1875T+TR Pon triplexer and sfp controller Datasheet

Rev 1; 10/08
PON Triplexer and SFP Controller
The DS1875 controls and monitors all functions for burstmode transmitters, APD receivers, and video receivers.
It also includes a power-supply controller for APD bias
generation, and provides all SFF-8472 diagnostic and
monitoring functionality. The combined solution of the
DS1875 and the MAX3643 laser driver provides APC
loop, modulation current control, and eye safety functionality. Ten ADC channels monitor VCC, temperature
(both internal signals), and eight external monitor inputs
(MON1–MON8) that can be used to meet transmitter,
digital receiver, video receiver, and APD receiver-signal
monitoring requirements. Four total DAC outputs are
available. A PWM controller with feedback and compensation pins can be used to generate the bias for an APD
or as a step-down converter. Five I/O pins allow additional monitoring and configuration.
Applications
BPON, GPON, or EPON Optical Triplexers
SFF, SFP, and SFP+ Transceiver Modules
APD Controller
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS1875T+
-40°C to +95°C
38 TQFN-EP*
DS1875T+T&R
-40°C to +95°C
38 TQFN-EP*
+Denotes a lead-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
N.C.
MON3N
MON3P
DAC1
GND
M4DAC
FB
BIAS
MOD
COMP
VCC
TOP VIEW
BMD
Pin Configuration
31 30 29 28 27 26 25 24 23 22 21 20
GND 32
19 MON4
GND 33
18 MON2
SW 34
17 MON1
VCC 35
16 MON8/D3
DS1875
N.C. 36
15 MON7/D2
N.C. 37
14 MON6/D1
*EP
7
8
9
10 11 12
TX-D
VCC
GND
13 MON5/D0
♦ Meets All PON Burst-Timing Requirements for
Burst-Mode Operation
♦ Laser Bias Controlled by APC Loop and
Temperature Lookup Table (LUT)
♦ Laser Modulation Controlled by Temperature LUT
♦ Six Total DACs: Four External, Two Internal
♦ Two 8-Bit DACs, One of Which is Optionally
Controlled by MON4 Voltage
♦ Internal 8-Bit DAC Controlled by a TemperatureIndexed LUT
♦ PWM Controller
♦ Boost or Buck Mode
♦ Boost Mode: Uses Optional External
Components, Up to 90V Bias Generation
♦ 131kHz, 262kHz, 525kHz, or 1050kHz SelectableSwitching Frequency
♦ APD Overcurrent Protection Using Optional Fast
Shutdown
♦ 10 Analog Monitor Channels: Temperature, VCC,
Eight Monitors
♦ Internal, Factory-Calibrated Temperature Sensor
♦ RSSI with 29dB Electrical Dynamic
♦ Five I/O Pins for Additional Control and
Monitoring Functions, Four of Which are Either
Digital I/O or Analog Monitors
♦ Comprehensive Fault-Measurement System with
Maskable Laser Shutdown Capability
♦ Two-Level Password Access to Protect
Calibration Data
♦ 120 Bytes of Password-1 Protected Memory
♦ 128 Bytes of Password-2 Protected Memory in
Main Device Address
♦ 256 Additional Bytes Located at A0h Slave
Address
♦ I2C-Compatible Interface for Calibration and
Monitoring
♦ 2.85V to 3.9V Operating Voltage Range
♦ -40°C to +95°C Operating Temperature Range
♦ 38-Pin TQFN (5mm x 7mm) Package
LOSI
6
N.C.
5
N.C.
SCL
4
FETG
3
N.C.
2
TX-F
1
BEN
+
SDA
N.C. 38
Features
TQFN
(5mm × 7mm × 0.8mm)
*EXPOSED PAD.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
DS1875
General Description
DS1875
PON Triplexer and SFP Controller
TABLE OF CONTENTS
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Electrical Characteristics (DAC1 and M4DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Analog Input Characteristics (BMD, TXP HI, TXP LO, HBIAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Analog Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PWM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Timing Characteristics (Control Loop and Quick Trip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Analog Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Digital Thermometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Nonvolatile Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
I2C Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Typical Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Autodetect Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Open-Loop Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Closed-Loop Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Modulation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
BIAS and MOD Output During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
BIAS and MOD Output as a Function of Transmit Disable (TX-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
APC and Quick-Trip Shared Comparator Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Monitors and Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Power-On Analog (POA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Quick-Trip Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MON3 Quick Trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
ADC Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Right-Shifting ADC Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Transmit Fault (TX-F) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Safety Shutdown (FETG) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Determining Alarm Causes Using the I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2
_______________________________________________________________________________________
PON Triplexer and SFP Controller
Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Enhanced RSSI Monitoring (Dual Range Functionality) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Stability and Compensation Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
DAC1 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
M4DAC Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
I2C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
I2C Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Shadowed EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Lower Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 00h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 01h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 02h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 03h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 04h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 05h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 06h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 07h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 08h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Auxiliary A0h Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Lower Memory Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 00h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 01h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 02h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 03h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 04h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 05h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 06h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 07h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 08h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
_______________________________________________________________________________________
3
DS1875
TABLE OF CONTENTS (continued)
DS1875
PON Triplexer and SFP Controller
TABLE OF CONTENTS (continued)
Auxiliary Memory A0h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
LIST OF FIGURES
Figure 1. Power-Up Timing (BEN is a Long Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 2. TX-D Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 3. APC Loop and Quick-Trip Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 4. M3QT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 5. ADC Timing with EN5TO8B = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 6. ADC Timing with EN5TO8B = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 7. TX-F Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 8. FETG/Output Disable Timing (Fault Condition Detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 9. SEE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 10. RSSI Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 11. PWM Controller Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 12. PWM Controller Typical APD Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 13. PWM Controller Voltage Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 14. PWM Controller Current-Sink Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 15. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 16. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
LIST OF TABLES
Table 1. DS1875 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 2. Update Rate Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 3. ADC Default Monitor Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 4. TX-F as a Function of TX-D and Alarm Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 5. FETG, MOD, and BIAS Outputs as a Function of TX-D and Alarm Sources . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 6. MON3 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 7. MON3 Hysteresis Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4
_______________________________________________________________________________________
PON Triplexer and SFP Controller
Operating Temperature Range ...........................-40°C to +95°C
Programming Temperature Range .........................0°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
*Subject to not exceeding +6V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
MAX
UNITS
+2.85
+3.9
V
VIH:1
0.7 x
VCC
VCC +
0.3
V
Low-Level Input Voltage
(SDA, SCL, BEN)
VIL:1
-0.3
0.3 x
VCC
V
High-Level Input Voltage
(TX-D, LOSI, D0, D1, D2, D3)
VIH:2
2.0
VCC +
0.3
V
Low-Level Input Voltage
(TX-D, LOSI, D0, D1, D2, D3)
VIL:2
-0.3
+0.8
V
TYP
MAX
UNITS
5.5
10
mA
1
μA
Main Supply Voltage
VCC
High-Level Input Voltage
(SDA, SCL, BEN)
CONDITIONS
(Note 1)
MIN
TYP
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Supply Current
ICC
(Notes 1, 2)
Output Leakage
(SDA, TX-F, D0, D1, D2, D3)
ILO
(Note 2)
Low-Level Output Voltage
(SDA, TX-F, FETG, D0, D1, D2, D3)
VOL
High-Level Output Voltage
(FETG)
VOH
FETG Before Recall
MIN
I OL = 4mA
0.4
I OL = 6mA
0.6
I OH = 4mA
VCC 0.4
(Note 3)
V
V
10
100
nA
1
μA
Input Leakage Current
(SCL, BEN, TX-D, LOSI)
ILI:1
Digital Power-On Reset
POD
1.0
2.2
V
Analog Power-On Reset
POA
2.1
2.75
V
_______________________________________________________________________________________
5
DS1875
ABSOLUTE MAXIMUM RATINGS
Voltage Range on MON1–MON8,
BEN, BMD, and TX-D Pins
Relative to Ground .................................-0.5V to (VCC + 0.5V)*
Voltage Range on VCC, SDA, SCL,
D0–D3, and TX-F Pins Relative to Ground...............-0.5V to 6V
DS1875
PON Triplexer and SFP Controller
ELECTRICAL CHARACTERISTICS (DAC1 AND M4DAC)
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
DAC Output Range
DAC Output Resolution
TYP
MAX
UNITS
2.5
V
8
Bits
DAC Output Integral Nonlinearity
-1
+1
LSB
DAC Output Differential
Nonlinearity
-1
+1
LSB
DAC Error
-1.25
+1.25
%FS
DAC Temperature Drift
TA = +25°C
-2
+2
%FS
DAC Offset
-12
+12
mV
Maximum Load
-500
+500
μA
250
pF
MAX
UNITS
Maximum Load Capacitance
ANALOG INPUT CHARACTERISTICS (BMD, TXP HI, TXP LO, HBIAS)
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
BMD, TXP HI, TXP LO Full-Scale
Voltage
VAPC
HBIAS Full-Scale Voltage
CONDITIONS
MIN
(Note 4)
2.5
(Note 5)
V
1.25
BMD Input Resistance
35
Resolution
Error
TYP
TA = +25°C (Note 6)
Integral Nonlinearity
50
Temperature Drift
k
8
Bits
±2
%FS
-1
Differential Nonlinearity
V
65
+1
LSB
-1
+1
LSB
-2.5
+2.5
%FS
MAX
UNITS
ANALOG OUTPUT CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
BIAS Current
IBIAS Shutdown Current
SYMBOL
IBIAS
CONDITIONS
0.7
VMOD
TYP
1.2
IBIAS:OFF
Voltage at IBIAS
MOD Full-Scale Voltage
MIN
(Note 1)
mA
10
100
1.2
1.4
nA
V
(Note 5)
1.25
V
MOD Output Impedance
(Note 7)
3
k
VMOD Error
TA = +25°C (Note 8)
-1.25
+1.25
VMOD Integral Nonlinearity
-1
+1
LSB
VMOD Differential Nonlinearity
-1
+1
LSB
VMOD Temperature Drift
-2
+2
%FS
6
_______________________________________________________________________________________
%FS
PON Triplexer and SFP Controller
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
PWM-DAC Full-Scale Voltage
SYMBOL
CONDITIONS
MIN
VPWM-DAC
TYP
PWM-DAC Resolution
VPWM-DAC Full-Scale Voltage
Error
MAX
UNITS
8
Bits
1.25
TA = +25°C
V
1.25
%
VPWM-DAC Integral Nonlinearity
-1
1
LSB
VPWM-DAC Differential
Nonlinearity
-1
1
LSB
VPWM-DAC Temperature Drift
-2
+2
%FS
20
-5
+7
%
91
%
SW Output Impedance
SW Frequency Error
f SWER
SW Duty Cycle
DMAX
(Note 9)
89
90
Error-Amplifier Source Current
-10
μA
Error-Amplifier Sink Current
+10
μA
COMP High-Voltage Clamp
2.1
V
COMP Low-Voltage Clamp
0.8
V
Error-Amplifier
Transconductance
GM
425
μS
Error-Amplifier Output
Impedance
REA
260
M
5
pF
FB Pin Capacitance
TIMING CHARACTERISTICS (CONTROL LOOP AND QUICK TRIP)
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
First BMD Sample Following BEN
tFIRST
(Note 10)
CONDITIONS
Remaining Updates During BEN
tUPDATE
(Note 10)
MIN
TYP
MAX
UNITS
BEN High Time
tBEN:HIGH
400
BEN Low Time
tBEN:LOW
96
ns
ns
Output-Enable Time Following POA
t INIT
10
ms
BIAS and MOD Turn-Off Delay
t OFF
5
μs
BIAS and MOD Turn-On Delay
t ON
5
μs
FETG Turn-On Delay
tFETG:ON
5
μs
FETG Turn-Off Delay
tFETG:OFF
5
μs
_______________________________________________________________________________________
7
DS1875
PWM CHARACTERISTICS
DS1875
PON Triplexer and SFP Controller
ANALOG VOLTAGE MONITORING
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
ADC Resolution
MAX
13
Input/Supply Accuracy
(MON1–MON8, VCC)
ACC
Update Rate for Temp,
MON1–MON4, and VCC
tFRAME:1
Update Rate for MON5–MON8
tFRAME:2
Input/Supply Offset
(MON1–MON8, VCC)
VOS
At factory setting
Bit EN5TO8B is enabled in Table 02h,
Register 89h
(Note 11)
MON1–MON8
Factory Setting
TYP
Bits
0.25
0.50
%FS
78
95
ms
156
190
ms
0
5
LSB
2.5
Full scales are user programmable
VCC
V
6.5536
MON3 Fine
UNITS
312.5
μV
DIGITAL THERMOMETER
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
Thermometer Error
SYMBOL
T ERR
CONDITIONS
MIN
TYP
-40°C to +95°C
MAX
UNITS
±3.0
°C
MAX
UNITS
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
EEPROM Write Cycles
8
SYMBOL
CONDITIONS
MIN
At +85°C (Note 11)
50,000
At +25°C (Note 11)
200,000
TYP
_______________________________________________________________________________________
PON Triplexer and SFP Controller
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN).) (See Figure 15.)
PARAMETER
SYMBOL
CONDITIONS
(Note 12)
MIN
0
TYP
MAX
UNITS
400
kHz
SCL Clock Frequency
f SCL
Clock Pulse-Width Low
tLOW
1.3
μs
Clock Pulse-Width High
tHIGH
0.6
μs
Bus-Free Time Between STOP
and START Condition
tBUF
1.3
μs
START Hold Time
tHD:STA
0.6
μs
START Setup Time
t SU:STA
0.6
μs
Data in Hold Time
tHD:DAT
0
Data in Setup Time
t SU:DAT
100
0.9
μs
400
pF
ns
Capacitive Load for Each Bus Line
CB
Rise Time of Both SDA and SCL
Signals
tR
(Note 13)
20 +
0.1CB
300
ns
Fall Time of Both SDA and SCL
Signals
tF
(Note 13)
20 +
0.1CB
300
ns
20
ms
STOP Setup Time
t SU:STO
EEPROM Write Time
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
tW
0.6
(Note 14)
μs
All voltages are referenced to ground. Current into IC is positive, and current out of the IC is negative.
Digital inputs are at rail. FETG is disconnected. SDA = SCL = VCC. SW, DAC1, and M4DAC are not loaded.
See the Safety Shutdown (FETG) Output section for details.
Eight ranges allow the full scale to change from 625mV to 2.5V.
Eight ranges allow the full scale to change from 312.5mV to 1.25V.
This specification applies to the expected full-scale value for the selected range. See the COMP RANGING register
description for available full-scale ranges.
The output impedance of the DS1875 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be approximately 1.56kΩ.
This specification applies to the expected full-scale value for the selected range. See the MOD RANGING register
description for available full-scale ranges.
The switching frequency is selectable between four values: 131.25kHz, 262.5kHz, 525kHz, and 1050kHz.
See the APC and Quick-Trip Shared Comparator Timing section for details.
Guaranteed by design.
I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard mode.
CB—Total capacitance of one bus line in pF.
EEPROM write begins after a STOP condition occurs.
_______________________________________________________________________________________
9
DS1875
I2C TIMING SPECIFICATIONS
Typical Operating Characteristics
(VCC = +2.85V to +3.9V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
+95°C
+25°C
6.5
6.0
5.5
7.4
7.3
7.2
VCC = 3.9V
8.0
7.1
7.5
ICC (mA)
SUPPLY CURRENT (mA)
7.0
VCC = 2.85V
6.5
6.7
6.6
5.0
5.0
6.5
4.5
4.5
6.4
3.35
3.85
-40
-20
0
VCC (V)
8.0
SW = 131.25kHz
7.6
7.4
0
20
40
60
60
80
0.8
0.4
0.2
0
-0.2
-0.4
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
0
50
100
150
200
50
0
250
100
150
200
DAC1 AND M4DAC POSITION (DEC)
DAC1 AND M4DAC POSITION (DEC)
DAC1 AND M4DAC OFFSET vs. VCC
DAC1 AND M4DAC OFFSET VARIATION
vs. LOAD CURRENT
DAC1 AND M4DAC OUTPUT
vs. LOAD CURRENT
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
0.0008
VCC = 2.85V
0.0006
0.0004
VCC = 3.6V
0.0002
0
-0.0002
VCC = 3.9V
-0.0004
-0.0006
3.25
3.45
VCC (V)
3.65
3.85
OUTPUT WITHOUT OFFSET
1.257
VCC = 2.85V
1.255
1.253
1.251
VCC = 3.9V
1.249
1.245
-0.0010
3.05
250
1.247
-0.0008
-0.05
1.259
DAC1 AND M4DAC OUTPUT (V)
0.03
0.0010
DAC1 AND M4DAC OFFSET (mV)
DS1875 toc07
TEMPERATURE (°C)
TA = -40°C TO +95°C
LOAD = -0.5mA TO +0.5mA
2.85
40
DS1875 toc06
DS1875 toc05
0.6
80
20
DAC1 AND M4DAC INL
-1.0
-20
0
1.0
DAC1 AND M4DAC INL (LSB)
SW = 525kHz
-40
-20
TEMPERATURE (°C)
DS1875 toc08
ICC (mA)
SW = 1050kHz
0.04
-40
80
0.8
8.4
0.05
60
DAC1 AND M4DAC DNL
DAC1 AND M4DAC DNL (LSB)
8.6
SW = 262.5kHz
40
1.0
DS1875 toc04
8.8
7.8
20
SW = 131.25kHz
TEMPERATURE (°C)
SUPPLY CURRENT vs. TEMPERATURE
VCC = 5V, NO BIAS CURRENT
8.2
SW = 262.5kHz
6.8
6.0
-40°C
10
6.9
5.5
2.85
SW = 1050kHz
SW = 525kHz
7.0
DS1875 toc09
SUPPLY CURRENT (mA)
8.0
7.0
SDA = SCL = VCC
8.5
DS1875 toc03
9.0
DS1875 toc02
SDA = SCL = VCC
8.5
7.5
SUPPLY CURRENT vs. TEMPERATURE
VCC = 3.3V, NO BIAS CURRENT
SUPPLY CURRENT
vs. TEMPERATURE
DS1875 toc01
9.0
DAC1 AND M4DAC OFFSET (mV)
DS1875
PON Triplexer and SFP Controller
-0.5
-0.3
-0.1
0.1
LOAD CURRENT (mA)
0.3
0.5
-0.5
-0.3
-0.1
0.1
LOAD CURRENT (mA)
______________________________________________________________________________________
0.3
0.5
PON Triplexer and SFP Controller
40
30
70
CALCULATED
VALUE
60
50
40
30
0.2
0
-0.2
-0.4
20
-0.6
10
10
-0.8
0
0
-1.0
000 001 002 003 004 005 006 007
000 001 010 011 100 101 110 111
MOD RANGING VALUE (DEC)
COMP RANGING (DEC)
0
-0.2
0.4
0.8
0.6
0.2
0
-0.2
0.4
0.2
0
-0.2
-0.4
-0.4
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
-1.0
-1.0
0.5
1.0
1.5
2.5
2.0
0
50
100
150
MON1 TO MON8 INPUT VOLTAGE (V)
APC INDEX (DEC)
FB VOLTAGE vs. TEMPERATURE
PWM DAC = FFh
VOUT vs. VCC
VIN = 3.3V
200
DS1875 toc17
76.6
VOUT (V)
VOUT (V)
76.2
76.0
90.25
90.00
89.75
89.50
89.25
75.2
75.0
-20
0
20
40
TEMPERATURE (°C)
60
80
250
90.50
75.4
-40
200
90.75
75.6
1.240
150
DUTY-CYCLE LIMIT vs. TEMPERATURE
75.8
1.245
100
91.00
76.4
1.250
50
MOD INDEX (DEC)
76.8
1.255
0
250
77.0
DS1875 toc16
1.260
2.5
2.0
DS1875 toc15
0.6
VMOD INL (LSB)
0.2
1.5
VMOD INL vs. MOD INDEX
0.8
VBMD INL (LSB)
0.4
1.0
1.0
DS1875 toc14
0.6
0
0.5
MON1 TO MON8 INPUT VOLTAGE (V)
1.0
DS1875 toc13
USING FACTORY-PROGRAMMED
FULL-SCALE VALUE OF 2.5V
0.8
0
VBMD INL vs. APC INDEX
MON1 TO MON8 DNL
MON1 TO MON8 DNL (LSB)
0.4
20
1.0
VOUT (V)
0.6
DS1875 toc18
50
DESIRED
VALUE
80
USING FACTORY-PROGRAMMED
FULL-SCALE VALUE OF 2.5V
0.8
MON1 TO MON8 INL (LSB)
CHANGE IN VMOD (%)
CALCULATED
VALUE
60
90
CHANGE IN VBMD (%)
DESIRED
VALUE
70
MON1 TO MON8 INL
1.0
DS1875 toc11
90
80
100
DS1875 toc10
100
DESIRED AND CALCULATED CHANGE
IN VBMD vs. COMP RANGING
DS1875 toc12
CALCULATED AND DESIRED % CHANGE
IN VMOD vs. MOD RANGING
SW FREQUENCY
525kHz
262.5kHz
131.25kHZ
1050kHz
89.00
2.85
3.35
VCC (V)
3.85
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
______________________________________________________________________________________
11
DS1875
Typical Operating Characteristics (continued)
(VCC = +2.85V to +3.9V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VCC = +2.85V to +3.9V, TA = +25°C, unless otherwise noted.)
PWM DAC INL
0.75
0.75
0.25
0
-0.25
0.50
DAC DNL (LSB)
0.50
DAC INL (LSB)
0.50
1.00
DS1875 toc20
DS1875 toc19
0.75
M3QT DAC DNL
1.00
0.25
0
-0.25
0.25
0
-0.25
-0.50
-0.50
-0.50
-0.75
-0.75
-0.75
-1.00
-1.00
0
32
64
96
128 160 192 224 256
-1.00
0
32
64
DAC SETTING (DEC)
96
128 160 192 224 256
0
32
DAC SETTING (DEC)
64
128 160 192 224 256
96
DAC SETTING (DEC)
SW CURRENT INTO BSS123 FET
FREQUENCY = 1050kHz 50% DUTY CYCLE
M3QT DAC INL
DS1875 toc23
DS1875 toc22
1.00
0.75
1V/div
SW
0V
0.50
DAC INL (LSB)
DS1875 toc21
PWM DAC DNL
1.00
DAC DNL (LSB)
DS1875
PON Triplexer and SFP Controller
0.25
0
-0.25
10mA/div
-0.50
0mA
SW
CURRENT
-0.75
-1.00
0
32
64
96
128 160 192 224 256
100ns/div
DAC SETTING (dec)
SWITCHING WAVEFORMS
VIN = 3.3V, VOUT ~ 90V, IOUT ~ 1.25mA,
C2 = 0.1μF
PWM DAC CHANGING FROM 00h TO 80h
RCOMP = 24.3kΩ, CCOMP = 220nF
DS1875 toc25
DS1875 toc24
20V/div
0V
200mV/div
0V
VOUT
5V/div
0V
FB
50V/div
SW
0V
COMP
100mA/div
200mV/div
DUTY CYCLE
0mA
10%/div
0%
0V
5ms/div
12
INDUCTOR
VOLTAGE
100mV/div
0V
INDUCTOR
CURRENT
VOUT RIPPLE (AC-COUPLED)
2μs/div
______________________________________________________________________________________
PON Triplexer and SFP Controller
PIN
NAME
1
BEN
Burst-Enable Input. Triggers the samples for the APC and quick-trip monitors.
FUNCTION
2
SDA
I2C Serial-Data Input/Output
3
SCL
I2C Serial-Clock Input
4
TX-F
Transmit-Fault Output
5, 7, 11, 20,
36, 37, 38
N.C.
No Connection
6
FETG
FET Gate Output. Signals an external n-channel or p-channel MOSFET to enable/disable the
laser’s current.
Transmit-Disable Input. Disables analog outputs.
8
TX-D
9, 31, 35
VCC
Power-Supply Input (2.85V to 3.9V)
10, 24, 32, 33
GND
Ground Connection
12
LOSI
Loss-of-Signal Input. Open-collector buffer for external loss-of-signal input. This input is
accessible in the status register through the I2C interface.
13
MON5/D0
External Monitor Input 5 or Digital I/O 0. This signal is the open-collector output driver for IN. It
can also be controlled by the MUX0 and OUT0 bits. The voltage level of this pin can be read at
IN0. In analog input mode, the voltage at this pin is digitized by the internal 13-bit analog-todigital converter and can be read through the I2C interface. Alarm and warning values can be
assigned to interrupt the processor based on the ADC result.
External Monitor Inputs 6, 7, and 8 or Digital I/O 1, 2, and 3. In digital mode, these open-collector
outputs are controlled by the OUTx bits, and their voltage levels can be read at the INx bits. In
analog input mode, the voltages at these pins are digitized by the internal 13-bit analog-to-digital
converter and can be read through the I2C interface. Alarm and warning values can be assigned
to interrupt the processor based on the ADC result. D2 is configurable as a quick-trip output for
MON3.
External Monitor Input 1, 2, and 4. The voltage at these pins is digitized by the internal 13-bit
analog-to-digital converter and can be read through the I2C interface. Alarm and warning values
can be assigned to interrupt the processor based on the ADC result.
14, 15, 16
MON6/D1,
MON7/D2,
MON8/D3
17, 18, 19
MON1,
MON2,
MON4
21, 22
MON3N,
MON3P
23
DAC1
25
M4DAC
26
FB
27
BIAS
Bias-Current Output. This 13-bit current output generates the bias current reference for the MAX3643.
28
MOD
Modulation Output Voltage. This 8-bit voltage output has eight full-scale ranges from 1.25V to
0.3125V. This pin is connected to the MAX3643’s VMSET input to control the modulation current.
29
COMP
Compensation for Error Amplifier in PWM Controller
30
BMD
External Monitor Input 3. This is a differential input that is digitized by the internal 13-bit ADC
and can be read through the I2C interface. Alarm and warning values can be assigned to interrupt
the processor based on the ADC result. When used as a single-ended input, connect MON3N to
ground.
8-Bit DAC Output. Driven either by I2C interface or temperature-indexed LUT.
8-Bit DAC Output for Generating Analog Voltage. Can be controlled by a LUT indexed by the
voltage applied to MON4.
Converter Feedback. Input to error amplifier. The other input to the error amplifier is an 8-bit DAC.
The DAC can be driven by a temperature-indexed LUT. The output of the error amplifier is the
input of the comparator used to create the PWM signal.
Back Monitor Diode Input (Feedback Voltage, Transmit Power Monitor)
34
SW
PWM Output. This is typically the switching node of a PWM converter. In conjunction with FB, a
boost converter, buck converter, or analog 8-bit output can be created.
—
EP
Exposed Pad
______________________________________________________________________________________
13
DS1875
Pin Description
PON Triplexer and SFP Controller
DS1875
Block Diagram
DS1865 MEMORY ORGANIZATION
VCC
VCC
SDA
SCL
MAIN MEMORY
EEPROM/SRAM
ADC CONFIGURATION/RESULTS
TABLE 00h (EEPROM)
SYSTEM STATUS BITS
ADDITIONAL MONITORS
ALARM/WARNING COMPARISONS
I2C
INTERFACE
EEPROM
256 BYTES AT
A0h SLAVE
ADDRESS
VCC
TABLE 01h (EEPROM)
USER MEMORY, ALARM TRAP
TABLE 05h (EEPROM)
ADC TE LUT
TABLE 02h (EEPROM)
CONFIGURATION AND CALIBRATION
TABLE 06h (EEPROM)
M4DAC LUT
TABLE 03h (EEPROM)
USER MEMORY
TABLE 07h (EEPROM)
PWM LUT
TABLE 04h (EEPROM)
MODULATION LUT
TABLE 08h (EEPROM)
BIAS OL LUT
SRAM RESET
POWER-ON ANALOG
VCC > VPOA
NONMASKABLE
INTERRUPT
MON1
MON2
TX-F
ANALOG MUX
MON3N
MON3P
MON4
INTERRUPT
MASK
DIGITAL LIMIT
COMPARATOR FOR
ADC RESULTS
13-BIT
ADC
LATCH
ENABLE
INTERRUPT
LATCH
MON[5:8]
TEMP
SENSOR
INTERRUPT
MASK
SAMPLE
CONTROL
BEN
INTERRUPT
LATCH
FETG
TABLE 08h
BIAS OL LUT
TEMP INDEXED
BIAS MAX
QUICK TRIP
MUX
BMD
HBIAS
QUICK-TRIP LIMIT
MUX
HTXP
QUICK-TRIP LIMIT
LTXP
QUICK-TRIP LIMIT
DIGITAL
APC
INTEGRATOR
8-BIT
DAC WITH
SCALING
MUX
APC SET POINT FROM
TRACKING-ERROR TABLE
TX-D INPUT
MOD LUT
TX-D
MON5/D0
TTL
MON5
0
1
TTL
LOS STATUS/
D0 IN
D0 OUT
INV0
TABLE 07h
PWM VOLTAGE
LUT CAN BE INDEXED BY
TEMP SENSOR
MUX
13-BIT
DAC
BIAS
8-BIT
DAC WITH
SCALING
MOD
PWM
SW
8-BIT
PWM-DAC
LOSI
MUX0
MON6/D1
TTL
MON6
D1 OUT
MON7/D2
TTL
MON7
MON8/D3
GND
14
0
1
TTL
TTL
MON8
D1 IN
D2 IN
D2 OUT
INV M3QT
COMP
I2C CONTROL
FB
TABLE 06h
M4DAC LUT INDEXED BY MON4
M4DAC
8-BIT, 2.5V
FULL SCALE
M4DAC
I2C CONTROL
DAC1
8-BIT, 2.5V
FULL SCALE
DAC1
M3QT
MUX2
D3 IN
D3 OUT
DS1875
______________________________________________________________________________________
PON Triplexer and SFP Controller
3.3V
IN+
VCC
IN-
OUT+
BEN+
OUT-
BEN-
BIASMAX3643
DIS
BCMON
BENOUT
BIASSET
VBSET
VREF
MODSET
IMAX
VMSET
GND
BIAS+
MAX4003
RF DETECTOR
12V
MOD
I2C COMMUNICATION
BIAS BEN
SDA
BMD
SCL
MON1
FAULT OUTPUT
TX-F
MON2
TRANSMIT POWER
DISABLE INPUT
TX-D
MON3
RECEIVER LOS
LOSI
MON4
RECEIVE POWER
CATV RF POWER
OPEN-DRAIN LOS OUTPUT
CATV
FETG
D0
GAIN CONTROL
M4DAC
ADDITIONAL DIGITAL I/O
MAX3654
FTTH CATV
TIA
D3
D1
CATV SHUTDOWN CONTROL
3.3V
VCC
RAGC
DS1875
3.3V
SW
GND
ADDITIONAL MONITORS
MON[5:7]
MAX4007
CURRENT MONITOR
FB
DAC1
D2
MON8
RECEIVE
POWER
(CURRENT)
VOLTAGE REFERENCE
APD OVERLOAD QUICK TRIP
APD VOLTAGE MONITOR
COMP
ROSA
APD
TIA
OPTIONAL
______________________________________________________________________________________
15
DS1875
Typical Operating Circuit
DS1875
PON Triplexer and SFP Controller
Detailed Description
The DS1875 integrates the control and monitoring functionality required to implement a PON system using
Maxim’s MAX3643 compact burst-mode laser driver.
The compact laser-driver solution offers a considerable
cost benefit by integrating control and monitoring features in the low-power CMOS process, while leaving
only the high-speed portions to the laser driver. Key
components of the DS1875 are shown in the Block
Diagram and described in subsequent sections. Table
1 contains a list of acronyms used in this data sheet.
Table 1. DS1875 Acronyms
ACRONYM
10GEPON
ADC
Analog-to-Digital Converter
AGC
Automatic Gain Control
APC
Automatic Power Control
APD
Avalanche Photodiode
BM
Burst Mode
BPON
Broadband PON
CATV
Cable Television
EPON
Ethernet PON
ER
Extinction Ratio
DAC
Digital-to-Analog Converter
FTTH
Fiber-to-the-Home
FTTX
Fiber-to-the-X
GEPON
Gigabit Ethernet PON
GPON
Gigabit PON
LOS
Loss of Signal
LUT
Lookup Table
TE
Tracking Error
TIA
Transimpedance Amplifier
ROSA
Receiver Optical Subassembly
RSSI
Receive Signal Strength Indicator
PON
Passive Optical Network
PWM
Pulse-Width Modulation
SFF
Small Form Factor
SFF-8472
SFP
16
DEFINITION
10-Gigabit Ethernet PON
Document Defining Register Map of
SFPs and SFFs
Small Form Factor Pluggable
SFP+
Enhanced SFP
TOSA
Transmit Optical Subassembly
Bias Control
Bias current is controlled by an APC loop. The APC
loop uses digital techniques to overcome the difficulties
associated with controlling burst-mode systems.
Autodetect Bias Control
This is the default mode of operation. In autodetect bias
control, transmit burst length is monitored. A “short
burst” is declared when the burst is shorter than
expected based on the sample rate setting in Table
02h, Register 88h. In the case that 32 consecutive short
bursts are transmitted, the integrator is disabled and
the BIAS DAC is loaded from the BIAS LUT (Table 08h).
Any single burst of adequate burst length re-enables
the APC integrator.
Open-Loop Bias Control
Open-loop control is configured by setting FBOL in
Table 02h, Register C7h. In this mode, the BIAS LUT
(Table 08h) is directly loaded to the BIAS DAC output.
The BIAS LUT can be programmed in 2°C increments
over the 40°C to +102°C range. It is left-shifted so that
the LUT value is loaded to either the DAC MSB or the
DAC MSB-1 (Bit BOLFS, Table 02h, Register 89h).
Closed-Loop Bias Control
The closed-loop control requires a burst length long
enough to satisfy the sample rate settings in Table 02h,
Register 88h (APC_SR[3:0]). Closed-loop control is
configured by setting FBCL in Table 02h, Register C7h.
In this mode, the APC integrator is enabled, which controls the BIAS DAC.
The APC loop begins by loading the value from the
BIAS LUT (Table 08h) indexed by the present temperature conversion. The feedback for the APC loop is the
monitor diode (BMD) current, which is converted to a
voltage using an external resistor. The feedback voltage is compared to an 8-bit scaleable voltage reference, which determines the APC set point of the
system. Scaling of the reference voltage accommodates the wide range in photodiode sensitivities. This
allows the application to take full advantage of the APC
reference’s resolution.
The DS1875 has an LUT to allow the APC set point to
change as a function of temperature to compensate for
TE. The TE LUT (Table 05h) has 36 entries that determine the APC setting in 4°C windows between -40°C to
+100°C. Ranging of the APC DAC is possible by programming a single byte in Table 02h, Register 8Dh.
______________________________________________________________________________________
PON Triplexer and SFP Controller
BIAS and MOD Output During Power-Up
On power-up the modulation and bias outputs remain off
until VCC is above VPOA, a temperature conversion has
been completed, and, if the VCC ADC alarm is enabled,
a VCC conversion above the customer-defined VCC low
alarm level must clear the VCC low alarm (tINIT). Once all
these conditions (tINIT) are satisfied, the MOD output is
enabled with the value determined by the temperature
conversion and the modulation LUT (Table 04h).
When the MOD output is enabled, the BIAS output is
turned on to a value equal to the temperature-indexed
value in the BIAS LUT (Table 08h). Next, the APC integrator is enabled, and single LSB steps are taken to
tightly control the average power.
Modulation Control
The MOD output is an 8-bit scaleable voltage output
that interfaces with the MAX3643’s VMSET input. An
external resistor to ground from the MAX3643’s
MODSET pin sets the maximum current that the voltage
at the VMSET input can produce for a given output
range. This resistor value should be chosen to produce
the maximum modulation current the laser type requires
over temperature. Then the MOD output’s scaling is
used to calibrate the full-scale (FS) modulation output
to a particular laser’s requirements. This allows the
application to take full advantage of the MOD output’s
resolution. The modulation LUT can be programmed in
2°C increments over the -40°C to +102°C range.
Ranging of the MOD DAC is possible by programming
a single byte in Table 02h, Register 8Bh.
VCC
If a fault is detected and TX-D is toggled to re-enable
the outputs, the DS1875 powers up following a similar
sequence to an initial power-up. The only difference is
that the DS1875 already determined the present temperature, so the t INIT time is not required for the
DS1875 to recall the APC and MOD set points from
EEPROM.
VPOA
tINIT
VMOD
BIAS LUT
VALUE
APC INTEGRATOR ON
IBIAS
BIAS
SAMPLE
1
2
3
4
5
6
7
8
9
10
11
12
13
Figure 1. Power-Up Timing (BEN is a Long Burst)
______________________________________________________________________________________
17
DS1875
DC Operation
When using autodetect mode or closed-loop mode,
BEN should be equal to VCC or long burst. In open-loop
mode, BEN should be ground or any burst length.
DS1875
PON Triplexer and SFP Controller
BIAS and MOD Output as a Function of
Transmit Disable (TX-D)
If the TX-D pin is asserted (logic 1) during normal operation, the outputs are disabled within tOFF. When TX-D
is deasserted (logic 0), the DS1875 turns on the MOD
output with the value associated with the present temperature and initializes the BIAS using the same search
algorithm used at startup. When asserted, the SOFT
TX-D bit (Lower Memory, Register 6Eh) offers a software control identical to the TX-D pin (see Figure 2).
The DS1875 has a programmable comparator sample
time based on an internally generated clock to facilitate
a wide variety of external filtering options suitable for
burst-mode transmitters. The rising edge of BEN triggers the sample to occur, and the Update Rate register
(Table 02h, Register 88h) determines the sampling time.
The first sample occurs (tFIRST) after the rising edge of
BEN. The internal clock is asynchronous to BEN, causing a ±50ns uncertainty regarding when the first sample
will occur following BEN. After the first sample occurs,
subsequent samples occur on a regular interval, tREP.
Table 2 shows the sample rate options available.
IBIAS
tOFF
tON
Updates to the TXP HI and TXP LO quick-trip alarms do
not occur during the BEN low time. The BIAS HI quick
trip can be sampled during the burst-low time. Any
VMOD
tOFF
tON
Table 2. Update Rate Timing
TX-D
APC_SR[3:0]
MINIMUM TIME
FROM BEN TO
FIRST SAMPLE
(tFIRST) ±50ns
(ns)
REPEATED
SAMPLE PERIOD
FOLLOWING FIRST
SAMPLE (tREP)
(ns)
0000b
350
800
0001b
550
1200
0010b
750
1600
0011b
950
2000
0100b
1350
2800
0101b
1550
3200
0110b
1750
3600
0111b
2150
4400
1000b
2950
6000
1001b*
3150
6400
Figure 2. TX-D Timing
APC and Quick-Trip Shared Comparator
Timing
As shown in Figure 3, the DS1875’s input comparator is
shared between the APC control loop and the three
quick-trip alarms (TXP HI, TXP LO, and BIAS HI). The
comparator polls the alarms in a multiplexed sequence.
Six of every eight comparator readings are used for
APC loop-bias current control. The other two updates
are used to check the HTXP/LTXP (monitor diode voltage) and the HBIAS (MON1) signals against the internal APC and BIAS reference. If the last APC
comparison was higher than the APC set point, it
makes an HTXP comparison, and if it is lower, it makes
an LTXP comparison. Depending on the results of the
comparison, the corresponding alarms and warnings
(TXP HI, TXP LO) are asserted or deasserted.
BEN
*All codes greater than 1001b (1010b to 1111b) use the
maximum sample time of code 1001b.
tFIRST
tREP
APC QUICK-TRIP
SAMPLE TIMES
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
HTXP/LTXP
SAMPLE
HBIAS
SAMPLE
Figure 3. APC Loop and Quick-Trip Sample Timing
18
______________________________________________________________________________________
APC
SAMPLE
PON Triplexer and SFP Controller
Monitors and Fault Detection
Monitors
Monitoring functions on the DS1875 include a power-on
analog (POA) VCC comparison, five quick-trip comparators, and ADC channels. This monitoring combined
with the interrupt masks determine if the DS1875 shuts
down its outputs and triggers the TX-F and FETG outputs. All the monitoring levels and interrupt masks are
user programmable with the exception of POA, which
trips at a fixed range and is nonmaskable for safety
reasons.
Power-On Analog (POA)
POA holds the DS1875 in reset until VCC is at a suitable
level (VCC > VPOA) for the part to accurately measure
with its ADC and compare analog signals with its quicktrip monitors. Because VCC cannot be measured by the
ADC when VCC is less than VPOA, POA also asserts the
VCC low alarm, which is cleared by a VCC ADC conversion greater than the customer-programmable VCC low
ADC limit. This allows a programmable limit to ensure
that the head room requirements of the transceiver are
satisfied during slow power-up. The TX-F and FETG
outputs do not latch until there is a conversion above
the VCC low limit. The POA alarm is nonmaskable. The
TX-F and FETG outputs are asserted when V CC is
below VPOA. See the Low-Voltage Operation section for
more information.
Five Quick-Trip Monitors and Alarms
Five quick-trip monitors are provided to detect potential
laser safety issues. These monitor:
1) High Bias Current (HBIAS)
2) Low Transmit Power (LTXP)
3) High Transmit Power (HTXP)
4) Max Output Current (BIAS MAX)
5) MON3 Quick Trip (M3QT)
The high- and low-transmit power quick-trip registers
(HTXP and LTXP) set the thresholds used to compare
against the BMD voltage to determine if the transmit
power is within specification. The HBIAS quick trip compares the MON1 input (generally from the MAX3643
bias monitor output) against its threshold setting to
determine if the present bias current is above specifica-
tion. The BIAS MAX quick trip is a digital comparison
that determines if the BIAS DAC indicates that the bias
current is above specification. IBIAS is not allowed to
exceed the value set in the MAX BIAS register. When
the DS1875 detects that the bias is at the limit, it sets
the BIAS MAX status bit and clamps the bias current at
the MAX BIAS level. In the closed-loop mode, if the
recalled value from the BIAS LUT is greater than MAX
BIAS then, the update is not done and IBIAS reverts to
the previous IBIAS value. The quick trips are routed to
the TX-F and FETG outputs through interrupt masks to
allow combinations of these alarms to be used to trigger
these outputs. When FETG is triggered, the DS1875 also
disables the MOD and BIAS outputs. See the BIAS and
MOD Output During Power-Up section for details.
MON3 Quick Trip
One additional quick trip is used to protect the APD
from overcurrent. MON3P is used to monitor the current
through the APD. When MON3P exceeds a threshold
set by the M3QT DAC register (Table 02h, Register
C3h), the PWM is shut down by blocking SW pulses.
The MON3 comparison is single-ended referenced to
ground. In the case where MON3 is used differentially
and not referenced to ground, this must be considered
when setting the MON3 quick-trip threshold.
Additionally, the D2 pin can be driven either high or low
as determined by INV M3QT and MUX M3QT bits in
Lower Memory, Register 79h. An external switch controlled by pin D2 may be used to clamp the converter’s
output when MON3 quick trip occurs. This external
switch discharges the output voltage much faster than
allowing the load to discharge the rail. The MON3
quick-trip alarm can be latched by enabling M3QT LEN
in Table 02h, Register 89h. The latch is reset by setting
M3QT RESET in Lower Memory, Register 78h. A soft
quick trip is performed by setting SOFT M3QT in Lower
Memory, Register 78h (see Figure 4).
ADC Monitors and Alarms
The ADC monitors six channels that measure temperature (internal temp sensor), VCC, and MON1–MON4
using an analog multiplexer to measure them round
robin with a single ADC. Each channel has a customerprogrammable full-scale range and offset value that is
factory programmed to default value (see Table 3).
Additionally, MON1–MON4 can right-shift results by up
to 7 bits before the results are compared to alarm
thresholds or read over the I2C bus. This allows customers with specified ADC ranges to calibrate the ADC
full scale to a factor of 1/2n their specified range to
measure small signals. The DS1875 can then right-shift
the results by n bits to maintain the bit weight of their
specification.
______________________________________________________________________________________
19
DS1875
quick-trip alarm that is detected by default remains
active until a subsequent comparator sample shows the
condition no longer exists. A second bias-current monitor (BIAS MAX) compares the DS1875’s BIAS DAC’s
code to a digital value stored in the MAX BIAS register.
This comparison is made at every bias-current update
to ensure that a high bias current is quickly detected.
DS1875
PON Triplexer and SFP Controller
TRIP CONDITION
mCLK
(525kHz)
CAPTURE ALARM
M3QT ALARM
(UNLATCHED)
Figure 4. M3QT Timing
ONE ADC CYCLE
MON4
TEMP
VCC
MON1
MON2
MON3
MON4
TEMP
tFRAME1
Figure 5. ADC Timing with EN5TO8B = 0
TEMP
VCC
MON1
MON2
MON3
MON4
MON5
MON6
tFRAME2
TEMP
VCC
MON1
MON2
MON3
MON4
MON7
MON8
tFRAME2
Figure 6. ADC Timing with EN5TO8B = 1
The ADC results (after right-shifting, if used) are compared to high and low alarm and warning thresholds
after each conversion. The alarm values can be used to
trigger the TX-F or FETG outputs. These ADC thresholds
are user programmable through the I2C interface, as
well as masking registers that can be used to prevent
the alarms from triggering the TX-F and FETG outputs.
Table 3. ADC Default Monitor Ranges
+FS
SIGNAL
+FS
HEX
-FS
SIGNAL
-FS
HEX
Temperature (°C)
127.996
7FFF
-128
8000
VCC (V)
6.5528
FFF8
0
0000
MON1–MON8 (V)
2.4997
FFF8
0
0000
SIGNAL
20
ADC Timing
There are 10 analog channels that are digitized in a
sequential fashion. The MON5–MON8 channels are
sampled depending on the state of the EN5TO8B bit in
Table 02h, Register 89h. If the bit is programmed to
logic 0, the ADC cycles through temperature, VCC, and
MON1–MON4 (Figure 5). If the bit is programmed to
logic 1, all 10 channels are digitized, including channels MON5–MON8 (Figure 6). In this mode (EN5TO8B
= 0), each of MON5–MON8 is sampled on alternate
cycles, as shown in Figure 5. The total time required to
convert one set of channels is the sequential ADC
cycle time, tFRAME1 or tFRAME2 (see Figure 6).
______________________________________________________________________________________
PON Triplexer and SFP Controller
62h–6Bh). This is true during the setup of internal calibration as well as during subsequent data conversions.
Transmit Fault (TX-F) Output
The TX-F output has masking registers for the ADC
alarms and the QT alarms to select which comparisons
cause it to assert. In addition, the FETG alarm is selectable through the TX-F mask to cause TX-F to assert. All
alarms, with the exception of FETG, only cause TX-F to
remain active while the alarm condition persists.
However, the TX-F latch bit can enable the TX-F output
to remain active until it is cleared by the TX-F reset bit,
TX-D, SOFT TX-D, or by power cycling the part. If the
FETG output is configured to trigger TX-F, it indicates
that the DS1875 is in shutdown and requires TX-D,
SOFT TX-D, or cycling power to reset. Only enabled
alarms activate TX-F (see Figure 7). Table 4 shows
TX-F as a function of TX-D and the alarm sources.
Table 4. TX-F as a Function of TX-D and
Alarm Sources
VCC > VPOA
TX-D
NONMASKED
TX-F ALARM
TX-F
No
X
X
1
Yes
0
0
0
Yes
0
1
1
Yes
1
X
0
TX-F LATCHED OPERATION
DETECTION OF
TX-F FAULT
TX-D OR
TX-F RESET
TX-F
TX-F NONLATCHED OPERATION
DETECTION OF
TX-F FAULT
TX-F
Figure 7. TX-F Timing
______________________________________________________________________________________
21
DS1875
Right-Shifting ADC Result
If the weighting of the ADC digital reading must conform to a predetermined full-scale value defined by a
standard’s specification, then right-shifting can be used
to adjust the predetermined full-scale analog measurement range while maintaining the weighting of the ADC
results. The DS1875’s range is wide enough to cover all
requirements; when the maximum input value is ≤ 1/2
the FS value, right-shifting can be used to obtain
greater accuracy. For instance, the maximum voltage
might be 1/8th the specified predetermined full-scale
value, so only 1/8th the converter’s range is used. An
alternative is to calibrate the ADC’s full-scale range to
1/8th the readable predetermined full-scale value and
use a right-shift value of 3. With this implementation, the
resolution of the measurement is increased by a factor
of 8, and because the result is digitally divided by 8 by
right-shifting, the bit weight of the measurement still
meets the standard’s specification (i.e., SFF-8472).
The right-shift operation on the ADC result is carried out
based on the contents of RIGHT SHIFT1/0 registers
(Table 02h, Registers 8Eh–8Fh). Four analog channels,
MON1–MON4, have 3 bits each allocated to set the
number of right-shifts. Up to seven right-shift operations
are allowed and are executed as a part of every conversion before the results are compared to the high and
low alarm levels, or loaded into their corresponding
measurement registers (Table 01h, Registers
DS1875
PON Triplexer and SFP Controller
DETECTION OF
FETG FAULT
TX-D
IBIAS
VMOD
FETG*
tOFF
tON
tOFF
tON
tFETG:ON
tFETG:OFF
*FETG DIR = 0
Figure 8. FETG/Output Disable Timing (Fault Condition Detected)
Safety Shutdown (FETG) Output
The FETG output has masking registers (separate from
TX-F) for the ADC alarms and the QT alarms to select
which comparisons cause it to assert. Unlike TX-F, the
FETG output is always latched. Its output polarity is
programmable to allow an external nMOS or pMOS to
open during alarms to shut off the laser-diode current.
If the FETG output triggers, indicating that the DS1875
is in shutdown, it requires TX-D, SOFT TX-D, or cycling
power to be reset. Under all conditions, when the analog outputs are reinitialized after being disabled, all the
alarms with the exception of the VCC low ADC alarm
are cleared. The VCC low alarm must remain active to
prevent the output from attempting to operate when
inadequate VCC exists to operate the laser driver. Once
adequate VCC is present to clear the VCC low alarm,
the outputs are enabled following the same sequence
as the power-up sequence.
As previously mentioned, the FETG is an output used to
disable the laser current through a series nMOS or
pMOS. This requires that the FETG output can sink or
source current. Because the DS1875 does not know if it
should sink or source current before V CC exceeds
VPOA, which triggers the EE recall, this output is high
impedance when VCC is below VPOA (see the LowVoltage Operation section for details and diagram). The
application circuit should use a pullup or pulldown
resistor on this pin that pulls FETG to the alarm/shutdown state (high for a pMOS, low for a nMOS). Once
VCC is above VPOA, the DS1875 pulls the FETG output
to the state determined by the FETG DIR bit (Table 02h,
22
Register 89h). Set FETG DIR to 0 if an nMOS is used
and 1 if a pMOS is used.
Table 5. FETG, MOD, and BIAS Outputs
as a Function of TX-D and Alarm Sources
VCC >
VPOA
TX-D
NONMASKED
FETG ALARM
FETG
MOD AND
BIAS
OUTPUTS
Yes
0
0
FETG
DIR
Enabled
Yes
0
1
FETG
DIR
Disabled
Yes
1
X
FETG
DIR
Disabled
Determining Alarm Causes Using the I2C
Interface
To determine the cause of the TX-F or FETG alarm, the
system processor can read the DS1875’s alarm trap bytes
(ATB) through the I2C interface (Table 01h, Registers
F8h–FBh). The ATB has a bit for each alarm. Any time an
alarm occurs, regardless of the mask bit’s state, the
DS1875 sets the corresponding bit in the ATB. Active ATB
bits remain set until written to 0s through the I2C interface.
On power-up, the ATB is 0s until alarms dictate otherwise.
FETG causes additional alarms that make it difficult to
determine the root cause of the problem. Therefore, no
updates are made to the ATB when FETG occurs.
______________________________________________________________________________________
PON Triplexer and SFP Controller
Low-Voltage Operation
The DS1875 contains two power-on reset (POR) levels.
The lower level is a digital POR (VPOD) and the higher
level is an analog POR (VPOA). At startup, before the
supply voltage rises above VPOA, the outputs are disabled (FETG and BIAS outputs are high impedance,
MOD is low), all SRAM locations are low (including
shadowed EEPROM (SEE)), and all analog circuitry is
disabled. When V CC reaches V POA , the SEE is
recalled, and the analog circuitry is enabled. While VCC
remains above VPOA, the device is in its normal operating state, and it responds based on its nonvolatile configuration. If during operation VCC falls below VPOA but
is still above VPOD, the SRAM retains the SEE settings
from the first SEE recall, but the device analog is shut
down and the outputs are disabled. FETG is driven to
its alarm state defined by the FETG DIR bit (Table 02h,
Register 89h). If the supply voltage recovers back
above VPOA, the device immediately resumes normal
functioning. When the supply voltage falls below VPOD,
the device SRAM is placed in its default state and
another SEE recall is required to reload the nonvolatile
settings. The EEPROM recall occurs the next time VCC
exceeds VPOA. Figure 9 shows the sequence of events
as the voltage varies.
SEE RECALL
Any time VCC is above VPOD, the I2C interface can be
used to determine if VCC is below the VPOA level. This
is accomplished by checking the RDYB bit in the status
(Lower Memory, Register 6Eh) byte. RDYB is set when
V CC is below V POA . When V CC rises above V POA ,
RDYB is timed (within 500µs) to go to 0, at which point
the part is fully functional.
For all device addresses sourced from EEPROM (Table
02h, Register 8Ch), the default device address is A2h
until VCC exceeds VPOA, allowing the device address
to be recalled from the EEPROM.
Enhanced RSSI Monitoring (Dual Range
Functionality)
The DS1875 offers a new feature to improve the accuracy and range of MON3, which is most commonly
used for monitoring RSSI. This feature enables rightshifting (along with its gain and offset settings) when
the input signal is below a set threshold (within the
range that benefits using right-shifting) and then automatically disables right-shifting (recalling different gain
and offset settings) when the input signal exceeds the
threshold. Also, to prevent “chattering,” hysteresis prevents excessive switching between modes in addition
to ensuring that continuity is maintained. Dual range
operation is enabled by default (factory programmed in
EEPROM). However, it can easily be disabled through
the RSSI_FF and RSSI_FC bits. When dual range operation is disabled, MON3 operates identically to the
other MON channels, although featuring a differential
input.
SEE RECALL
VPOA
VCC
VPOD
FETG
HIGH
IMPEDANCE
SEE
PRECHARGED
TO 0
NORMAL
OPERATION
DRIVEN TO
FETG DIR
RECALLED
VALUE
HIGH
IMPEDANCE
PRECHARGED
TO 0
NORMAL
OPERATION
DRIVEN TO
FETG DIR
NORMAL
OPERATION
RECALLED
VALUE
DRIVEN TO
FETG DIR
HIGH
IMPEDANCE
PRECHARGED
TO 0
Figure 9. SEE Timing
______________________________________________________________________________________
23
DS1875
Die Identification
The DS1875 has an ID hard-coded to its die. Two registers (Table 02h, Registers 86h–87h) are assigned for
this feature. Byte 86h reads 75h to identify the part as
the DS1875; byte 87h reads the die revision.
DS1875
PON Triplexer and SFP Controller
Dual-range functionality consists of two modes of operation: fine mode and coarse mode. Each mode is calibrated for a unique transfer function, hence the term, dual
range. Table 6 highlights the registers related to MON3.
Fine mode is equivalent to the other MON channels. Fine
mode is calibrated using the gain, offset, and right-shifting registers at locations shown in Table 6 and is ideal
for relatively small analog input voltages. Coarse mode is
automatically switched to when the input exceeds the
threshold (to be discussed in a subsequent paragraph).
Coarse mode is calibrated using different gain and offset
registers, but lacks right-shifting (since coarse mode is
only used on large input signals). The gain and offset
registers for coarse mode are also shown in Table 6.
With the use of right-shifting, the fine mode full scale is
programmed to (1/2N)th the coarse mode full scale. The
DS1875 will now autorange to choose the range that
gives the best resolution for the measurement. To eliminate chatter, 6.25% of hysteresis is applied when the
input resides at the boundary of the two ranges. See
Figure 10. Additional information for each of the registers
can be found in the Memory Map section.
Dual range operation is transparent to the end user. The
results of MON3 analog-to-digital conversions are still
stored/reported in the same memory locations (68–69h,
Lower Memory) regardless of whether the conversion
was performed in fine mode or coarse mode.
When the DS1875 is powered up, analog-to-digital conversions begin in a round-robin fashion. Every MON3
timeslice begins with a fine mode analog-to-digital conversion (using fine mode’s gain, offset, and right-shifting settings). See the flowchart in Figure 10. Then,
depending on whether the last MON3 timeslice resulted
in a coarse-mode conversion and also depending on
the value of the current fine conversion, decisions are
made whether to use the current fine-mode conversion
result or to make an additional conversion (within the
same MON3 timeslice), using coarse mode (using
coarse mode’s gain and offset settings, and no rightshifting) and reporting the coarse-mode result. The
flowchart also illustrates how hysteresis is implemented. The fine-mode conversion is compared to one of
MON3
TIMESLICE
PERFORM FINEMODE CONVERSION
DID PRIOR MON3
TIMESLICE RESULT IN A
COARSE CONVERSION?
(LAST RSSI = 1?)
Y
N
DID CURRENT FINEMODE CONVERSION
REACH MAX?
N
Y
WAS CURRENT FINEMODE CONVERSION
≥ 93.75% OF FS?
Y
PERFORM COARSEMODE CONVERSION
N
LAST RSSI = 0
LAST RSSI = 1
REPORT FINE
CONVERSION RESULT
REPORT COARSE
CONVERSION RESULT
END OF MON3
TIMESLICE
Figure 10. RSSI Flowchart
Table 6. MON3 Configuration Registers
REGISTER
24
FINE MODE
COARSE MODE
MON3 FINE SCALE
98h–99h, Table 02h
9Ch–9Dh, Table 02h
MON3 FINE OFFSET
A8h–A9h, Table 02h
ACh–ADh, Table 02h
RIGHT SHIFT0/1
8Eh–8Fh, Table 02h
—
CONFIG (RSSI_FC, RSSI_FF bits)
89h, Table 02h
MON3 VALUE
68h–69h, Lower Memory
______________________________________________________________________________________
PON Triplexer and SFP Controller
NO. OF RIGHTSHIFTS
FINE MODE
(MAX)
COARSE MODE
(MIN*)
0
FFF8h
F000h
1
7FFCh
7800h
2
3FFEh
3C00h
3
1FFFh
1E00h
4
0FFFh
0F00h
5
07FFh
0780h
6
03FFh
03C0h
7
01FFh
01E0h
*This is the minimum reported coarse-mode conversion.
two thresholds. The actual threshold values are a function of the number of right-shifts being used. Table 7
shows the threshold values for each possible number
of right-shifts.
The RSSI_FF and RSSI_FC (Table 02h, Register 89h)
bits are used to force fine-mode or coarse-mode conversions, or to disable the dual-range functionality.
Dual-range functionality is enabled by default (both
RSSI_FC and RSSI_FF are factory programmed to 0 in
EEPROM). It can be disabled by setting RSSI_FC to 0
and RSSI_FF to 1. These bits are also useful when calibrating MON3. For additional information, see the
Memory Map section.
PWM Controller
The DS1875 has a PWM controller that, when used with
external components, generates a low-noise, high-voltage output to bias APDs in optical receivers. The
achievable boost voltage is determined by the external
component selection. Figure 12 shows a typical
schematic. Selection of switching frequency, external
inductor, capacitors, resistor network, switching FET,
and switch diode determine the performance of the
DC-DC converter. The PWM controller can be configured in boost or buck mode. Both modes require an
external nMOS or npn transistor.
The DS1875 PWM controller consists of several sections used to create a PWM signal to drive a DC-DC
converter. Figure 11 is a block diagram of the DS1875
PWM controller. Following is a description of each
block in the PWM controller and some guidelines for
selecting components for the DC-DC converter.
The PWM DAC is used to set the desired output voltage
of the DC-DC converter section. The feedback from the
DC-DC converter is compared to the output from the
PWM DAC by an error amplifier. If the FB level is less
VOLTAGE CLAMP
HIGH = 2.1V
LOW = 0.8V
PWM EN
PWM DAC TEMPERATUREREFERENCED LUT
TABLE 07h
COMP
10μA
MUX
MANUAL I2C CONTROL
PWM DAC
TABLE 02h
REGISTER FEh
PWM DAC
8-BIT
0 TO 1.25V
M3QT
ERROR
AMPLIFIER
GATE DRIVER
90% MAX
DUTY CYCLE
SW
10μA
1.9V
DS1875
RAMP
1.0V
PWM CONTROLLER
PWM_FR[1:0]
90% DUTY
CYCLE OSC
FB
Figure 11. PWM Controller Diagram
______________________________________________________________________________________
25
DS1875
Table 7. MON3 Hysteresis Threshold Values
DS1875
PON Triplexer and SFP Controller
than the PWM DAC level, the error amplifier increases
the level on the COMP pin. The level on the COMP pin
is compared to the signal from the oscillator and ramp
generator to set the duty cycle that is input to the gate
driver and maximum duty-cycle limiting block. An
increase on the COMP pin increases the duty cycle.
Conversely, if FB is greater than the PWM DAC, the
level on COMP is decreased, decreasing the duty
cycle. The gate driver and maximum duty-cycle block
is used to limit the maximum duty cycle of the PWM
controller to 90%. This block also disables the PWM driver if an M3QT has resulted from the APD current
exceeding a desired limit.
The output from the PWM DAC is used to control the
output voltage of the DC-DC converter. The values for
the PWM DAC are recalled from the Table 07h, which is
a temperature-indexed LUT. The temperature-indexed
value from the LUT is written to the PWM DAC register
(Table 02h, Register FEh), which updates the setting of
the PWM DAC. The PWM DAC can also be operated in
a manual mode by disabling the automatic updating
from the LUT. This is done by clearing the PWM EN bit
(Table 02h, Register 80h, Bit 5). The PWM DAC fullscale output is 1.25V with 8 bits of resolution. When
designing the feedback for the DC-DC converter section, the user needs to make sure that the desired level
applied to the FB pin is in this range.
the comparator outputs a 100% duty-cycle signal to the
gate driver and duty-cycle limiting block. The dutycycle liming block is used to limit the duty cycle of the
PWM signal from the SW pin to 90%.
The PWM controller is designed to protect expensive
APDs against adverse operating conditions while providing optimal bias. The PWM controller monitors photodiode current to protect APDs under avalanche
conditions using the MON3 quick trip. A voltage level
that is proportional to the APD current can be input to
the MON3 pin. When this voltage exceeds the level set
by the M3QT DAC (Table 02h, Register C3h), pulses
from the PWM controller are blocked until the fault is
cleared. The quick trip can also toggle the digital output
D2. D2 can be connected to an external FET to quickly
discharge the DC-DC converter filter capacitors.
The COMP pin is driven by the error amplifier comparing the PWM DAC to the DC-DC converter feedback
signal at the FB pin. The error amplifier can sink and
source 10µA. An external resistor and capacitor connected to the COMP pin determine the rate of change
the COMP pin. The resistor provides an initial step
when the current from the error amplifier changes. The
capacitor determines how quickly the COMP pin
charges to the desired level. The COMP pin has internal voltage clamps that limit the voltage level to a minimum of 0.8V and a maximum of 2.1V.
Where:
VIN = DC-DC converter input voltage
VOUT = Output of DC-DC converter
IOUT(MAX) = Maximum output current delivered
The oscillator and ramp generator create a ramped signal. The frequency of this signal can be 131.25kHz,
262.5kHz, 525kHz, or 1050kHz and is set by the
PWM_FR[1:0] bits (Table 02h, Register 88h, Bits 5:4).
The low level and high level for the ramped signal are
approximately 1.0V and 1.9V, respectively.
The ramped signal is compared to the voltage level on
the COMP pin to determine the duty cycle that is input
to the gate driver and duty-cycle limiting block. When
COMP is clamped low at 0.8V, below the level of the
ramped signal, the comparator outputs a 0% dutycycle signal to the gate driver block. When COMP is
clamped at 2.1V, above the level of the ramped signal,
26
Inductor Selection
Optimum inductor selection depends on input voltage,
output voltage, maximum output current, switching frequency, and inductor size. Inductors are typically specified by their inductance (L), peak current (IPK), and
resistance (LR).
The inductance value is given by:
L=
VIN 2 × D 2 × T × η
2 IOUT(MAX) × VOUT
T = Time period of switching frequency (seconds)
D = Duty cycle
η = Estimated power conversion efficiency
The equation for inductance factors in conversion efficiency. For inductor calculation purposes, an η of 0.5
to 0.75 is usually suitable.
For example, to obtain an output of 80V with a load current of 1.0mA from an input voltage of 5.0V using the
maximum 90% duty cycle and frequency of 1050kHz
(T = 952ns), and assuming an efficiency of 0.5, the previous equation yields an L of 120µH, so a 100µH inductor would be a suitable value.
The peak inductor current is given by:
IPK =
VIN × D × T
L
______________________________________________________________________________________
PON Triplexer and SFP Controller
POLE1 (dominant pole) = 1/(2π × REA × CCOMP)
ZERO1 (compensation zero) = 1/(2π × RCOMP × CCOMP)
POLE2 (output load pole) =
2 × VOUT − VIN
1
×
VOUT − VIN
2π × R LOAD × ( C2 + C3 )
POLE3 (output filter pole) = 1/(2π × R1 × C3)
The DC open-loop gain is given by:
AOL = GM × R EA ×
⎛V
− VIN R LOAD × T ⎞
2 × VIN
VFB
×
× ⎜ OUT
×
⎟
0. 85 2 × VOUT − VIN
2×L
VOUT
⎝
⎠
Where:
REA = 260MΩ
GM = 425µS
RLOAD = Parallel combination of feedback network and
load resistance
VOUT = Output of DC-DC converter
VIN = DC-DC converter input voltage
VFB = Feedback voltage at the FB pin
T = Time period of switching frequency (seconds)
L = Inductor value (henries)
DAC1 Output
The DAC1 output has a full-scale 2.5V range with 8 bits
of resolution, and is programmed through the I2C interface. The DAC1 setting is nonvolatile and password-2
(PW2) protected.
M4DAC Output
The M4DAC output has a full-scale 2.5V range with 8
bits of resolution, and is controlled by an LUT indexed
by the MON4 voltage. The M4DAC LUT (Table 06h) is
nonvolatile and PW2 protected. See the Memory
Organization section for details. The recalled value is
either 16-bit or 32-bit depending on bits DBL_SB and
UP_LOWB in Table 02h, Register C7h.
Digital I/O Pins
Five digital I/O pins are provided for additional monitoring and control. By default the LOSI pin is used to convert a standard comparator output for loss of signal
(LOSI) to an open-collector output. This means the mux
shown on the block diagram by default selects the LOSI
pin as the source for the D0 output transistor. The level
of the D0 pin can be read in the STATUS byte (Lower
Memory, Register 6Eh) as the LOS STATUS bit. The
LOS STATUS bit reports back the logic level of the D0
pin, so an external pullup resistor must be provided for
this pin to output a high level. The LOSI signal can be
inverted before driving the open-drain output transistor
using the XOR gate provided. The MUX LOS allows the
D0 pin to be used identically to the D1, D2, and D3
pins. However, the mux setting (stored in the EEPROM)
does not take effect until VCC > VPOA, allowing the EEPROM to recall. This requires the LOSI pin to be grounded for D0 to act identical to the D1, D2, and D3 pins.
Digital pins D1, D2, and D3 can be used as inputs or
outputs. External pullup resistors must be provided to
realize high-logic levels. The DIN byte indicates the
logic levels of these input pins (Lower Memory, Register
79h), and the open-drain outputs can be controlled
using the DOUT byte (Lower Memory, Register 78h).
When VCC < VPOA, these outputs are high impedance.
Once V CC ≥ V POA , the outputs go to the power-on
default state stored in the DPU byte (Table 02h, Register
C0h). The EEPROM-determined default state of the pin
can be modified with PW2 access. After the default
state has been recalled, the SRAM registers controlling
outputs can be modified without password access. This
allows the outputs to be used to control serial interfaces
without wearing out the default EEPROM setting.
D2 can be configured as the output of a quick-trip monitor for MON3. The main application is to quickly shut
down the PWM converter and discharge the voltage
created by the converter. This is shown in the typical
application circuit.
______________________________________________________________________________________
27
DS1875
Stability and Compensation Component Selection
The components connected to the COMP pin (RCOMP
and CCOMP) introduce a pole and zero that are necessary for stable operation of the PWM controller
(Figure 12).
The dominant pole, POLE1, is formed by the output
impedance of the error amplifier (REA) and CCOMP. The
zero formed by the components on COMP, ZERO1, is
selected to cancel POLE2 formed by the output filter
cap C3 and output load RLOAD. The additional pole,
POLE3, formed by R1 and C3 should be at least a
decade past the crossover frequency to not affect stability. The following formulas can be used to calculate
the poles and zero for the application shown in
Figure 12.
DS1875
PON Triplexer and SFP Controller
VIN
D1
L1
C1
R1
C2
VOUT
C3
R2
SW
R4
3.3V
Q1
R3
MAX4007
FB
RCOMP CCOMP
RMON
COMP
C4
DS1875
D2
APD OVERLOAD QUICK TRIP
ROSA
APD
TIA
MON3
Figure 12. PWM Controller Typical APD Bias Circuit
CURRENT SINK
VOLTAGE OUTPUT
SW
SW
DS1875
FB
COMP
Figure 13. PWM Controller Voltage Output Configuration
28
DS1875
FB
COMP
Figure 14. PWM Controller Current-Sink Output Configuration
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
SDA
tBUF
tF
tHD:STA
tLOW
tSP
SCL
tHIGH
tHD:STA
tHD:DAT
STOP
tSU:STA
tR
tSU:STO
tSU:DAT
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 15. I2C Timing Diagram
I2C Communication
I2C Definitions
The following terminology is commonly used to
describe I2C data transfers.
Master Device: The master device controls the
slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive
data at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inactive and in their logic-high states.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 15 for applicable timing.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition. See
Figure 15 for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one.
Repeated START conditions are commonly used
during read operations to identify a specific memory
address to begin a data transfer. A repeated START
condition is issued identically to a normal START
condition. See Figure 15 for applicable timing.
Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL
plus the setup and hold-time requirements (Figure
15). Data is shifted into the device during the rising
edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time before the next rising edge of SCL during a bit read (Figure 15). The device shifts out each
bit of data on SDA at the falling edge of the previous
SCL pulse and the data bit is valid at the rising edge
of the current SCL pulse. Remember that the master
generates all SCL clock pulses including when it is
reading bits from the slave.
Acknowledgement (ACK and NACK): An acknowledge-ment (ACK) or not acknowledge (NACK) is
always the 9th bit transmitted during a byte transfer.
The device receiving data (the master during a read
or the slave during a write operation) performs an
ACK by transmitting a zero during the 9th bit. A
device performs a NACK by transmitting a one during the 9th bit. Timing for the ACK and NACK is
identical to all other bit writes (Figure 15). An ACK is
the acknowledgment that the device is properly
receiving data. A NACK is used to terminate a read
sequence or as an indication that the device is not
receiving data.
______________________________________________________________________________________
29
PON Triplexer and SFP Controller
DS1875
Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave
(most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit
write definition and the acknowledgement is read
using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit read definition, and the master
transmits an ACK using the bit write definition to
receive additional data bytes. The master must
NACK the last byte read to terminate communication
so the slave returns control of SDA to the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave addressing byte sent immediately following a START condition. The slave address
byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit.
The DS1875 responds to two slave addresses. The
auxiliary memory always responds to a fixed I2C
slave address, A0h. The Lower Memory and tables
00h–08h respond to I2C slave addresses that can
be configured to any value between 00h–FEh using
the Device Address byte (Table 02h, Register 8Ch).
The user also must set the ASEL bit (Table 02h,
Register 89h) for this address to be active. By writing the correct slave address with R/W = 0, the master indicates it will write data to the slave. If R/W = 1,
the master reads data from the slave. If an incorrect
slave address is written, the DS1875 assumes the
master is communicating with another I2C device
and ignores the communications until the next
START condition is sent. If the main device’s slave
address is programmed to be A0h, access to the
auxiliary memory is disabled.
Memory Address: During an I2C write operation to
the DS1875, the master must transmit a memory
address to identify the memory location where the
slave is to store the data. The memory address is
always the second byte transmitted during a write
operation following the slave address byte.
I2C Protocol
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write the
byte of data, and generate a STOP condition. The
30
master must read the slave’s acknowledgement during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START condition, writes the slave address byte (R/W = 0),
writes the memory address, writes up to 8 data
bytes, and generates a STOP condition. The DS1875
writes 1 to 8 bytes (one page or row) with a single
write transaction. This is internally controlled by an
address counter that allows data to be written to
consecutive addresses without transmitting a memory address before each data byte is sent. The
address counter limits the write to one 8-byte page
(one row of the memory map). Attempts to write to
additional pages of memory without sending a STOP
condition between pages result in the address
counter wrapping around to the beginning of the
present row.
Example: A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that addresses 06h and 07h contain 11h and 22h, respectively,
and the third data byte, 33h, is written to address
00h.
To prevent address wrapping from occurring, the
master must send a STOP condition at the end of
the page, then wait for the bus-free or EEPROM
write time to elapse. Then the master can generate a
new START condition and write the slave address
byte (R/W = 0) and the first memory address of the
next memory row before continuing to write data.
Acknowledge Polling: Any time a EEPROM location
is written, the DS1875 requires the EEPROM write
time (tW) after the STOP condition to write the contents of the page to EEPROM. During the EEPROM
write time, the device does not acknowledge its
slave address because it is busy. It is possible to
take advantage of that phenomenon by repeatedly
addressing the DS1875, which allows the next page
to be written as soon as the DS1875 is ready to
receive the data. The alternative to acknowledge
polling is to wait for a maximum period of t W to
elapse before attempting to write again to the
DS1875.
EEPROM Write Cycles: When EEPROM writes
occur to the memory, the DS1875 writes the whole
EEPROM memory page, even if only a single byte
on the page was modified. Writes that do not modify
all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same
page. Because the whole page is written, bytes that
______________________________________________________________________________________
PON Triplexer and SFP Controller
Memory Map
Memory Organization
The DS1875 features 10 separate memory tables that
are internally organized into 8-byte rows.
The Lower Memory is addressed from 00h to 7Fh and
contains alarm and warning thresholds, flags, masks,
several control registers, password entry area (PWE),
and the table select byte.
Table 00h contains conversion results for MON5
through MON8.
Table 01h primarily contains user EEPROM (with PW1
level access) as well as some alarm and warning status
bytes.
Table 02h is a multifunction space that contains configuration registers, scaling and offset values, passwords,
interrupt registers, as well as other miscellaneous control bytes.
Table 03h is strictly user EEPROM that is protected by
a PW2-level password.
Table 04h contains a temperature-indexed LUT for
control of the modulation voltage. The modulation LUT
can be programmed in 2°C increments over the -40°C
to +102°C range. Access to this register is protected
by a PW2-level password.
Table 05h contains a temperature-indexed LUT that
allows the APC set point to change as a function of
temperature to compensate for Tracking Error (TE). The
APC LUT has 36 entries that determine the APC setting
in 4°C windows between -40°C to 100°C. Access to this
register is protected by a PW2-level password.
Table 06h contains a MON4-indexed LUT for control of
the M4DAC voltage. The MON4 LUT has 32 entries that
are configurable to act as one 32-entry LUT of two 16byte LUTs. When configured as one 32-byte LUT, each
entry corresponds to an increment of 1/32 the full scale.
When configured as two 16-byte LUTs, the first 16
bytes and the last 16 bytes each correspond to 1/16 full
scale. Either of the two sections is selected with a separate configuration bit. Access to this register is protected by a PW2-level password.
Table 07h contains a temperature-indexed LUT for
control of the PWM reference voltage (integration of FB
input). The PWM LUT has 36 entries that determine the
APC setting in 4°C windows between -40°C to +100°C.
Access to this register is protected by a PW2-level
password.
Table 08h contains a temperature-indexed LUT for
control of the BIAS current. The BIAS LUT can be programmed in 2°C increments over the 40°C to +102°C
range. Access to this register is protected by a PW2level password.
Auxiliary Memory (Device A0h) contains 256 bytes of
EE memory accessible from address 00h–FFh. It is
selected with the device address of A0h.
See the Register Descriptions section for a more complete detail of each byte’s function, as well as for
read/write permissions for each byte.
______________________________________________________________________________________
31
DS1875
were not modified during the transaction are still
subject to a write cycle. This can result in a whole
page being worn out over time by writing a single
byte repeatedly. Writing a page one byte at a time
wears the EEPROM out eight times faster than writing the entire page at once. The DS1875’s EEPROM
write cycles are specified in the Nonvolatile Memory
Characteristics table. The specification shown is at
the worst-case temperature. It can handle approximately 10 times that many writes at room temperature. Writing to SRAM-shadowed EEPROM memory
with SEEB = 1 does not count as a EEPROM write
cycle when evaluating the EEPROM’s estimated lifetime.
Reading a Single Byte from a Slave: Unlike the
write operation that uses the memory address byte
to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the
slave, the master generates a START condition,
writes the slave address byte with R/W = 1, reads
the data byte with a NACK to indicate the end of the
transfer, and generates a STOP condition.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
pointer to a particular value. To do this, the master
generates a START condition, writes the slave
address byte (R/W = 0), writes the memory address
where it desires to read, generates a repeated
START condition, writes the slave address byte (R/W
= 1), reads data with ACK or NACK as applicable,
and generates a STOP condition.
DS1875
PON Triplexer and SFP Controller
DEC HEX
0
0h
I2C SLAVE ADDRESS A0h
(FIXED)
I2C SLAVE ADDRESS A2h
(DEFAULT)
00h
00h
LOWER MEMORY
AUXILIARY MEMORY
DIGITAL DIAGNOSTIC
FUNCTIONS
2Fh
30h
PW2 LEVEL ACCESS
EEPROM
(48 BYTES)
5Fh
60h
DIGITAL DIAGNOSTIC
FUNCTIONS
7Ah
PASSWORD ENTRY (PWE)
(7Bh–Eh)
TABLE SELECT BYTE
7Fh
EEPROM
DEC HEX
128 80h 80h
MON5–MON8 CONV
80h
80h
80h
80h
80h
80h
80h
80h
88h
89h
TABLE 01h
TABLE 02h
TABLE 03h
TABLE 04h
TABLE 05h
TABLE 06h
TABLE 07h
TABLE 08h
PW1 LEVEL ACCESS
EEPROM
(120 BYTES)
CONFIGURATION AND
CONTROL
PW2 LEVEL ACCESS
EEPROM
(128 BYTES)
MODULATION
LUT
APC TE LUT
M4DAC LUT
PWM REF LUT
BIAS
OPEN-LOOP
LUT
9Fh
A3h
A3h
TABLE 00h
D7h
NO MEMORY
C7h
D8h
C7h
NO MEMORY
F8h
255
FFh
FFh
255
FFh
FFh
ATB
F7h
F7h
FFh
F8h MISC. CONTROL
FFh
BITS
FFh
Figure 16. Memory Map
Shadowed EEPROM
Many NV memory locations (listed within the Register
Descriptions section) are actually shadowed EEPROM
that are controlled by the SEEB bit in Table 02h, Byte
80h.
The DS1875 incorporates shadowed-EEPROM memory
locations for key memory addresses that can be written
many times. By default the shadowed-EEPROM bit,
SEEB, is not set and these locations act as ordinary
EEPROM. By setting SEEB, these locations function like
SRAM cells, which allow an infinite number of write
32
cycles without concern of wearing out the EEPROM.
This also eliminates the requirement for the EEPROM
write time, tWR. Because changes made with SEEB disabled do not affect the EEPROM, these changes are
not retained through power cycles. The power-on value
is the last value written with SEEB enabled. This function can be used to limit the number of EEPROM writes
during calibration or to change the monitor thresholds
periodically during normal operation helping to reduce
the number of times EEPROM is written. The Memory
Map description indicates which locations are shadowed EEPROM.
______________________________________________________________________________________
PON Triplexer and SFP Controller
Lower Memory Register Map
This register map shows each byte/word (2 bytes) in terms of the row it is on in the memory. The first byte in the row is
located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte on the row is
one/two memory locations beyond the previous byte/word’s address. A total of 8 bytes are present on each row. For
more information about each of these bytes, see the corresponding register description.
LOWER MEMORY
WORD 0
WORD 1
WORD 2
WORD 3
ROW
(HEX)
ROW NAME
00
<1>THRESHOLD0
TEMP ALARM HI
TEMP ALARM LO
TEMP WARN HI
TEMP WARN LO
08
<1>THRESHOLD1
VCC ALARM HI
VCC ALARM LO
VCC WARN HI
VCC WARN LO
10
<1>THRESHOLD2
MON1 ALARM HI
MON1 ALARM LO
MON1 WARN HI
MON1 WARN LO
18
<1>THRESHOLD3
MON2 ALARM HI
MON2 ALARM LO
MON2 WARN HI
MON2 WARN LO
20
<1>THRESHOLD4
MON3 ALARM HI
MON3 ALARM LO
MON3 WARN HI
MON3 WARN LO
28
<1>THRESHOLD5
MON4 ALARM HI
MON4 ALARM LO
MON4 WARN HI
MON4 WARN LO
30
<1>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
38
<1>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
40
<1>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
48
<1>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
50
<1>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
58
<1>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
60
68
70
78
ACCESS
CODE
Read
Access
Write
Access
BYTE 0/8
<2>ADC
<2>ALARM/
WARN
<0>TABLE
SELECT
<0>
See each
bit/byte
separately
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
TEMP VALUE
VCC VALUE
MON1 VALUE
<2>MON3 VALUE
<2>MON4 VALUE
<2>RESERVED
VALUES0
<0>ADC
VALUES1
BYTE 1/9
ALARM3
ALARM2
<5>DOUT
<2>DIN
ALARM1
ALARM0
<6>
WARN3
<6>PWE MSB
RESERVED
WARN2
BYTE 6/E
BYTE 7/F
MON2 VALUE
<0>STATUS
<3>UPDATE
RESERVED RESERVED
<5>TBL
<6>PWE LSB
SEL
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1875
hardware
PW2 +
mode
bit
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
33
DS1875
Register Descriptions
DS1875
PON Triplexer and SFP Controller
Table 00h Register Map
TABLE 00h
ROW
(HEX)
ROW
NAME
80
<2>ADC VALUES2
88–FF
EMPTY
ACCESS
CODE
Read
Access
Write
Access
34
<0>
See each
bit/byte
separately
WORD 0
BYTE 0/8
WORD 1
BYTE 1/9
BYTE 2/A
MON5 VALUE
EMPTY
BYTE 3/B
WORD 2
BYTE 4/C
MON6 VALUE
EMPTY
EMPTY
WORD 3
BYTE 5/D
BYTE 6/E
MON7 VALUE
EMPTY
EMPTY
EMPTY
BYTE 7/F
MON8 VALUE
EMPTY
EMPTY
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1875
hardware
PW2 +
mode
bit
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
PON Triplexer and SFP Controller
TABLE 01h (PW1)
WORD 0
WORD 1
WORD 2
WORD 3
ROW
(HEX)
ROW
NAME
BYTE 0/8
BYTE 1/9
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
BYTE 6/E
BYTE 7/F
80
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
88
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
90
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
98
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
A0
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
A8
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
B0
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
B8
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
C0
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
C8
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
D0
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
D8
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
E0
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
E8
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
F0
<7>PW1 EE
EE
EE
EE
EE
EE
EE
EE
EE
ALARM3
ALARM2
ALARM1
ALARM0
WARN3
WARN2
RESERVED
RESERVED
F8
<11>ALARM
ACCESS
CODE
Read
Access
Write
Access
TRAP
<0>
See each
bit/byte
separately
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1875
hardware
PW2 +
mode
bit
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
35
DS1875
Table 01h Register Map
DS1875
PON Triplexer and SFP Controller
Table 02h Register Map
TABLE 02h (PW2)
ROW
(HEX)
ROW
NAME
WORD 0
BYTE 0/8
WORD 1
BYTE 1/9
BYTE 2/A
WORD 2
BYTE 3/B
BYTE 4/C
BYTE 7/F
<10>DEVICE <10>DEVICE
<0>CONFIG0
<8>MODE
88
<8>CONFIG1
SAMPLE
RATE
90
<8>SCALE0
RESERVED
VCC SCALE
MON1 SCALE
MON2 SCALE
98
<8>SCALE1
MON3 FINE SCALE
MON4 SCALE
MON3 COARSE SCALE
RESERVED
A0
<8>OFFSET0
RESERVED
VCC OFFSET
MON1 OFFSET
MON2 OFFSET
MON4 OFFSET
MON3 COARSE OFFSET
INTERNAL TEMP
OFFSET*
PW1 LSW
PW2 MSW
PW2 LSW
<8>OFFSET1
B0
<9>PWD VALUE
PW1 MSW
B8
<8>INTERRUPT
C0
<8>CNTL OUT
DPU
C8
D0
<8>SCALE2
<8>OFFSET1
D8–F7
EMPTY
<0>MAN BIAS
RESERVED
MON3 FINE OFFSET
FETG
ENABLE1
F8
CONFIG
MOD
RANGING
DEVICE
ADDRESS
<4>M4DAC
WORD 3
BYTE 6/E
80
A8
<4>TINDEX <4>MOD DAC <4>APC DAC <4>VINDEX
BYTE 5/D
COMP
RANGING
ID
VER
RSHIFT1
RSHIFT0
FETG
ENABLE0
TX-F
ENABLE1
TX-F
ENABLE0
HTXP
LTXP
HBIAS
MAX BIAS
RESERVED
RESERVED
M3QT DAC
DAC1
RESERVED
RESERVED
M4 LUT
CNTL
MON5 SCALE
MON6 SCALE
MON5 OFFSET
MON7 SCALE
MON6 OFFSET
MON8 SCALE
MON7 OFFSET
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
<4>MAN
<4>MAN
<4>MAN_
<10>BIAS
<10>BIAS
BIAS1
BIAS0
CNTL
DAC1
DAC0
MON8 OFFSET
EMPTY
EMPTY
EMPTY
BIAS OL
PWM DAC
RESERVED
*The final result must be XORed with BB40h before writing to this register.
ACCESS
CODE
Read
Access
Write
Access
36
<0>
See each
bit/byte
separately
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1875
hardware
PW2 +
mode
bit
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
PON Triplexer and SFP Controller
TABLE 03h (PW2)
WORD 0
WORD 1
WORD 2
WORD 3
ROW
(HEX)
ROW
NAME
BYTE 0/8
BYTE 1/9
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
BYTE 6/E
BYTE 7/F
80
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
88
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
90
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
98
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
A0
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
A8
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
B0
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
B8
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
C0
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
C8
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
D0
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
D8
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
E0
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
E8
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
F0
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
F8
<8>PW2 EE
EE
EE
EE
EE
EE
EE
EE
EE
ACCESS
CODE
Read
Access
Write
Access
<0>
See each
bit/byte
separately
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1875
hardware
PW2 +
mode
bit
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
37
DS1875
Table 03h Register Map
DS1875
PON Triplexer and SFP Controller
Table 04h Register Map
TABLE 04h (MODULATION LUT)
WORD 0
WORD 1
WORD 2
WORD 3
ROW
(HEX)
ROW
NAME
BYTE 0/8
BYTE 1/9
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
BYTE 6/E
BYTE 7/F
80
<8>LUT4
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
88
<8>LUT4
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
90
<8>LUT4
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
98
<8>LUT4
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
A0
<8>LUT4
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
A8
<8>LUT4
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
B0
<8>LUT4
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
B8
<8>LUT4
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
C0
<8>LUT4
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
ACCESS
CODE
Read
Access
Write
Access
<0>
See each
bit/byte
separately
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1875
hardware
PW2 +
mode
bit
All
All
PW1
PW2
PW2
N/A
PW1
Table 05h Register Map
TABLE 05h (APC TE LUT)
WORD 0
WORD 1
WORD 2
WORD 3
ROW
(HEX)
ROW
NAME
BYTE 0/8
BYTE 1/9
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
BYTE 6/E
BYTE 7/F
80
<8>LUT5
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
88
<8>LUT5
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
90
<8>LUT5
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
98
<8>LUT5
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
APC REF
A0
<8>LUT5
APC REF
APC REF
APC REF
APC REF
RESERVED
RESERVED
RESERVED
RESERVED
ACCESS
CODE
Read
Access
Write
Access
38
<0>
See each
bit/byte
separately
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1875
hardware
PW2 +
mode
bit
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
PON Triplexer and SFP Controller
TABLE 06h (M4DAC LUT)
WORD 0
WORD 1
WORD 2
WORD 3
ROW
(HEX)
ROW
NAME
BYTE 0/8
BYTE 1/9
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
BYTE 6/E
BYTE 7/F
80
<8>LUT6
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
88
<8>LUT6
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
90
<8>LUT6
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
98
<8>LUT6
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
M4DAC
ACCESS
CODE
Read
Access
Write
Access
<0>
See each
bit/byte
separately
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1875
hardware
PW2 +
mode
bit
All
All
PW1
PW2
PW2
N/A
PW1
Table 07h Register Map
TABLE 07h (PWM REFERENCE LUT)
WORD 0
WORD 1
WORD 2
WORD 3
ROW
(HEX)
ROW
NAME
BYTE 0/8
BYTE 1/9
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
BYTE 6/E
BYTE 7/F
80
<8>LUT7
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
88
<8>LUT7
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
90
<8>LUT7
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
98
<8>LUT7
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
PWM REF
A0
<8>LUT7
PWM REF
PWM REF
PWM REF
PWM REF
RESERVED
RESERVED
RESERVED
RESERVED
ACCESS
CODE
Read
Access
Write
Access
<0>
See each
bit/byte
separately
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1875
hardware
PW2 +
mode
bit
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
39
DS1875
Table 06h Register Map
DS1875
PON Triplexer and SFP Controller
Table 08h Register Map
TABLE 08h (BIAS OPEN-LOOP LUT)
WORD 0
WORD 1
WORD 2
WORD 3
ROW
(HEX)
ROW
NAME
BYTE 0/8
BYTE 1/9
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
BYTE 6/E
BYTE 7/F
80
<8>LUT8
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
88
<8>LUT8
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
90
<8>LUT8
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
98
<8>LUT8
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
A0
<8>LUT8
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
A8
<8>LUT8
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
B0
<8>LUT8
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
B8
<8>LUT8
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
C0
<8>LUT8
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
BIAS_OL
ACCESS
CODE
Read
Access
Write
Access
40
<0>
See each
bit/byte
separately
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1875
hardware
PW2 +
mode
bit
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
PON Triplexer and SFP Controller
AUXILIARY MEMORY (A0h)
WORD 0
ROW
(HEX)
ROW
NAME
00
08
10
18
20
28
30
38
40
48
50
58
60
68
70
78
80
88
90
98
A0
A8
B0
B8
C0
C8
D0
D8
E0
E8
F0
F8
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
<5>AUX EE
ACCESS
CODE
Read
Access
Write
Access
<0>
See each
bit/byte
separately
WORD 1
WORD 2
WORD 3
BYTE 0/8
BYTE 1/9
BYTE 2/A
BYTE 3/B
BYTE 4/C
BYTE 5/D
BYTE 6/E
BYTE 7/F
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
All
All
All
PW2
All
N/A
PW1
PW2
N/A
PW2
All
PW2
N/A
All and
DS1875
hardware
PW2 +
mode
bit
All
All
PW1
PW2
PW2
N/A
PW1
______________________________________________________________________________________
41
DS1875
Auxiliary A0h Memory Register Map
DS1875
PON Triplexer and SFP Controller
Lower Memory Register Descriptions
Lower Memory, Register 00h to 01h: TEMP ALARM HI
Lower Memory, Register 04h to 05h: TEMP WARN HI
FACTORY DEFAULT
7FFFh
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
00h, 04h
S
26
25
24
23
22
21
20
01h, 05h
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
BIT 7
BIT 0
Temperature measurement updates above this two’s complement threshold set its corresponding alarm or
warning bit. Temperature measurement updates equal to or below this threshold clear its alarm or warning bit.
Lower Memory, Register 02h to 03h: TEMP ALARM LO
Lower Memory, Register 06h to 07h: TEMP WARN LO
FACTORY DEFAULT
8000h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
02h, 06h
S
26
25
24
23
22
21
20
03h, 07h
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
BIT 7
BIT 0
Temperature measurement updates below this two’s complement threshold set its corresponding alarm or
warning bit. Temperature measurement updates equal to or above this threshold clear its alarm or warning bit.
42
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Lower Memory, Register 08h to 09h: VCC ALARM HI
Lower Memory, Register 0Ch to 0Dh: VCC WARN HI
Lower Memory, Register 10h to 11h: MON1 ALARM HI
Lower Memory, Register 14h to 15h: MON1 WARN HI
Lower Memory, Register 18h to 19h: MON2 ALARM HI
Lower Memory, Register 1Ch to 1Dh: MON2 WARN HI
Lower Memory, Register 20h to 21h: MON3 ALARM HI
Lower Memory, Register 24h to 25h: MON3 WARN HI
Lower Memory, Register 28h to 29h: MON4 ALARM HI
Lower Memory, Register 2Ch to 2Dh: MON4 WARN HI
08h, 0Ch,
10h, 14h, 18h,
1Ch, 20h,
24h, 28h, 2Ch
09h, 0Dh,
11h, 15h, 19h,
1Dh, 21h,
25h, 29h, 2Dh
FACTORY DEFAULT
FFFFh
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
BIT 7
BIT 0
Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit.
Voltage measurements equal to or below this threshold clear its alarm or warning bit.
______________________________________________________________________________________
43
DS1875
PON Triplexer and SFP Controller
Lower Memory, Register 0Ah to 0Bh: VCC ALARM LO
Lower Memory, Register 0Eh to 0Fh: VCC WARN LO
Lower Memory, Register 12h to 13h: MON1 ALARM LO
Lower Memory, Register 16h to 17h: MON1 WARN LO
Lower Memory, Register 1Ah to 1Bh: MON2 ALARM LO
Lower Memory, Register 1Eh to 1Fh: MON2 WARN LO
Lower Memory, Register 22h to 23h: MON3 ALARM LO
Lower Memory, Register 26h to 27h: MON3 WARN LO
Lower Memory, Register 2Ah to 2Bh: MON4 ALARM LO
Lower Memory, Register 2Eh to 2Fh: MON4 WARN LO
0Ah, 0Eh,
12h, 16h,
1Ah, 1Eh,
22h, 26h,
2Ah, 2Eh
0Bh, 0Fh,
13h, 17h,
1Bh, 1Fh,
23h, 27h,
2Bh, 2Fh
FACTORY DEFAULT
0000h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
BIT 7
BIT 0
Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit.
Voltage measurements equal to or above this threshold clear its alarm or warning bit.
44
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Lower Memory, Register 30h to 5Fh: PW2 EE
30h to 5Fh
FACTORY DEFAULT
00h
READ ACCESS
All
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (EE)
EE
EE
EE
EE
EE
EE
EE
BIT 7
EE
BIT 0
PW2 level access-controlled EEPROM.
Lower Memory, Register 60h to 61h: TEMP VALUE
FACTORY DEFAULT
0000h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
60h
S
26
25
24
23
22
21
20
61h
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
BIT 7
BIT 0
Signed two’s complement direct-to-temperature measurement.
______________________________________________________________________________________
45
DS1875
PON Triplexer and SFP Controller
Lower Memory, Register 62h to 63h: VCC VALUE
Lower Memory, Register 64h to 65h: MON1 VALUE
Lower Memory, Register 66h to 67h: MON2 VALUE
Lower Memory, Register 68h to 69h: MON3 VALUE
Lower Memory, Register 6Ah to 6Bh: MON4 VALUE
62h, 64h,
66h, 68h,
6Ah
63h, 65h,
67h, 69h,
6Bh
POWER-ON VALUE
0000h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
BIT 7
BIT 0
Left-justified unsigned voltage measurement.
Lower Memory, Register 6Ch to 6D: RESERVED
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
6Ch, 6Dh
0
0
0
0
0
0
0
BIT 7
These registers are reserved. The value when read is 00h.
46
______________________________________________________________________________________
0
BIT 0
PON Triplexer and SFP Controller
DS1875
Lower Memory, Register 6Eh: STATUS
Write
Access
6Eh
POWER-ON VALUE
X000 0XXXb
READ ACCESS
All
WRITE ACCESS
See below
MEMORY TYPE
Volatile
N/A
All
N/A
All
All
N/A
N/A
N/A
FETG
STATUS
SOFT
FETG
RESERVED
TX-F
RESET
SOFT
TX-D
TX-F
STATUS
LOS
STATUS
RDYB
BIT 7
BIT 0
BIT 7
FETG STATUS: Reflects the active state of FETG. The FETG DIR bit in Table 02h, Register 89h
defines the polarity of FETG.
0 = Normal operation. Bias and modulation outputs are enabled.
1 = The FETG output is active. Bias and modulation outputs are disabled.
BIT 6
SOFT FETG:
0 = (Default)
1 = Forces the bias and modulation outputs to their off state and assert the FETG output.
BIT 5
RESERVED (Default = 0)
BIT 4
TX-F RESET:
0 = (Default)
1 = Resets the latch for the TX-F output. This bit is self-clearing after resetting TX-F.
BIT 3
SOFT TX-D: This bit allows a software control that is identical to the TX-D pin. See the BIAS and
MOD Output as a Function of Transmit Disable (TX-D) section for further information. Its value is
wired-ORed with the logic value of the TX-D pin.
0 = Internal TX-D signal is equal to the external TX-D pin.
1 = Internal TX-D signal is high.
BIT 2
TX-F STATUS: Reflects the active state of the TX-F pin.
0 = TX-F pin is not active.
1 = TX-F pin is active.
BIT 1
LOS STATUS: Loss of Signal. Reflects the logic level of the LOSI input pin.
0 = LOSI is logic-low.
1 = LOSI is logic-high.
BIT 0
RDBY: Ready Bar.
0 = VCC is above POA.
1 = VCC is below POA and/or too low to communicate over the I2C bus.
______________________________________________________________________________________
47
DS1875
PON Triplexer and SFP Controller
Lower Memory, Register 6Fh: UPDATE
6Fh
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
All + DS1875 Hardware
MEMORY TYPE
Volatile
TEMP RDY
VCC RDY
MON1 RDY
MON2 RDY
MON3 RDY
MON4 RDY
MON5/7 RDY
BIT 7
MON6/8 RDY
BIT 0
Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is completed.
These bits can be cleared so that a completion of a new conversion is verified.
48
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Lower Memory, Register 70h: ALARM3
70h
POWER-ON VALUE
10h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
TEMP HI
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
BIT 7
MON2 HI
MON2 LO
BIT 0
BIT 7
TEMP HI: High alarm status for temperature measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
TEMP LO: Low alarm status for temperature measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
VCC HI: High alarm status for VCC measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
VCC LO: Low alarm status for VCC measurement. This bit is set when the VCC supply is below the POA
trip point value. It clears itself when a VCC measurement is completed and the value is above the low
threshold.
0 = Last measurement was equal to or above threshold setting.
1 = (Default) Last measurement was below threshold setting.
BIT 3
MON1 HI: High alarm status for MON1 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 2
MON1 LO: Low alarm status for MON1 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 1
MON2 HI: High alarm status for MON2 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 0
MON2 LO: Low alarm status for MON2 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
______________________________________________________________________________________
49
DS1875
PON Triplexer and SFP Controller
Lower Memory, Register 71h: ALARM2
71h
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
MON3 HI
MON3 LO
MON4 HI
MON4 LO
RESERVED
RESERVED
RESERVED
BIT 7
50
BIT 0
BIT 7
MON3 HI: High alarm status for MON3 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
MON3 LO: Low alarm status for MON3 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
MON4 HI: High alarm status for MON4 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
MON4 LO: Low alarm status for MON4 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BITS 3:0
RESERVED
RESERVED
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Lower Memory, Register 72h: ALARM1
72h
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
RESERVED
RESERVED
RESERVED
RESERVED
BIAS HI
RESERVED
TXP HI
BIT 7
TXP LO
BIT 0
BITS 7:4
RESERVED
BIT 3
BIAS HI: High alarm status bias; fast comparison.
0 = (Default) Last comparison was below threshold setting.
1 = Last comparison was above threshold setting.
BIT 2
RESERVED
BIT 1
TXP HI: High alarm status TXP; fast comparison.
0 = (Default) Last comparison was below threshold setting.
1 = Last comparison was above threshold setting.
BIT 0
TXP LO: Low alarm status TXP; fast comparison.
0 = (Default) Last comparison was above threshold setting.
1 = Last comparison was below threshold setting.
Lower Memory, Register 73h: ALARM0
73h
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
M3QT HI
RESERVED
RESERVED
RESERVED
BIAS MAX
RESERVED
BIT 7
BIT 7
BITS 6:4
BIT 3
BITS 2:0
RESERVED
RESERVED
BIT 0
M3QT HI: High alarm status for MON3; fast comparison.
0 = (Default) Last comparison was below threshold setting.
1 = Last comparison was above threshold setting.
RESERVED
BIAS MAX: Alarm status for maximum digital setting of BIAS.
0 = (Default) The value for BIAS is equal to or below the MAX BIAS register.
1 = Requested value for BIAS is greater than the MAX BIAS register.
RESERVED
______________________________________________________________________________________
51
DS1875
PON Triplexer and SFP Controller
Lower Memory, Register 74h: WARN3
74h
POWER-ON VALUE
10h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
TEMP HI
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
MON2 HI
BIT 7
52
MON2 LO
BIT 0
BIT 7
TEMP HI: High warning status for temperature measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
TEMP LO: Low warning status for temperature measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
VCC HI: High warning status for VCC measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
VCC LO: Low warning status for VCC measurement. This bit is set when the VCC supply is below the
POA trip point value. It clears itself when a VCC measurement is completed and the value is above the
low threshold.
0 = Last measurement was equal to or above threshold setting.
1 = (Default) Last measurement was below threshold setting.
BIT 3
MON1 HI: High warning status for MON1 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 2
MON1 LO: Low warning status for MON1 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 1
MON2 HI: High warning status for MON2 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 0
MON2 LO: Low warning status for MON2 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Lower Memory, Register 75h: WARN2
75h
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
MON3 HI
MON3 LO
MON4 HI
MON4 LO
RESERVED
RESERVED
BIT 7
RESERVED
RESERVED
BIT 0
BIT 7
MON3 HI: High warning status for MON3 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
MON3 LO: Low warning status for MON3 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
MON4 HI: High warning status for MON4 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
MON4 LO: Low warning status for MON4 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BITS 3:0
RESERVED
Lower Memory Register 76h to 77h: RESERVED MEMORY
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
These registers are reserved. The value when read is 00h.
______________________________________________________________________________________
53
DS1875
PON Triplexer and SFP Controller
Lower Memory, Register 78h: DOUT
78h
POWER-ON VALUE
Recalled from Table 02h, Register C0h
READ ACCESS
All
WRITE ACCESS
All
MEMORY TYPE
Volatile
M3QT
RESET
SOFT
M3QT
RESERVED
RESERVED
D3 OUT
D2 OUT
D1 OUT
D0 OUT
BIT 7
BIT 0
BIT 7
M3QT RESET: Resets the latch for M3QT. The PWM does not begin normal operation until the MON3
voltage is below M3QT, regardless of resetting the latch.
0 = (default)
1 = M3QT alarm is reset.
BIT 6
SOFT M3QT: Software control for setting the M3QT alarm. The PWM output pulse SW is disabled.
0 = (Default) Internal signal is controlled by trip point comparison.
1 = M3QT alarm is set to 1.
BITS 5:4
RESERVED
BIT 3
D3 OUT: Controls the output of the open-drain pin D3.
0 = Output is held low.
1 = Output is high impedance.
BIT 2
D2 OUT: Controls the output of the open-drain pin D2.
0 = Output is held low.
1 = Output is high impedance.
BIT 1
D1 OUT: Controls the output of the open-drain pin D1.
0 = Output is held low.
1 = Output is high impedance.
BIT 0
D0 OUT: Controls the output of the open-drain pin D0.
0 = Output is held low.
1 = Output is high impedance.
At power-on, these bits are defined by the value stored in the DPU byte (Table 02h, Register C0h). These bits define
the value of the logic states of their corresponding output pins.
54
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Lower Memory, Register 79h: DIN
79h
POWER-ON VALUE
See description
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
INV M3QT
MUX M3QT
INV LOS
MUX LOS
D3 IN
D2 IN
D1 IN
BIT 7
D0 IN
BIT 0
BIT 7
INV M3QT: Status of inversion of M3QT (internal signal) to D2 pin. MUX M3QT bit must be set to 1 or
this bit does not affect the output. The value is controlled (or set) by the DPU byte.
1 = M3QT buffered to D2 is inverted.
BIT 6
MUX M3QT: Determines control of D2 pin. The value is controlled (or set) by the DPU byte.
0 = Logic value of D2 is controlled by DOUT byte.
1 = Logic value of D2 is controlled by M3QT (internal signal) and INV M3QT bit.
BIT 5
INV LOS: Status of inversion of LOSI pin to D0 pin. MUX LOS bit must be set to 1 or this bit does not
effect the output. The value is controlled (or set) by the DPU byte.
1 = LOSI buffered D0 is inverted.
BIT 4
MUX LOS: Determines control of D0 pin. The value is controlled (or set) by the DPU byte.
0 = Logic value of D0 is controlled by DOUT byte.
1 = Logic value of D0 is controlled by LOSI pin and INV LOS bit.
BIT 3
D3 IN: Reflects the logic value of D3 pin.
BIT 2
D2 IN: Reflects the logic value of D2 pin.
BIT 1
D1 IN: Reflects the logic value of D1 pin.
BIT 0
D0 IN: Reflects the logic value of D0 pin.
Lower Memory, Register 7Ah: RESERVED
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
N/A
This register is reserved. The value when read is 00h.
______________________________________________________________________________________
55
DS1875
PON Triplexer and SFP Controller
Lower Memory, Register 7Bh to 7Eh: Password Entry (PWE)
POWER-ON VALUE
FFFF FFFFh
READ ACCESS
N/A
WRITE ACCESS
All
MEMORY TYPE
Volatile
7Bh
231
230
229
228
227
226
225
224
7Ch
223
222
221
220
219
218
217
216
7Dh
215
214
213
212
211
210
29
28
7Eh
27
26
25
24
23
22
21
20
BIT 7
BIT 0
There are two passwords for the DS1875. Each password is 4 bytes long. The lower level password (PW1) has all the
access of a normal user plus those made available with PW1. The higher level password (PW2) has all the access of
PW1 plus those made available with PW2. The values of the passwords reside in EEPROM inside PW2 memory. At
power-up, all PWE bits are set to 1. All reads at this location are 0.
Lower Memory, Register 7Fh: Table Select (TBL SEL)
7Fh
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
All
MEMORY TYPE
Volatile
27
26
25
24
23
22
21
BIT 7
20
BIT 0
The upper memory tables (Table 00h to 08h) of the DS1875 are accessible by writing the desired table value in this
register.
56
______________________________________________________________________________________
PON Triplexer and SFP Controller
Table 00h, Register 80h to 81h: MON5 VALUE
Table 00h, Register 82h to 83h: MON6 VALUE
Table 00h, Register 84h to 85h: MON7 VALUE
Table 00h, Register 86h to 87h: MON8 VALUE
80h, 82h,
84h, 86h
81h, 83h,
85h, 87h
POWER-ON VALUE
0000h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
BIT 7
BIT 0
Left-justified unsigned voltage measurement.
Table 01h Register Descriptions
Table 01h, Register 80h to F7h: PW1 EEPROM
80h to F7h
POWER-ON VALUE
00h
READ ACCESS
PW1
WRITE ACCESS
PW1
MEMORY TYPE
Nonvolatile (EE)
EE
EE
BIT 7
EE
EE
EE
EE
EE
EE
BIT 0
EEPROM for PW1-level access.
______________________________________________________________________________________
57
DS1875
Table 00h Register Descriptions
DS1875
PON Triplexer and SFP Controller
Table 01h, Register F8h: ALARM3
POWER-ON VALUE
F8h
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
TEMP HI
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
MON2 HI
BIT 7
MON2 LO
BIT 0
Layout is identical to ALARM3 in Lower Memory, Register 70h with two exceptions.
1. VCC LO alarm is not set at power-on.
2. These bits are latched. They are cleared by power-down or a write with PW1 access.
Table 01h, Register F9h: ALARM2
F9h
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
MON3 HI
MON3 LO
MON4 HI
MON4 LO
RESERVED
RESERVED
RESERVED
BIT 7
Layout is identical to ALARM2 in Lower Memory, Register 71h with one exception.
1. These bits are latched. They are cleared by power-down or a write with PW1 access.
58
______________________________________________________________________________________
RESERVED
BIT 0
PON Triplexer and SFP Controller
DS1875
Table 01h, Register FAh: ALARM1
FAh
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
RESERVED
RESERVED
RESERVED
RESERVED
BIAS HI
RESERVED
TXP HI
BIT 7
TXP LO
BIT 0
Layout is identical to ALARM1 in Lower Memory, Register 72h with one exception.
1. These bits are latched. They are cleared by power-down or a write with PW1 access.
Table 01h, Register FBh: ALARM0
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
FBh
M3QT HI
RESERVED
RESERVED
RESERVED
BIAS MAX
RESERVED
RESERVED
BIT 7
RESERVED
BIT 0
Layout is identical to ALARM0 in Lower Memory, Register 73h with one exception.
1. These bits are latched. They are cleared by power-down or a write with PW1 access
Table 01h, Register FCh: WARN3
FCh
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
TEMP HI
TEMP LO
VCC HI
VCC LO
MON1 HI
MON1 LO
BIT 7
MON2 HI
MON2 LO
BIT 0
Layout is identical to WARN3 in Lower Memory, Register 74h with two exceptions.
1. VCC LO warning is not set at power-on.
2. These bits are latched. They are cleared by power-down or a write with PW1 access.
______________________________________________________________________________________
59
DS1875
PON Triplexer and SFP Controller
Table 01h, Register FDh: WARN2
FDh
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
MON3 HI
MON3 LO
MON4 HI
MON4 LO
RESERVED
RESERVED
RESERVED
BIT 7
BIT 0
Layout is identical to WARN2 in Lower Memory, Register 75h with one exception.
1. These bits are latched. They are cleared by power-down or a write with PW1 access.
Table 01h, Register FEh to FFh: RESERVED
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
PW1
MEMORY TYPE
Volatile
These registers are reserved.
60
RESERVED
______________________________________________________________________________________
PON Triplexer and SFP Controller
Table 02h, Register 80h: MODE
80h
POWER-ON VALUE
3Fh
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Volatile
SEEB
RESERVED
BIT 7
PWM EN
M4DAC EN
AEN
MOD EN
APC EN
BIAS EN
BIT 0
BIT 7
SEEB:
0 = (Default) Enables EEPROM writes to SEE bytes.
1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the
part is not delayed by the EE cycle time. Once the values are known, write this bit to a 0 and
write the SEE locations again for data to be written to the EEPROM.
BIT 6
RESERVED
BIT 5
PWM EN:
0 = PWM DAC is writable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the DAC value for the PWM DAC. The output is updated with
the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control of the LUT for PWM DAC.
BIT 4
M4DAC EN:
0 = M4DAC is writable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the DAC value for M4DAC. The output is updated with
the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control of the LUT for M4DAC.
BIT 3
AEN:
0 = The temperature-calculated index value TINDEX is writable by users and the updates of
calculated indexes are disabled. This allows users to interactively test their modules by
controlling the indexing for the LUTs. The recalled values from the LUTs appear in the DAC
registers after the next completion of a temperature conversion.
BIT 2
MOD EN:
0 = MOD DAC is writable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the DAC value for modulation. The output is updated with
the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control of the LUT for modulation.
BIT 1
APC EN:
0 = APC DAC is writable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the DAC value for APC reference. The output is updated
with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control of the LUT for APC reference.
BIT 0
BIAS EN:
0 = BIAS DAC is controlled by the user and the APC is in manual mode. The BIAS DAC value is
written to the MAN BIAS register. All values that are written to MAN BIAS and are greater than the
MAX BIAS register setting are not updated and set the BIAS MAX alarm bit. The BIAS DAC register
continues to reflect the value of the BIAS DAC. This allows users to interactively test their
modules by writing the DAC value for bias. The output is updated with the new value at the end of
the write cycle to the MAN BIAS register. The I2C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control for the APC feedback.
______________________________________________________________________________________
61
DS1875
Table 02h Register Descriptions
DS1875
PON Triplexer and SFP Controller
Table 02h, Register 81h: Temperature Index (TINDEX)
81h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and AEN = 0
MEMORY TYPE
Volatile
27
26
25
24
23
22
21
BIT 7
20
BIT 0
Holds the calculated index based on the temperature measurement. This index is used for the address during
lookup of Tables 04h, 05h, 07h, and 08h. Temperature measurements below -40°C or above +102°C are clamped
to 00h and C7h, respectively. The calculation of TINDEX is as follows:
TINDEX =
Temp _ Value + 40°C
+ 80h
2°C
For the temperature-indexed LUTs, the index used during the lookup function for each table is as follows:
Table 04h (MOD)
1
TINDEX6
TINDEX5
TINDEX4
TINDEX3
TINDEX2
TINDEX1
TINDEX0
Table 05h (APC)
1
0
TINDEX6
TINDEX5
TINDEX4
TINDEX3
TINDEX2
TINDEX1
Table 07h (PWM)
1
1
0
TINDEX6
TINDEX6
TINDEX5
TINDEX5
TINDEX4
TINDEX4
TINDEX3
TINDEX3
TINDEX2
TINDEX2
TINDEX1
TINDEX1
TINDEX0
Table 08h (BIAS)
Table 02h, Register 82h: MOD DAC
82h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and MOD EN = 0
MEMORY TYPE
Volatile
27
26
25
24
23
22
21
BIT 7
20
BIT 0
The digital value used for MOD and recalled from Table 04h at the adjusted memory address found in TINDEX.
This register is updated at the end of the temperature conversion.
VMOD =
62
Full Scale
MOD DAC
255
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Table 02h, Register 83h: APC DAC
83h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and APC EN = 0
MEMORY TYPE
Volatile
27
26
25
24
23
22
21
BIT 7
20
BIT 0
The digital value used for APC reference and recalled from Table 05h at the adjusted memory address found in
TINDEX. This register is updated at the end of the temperature conversion.
VBMD =
Full Scale
APC DAC
255
Table 02h, Register 84h: Voltage Index (VINDEX)
84h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and AEN = 0
MEMORY TYPE
Volatile
27
26
25
24
23
22
21
BIT 7
20
BIT 0
Holds the calculated index based on the MON4 voltage measurement. This index is used for the address during
lookup of Table 06h. M4DAC LUT is 32 bytes from address 80h to 9Fh. The calculation of VINDEX is as follows:
VINDEX =
MON4
+ 80h
800h
When configured as a single LUT, all 32 bytes are used for lookup.
When configured as a double LUT, the first 16 bytes (80h to 8Fh) form the lower LUT and the last 16 bytes (90h to
9Fh) form the upper LUT.
For the three different modes, the index used during the lookup function of Table 06h is as follows:
Single
Double/Lower
Double/Upper
1
1
1
0
0
0
0
0
0
VINDEX4
0
1
VINDEX3
VINDEX4
VINDEX4
VINDEX2
VINDEX3
VINDEX3
VINDEX1
VINDEX2
VINDEX2
VINDEX0
VINDEX1
VINDEX1
______________________________________________________________________________________
63
DS1875
PON Triplexer and SFP Controller
Table 02h, Register 85h: M4DAC
85h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and M4DAC EN = 0
MEMORY TYPE
Volatile
27
26
25
24
23
22
21
BIT 7
20
BIT 0
The digital value used for M4DAC and recalled from Table 06h at the adjusted memory address found in
VINDEX. This register is updated at the end of the MON4 conversion.
VM4DAC =
2.5
(M4DAC + 1)
256
Table 02h, Register 86h: DEVICE ID
86h
FACTORY DEFAULT
75h
READ ACCESS
PW2
WRITE ACCESS
N/A
MEMORY TYPE
ROM
0
1
1
1
0
1
0
BIT 7
1
BIT 0
Hardwired connections to show the device ID.
Table 02h, Register 87h: DEVICE VER
FACTORY DEFAULT
DEVICE VERSION
READ ACCESS
PW2
WRITE ACCESS
N/A
MEMORY TYPE
ROM
87h
DEVICE VERSION
BIT 7
Hardwired connections to show device version.
64
______________________________________________________________________________________
BIT 0
PON Triplexer and SFP Controller
DS1875
Table 02h, Register 88h: SAMPLE RATE
88h
FACTORY DEFAULT
30h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
SEE
SEE
PWM_FR1
PWM_FR0
APC_SR3
APC_SR2
APC_SR1
BIT 7
APC_SR0
BIT 0
BITS 7:6
SEE
BITS 5:4
PWM_FR[1:0]: 2-bit frequency rate for the SW pulsed output used with PWM. When switching a
lower to a higher frequency, disable the SW output by setting SOFT M3QT (Byte 78h) to a 1 before
changing PWM_FR. After changing PWM_FR, wait 200 periods of the new frequency before
enabling the SW output. This delay allows for the internal signals to integrate and lock to the new
frequency without creating a large duty cycle.
00b: 131.25kHz
01b: 262.5kHz
10b: 525kHz
11b: 1050kHz (Default)
BITS 3:0
APC_SR[3:0]: 4-bit sample rate for comparison of APC control.
Defines the sample rate for comparison of APC control.
REPEATED SAMPLE
PERIOD FOLLOWING
FIRST SAMPLE (tREP)
(ns)
APC_SR[3:0]
MINIMUM TIME FROM
BEN TO FIRST SAMPLE
(tFIRST) ±50ns
(ns)
0000b
350
800
0001b
550
1200
0010b
750
1600
0011b
950
2000
0100b
1350
2800
0101b
1550
3200
0110b
1750
3600
0111b
2150
4400
1000b
2950
6000
1001b*
3150
6400
*All codes greater than 1001b (1010b to 1111b) use the maximum sample time of
code 1001b.
______________________________________________________________________________________
65
DS1875
PON Triplexer and SFP Controller
Table 02h, Register 89h: CONFIG
89h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
FETG DIR
TX-F LEN
M3QT LEN
ASEL
BOLFS
RSSI_FC
RSSI_FF
BIT 7
EN5TO8B
BIT 0
Configure the memory location and the polarity of the digital outputs.
BIT 7
FETG DIR: Chooses the direction or polarity of the FETG output for normal operation.
0 = (Default) Under normal operation, FETG is pulled low.
1 = Under normal operation, FETG is pulled high.
BIT 6
TX-F LEN: The TX-F output pin always reflects the wired-OR of all TX-F enabled alarm states. This
bit enables the latching of the alarm state for the TX-F output pin.
0 = (Default) Not latched.
1 = The alarm bits are latched until cleared by a TX-D transition or power-down. If the VCC alarm is
enabled for either FETG or TX-F, then latching is disabled until after the first VCC measurement is
made above the VCC ALARM LO set point to allow for proper operation during slow power-on
cycles.
BIT 5
M3QT LEN: This bit enables the latching of the alarm for the M3QT.
0 = (Default) Not latched.
1 = The alarm bit is latched until cleared by setting the M3QT RESET bit (Byte 78h).
BIT 4
ASEL: Address select.
0 = (Default) Device address of A2h.
1 = Device address is equal to the value found in the DEVICE ADDRESS byte (Table 02h, 8Ch).
BIT 3
BOLFS: Bias open-loop full scale.
0 = (Default) Full scale is 600μA.
1 = Full scale is 1.2mA.
BITS 2:1
BIT 0
66
RSSI_FC and RSSI_FF: RSSI force coarse and RSSI force fine. Control bits for RSSI mode of
operation on the MON3 conversion.
00b = (Default) Normal RSSI mode of operation.
01b = The fine settings of scale and offset are used for MON3 conversions.
10b = The coarse settings of scale and offset are used for MON3 conversions.
11b = Normal RSSI mode of operation.
EN5TO8B: This bit enables MON5–MON8 conversion (voltage of D0–D3 pins).
0 = (Default) Temperature, VCC, and MON1–MON8 conversions are enabled.
1 = Temperature, VCC, and MON1–MON4 conversions are enabled.
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Table 02h, Register 8Ah: RESERVED
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
This register is reserved.
Table 02h, Register 8Bh: MOD RANGING
8Bh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MOD2
MOD1
BIT 7
MOD0
BIT 0
The lower nibble of this byte controls the full-scale range of the Modulation DAC
BITS 7:3
RESERVED (Default = 0)
MOD[2:0]: MOD FS RANGING: 3-bit value to select the FS output voltage for MOD. Default is 000b
and creates a FS of 1.25V.
BITS 2:0
MOD[2:0]
000b
001b
010b
011b
100b
101b
110b
111b
% OF 1.25V
100.00
80.05
66.75
50.13
40.15
33.50
28.74
25.17
FS VOLTAGE (V)
1.250
1.001
0.834
0.627
0.502
0.419
0.359
0.315
______________________________________________________________________________________
67
DS1875
PON Triplexer and SFP Controller
Table 02h, Register 8Ch: DEVICE ADDRESS
8Ch
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
27
26
25
24
23
22
21
BIT 7
20
BIT 0
This value becomes the I2C slave address for the main memory when the ASEL (Table 02h, Register 89h) bit
is set. If A0h is programmed to this register, the auxiliary memory is disabled.
68
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Table 02h, Register 8Dh: COMP RANGING
8Dh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
RESERVED
BIAS2
BIAS1
BIAS0
RESERVED
APC2
APC1
BIT 7
APC0
BIT 0
The upper nibble of this byte controls the full-scale range of the quick-trip monitoring for BIAS. The lower nibble
of this byte controls the full-scale range for the quick-trip monitoring of the APC reference as well as the closedloop monitoring of APC.
BIT 7
RESERVED (Default = 0)
BIAS[2:0] BIAS Full-Scale Ranging. 3-bit value to select the FS comparison voltage for BIAS found
on MON1. Default is 000b and creates a FS of 1.25V.
BITS 6:4
BIT 3
BIAS[2:0]
% OF 1.25V
FS VOLTAGE (V)
000b
100.00
1.250
001b
80.04
1.001
010b
66.73
0.834
011b
50.10
0.626
100b
40.11
0.501
101b
33.45
0.418
110b
28.69
0.359
111b
25.12
0.314
RESERVED (Default = 0)
APC[2:0] APC Full-Scale Ranging. 3-bit value to select the FS comparison voltage for BMD with
the APC. Default is 000b and creates a FS of 2.5V.
BITS 2:0
APC[2:0]
% OF 2.50V
FS VOLTAGE (V)
000b
100.00
1.250
001b
80.04
1.001
010b
66.73
0.834
011b
50.10
0.626
100b
40.11
0.501
101b
33.45
0.418
110b
28.69
0.359
111b
25.12
0.314
______________________________________________________________________________________
69
DS1875
PON Triplexer and SFP Controller
Table 02h, Register 8Eh: RIGHT SHIFT1 (RSHIFT1)
FACTORY DEFAULT
8Eh
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
RESERVED
MON11
MON12
MON10
RESERVED
MON22
MON21
BIT 7
MON20
BIT 0
Allows for right-shifting the final answer of MON1 and MON2 voltage measurements. This allows for scaling the
measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is
weighted to the correct LSB.
Table 02h, Register 8Fh: RIGHT SHIFT0 (RSHIFT0)
8Fh
FACTORY DEFAULT
30h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
RESERVED
MON31
MON32
MON30
RESERVED
MON42
MON41
BIT 7
MON40
BIT 0
Allows for right-shifting the final answer of MON3 and MON4 voltage measurements. This allows for scaling the
measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is
weighted to the correct LSB.
Table 02h, Register 90h to 91h: RESERVED
FACTORY DEFAULT
0000h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
These registers are reserved.
70
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Table 02h, Register 92h to 93h: VCC SCALE
Table 02h, Register 94h to 95h: MON1 SCALE
Table 02h, Register 96h to 97h: MON2 SCALE
Table 02h, Register 98h to 99h: MON3 FINE SCALE
Table 02h, Register 9Ah to 9Bh: MON4 SCALE
Table 02h, Register 9Ch to 9Dh: MON3 COARSE SCALE
FACTORY CALIBRATED
92h, 94h,
96h, 98h,
9Ah, 9Ch
93h, 95h,
97h, 99h,
9Bh, 9Dh
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
BIT 7
BIT 0
Controls the scaling or gain of the FS voltage measurements. The factory-calibrated value produces an FS
voltage of 6.5536V for VCC and 2.5V for MON1, MON2, MON3, and MON4.
Table 02h, Register 9Eh to A1h: RESERVED
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
These registers are reserved.
______________________________________________________________________________________
71
DS1875
PON Triplexer and SFP Controller
Table 02h, Register A2h to A3h: VCC OFFSET
Table 02h, Register A4h to A5h: MON1 OFFSET
Table 02h, Register A6h to A7h: MON2 OFFSET
Table 02h, Register A8h to A9h: MON3 FINE OFFSET
Table 02h, Register AAh to ABh: MON4 OFFSET
Table 02h, Register ACh to ADh: MON3 COARSE OFFSET
A2h, A4h,
A6h, A8h,
AAh, ACh
A3h, A5h,
A7h, A9h,
ABh, ADh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
S
S
215
214
213
212
211
210
29
28
27
26
25
24
23
22
BIT 7
BIT 0
Allows for offset control of these voltage measurements if desired.
Table 02h, Register AEh to AFh: INTERNAL TEMP OFFSET
FACTORY CALIBRATED
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
AEh
S
28
27
26
25
24
23
22
AFh
21
20
2-1
2-2
2-3
2-4
2-5
2-6
BIT 7
BIT 0
Allows for offset control of temperature measurement if desired. The final result must be XORed with BB40h
before writing to this register. Factory calibration contains the desired value for a reading in degrees Celsius.
72
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Table 02h, Register B0h to B3h: PW1
FACTORY DEFAULT
FFFF FFFFh
READ ACCESS
N/A
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
B0h
231
230
229
228
227
226
225
224
B1h
223
222
221
220
219
218
217
216
B2h
215
214
213
212
211
210
29
28
B3h
27
26
25
24
23
22
21
20
BIT 7
BIT 0
The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the
PWE value is set to all 1s. Thus, writing these bytes to all 1s grants PW1 access on power-on without writing
the password entry. All reads of this register are 00h.
Table 02h, Register B4h to B7h: PW2
FACTORY DEFAULT
FFFF FFFFh
READ ACCESS
N/A
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
B4h
231
230
229
228
227
226
225
224
B5h
223
222
221
220
219
218
217
216
B6h
215
214
213
212
211
210
29
28
B7h
27
26
25
24
23
22
21
20
BIT 7
BIT 0
The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the
PWE value is set to all 1s. Thus writing these bytes to all 1s grants PW2 access on power-on without writing
the password entry. All reads of this register are 00h.
______________________________________________________________________________________
73
DS1875
PON Triplexer and SFP Controller
Table 02h, Register B8h: FETG ENABLE1
B8h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
TEMP EN
VCC EN
MON1 EN
MON2 EN
MON3 EN
MON4 EN
RESERVED
BIT 7
RESERVED
BIT 0
Configures the maskable interrupt for the FETG pin.
BIT 7
TEMP EN: Enables/disables active interrupts on the FETG pin due to temperature measurements
outside the threshold limits.
0 = Disable (Default)
1 = Enable
BIT 6
VCC EN: Enables/disables active interrupts on the FETG pin due to VCC measurements outside
the threshold limits.
0 = Disable (Default)
1 = Enable
BIT 5
MON1 EN: Enables/disables active interrupts on the FETG pin due to MON1 measurements outside
the threshold limits.
0 = Disable (Default)
1 = Enable
BIT 4
MON2 EN: Enables/disables active interrupts on the FETG pin due to MON2 measurements outside
the threshold limits.
0 = Disable (Default)
1 = Enable
BIT 3
MON3 EN: Enables/disables active interrupts on the FETG pin due to MON3 measurements outside
the threshold limits.
0 = Disable (Default)
1 = Enable
BIT 2
MON4 EN: Enables/disables active interrupts on the FETG pin due to MON4 measurements outside
the threshold limits.
0 = Disable (Default)
1 = Enable
BITS 1:0
74
RESERVED (Default = 0)
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Table 02h, Register B9h: FETG ENABLE0
B9h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
TXP HI EN
TXP LO EN
BIAS HI EN
BIAS MAX
EN
BIT 7
RESERVED
RESERVED
RESERVED
RESERVED
BIT 0
Configures the maskable interrupt for the FETG pin.
BIT 7
TXP HI EN: Enables/disables active interrupts on the FETG pin due to TXP fast comparisons above the
threshold limit.
0 = Disable (Default)
1 = Enable
BIT 6
TXP LO EN: Enables/disables active interrupts on the FETG pin due to TXP fast comparisons below the
threshold limit.
0 = Disable (Default)
1 = Enable
BIT 5
BIAS HI EN: Enables/disables active interrupts on the FETG pin due to BIAS fast comparisons above
the threshold limit.
0 = Disable. (Default)
1 = Enable
BIT 4
BIAS MAX EN: Enables/disables active interrupts on the FETG pin due to BIAS fast comparisons
below the threshold limit.
0 = Disable (Default)
1 = Enable
BITS 3:0
RESERVED (Default = 0)
______________________________________________________________________________________
75
DS1875
PON Triplexer and SFP Controller
Table 02h, Register BAh: TX-F ENABLE1
BAh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
TEMP EN
VCC EN
MON1 EN
MON2 EN
MON3 EN
MON4 EN
RESERVED
BIT 7
RESERVED
BIT 0
Configures the maskable interrupt for the TX-F pin.
BIT 7
TEMP EN: Enables/disables active interrupts on the TX-F pin due to temperature measurements outside
the threshold limits.
0 = Disable (Default)
1 = Enable
BIT 6
VCC EN: Enables/disables active interrupts on the TX-F pin due to VCC measurements outside
the threshold limits.
0 = Disable (Default)
1 = Enable
BIT 5
MON1 EN: Enables/disables active interrupts on the TX-F pin due to MON1 measurements outside the
threshold limits.
0 = Disable (Default)
1 = Enable
BIT 4
MON2 EN: Enables/disables active interrupts on the TX-F pin due to MON2 measurements outside the
threshold limits.
0 = Disable (Default)
1 = Enable
BIT 3
MON3 EN: Enables/disables active interrupts on the TX-F pin due to MON3 measurements outside the
threshold limits.
0 = Disable (Default)
1 = Enable
BIT 2
MON4 EN: Enables/disables active interrupts on the TX-F pin due to MON4 measurements outside the
threshold limits.
0 = Disable (Default)
1 = Enable
BITS 2:0
76
RESERVED (Default = 0)
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Table 02h, Register BBh: TX-F ENABLE0
BBh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
TXP HI EN
TXP LO EN
BIAS HI EN
BIAS MAX
EN
RESERVED
BIT 7
RESERVED
RESERVED
FETG EN
BIT 0
Configures the maskable interrupt for the TX-F pin.
BIT 7
TXP HI EN: Enables/disables active interrupts on the TX-F pin due to TXP fast comparisons above the
threshold limit.
0 = Disable (Default)
1 = Enable
BIT 6
TXP LO EN: Enables/disables active interrupts on the TX-F pin due to TXP fast comparisons below the
threshold limit.
0 = Disable (Default)
1 = Enable
BIT 5
BIAS HI EN: Enables/disables active interrupts on the TX-F pin due to BIAS fast comparisons above
the threshold limit.
0 = Disable (Default)
1 = Enable
BIT 4
BIAS MAX EN: Enables/disables active interrupts on the TX-F pin due to BIAS fast comparisons
above the threshold limit.
0 = Disable (Default)
1 = Enable
BITS 3:1
BIT 0
RESERVED (Default = 0)
FETG EN:
0 = Normal FETG operation (Default).
1 = Enables FETG to act as an input to TX-F output.
______________________________________________________________________________________
77
DS1875
PON Triplexer and SFP Controller
Table 02h, Register BCh: HTXP
BCh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
27
26
25
24
23
22
21
BIT 7
20
BIT 0
Fast comparison DAC threshold adjust for high TXP. This value is added to the APC DAC value recalled from
Table 04h. If the sum is greater than 0xFF, 0xFF is used. Comparisons greater than VHTXP, compared against
VBMD, create a TXP HI alarm. The same ranging applied to the APC DAC should be used here.
VHTXP =
Full Scale
(HTXP + APC DAC)
255
Table 02h, Register BDh: LTXP
BDh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
27
26
25
24
23
22
21
BIT 7
20
BIT 0
Fast-comparison DAC threshold adjust for low TXP. This value is subtracted from the APC DAC value recalled
from Table 04h. If the difference is less than 0x00, 0x00 is used. Comparisons less than VLTXP, compared
against VBMD, create a TXP LO alarm. The same ranging applied to the APC DAC should be used here.
VLTXP =
78
Full Scale
( APC DAC LTXP )
255
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Table 02h, Register BEh: HBIAS
BEh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
27
26
25
24
23
22
21
BIT 7
20
BIT 0
Fast-comparison DAC setting for high BIAS. Comparisons greater than VHBIAS, found on the MON1 pin, create a
BIAS HI alarm.
Full Scale
VHBIAS =
HBIAS
255
Table 02h, Register BFh: MAX BIAS
BFh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
212
BIT 7
211
210
29
28
27
26
25
BIT 0
This value defines the maximum DAC value allowed for the upper 8 bits of BIAS output during all operations.
______________________________________________________________________________________
79
DS1875
PON Triplexer and SFP Controller
Table 02h, Register C0h: DPU
FACTORY DEFAULT
C0h
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
INV M3QT
MUX M3QT
INV LOS
MUX LOS
D3 CNTL
D2 CNTL
D1 CNTL
D0 CNTL
BIT 7
BIT 0
BIT 7
INV M3QT: Inverts the internal M3QT signal to output pin D2 if MUX M3QT is set. If MUX M3QT is
not set, this bit’s value is a don’t care.
0 = (Default) Noninverted M3QT to D2 pin.
1 = Inverted M3QT to D2 pin.
BIT 6
MUX M3QT: Chooses the control for D2 output pin.
0 = (Default) D2 is controlled by bit D2 IN found in byte 79h.
1 = M3QT is buffered to D2 pin.
BIT 5
INV LOS: Inverts the buffered input pin LOSI to output pin D0 if MUX LOS is set. If MUX LOS is
not set, this bit’s value is a don’t care.
0 = (Default) Noninverted LOSI to D0 pin.
1 = Inverted LOSI to D0 pin.
BIT 4
MUX LOS: Chooses the control for D0 output pin.
0 = (Default) DO is controlled by bit D0 IN found in byte 79h.
1 = LOSI is buffered to D0 pin.
BIT 3
D3 CNTL: At power-on, this bit’s value is loaded into bit D3 OUT of byte 78h to control the output
pin D3.
0 = (Default)
BIT 2
D2 CNTL: At power-on, this bit’s value is loaded into bit D2 OUT of byte 78h to control the output
pin D2.
0 = (Default)
BIT 1
D1 CNTL: At power-on, this bit’s value is loaded into bit D1 OUT of byte 78h to control the output
pin D1.
0 = (Default)
BIT 0
D0 CNTL: At power-on, this bit’s value is loaded into bit D0 OUT of byte 78h to control the output
pin D0.
0 = (Default)
Controls the power-on values for D3, D2, D1, and D0 output pins and mux and invertion of the LOSI pin.
80
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Table 02h, Register C1h to C2h: RESERVED
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register C3h: M3QT DAC
FACTORY DEFAULT
C3h
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
27
26
25
24
23
22
21
BIT 7
20
BIT 0
Register to control M3QT DAC.
VM3QT =
1.25
(M3QT DAC + 1)
256
Table 02h, Register C4h: DAC1
C4h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
27
26
25
24
23
BIT 7
22
21
20
BIT 0
Register to control DAC1.
VDACI =
2.5
(DAC1+ 1)
256
______________________________________________________________________________________
81
DS1875
PON Triplexer and SFP Controller
Table 02h, Register C5h to C6h: RESERVED
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register C7h: M4 LUT CNTL
C7h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
RESERVED
RESERVED
RESERVED
RESERVED
FBOL
FBCL
DBL_SB
BIT 7
BIT 0
BITS 7:4
RESERVED (Default = 000000b)
BITS 3:2
FBOL and FBCL: Force bias open loop and force bias closed loop.
00b = (Default) normal operation.
10b = Force control of IBIAS to be open loop regardless of duration of BEN pulses.
01b = Force control of IBIAS to be closed loop regardless of duration of BEN pulses.
11b = Same as 10b.
When forcing open-loop mode, BEN should be ground or at any burst length.
BIT 1
DBL_SB: Chooses the size of LUT for Table 06h.
0 = (Default) Single LUT of 32 bytes.
1 = Double LUT of 16 bytes.
BIT 0
UP_LOWB: Determines which 16-byte LUT is used if DBL_SB = 1. If DBL_SB = 0, the value of
this bit is a don’t care.
0 = (Default) Chooses the lower 16 bytes of Table 06h (80h to 8Fh).
1 = Chooses the upper 16 bytes of Table 06h (90h to 9Fh).
Controls the size and location of LUT functions for the MON4 measurement.
82
UP_LOWB
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Table 02h, Register C8h to C9h: MON5 SCALE
Table 02h, Register CAh to CBh: MON6 SCALE
Table 02h, Register CCh to CDh: MON7 SCALE
Table 02h, Register CEh to CFh: MON8 SCALE
FACTORY CALIBRATED
C8h, CAh,
CCh, CEh
C9h, CBh,
CDh, CFh
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
BIT 7
BIT 0
Controls the scaling or gain of the FS voltage measurements. The factory-calibrated value produces an FS
voltage of 2.5V for MON5, MON6, MON7, and MON8.
Table 02h, Register D0h to D1h: MON5 OFFSET
Table 02h, Register D2h to D3h: MON6 OFFSET
Table 02h, Register D4h to D5h: MON7 OFFSET
Table 02h, Register D6h to D7h: MON8 OFFSET
D0h, D2h,
D4h, D6h
D1h, D3h,
D5h, D7h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
S
S
215
214
213
212
211
210
29
28
27
26
25
24
23
22
BIT 7
BIT 0
Allows for offset control of these voltage measurements if desired.
______________________________________________________________________________________
83
DS1875
PON Triplexer and SFP Controller
Table 02h, Register D8h to F7h: EMPTY
Table 02h, Register F8h to F9h: MAN BIAS
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and BIAS EN = 1
MEMORY TYPE
Volatile
F8h
RESERVED
RESERVED
212
211
210
29
28
27
F9h
27
26
25
24
23
22
21
20
BIT 7
BIT 0
When BIAS EN (Table 02h, Register 80h) is written to 0, writes to these bytes control the BIAS DAC.
Table 02h, Register FAh: MAN_CNTL
FAh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and BIAS EN = 1
MEMORY TYPE
Volatile
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BIT 7
MAN_CLK
BIT 0
When BIAS EN (Table 02h, Register 80h) is written to 0, bit 0 of this byte controls the updates of the MAN BIAS
value to the BIAS output. The values of MAN BIAS should be written with a separate write command. Setting bit 0
to a 1 clocks the MAN BIAS value to the output DAC.
1.
Write the MAN BIAS value with a write command.
2.
Set the MAN_CLK bit to a 1 with a separate write command.
3.
Clear the MAN_CLK bit to a 0 with a separate write command.
84
______________________________________________________________________________________
PON Triplexer and SFP Controller
DS1875
Table 02h, Register FBh to FCh: BIAS DAC
FACTORY DEFAULT
8000h
READ ACCESS
PW2
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
FBh
BOL
0
212
211
210
29
28
27
FCh
27
26
25
24
23
22
21
20
BIT 7
BIT 0
The bias open-loop bit (BOL) reflects the status of the BIAS current-control loop. If it is 1, the loop is open and
the DS1875 is controlling the BIAS output from the LUT. If it is 0, the loop is closed and the BIAS output is
controlled by active feedback from the BMD pin. The remaining bits are the digital value used for the BIAS
output regardless of the value of OL.
Table 02h, Register FDh: BIAS OL
FDh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and APC EN = 1
MEMORY TYPE
Volatile
27
BIT 7
26
25
24
23
22
21
20
BIT 0
The digital value used for BIAS at power-on and during open loop. It is recalled from Table 08h at the adjusted
memory address found in TINDEX. This register is updated at the end of the temperature conversion. The
correct value depends on the value of BOLFS (Table 02h, Register 89h, bit 3).
If BOLFS = 0, BIAS OL[7:0] = IBIAS[11:4].
If BOLFS = 1, BIAS OL[7:0] = IBIAS [12:5].
______________________________________________________________________________________
85
DS1875
PON Triplexer and SFP Controller
Table 02h, Register FEh: PWM DAC
FEh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2 and PWM EN = 0
MEMORY TYPE
Volatile
27
26
25
24
23
22
21
BIT 7
20
BIT 0
The digital value used for PWM integration of the FB pin. It is recalled from Table 07h at the adjusted memory
address found in TINDEX. This register is updated at the end of the temperature conversion.
VPWM =
1.25
(PWM DAC + 1)
256
Table 02h, Register FFh: RESERVED
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
N/A
MEMORY TYPE
N/A
This register is reserved.
86
______________________________________________________________________________________
PON Triplexer and SFP Controller
Table 03h, Register 80h to FFh: PW2 EEPROM
80h to FFh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (EE)
EE
EE
EE
EE
EE
EE
EE
BIT 7
EE
BIT 0
PW2-protected EEPROM.
Table 04h Register Descriptions
Table 04h, Register 80h to C7h: MODULATION LUT
80h to C7h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (EE)
27
BIT 7
26
25
24
23
22
21
20
BIT 0
The digital value for the modulation DAC output.
The MODULATION LUT is a set of registers assigned to hold the temperature profile for the modulation DAC.
The values in this table combined with the MOD bits in the MOD RANGING register (Table 02h, Register 8Bh)
determine the set point for the modulation voltage. The temperature measurement is used to index the LUT
(TINDEX, Table 02h, Register 81h) in 2°C increments from -40°C to +102°C, starting at 80h in Table 04h.
Register 80h defines the -40°C to -38°C MOD output, Register 81h defines the -38°C to -36°C MOD output, and
so on. Values recalled from this EEPROM memory table are written into the MOD DAC (Table 02h, Register 82h)
location that holds the value until the next temperature conversion. The DS1875 can be placed into a manual
mode (MOD EN bit, Table 02h, Register 80h), where MOD DAC is directly controlled for calibration. If the
temperature compensation functionality is not required, then program the entire Table 04h, to the desired
modulation setting.
______________________________________________________________________________________
87
DS1875
Table 03h Register Descriptions
DS1875
PON Triplexer and SFP Controller
Table 05h Register Descriptions
Table 05h, Register 80h to A3h: APC TE LUT
80h to A3h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (EE)
27
26
25
24
23
22
21
BIT 7
20
BIT 0
The APC TE LUT is a set of registers assigned to hold the temperature profile for the APC reference DAC. The
values in this table combined with the APC bits in the COMP RANGING register (Table 02h, Register 8Dh)
determine the set point for the APC loop. The temperature measurement is used to index the LUT (TINDEX,
Table 02h, Register 81h) in 4°C increments from -40°C to +100°C, starting at Register 80h in Table 05h.
Register 80h defines the -40°C to -36°C APC reference value, Register 81h defines the -36°C to -32°C APC
reference value, and so on. Values recalled from this EEPROM memory table are written into the APC DAC
(Table 02h, Register 83h) location that holds the value until the next temperature conversion. The DS1875 can
be placed into a manual mode (APC EN bit, Table 02h, Register 80h), where APC DAC can be directly
controlled for calibration. If TE temperature compensation is not required by the application, program the entire
LUT to the desired APC set point.
Table 05h, Register A4h to A7h: RESERVED
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (EE)
These registers are reserved.
88
______________________________________________________________________________________
PON Triplexer and SFP Controller
Table 06h, Register 80h to 9Fh: M4DAC LUT
80h to 9Fh
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (EE)
27
BIT 7
26
25
24
23
22
21
20
BIT 0
The M4DAC LUT is set of registers assigned to hold the voltage profile for the M4DAC. The values in this table
determine the set point for the M4DAC. The MON4 voltage measurement is used to index the LUT (VINDEX,
Table 02h, Register 84h), starting at Register 80h in Table 06h. Values recalled from this EEPROM memory
table are written into the M4DAC (Table 02h, Register 85h) location that holds the value until the next MON4
voltage conversion. The DS1875 can be placed into a manual mode (M4DAC EN bit, Table 02h, Register 80h),
where M4DAC is directly controlled for calibration. If voltage compensation is not required by the application,
program the entire LUT to the desired M4DAC set point.
______________________________________________________________________________________
89
DS1875
Table 06h Register Descriptions
DS1875
PON Triplexer and SFP Controller
Table 07h Register Descriptions
Table 07h, Register 80h to A3h: PWM REFERENCE LUT
80h to A3h
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (EE)
27
26
25
24
23
22
21
BIT 7
20
BIT 0
The PWM REFERENCE LUT is a set of registers assigned to hold the temperature profile for the PWM feedback.
The values in this table determine the set point for the PWM loop. The temperature measurement is used to
index the LUT (TINDEX, Table 02h, Register 81h) in 4°C increments from -40°C to +100°C, starting at Register
80h in Table 07h. Register 80h defines the -40°C to -36°C PWM reference value, Register 81h defines the -36°C
to -32°C PWM reference value, and so on. Values recalled from this EEPROM memory table are written into the
PWM DAC (Table 02h, Register FEh) location that holds the value until the next temperature conversion. The
DS1875 can be placed into a manual mode (PWM EN bit, Table 02h, Register 80h), where PWM DAC can be
directly controlled for calibration. If temperature compensation is not required by the application, program the
entire LUT to the desired PWM set point.
Table 07h, Register A4h to A7h: RESERVED
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE
Nonvolatile (SEE)
These registers are reserved.
90
______________________________________________________________________________________
PON Triplexer and SFP Controller
Table 08h, Register 80h to C7h: BIAS OPEN-LOOP LUT
80h to C7h
FACTORY DEFAULT
00h
READ ACCESS
All
WRITE ACCESS
All
MEMORY TYPE
Nonvolatile (EE)
27
26
25
24
23
22
21
BIT 7
20
BIT 0
The BIAS OPEN-LOOP LUT is a set of registers assigned to hold the temperature profile for the BIAS OL DAC.
The values in this table determine the set point for the BIAS current. The temperature measurement is used to
index the LUT (TINDEX, Table 02h, Register 81h) in 2°C increments from -40°C to +102°C, starting at 80h in
Table 08h. Register 80h defines the -40°C to -38°C BIAS OL output, Register 81h defines the -38°C to -36°C
BIAS OL output, and so on. Values recalled from this EEPROM memory table are written into the BIAS OL (Table
02h, Register FDh) location that holds the value until the next temperature conversion. The DS1875 can be
placed into a manual mode (BIAS EN bit, Table 02h, Register 80h), where BIAS OL DAC is directly controlled for
calibration. If the temperature compensation functionality is not required, then program the entire Table 08h to
the desired BIAS OL setting.
Auxiliary Memory A0h Register Descriptions
Auxiliary Memory A0h, Register 00h to FFh: EEPROM
80h to FFh
FACTORY DEFAULT
00h
READ ACCESS
ALL
WRITE ACCESS
ALL
MEMORY TYPE
Nonvolatile (EE)
27
26
25
24
23
22
21
BIT 7
20
BIT 0
Accessible with the slave address A0h.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
38 TQFN-EP
T3857+1
21-0172
______________________________________________________________________________________
91
DS1875
Table 08h Register Descriptions
DS1875
PON Triplexer and SFP Controller
Revision History
REVISION
NUMBER
REVISION
DATE
0
7/08
1
10/08
DESCRIPTION
Initial release.
PAGES
CHANGED
—
Updated all instances of the operating voltage range from 5.5V to 3.9V on
multiple pages.
1, 5–13
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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