LF411QML LF411QML Low Offset, Low Drift JFET Input Operational Amplifier Literature Number: SNOSAO6B LF411QML Low Offset, Low Drift JFET Input Operational Amplifier General Description Features This device is a low cost, high speed, JFET input operational amplifier with very low input offset voltage and guaranteed input offset voltage drift. It requires low supply current yet maintains a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The LF411QML is pin compatible with the standard LM741 allowing designers to immediately upgrade the overall performance of existing designs. This amplifier may be used in applications such as high speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage and drift, low input bias current, high input impedance, high slew rate and wide bandwidth. ■ Available with radiation guarantee — ELDRS FREE Internally trimmed offset voltage: Input offset voltage drift: Low input bias current: Low input noise current: Wide gain bandwidth: High slew rate: Low supply current: High input impedance: Low total harmonic distortion: AV = 10, RL = 10KΩ, VO = 20VP-P, BW = 20Hz - 20KHz ■ Low 1/f noise corner: ■ Fast settling time to 0.01%: 100 krad(Si) 0.5 mV(Typ) 10 μV/°C 50 pA 0.01 pA/√Hz 3 MHz 10V/μs 1.8 mA 1012Ω <0.0 2% ■ ■ ■ ■ ■ ■ ■ ■ ■ 50 Hz 2 μs Ordering Information NS Part Number SMD Part Number LF411MH/883 NS Package Number H08C Package Description 8LD T0–99 Can LF411MWG/883 WG10A 10LD Ceramic SOIC LF411MWG-MLS 50 krad(Si) (Note 9) WG10A 10LD Ceramic SOIC WG10A 10LD Ceramic SOIC LF411MWGRLQMLV 100 krad(Si) (Note 10) 5962R1122201VZA ELDRS Free Connection Diagrams Metal Can Package 10LD Ceramic SOIC Package 20149244 Top View See NS Package Number WG10A 20149205 Note: Pin 4 connected to case. Top View See NS Package Number H08A BI-FET II™ is a trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation 201492 www.national.com LF411QML Low Offset, Low Drift JFET Input Operational Amplifier June 30, 2011 LF411QML Simplified Schematic 20149206 Detailed Schematic 20149234 www.national.com 2 LF411QML Absolute Maximum Ratings (Note 1) Supply Voltage Differential Input Voltage Input Voltage Range (Note 4) Output Short Circuit Duration Power Dissipation (Note 2), (Note 3) H Package WG Package TJmax H Package WG Package Thermal Resistance ±18V ±30V ±15V Continuous 670mW 670mW 150°C 150°C θJA H Package Still Air H Package 500LF/Min Air Flow WG Package Still Air WG Package 500LF/Min Air Flow 162°C/W 65°C/W 170°C/W 120°C/W θJC H Package WG Package Operating Temperature Range 20°C/W 26°C/W −55°C ≤ TA ≤ 125°C −65°C ≤ TA ≤ 150°C 260°C Storage Temperature Range Lead Temperature (Soldering, 10 seconds) Package Weight (Typical) H Package WG Package ESD Tolerance (Note 5) TBD 220mg 750V Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description 1 Static tests at Temp °C +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Settling time at +25 13 Settling time at +125 14 Settling time at -55 3 www.national.com LF411QML LF411 883 Electrical Characteristics DC Parameters The following conditions apply, unless otherwise specified. DC: VCC = ±15V, VCM = 0V, RS = 0Ω Symbol VIO IIO Parameter Input Offset Voltage Conditions Notes RS = 10KΩ Input Offset Current (Note 8) ±IIB Input Bias Current Min Max Unit Subgroups -2.0 2.0 mV 1 -3.7 3.7 mV 2 -3.3 3.3 mV 3 -0.1 0.1 nA 1 -25 25 nA 2 1 -0.2 0.2 nA (Note 8) -50 50 nA 2 (Note 6) ±9.0 V 1, 2, 3 VCM Input Common Mode Voltage Range CMRR Common Mode Rejection Ratio RS ≤ 10KΩ, VCM = ±9V 70 dB 1, 2, 3 +PSRR Supply Voltage Rejection Ratio +VCC = 6V, -VCC = -15V 70 dB 1, 2, 3 -PSRR Supply Voltage Rejection Ratio +VCC = 15V, -VCC = -6V 70 IS Supply Current -IOS Output Short Circuit Current +IOS Output Short Circuit Current +VIO Adj Input Offset Voltage Adjustment -VIO Adj Input Offset Voltage Adjustment +AVS Large Signal Voltage Gain -AVS Large Signal Voltage Gain VO+ Output Voltage Swing VO- Output Voltage Swing dB 1, 2, 3 3.4 mA 1, 2, 3 +VI = -11V, -VI = 11V, 13 50 mA 1 RS = 10KΩ 6.0 60 mA 2, 3 +VI = 11V, -VI = -11V, -50 -13 mA 1 RS = 10KΩ -60 -6.0 mA 2, 3 mV 1 8.0 mV 1 VO = 0 to 10V, RL = 2KΩ (Note 7) 25 -8.0 V/mV 4 VO = 0 to 10V, RL = 2KΩ (Note 7) 15 V/mV 5, 6 VO = 0 to -10V, RL = 2KΩ (Note 7) 25 V/mV 4 VO = 0 to -10V, RL = 2KΩ (Note 7) 15 V/mV 5, 6 12 V 4, 5, 6 -12 V 4, 5, 6 Max Unit Subgroups RL = 10KΩ, +VI = 11V, -VI = -11V, RS = 10KΩ RL = 10KΩ, +VI = -11V, -VI = 11V, RS = 10KΩ AC Parameters The following conditions apply, unless otherwise specified. AC: VCC = ±15V, VCM = 0V, RS = 0Ω Symbol Parameter Conditions Notes Min SR+ Slew Rate VO = -5V to 5V 8.0 V/µS 7 SR- Slew Rate VO = 5V to -5V 8.0 V/µS 7 GBW Gain Bandwidth Product 2.7 MHz 7 www.national.com 4 LF411QML Space Level Electrical Characteristics DC Parameters The following conditions apply, unless otherwise specified. DC: VCC = ±15V, VCM = 0V, RS = 0Ω Symbol VIO IIO Parameter Input Offset Voltage Conditions Notes RS = 10KΩ Input Offset Current (Note 8) ±IIB Input Bias Current Min Max Unit Subgroups -2.0 2.0 mV 1 -3.7 3.7 mV 2 -3.3 3.3 mV 3 -0.1 0.1 nA 1 -25 25 nA 2 1 -0.2 0.2 nA (Note 8) -50 50 nA 2 (Note 6) ±9.0 V 1, 2, 3 VCM Input Common Mode Voltage Range CMRR Common Mode Rejection Ratio RS ≤ 10KΩ, VCM = ±9V 70 dB 1, 2, 3 +PSRR Supply Voltage Rejection Ratio +VCC = 6V, -VCC = -15V 70 dB 1, 2, 3 -PSRR Supply Voltage Rejection Ratio +VCC = 15V, -VCC = -6V 70 IS Supply Current -IOS Output Short Circuit Current +IOS Output Short Circuit Current +VIO Adj Input Offset Voltage Adjustment -VIO Adj Input Offset Voltage Adjustment +AVS Large Signal Voltage Gain -AVS Large Signal Voltage Gain VO+ Output Voltage Swing VO- Output Voltage Swing dB 1, 2, 3 3.4 mA 1, 2, 3 +VI = -11V, -VI = 11V, 13 50 mA 1 RS = 10KΩ 6.0 60 mA 2, 3 +VI = 11V, -VI = -11V, -50 -13 mA 1 RS = 10KΩ -60 -6.0 mA 2, 3 mV 1 8.0 mV 1 VO = 0 to 10V, RL = 2KΩ (Note 7) 25 -8.0 V/mV 4 VO = 0 to 10V, RL = 2KΩ (Note 7) 15 V/mV 5, 6 VO = 0 to -10V, RL = 2KΩ (Note 7) 25 V/mV 4 VO = 0 to -10V, RL = 2KΩ (Note 7) 15 V/mV 5, 6 12 V 4, 5, 6 -12 V 4, 5, 6 Max Unit Subgroups RL = 10KΩ, +VI = 11V, -VI = -11V, RS = 10KΩ RL = 10KΩ, +VI = -11V, -VI = 11V, RS = 10KΩ AC Parameters The following conditions apply, unless otherwise specified. AC: VCC = ±15V, VCM = 0V, RS = 0Ω Symbol Parameter Conditions Notes Min SR+ Slew Rate VO = -5V to 5V 8.0 V/µS 7 SR- Slew Rate VO = 5V to -5V 8.0 V/µS 7 GBW Gain Bandwidth Product 2.7 MHz 7 5 www.national.com LF411QML Space Level Electrical Characteristics (Continued) DC Parameters - Drift Values The following conditions apply, unless otherwise specified. DC: VCC = ±15V, VCM = 0V, RS = 0Ω “Delta calculations performed on Space Level devices at Group B Subgroup 5 ONLY” Symbol Parameter Conditions Notes Min Max Unit Subgroups −1 1 mV 1 VIO Input Offset Voltage +IIB Input Bias Current −0.1 0.1 nA 1 −IIB Input Bias Current −0.1 0.1 nA 1 Min Max Unit Subgroups LF411–MLS 50k Radiation Electrical Characteristics DC Parameters - Post Radiation Limits (Note 9) The following conditions apply, unless otherwise specified. DC: VCC = ±15V, VCM = 0V, RS = 0Ω Post Radiation Limits +25°C Symbol Parameter Conditions Notes IIO Input Offset Current −0.25 0.25 nA 1 IIB+ Input Bias Current −1.0 1.0 nA 1 IIB- Input Bias Current −1.0 1.0 nA 1 LF411MWGRLQMLV 100k Radiation Electrical Characteristics — ELDRS Free Only SMD# 5962R1122201 DC Parameters - Post Radiation Limits (Note 10) The following conditions apply, unless otherwise specified. DC: VCC = ±15V, VCM = 0V, RS = 0Ω Post Radiation Limits +25°C Symbol Parameter Conditions Notes Min Max Unit Subgroups IIO Input Offset Current −1.0 1.0 nA 1 IIB+ Input Bias Current −0.20 6.0 nA 1 IIB- Input Bias Current −0.20 6.0 nA 1 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/ θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 3: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside guaranteed limits. Note 4: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 5: Human body model, 100pF discharged through 1.5KΩ. Note 6: Parameters guaranteed by CMRR test. Note 7: Datalog in K = V/mV. Note 8: RS = 10KΩ @ +125°C. Note 9: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in MIL-STD-883, Method 1019 Note 10: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table. These parts may be sensitive in a high dose rate environment. Low dose rate testing has been performed on a wafer-by-wafer basis, per Test Method 1019, Condition D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS). www.national.com 6 LF411QML Typical Connection 20149201 Typical Performance Characteristics Input Bias Current Input Bias Current 20149211 20149212 Supply Current Positive Common-Mode Input Voltage Limit 20149213 20149214 7 www.national.com LF411QML Negative Common-Mode Input Voltage Limit Positive Current Limit 20149216 20149215 Negative Current Limit Output Voltage Swing 20149217 20149218 Output Voltage Swing Gain Bandwidth 20149219 www.national.com 20149220 8 LF411QML Bode Plot Slew Rate 20149222 20149221 Distortion vs Frequency Undistorted Output Voltage Swing 20149223 20149224 Open Loop Frequency Response Common-Mode Rejection Ratio 20149225 20149226 9 www.national.com LF411QML Power Supply Rejection Ratio Equivalent Input Noise Voltage 20149227 20149228 Open Loop Voltage Gain Output Impedance 20149229 20149230 Inverter Settling Time 20149231 www.national.com 10 LF411QML Pulse Response RL=2 kΩ, CL10 pF Small Signal Inverting Small Signal Non-Inverting 20149240 20149239 Large Signal Inverting Large Signal Non-Inverting 20149241 20149242 Current Limit (RL=100Ω) 20149243 11 www.national.com LF411QML The LF411QML will drive a 2 kΩ load resistance to ±10V over the full temperature range. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency, a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Application Hints The LF411QML series of internally trimmed JFET input op amps ( BI-FET II™ ) provide very low input offset voltage and guaranteed input offset voltage drift. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier may be forced to a high state. The amplifier will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. The LF411QML is biased by a zener reference which allows normal circuit operation on ±4.5V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. www.national.com 12 LF411QML Typical Applications High Speed Current Booster 20149209 PNP=2N2905 NPN=2N2219 unless noted TO-5 heat sinks for Q6-Q7 13 www.national.com LF411QML 10-Bit Linear DAC with No VOS Adjust 20149232 where AN=1 if the AN digital input is high AN=0 if the AN digital input is low Single Supply Analog Switch with Buffered Output 20149233 www.national.com 14 Date Released Revision 10/11/05 Section Originator L. Lytle Changes A New Release to corporate format 05/07/07 B Features, Ordering Information Table, L. McGee LF411-MLS Electricals Added reference to Radiation and Radiation Electricals for LF411-MLS device. Revision A will be archived. 06/30/11 C Features, Ordering Information Table, L. McGee & LF411-MLS 50k Post Radiation K.Kruckmeyer Electricals, LF411MWGRLQMLV Post Radiation Electricals Added LF411MWGRLQMLV to Ordering Info and modified Radiation Electricals to “Radiation” devices. Added 50k and 100k Post Radiation DC parameter tables. Revision B will be archived. 15 1 MDS data sheet was converted into the corporate data sheet format. MDS MNLF411M-X Rev 2A2 will be archived. www.national.com LF411QML Revision History LF411QML Physical Dimensions inches (millimeters) unless otherwise noted Metal Can Package (H) NS Package Number H08C 10 Lead Ceramic SOIC (WG)) NS Package Number WG10A www.national.com 16 LF411QML Notes 17 www.national.com LF411QML Low Offset, Low Drift JFET Input Operational Amplifier Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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