dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Data Sheet High-Performance, 16-bit Digital Signal Controllers 2009 Microchip Technology Inc. Preliminary DS70292D Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70292D-page 2 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 High-Performance, 16-Bit Digital Signal Controllers Operating Range: Timers/Capture/Compare/PWM: • Up to 40 MIPS operation (at 3.0-3.6V): - Industrial temperature range (-40°C to +85°C) - Extended temperature range (-40°C to +125°C) • Up to 20 MIPS operation (at 3.0-3.6V): - High temperature range (-40°C to +140°C) • Timer/Counters, up to five 16-bit timers: - Can pair up to make two 32-bit timers - One timer runs as a Real-Time Clock with an external 32.768 kHz oscillator - Programmable prescaler • Input Capture (up to four channels): - Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture • Output Compare (up to four channels): - Single or Dual 16-bit Compare mode - 16-bit Glitchless PWM mode • Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions High-Performance DSC CPU: • • • • • • • • • • • • • • Modified Harvard architecture C compiler optimized instruction set 16-bit wide data path 24-bit wide instructions Linear program memory addressing up to 4M instruction words Linear data memory addressing up to 64 Kbytes 83 base instructions: mostly 1 word/1 cycle Two 40-bit accumulators with rounding and saturation options Flexible and powerful addressing modes: - Indirect - Modulo - Bit-Reversed Software stack 16 x 16 fractional/integer multiply operations 32/16 and 16/16 divide operations Single-cycle multiply and accumulate: - Accumulator write back for DSP operations - Dual data fetch Up to ±16-bit shifts for up to 40-bit data Interrupt Controller: • • • • • Digital I/O: • • • • • • • Direct Memory Access (DMA): • 8-channel hardware DMA • Up to 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: - Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) • Most peripherals support DMA 2009 Microchip Technology Inc. 5-cycle latency Up to 49 available interrupt sources Up to three external interrupts Seven programmable priority levels Five processor exceptions Peripheral pin Select functionality Up to 35 programmable digital I/O pins Wake-up/Interrupt-on-Change for up to 31 pins Output pins can drive from 3.0V to 3.6V Up to 5V output with open drain configuration All digital input pins are 5V tolerant 4 mA sink on all I/O pins On-Chip Flash and SRAM: • Flash program memory (up to 128 Kbytes) • Data SRAM (up to 16 Kbytes) • Boot, Secure and General Security for program Flash Preliminary DS70292D-page 3 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 System Management: Communication Modules: • Flexible clock options: - External, crystal, resonator, internal RC - Fully integrated Phase-Locked Loop (PLL) - Extremely low jitter PLL • Power-up Timer • Oscillator Start-up Timer/Stabilizer • Watchdog Timer with its own RC oscillator • Fail-Safe Clock Monitor • Reset by multiple sources • 4-wire SPI (up to two modules): - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes • I2C™: - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking • UART (up to two modules): - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN bus support - IrDA® encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS • Enhanced CAN (ECAN™ module) 2.0B active: - Up to eight transmit and up to 32 receive buffers - 16 receive filters and three masks - Loopback, Listen Only and Listen All - Messages modes for diagnostics and bus monitoring - Wake-up on CAN message - Automatic processing of Remote Transmission Requests - FIFO mode using DMA - DeviceNet™ addressing support • Parallel Master Slave Port (PMP/EPSP): - Supports 8-bit or 16-bit data - Supports 16 address lines • Programmable Cyclic Redundancy Check (CRC): - Programmable bit length for the CRC generator polynomial (up to 16-bit length) - 8-deep, 16-bit or 16-deep, 8-bit FIFO for data input Power Management: • On-chip 2.5V voltage regulator • Switch between clock sources in real time • Idle, Sleep, and Doze modes with fast wake-up Analog-to-Digital Converters (ADCs): • 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion: - Two and four simultaneous samples (10-bit ADC) - Up to 13 input channels with auto-scanning - Conversion start can be manual or synchronized with one of four trigger sources - Conversion possible in Sleep mode - ±2 LSb max integral nonlinearity - ±1 LSb max differential nonlinearity Audio Digital-to-Analog Converter (DAC): • 16-bit Dual Channel DAC module • 100 ksps maximum sampling rate • Second-Order Digital Delta-Sigma Modulator Data Converter Interface (DCI) module: • • • • Codec interface Supports I2S and AC’97 protocols Up to 16-bit data words, up to 16 words per frame 4-word deep TX and RX buffers Comparator Module: • Two analog comparators with programmable input/output configuration CMOS Flash Technology: • • • • • Low-power, high-speed Flash technology Fully static design 3.3V (±10%) operating voltage Industrial and Extended temperature Low power consumption DS70292D-page 4 Packaging: • 28-pin SDIP/SOIC/QFN-S • 44-pin TQFP/QFN Note: Preliminary See the device variant tables for exact peripheral features per device. 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 PRODUCT FAMILIES The device names, pin counts, memory sizes, and peripheral availability of each device are listed below. The following pages show their pinout diagrams. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families Program Flash Memory (Kbyte) RAM (Kbyte)(1) Remappable Pins 16-bit Timer(2) Input Capture Output Compare Standard PWM Data Converter Interface UART SPI ECAN™ External Interrupts(3) RTCC I2C™ CRC Generator 10-bit/12-bit ADC (Channels) 16-bit Audio DAC (Pins) Analog Comparator (2 Channels/Voltage Regulator) I/O Pins Packages dsPIC33FJ128GP804 44 128 16 26 5 4 4 1 2 2 1 3 1 1 1 13 6 1/1 11 35 QFN TQFP dsPIC33FJ128GP802 28 128 16 16 5 4 4 1 2 2 1 3 1 1 1 10 4 1/0 2 21 SDIP SOIC QFN-S dsPIC33FJ128GP204 44 128 8 26 5 4 4 1 2 2 0 3 1 1 1 13 0 1/1 11 35 QFN TQFP dsPIC33FJ128GP202 28 128 8 16 5 4 4 1 2 2 0 3 1 1 1 10 0 1/0 2 21 SDIP SOIC QFN-S dsPIC33FJ64GP804 44 64 16 26 5 4 4 1 2 2 1 3 1 1 1 13 6 1/1 11 35 QFN TQFP dsPIC33FJ64GP802 28 64 16 16 5 4 4 1 2 2 1 3 1 1 1 10 4 1/0 2 21 SDIP SOIC QFN-S dsPIC33FJ64GP204 44 64 8 26 5 4 4 1 2 2 0 3 1 1 1 13 0 1/1 11 35 QFN TQFP dsPIC33FJ64GP202 28 64 8 16 5 4 4 1 2 2 0 3 1 1 1 10 0 1/0 2 21 SDIP SOIC QFN-S dsPIC33FJ32GP304 44 32 4 26 5 4 4 1 2 2 0 3 1 1 1 13 0 1/1 11 35 QFN TQFP dsPIC33FJ32GP302 28 32 4 16 5 4 4 1 2 2 0 3 1 1 1 10 0 1/0 2 21 Note 1: 2: 3: 8-bit Parallel Master Port (Address Lines) Device Pins Remappable Peripheral SDIP SOIC QFN-S RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except dsPIC33FJ32GP302/304, which include 1 Kbyte of DMA RAM. Only four out of five timers are remappable. Only two out of three interrupts are remappable. 2009 Microchip Technology Inc. Preliminary DS70292D-page 5 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams 28-Pin SDIP, SOIC = Pins are up to 5V tolerant 1 28 AVDD 2 27 AVSS AN1/VREF-/CN3/RA1 3 26 AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 4 25 AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14 24 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13 (1) PGEC1/ AN3/C2IN+/RP1 /CN5/RB1 (1) AN4/C1IN-/RP2 /CN6/RB2 5 6 AN5/C1IN+/RP3(1)/CN7/RB3 7 VSS 8 OSC1/CLKI/CN30/RA2 9 dsPIC33FJ64GP802 dsPIC33FJ128GP802 MCLR AN0/VREF+/CN2/RA0 23 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12 22 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11 21 PGED2/TDI/RP10(1)/CN16/PMD2/RB10 20 VCAP/VDDCORE 19 VSS 18 TDO/SDA1/RP9(1)/CN21/PMD3/RB9 17 TCK/SCL1/RP8(1)/CN22/PMD4/RB8 13 16 INT0/RP7(1)/CN23/PMD5/RB7 14 15 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 OSC2/CLKO/CN29/PMA0/RA3 10 SOSCI/RP4(1)/CN1/PMBE/RB4 11 SOSCO/T1CK/CN0/PMA1/RA4 12 VDD PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 28-Pin SDIP, SOIC = Pins are up to 5V tolerant 1 28 AVDD 2 27 AVSS AN1/VREF-/CN3/RA1 3 26 AN9/RP15(1)/CN11/PMCS1/RB15 25 AN10/RTCC/RP14(1)/CN12/PMWR/RB14 24 AN11/RP13(1)/CN13/PMRD/RB13 23 AN12/RP12(1)/CN14/PMD0/RB12 22 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11 21 PGED2/TDI/RP10(1)/CN16/PMD2/RB10 20 VCAP/VDDCORE PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 4 PGEC1/ AN3/C2IN+/RP1(1)/CN5/RB1 5 AN4/C1IN-/RP2(1)/CN6/RB2 6 (1) AN5/C1IN+/RP3 /CN7/RB3 7 VSS 8 OSC1/CLKI/CN30/RA2 9 Note 1: DS70292D-page 6 19 VSS 18 TDO/SDA1/RP9(1)/CN21/PMD3/RB9 12 17 TCK/SCL1/RP8(1)/CN22/PMD4/RB8 13 16 INT0/RP7(1)/CN23/PMD5/RB7 14 15 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 OSC2/CLKO/CN29/PMA0/RA3 10 SOSCI/RP4(1)/CN1/PMBE/RB4 11 SOSCO/T1CK/CN0/PMA1/RA4 VDD (1)/CN27/PMD7/RB5 PGED3/ASDA1/RP5 dsPIC33FJ32GP302 dsPIC33FJ64GP202 dsPIC33FJ128GP202 MCLR AN0/VREF+/CN2/RA0 The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 28-Pin QFN-S(2) AVDD AVSS AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15 AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14 24 23 22 28 27 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR 26 25 = Pins are up to 5V tolerant PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 1 21 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 2 20 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12 AN4/C1IN-/RP2(1)/CN6/RB2 5 17 VCAP/VDDCORE OSC1/CLKI/CN30/RA2 6 16 VSS OSC2/CLKO/CN29/PMA0/RA3 7 15 TDO/SDA1/RP9(1)/CN21/PMD3/RB9 14 8 PGED2/TDI/RP10(1)/CN16/PMD2/RB10 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 TCK/SCL1/RP8(1)/CN22/PMD4/RB8 PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 SOSCO/T1CK/CN0/PMA1/RA4 VDD SOSCI/RP4(1)/CN1/PMBE/RB4 Note 12 13 VSS AN5/C1IN+/RP3 /CN7/RB3 10 11 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11 9 3 dsPIC33FJ64GP802 19 4 dsPIC33FJ128GP802 18 (1) 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 2009 Microchip Technology Inc. Preliminary DS70292D-page 7 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 28-Pin QFN-S(2) AVDD AVSS AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15 AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14 24 23 22 28 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 (1) PGEC1/AN3/C2IN+/RP1 /CN5/RB1 1 21 AN11/RP13(1)/CN13/PMRD/RB13 2 20 AN12/RP12(1)/CN14/PMD0/RB12 PGED2/TDI/RP10(1)/CN16/PMD2/RB10 OSC1/CLKI/CN30/RA2 6 16 VSS OSC2/CLKO/CN29/PMA0/RA3 7 15 TDO/SDA1/RP9(1)/CN21/PMD3/RB9 14 VCAP/VDDCORE PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 TCK/SCL1/RP8(1)/CN22/PMD4/RB8 PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 SOSCI/RP4(1)/CN1/PMBE/RB4 8 VSS SOSCO/T1CK/CN0/PMA1/RA4 VDD AN5/C1IN+/RP3 /CN7/RB3 12 13 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11 4 dsPIC33FJ64GP202 18 5 dsPIC33FJ128GP202 17 10 11 3 dsPIC33FJ32GP302 19 (1) 9 (1) AN4/C1IN-/RP2 /CN6/RB2 Note 27 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR 26 25 = Pins are up to 5V tolerant 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70292D-page 8 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) AN4/C1IN-/RP2(1)/CN6/RB2 (1) 23 22 21 20 19 18 17 16 15 14 13 12 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15 AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14 TCK/PMA7/RA7 TMS/PMA10/RA10 = Pins are up to 5V tolerant 11 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13 AN5/C1IN+/RP3 /CN7/RB3 24 10 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12 AN6/DAC1RM/RP16(1)/CN8/RC0 25 9 PGEC2/RP11 (1)/CN15/PMD1/RB11 AN7/DAC1LM/RP17(1)/CN9/RC1 26 8 PGED2/RP10(1)/CN16/PMD2/RB10 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 27 VDD 28 VSS 29 dsPIC33FJ64GP804 dsPIC33FJ128GP804 7 VCAP/VDDCORE 6 VSS 5 RP25(1)/CN19/PMA6/RC9 30 4 RP24(1)/CN20/PMA5/RC8 31 3 RP23(1)/CN17/PMA0/RC7 TDO/PMA8/RA8 32 2 RP22(1)/CN18/PMA1/RC6 SOSCI/RP4(1)/CN1/RB4 33 1 SDA1/RP9(1)/CN21/PMD3/RB9 SOSCO/T1CK/CN0/RA4 TDI/PMA9/RA9 RP19(1)/CN28/PMBE/RC3 RP20(1)/CN25/PMA4/RC4 RP21(1)/CN26/PMA3/RC5 VSS VDD (1) PGED3/ASDA1/RP5 /CN27/PMD7/RB5 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 SCL1/RP8(1)/CN22/PMD4/RB8 34 35 36 37 38 39 40 41 42 43 44 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. 2009 Microchip Technology Inc. Preliminary DS70292D-page 9 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15(1)/CN11/PMCS1/RB15 AN10/RTCC/RP14(1)/CN12/PMWR/RB14 TCK/PMA7/RA7 TMS/PMA10/RA10 = Pins are up to 5V tolerant AN11/RP13(1)/CN13/PMRD/RB13 23 24 10 AN12/RP12(1)/CN14/PMD0/RB12 AN6/RP16(1)/CN8/RC0 25 9 PGEC2/RP11 (1)/CN15/PMD1/RB11 8 PGED2/RP10(1)/CN16/PMD2/RB10 AN7/RP17(1)/CN9/RC1 26 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 27 VDD 28 22 21 20 19 18 17 16 15 14 13 12 AN4/C1IN-/RP2(1)/CN6/RB2 AN5/C1IN+/RP3(1)/CN7/RB3 dsPIC33FJ32GP304 dsPIC33FJ64GP204 dsPIC33FJ128GP204 11 7 VCAP/VDDCORE 6 VSS 29 5 RP25(1)/CN19/PMA6/RC9 30 4 RP24(1)/CN20/PMA5/RC8 OSC2/CLKO/CN29/RA3 31 3 RP23(1)/CN17/PMA0/RC7 TDO/PMA8/RA8 32 2 RP22(1)/CN18/PMA1/RC6 SOSCI/RP4(1)/CN1/RB4 33 1 SDA1/RP9(1)/CN21/PMD3/RB9 SOSCO/T1CK/CN0/RA4 TDI/PMA9/RA9 RP19(1)/CN28/PMBE/RC3 RP20(1)/CN25/PMA4/RC4 RP21(1)/CN26/PMA3/RC5 VSS VDD PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 SCL1/RP8(1)/CN22/PMD4/RB8 34 35 36 37 38 39 40 41 42 43 44 VSS OSC1/CLKI/CN30/RA2 Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70292D-page 10 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagram 44-Pin TQFP 11 10 9 8 dsPIC33FJ64GP804 7 6 dsPIC33FJ128GP804 5 4 3 2 1 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12 PGEC2/RP11(1)/CN15/PMD1/RB11 PGED2/EMCD2/RP10(1)/CN16/PMD2/RB10 VCAP/VDDCORE VSS RP25(1)/CN19/PMA6/RC9 RP24(1)/CN20/PMA5/RC8 RP23(1)/CN17/PMA0/RC7 RP22(1)/CN18/PMA1/RC6 SDA1/RP9(1)/CN21/PMD3/RB9 34 35 36 37 38 39 40 41 42 43 44 23 24 25 26 27 28 29 30 31 32 33 SOSCO/T1CK/CN0/RA4 TDI/PMA9/RA9 RP19(1)/CN28/PMBE/RC3 (1) RP20 /CN25/PMA4/RC4 RP21(1)/CN26/PMA3/RC5 VSS VDD (1) PGED3/ASDA1/RP5 /CN27/PMD7/RB5 PGEC2/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 SCL1/RP8(1)/CN22/PMD4/RB8 AN4/C1IN-/RP2(1)/CN6/RB2 AN5/C1IN+/RP3(1)/CN7/RB3 AN6/DAC1RM/RP16(1)/CN8/RC0 AN7/DAC1LM/RP17/(1)/CN9/RC1 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 VDD VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 SOSCI/RP4(1)/CN1/RB4 22 21 20 19 18 17 16 15 14 13 12 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15 AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14 TCK/PMA7/RA7 TMS/PMA10/RA10 = Pins are up to 5V tolerant Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. 2009 Microchip Technology Inc. Preliminary DS70292D-page 11 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagram 44-Pin TQFP 11 10 9 8 dsPIC33FJ32GP304 7 dsPIC33FJ64GP204 6 5 dsPIC33FJ128GP204 4 3 2 1 AN11/RP13(1)/CN13/PMRD/RB13 AN12/RP12(1)/CN14/PMD0/RB12 PGEC2/RP11(1)/CN15/PMD1/RB11 PGED2/EMCD2/RP10(1)/CN16/PMD2/RB10 VCAP/VDDCORE VSS RP25(1)/CN19/PMA6/RC9 RP24(1)/CN20/PMA5/RC8 RP23(1)/CN17/PMA0/RC7 RP22(1)/CN18/PMA1/RC6 SDA1/RP9(1)/CN21/PMD3/RB9 34 35 36 37 38 39 40 41 42 43 44 23 24 25 26 27 28 29 30 31 32 33 SOSCO/T1CK/CN0/RA4 TDI/PMA9/RA9 RP19(1)/CN28/PMBE/RC3 (1) RP20 /CN25/PMA4/RC4 RP21(1)/CN26/PMA3/RC5 VSS VDD PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 SCL1/RP8(1)/CN22/PMD4/RB8 AN4/C1IN-/RP2(1)/CN6/RB2 AN5/C1IN+/RP3(1)/CN7/RB3 AN6/RP16(1)/CN8/RC0 AN7/RP17(1)/CN9/RC1 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 VDD VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 SOSCI/RP4(1)/CN1/RB4 22 21 20 19 18 17 16 15 14 13 12 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15(1)/CN11/PMCS1/RB15 AN10/RTCC/RP14(1)/CN12/PMWR/RB14 TCK/PMA7/RA7 TMS/PMA10/RA10 = Pins are up to 5V tolerant Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. DS70292D-page 12 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Table of Contents dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Product Families............................................. 5 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 21 3.0 CPU............................................................................................................................................................................................ 25 4.0 Memory Organization ................................................................................................................................................................. 37 5.0 Flash Program Memory.............................................................................................................................................................. 73 6.0 Resets ....................................................................................................................................................................................... 79 7.0 Interrupt Controller ..................................................................................................................................................................... 87 8.0 Direct Memory Access (DMA) .................................................................................................................................................. 129 9.0 Oscillator Configuration ............................................................................................................................................................ 141 10.0 Power-Saving Features............................................................................................................................................................ 153 11.0 I/O Ports ................................................................................................................................................................................... 159 12.0 Timer1 ...................................................................................................................................................................................... 187 13.0 Timer2/3 and Timer4/5 feature ................................................................................................................................................ 189 14.0 Input Capture............................................................................................................................................................................ 195 15.0 Output Compare....................................................................................................................................................................... 197 16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 201 17.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 207 18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 215 19.0 Enhanced CAN (ECAN™) Module........................................................................................................................................... 221 20.0 Data Converter Interface (DCI) Module.................................................................................................................................... 247 21.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 253 22.0 Audio Digital-to-Analog Converter (DAC)................................................................................................................................. 265 23.0 Comparator Module.................................................................................................................................................................. 271 24.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 277 25.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 287 26.0 Parallel Master Port (PMP)....................................................................................................................................................... 291 27.0 Special Features ...................................................................................................................................................................... 299 28.0 Instruction Set Summary .......................................................................................................................................................... 309 29.0 Development Support............................................................................................................................................................... 317 30.0 Electrical Characteristics .......................................................................................................................................................... 321 31.0 High Temperature Electrical Characteristics ............................................................................................................................ 367 32.0 Packaging Information.............................................................................................................................................................. 377 Appendix A: Revision History............................................................................................................................................................. 387 Index .................................................................................................................................................................................................. 393 The Microchip Web Site ..................................................................................................................................................................... 399 Customer Change Notification Service .............................................................................................................................................. 399 Customer Support .............................................................................................................................................................................. 399 Reader Response .............................................................................................................................................................................. 400 Product Identification System ............................................................................................................................................................ 401 2009 Microchip Technology Inc. Preliminary DS70292D-page 13 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products. DS70292D-page 14 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 1.0 DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. This document contains device specific information for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 Digital Signal Controller (DSC) Devices. The dsPIC33F devices contain extensive Digital Signal Processor (DSP) functionality with a high performance 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 2009 Microchip Technology Inc. Preliminary DS70292D-page 15 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 1-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller PORTA 16 8 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch DMA RAM 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 PORTB 16 DMA 23 16 Controller 16 PORTC Address Generator Units Address Latch Remappable Program Memory Pins EA MUX Data Latch ROM Latch 24 Instruction Decode and Control Control Signals to Various Blocks OSC2/CLKO OSC1/CLKI 16 Divide Support 16 x 16 W Register Array 16 Oscillator Start-up Timer FRC/LPRC Oscillators Power-on Reset Precision Band Gap Reference 16-bit ALU Watchdog Timer 16 Brown-out Reset Voltage Regulator VCAP/VDDCORE Note: 16 DSP Engine Power-up Timer Timing Generation Instruction Reg Literal Data 16 VDD, VSS MCLR PMP/ EPSP Comparator 2 Ch. ECAN1 Timers 1-5 UART1, 2 ADC1 OC/ PWM1-4 RTCC DAC1 SPI1, 2 IC1, 2, 7, 8 CNx I2C1 DCI Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. DS70292D-page 16 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type AN0-AN12 I Analog CLKI I ST/CMOS No CLKO O — No OSC1 I ST/CMOS No OSC2 I/O — No SOSCI SOSCO I O ST/CMOS — No No 32.768 kHz low-power oscillator crystal input; CMOS otherwise. 32.768 kHz low-power oscillator crystal output. CN0-CN30 I ST No No Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. IC1-IC2 IC7-IC8 I I ST ST Yes Yes Capture inputs 1/2. Capture inputs 7/8. OCFA OC1-OC4 I O ST — Yes Yes Compare Fault A input (for Compare Channels 1, 2, 3 and 4). Compare outputs 1 through 4. INT0 INT1 INT2 I I I ST ST ST No Yes Yes External interrupt 0. External interrupt 1. External interrupt 2. RA0-RA4 RA7-RA10 I/O I/O ST ST No No PORTA is a bidirectional I/O port. PORTA is a bidirectional I/O port. RB0-RB15 I/O ST No PORTB is a bidirectional I/O port. RC0-RC9 I/O ST No PORTC is a bidirectional I/O port. T1CK T2CK T3CK T4CK T5CK I I I I I ST ST ST ST ST No Yes Yes Yes Yes Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. U1CTS U1RTS U1RX U1TX I O I O ST — ST — Yes Yes Yes Yes UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. U2CTS U2RTS U2RX U2TX I O I O ST — ST — Yes Yes Yes Yes UART2 clear to send. UART2 ready to send. UART2 receive. UART2 transmit. SCK1 SDI1 SDO1 SS1 I/O I O I/O ST ST — ST Yes Yes Yes Yes Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. SCK2 SDI2 SDO2 SS2 I/O I O I/O ST ST — ST Yes Yes Yes Yes Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out. SPI2 slave synchronization or frame pulse I/O. Pin Name PPS Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer 2009 Microchip Technology Inc. Analog = Analog input P = Power O = Output I = Input PPS = Peripheral Pin Select Preliminary DS70292D-page 17 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PPS SCL1 SDA1 ASCL1 ASDA1 I/O I/O I/O I/O ST ST ST ST No No No No Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Alternate synchronous serial clock input/output for I2C1. Alternate synchronous serial data input/output for I2C1. TMS TCK TDI TDO I I I O ST ST ST — No No No No JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. C1RX C1TX I O ST — Yes Yes ECAN1 bus receive pin. ECAN1 bus transmit pin. Pin Name Description RTCC O — No Real-Time Clock Alarm Output. CVREF O ANA No Comparator Voltage Reference Output. C1INC1IN+ C1OUT I I O ANA ANA — No No Yes Comparator 1 Negative Input. Comparator 1 Positive Input. Comparator 1 Output. C2INC2IN+ C2OUT I I O ANA ANA — No No Yes Comparator 2 Negative Input. Comparator 2 Positive Input. Comparator 2 Output. PMA0 I/O TTL/ST No PMA1 I/O TTL/ST No PMA2 -PMPA10 PMBE PMCS1 PMD0-PMPD7 O O O I/O — — — TTL/ST No No No No PMRD PMWR O O — — No No Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address (Demultiplexed Master Modes). Parallel Master Port Byte Enable Strobe. Parallel Master Port Chip Select 1 Strobe. Parallel Master Port Data (Demultiplexed Master mode) or Address/ Data (Multiplexed Master modes). Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. DAC1RN DAC1RP DAC1RM O O O — — — No No No DAC1 Right Channel Negative Output. DAC1 Right Channel Positive Output. DAC1 Right Channel Middle Point Value (typically 1.65V). DAC1LN DAC1LP DAC1LM O O O — — — No No No DAC1 Left Channel Negative Output. DAC1 Left Channel Positive Output. DAC1 Left Channel Middle Point Value (typically 1.65V). COFS I/O ST Yes Data Converter Interface frame synchronization pin. CSCK I/O ST Yes Data Converter Interface serial clock input/output pin. CSDI I ST Yes Data Converter Interface serial data input pin CSDO O — Yes Data Converter Interface serial data output pin. PGWD1 PGEC1 PGWD2 PGEC2 PGWD3 PGEC3 I/O I I/O I I/O I ST ST ST ST ST ST No No No No No No Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3. MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device. AVDD P P No Positive supply for analog modules. This pin must be connected at all times. Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer DS70292D-page 18 Analog = Analog input P = Power O = Output I = Input PPS = Peripheral Pin Select Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PPS AVSS P P No Ground reference for analog modules. VDD P — No Positive supply for peripheral logic and I/O pins. VCAP/VDDCORE P — No CPU logic filter capacitor connection. Vss P — No Ground reference for logic and I/O pins. VREF+ I Analog No Analog voltage reference (high) input. VREF- I Analog No Analog voltage reference (low) input. Pin Name Description Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer 2009 Microchip Technology Inc. Analog = Analog input P = Power O = Output I = Input PPS = Peripheral Pin Select Preliminary DS70292D-page 19 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 20 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS 2.2 The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 2.1 Decoupling Capacitors Basic Connection Requirements Getting started with the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 family of 16-bit Digital Signal Controllers (DSCs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All VDD and VSS pins (see Section 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins (regardless if ADC module is not used) (see Section 2.2 “Decoupling Capacitors”) • VCAP/VDDCORE (see Section 2.3 “Capacitor on Internal Voltage Regulator (VCAP/VDDCORE)”) • MCLR pin (see Section 2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator Pins”) Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: Recommendation of 0.1 µF (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. • Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of the ADC voltage reference source. 2009 Microchip Technology Inc. Preliminary DS70292D-page 21 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic R1 MCLR C 10 2.2.1 VDD 0.1 µF Ceramic VSS VSS AVSS VDD AVDD 0.1 µF Ceramic VDD The MCLR pin provides for two specific device functions: During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. dsPIC33F VSS Master Clear (MCLR) Pin • Device Reset • Device programming and debugging VSS R VDD VCAP/VDDCORE VDD 2.4 0.1 µF Ceramic 0.1 µF Ceramic For example, as shown in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. FIGURE 2-2: TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF. 2.3 Capacitor on Internal Voltage Regulator (VCAP/VDDCORE) EXAMPLE OF MCLR PIN CONNECTIONS VDD R R1 MCLR JP dsPIC33F C Note 1: R 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R1 470 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. A low-ESR (< 5 Ohms) capacitor is required on the VCAP/VDDCORE pin, which is used to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD, and must have a capacitor between 4.7 µF and 10 µF, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section 30.0 “Electrical Characteristics” for additional information. The placement of this capacitor should be close to the VCAP/VDDCORE. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 27.2 “On-Chip Voltage Regulator” for details. DS70292D-page 22 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2.5 ICSP Pins 2.6 The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes, and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™. Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3. FIGURE 2-3: For more information on ICD 2, ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip website. • “MPLAB® ICD 2 In-Circuit Debugger User’s Guide” DS51331 • “Using MPLAB® ICD 2” (poster) DS51265 • “MPLAB® ICD 2 Design Advisory” DS51566 • “Using MPLAB® ICD 3 In-Circuit Debugger” (poster) DS51765 • “MPLAB® ICD 3 Design Advisory” DS51764 • “MPLAB® REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 • “Using MPLAB® REAL ICE™” (poster) DS51749 2009 Microchip Technology Inc. External Oscillator Pins Preliminary SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Main Oscillator 13 Guard Ring 14 15 Guard Trace Secondary Oscillator 16 17 18 19 20 DS70292D-page 23 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < FIN < 8 MHz to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed. Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration word. 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins, by setting all bits in the AD1PCFGL register. The bits in this register that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3 or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFGL register during initialization of the ADC module. When MPLAB ICD 2, ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the AD1PCFGL register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect a 1k to 10k resistor to VSS on unused pins and drive the output to logic low. DS70292D-page 24 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.0 CPU Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 2. CPU” (DS70204) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 3.1 Overview The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any time. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. There are two classes of instruction in the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices: MCU and DSP. These two instruction classes are seamlessly integrated into a single CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction 2009 Microchip Technology Inc. cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 3-1, and the programmer’s model for the dsPIC33FJ32GP302/ 304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 is shown in Figure 3-2. 3.2 Data Addressing Overview The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific. Overhead-free circular buffers (Modulo Addressing mode) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program-to-data-space mapping feature lets any instruction access program space as if it were data space. 3.3 DSP Engine Overview The DSP engine features a high-speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is capable of shifting a 40-bit value up to 16 bits right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal realtime performance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers and accumulating and optionally saturating the result in the same cycle. This instruction functionality requires that the RAM data space be split for these instructions and linear for all others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space. Preliminary DS70292D-page 25 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.4 Special MCU Features The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 features a 17-bit by 17-bit single-cycle multiplier that is shared by both the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0). FIGURE 3-1: A 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 8 16 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch DMA 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic RAM 16 23 16 16 DMA Controller Address Generator Units Address Latch Program Memory EA MUX Data Latch ROM Latch 24 Instruction Reg 16 Literal Data Instruction Decode and Control 16 Control Signals to Various Blocks 16 DSP Engine Divide Support 16 x 16 W Register Array 16 16-bit ALU 16 To Peripheral Modules DS70292D-page 26 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 3-2: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand Registers W5 W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD39 Stack Pointer Limit Register AD15 AD31 AD0 ACCA DSP Accumulators ACCB PC22 PC0 Program Counter 0 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address DOEND DO Loop End Address 22 15 0 Core Configuration Register CORCON OA OB SA SB OAB SAB DA SRH 2009 Microchip Technology Inc. DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRL Preliminary DS70292D-page 27 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.5 CPU Control Registers REGISTER 3-1: R-0 OA SR: CPU STATUS REGISTER R-0 R/C-0 R/C-0 OB SA(1) (1) SB R-0 OAB R/C-0 (4) SAB R -0 R/W-0 DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) (2) IPL<2:0> R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OA: Accumulator A Overflow Status bit 1 = Accumulator A overflowed 0 = Accumulator A has not overflowed bit 14 OB: Accumulator B Overflow Status bit 1 = Accumulator B overflowed 0 = Accumulator B has not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed bit 10 SAB: SA || SB Combined Accumulator (Sticky) Status bit(4) 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated bit 9 DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1. 3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). 4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB. DS70292D-page 28 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (two’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: This bit can be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1. 3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). 4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB. 2009 Microchip Technology Inc. Preliminary DS70292D-page 29 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 — bit 15 U-0 — R/W-0 SATA bit 7 R/W-0 SATB bit 11 bit 10-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 R/W-0 US R/W-0 EDT(1) R-0 R-0 DL<2:0> R-0 bit 8 Legend: R = Readable bit 0’ = Bit is cleared bit 15-13 bit 12 U-0 — R/W-1 SATDW R/W-0 ACCSAT C = Clear only bit W = Writable bit ‘x = Bit is unknown R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ Unimplemented: Read as ‘0’ US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed EDT: Early DO Loop Termination Control bit(1) 1 = Terminate executing DO loop at end of current loop iteration 0 = No effect DL<2:0>: DO Loop Nesting Level Status bits 111 = 7 DO loops active • • • 001 = 1 DO loop active 000 = 0 DO loops active SATA: ACCA Saturation Enable bit 1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled SATB: ACCB Saturation Enable bit 1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation enabled 0 = Data space write saturation disabled ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space Note 1: This bit is always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70292D-page 30 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 3-2: bit 1 bit 0 CORCON: CORE CONTROL REGISTER (CONTINUED) RND: Rounding Mode Select bit 1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note 1: This bit is always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. 2009 Microchip Technology Inc. Preliminary DS70292D-page 31 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.6 3.6.2 Arithmetic Logic Unit (ALU) The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are two’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. Refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157) for information on the SR bits affected by each instruction. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division. 3.6.1 MULTIPLIER Using the high-speed 17-bit x 17-bit multiplier of the DSP engine, the ALU supports unsigned, signed or mixed-sign operation in several MCU multiplication modes: • • • • • • • 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 3.7 DSP Engine The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic). The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources can be used concurrently by the same instruction (e.g., ED, EDAC). The DSP engine can also perform inherent accumulator-to-accumulator operations that require no additional data. These instructions are ADD, SUB and NEG. The DSP engine has options selected through bits in the CPU Core Control register (CORCON), as listed below: • • • • • • Fractional or integer DSP multiply (IF) Signed or unsigned DSP multiply (US) Conventional or convergent rounding (RND) Automatic saturation on/off for ACCA (SATA) Automatic saturation on/off for ACCB (SATB) Automatic saturation on/off for writes to data memory (SATDW) • Accumulator Saturation mode selection (ACCSAT) A block diagram of the DSP engine is shown in Figure 3-3. DS70292D-page 32 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 3-1: DSP INSTRUCTIONS SUMMARY Instruction Algebraic Operation CLR A=0 ED EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC A = (x – y)2 A = A + (x – y)2 A = A + (x • y) A = A + x2 No change in A A=x•y A=x2 A=–x•y A=A–x•y FIGURE 3-3: ACC Write Back Yes No No Yes No Yes No No No Yes DSP ENGINE BLOCK DIAGRAM 40 40-bit Accumulator A 40-bit Accumulator B 40 Carry/Borrow Out Saturate Carry/Borrow In S a Round t 16 u Logic r a t e Adder Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array 2009 Microchip Technology Inc. Preliminary DS70292D-page 33 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.7.1 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value that is sign-extended to 40 bits. Integer data is inherently represented as a signed two’s complement value, where the Most Significant bit (MSb) is defined as a sign bit. The range of an N-bit two’s complement integer is -2N-1 to 2N-1 – 1. • For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including 0. • For a 32-bit integer, the data range is 2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7FFF FFFF). The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations. The MUL instruction can be directed to use byte or word-sized operands. Byte operands direct a 16-bit result, and word operands direct a 32-bit result to the specified registers in the W array. DATA ACCUMULATORS AND ADDER/SUBTRACTER The data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. 3.7.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. • In the case of addition, the Carry/Borrow input is active-high and the other input is true data (not complemented). • In the case of subtraction, the Carry/Borrow input is active-low and the other input is complemented. DS70292D-page 34 • Overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. • Overflow into guard bits 32 through 39: this is a recoverable overflow. This bit is set whenever all the guard bits are not identical to each other. The adder has an additional saturation block that controls accumulator data saturation, if selected. It uses the result of the adder, the Overflow Status bits described previously and the SAT<A:B> (CORCON<7:6>) and ACCSAT (CORCON<4>) mode control bits to determine when and to what value to saturate. Six STATUS register bits support saturation and overflow: When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement fraction, where the MSb is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1 – 21-N). For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0 and has a precision of 3.01518x10-5. In Fractional mode, the 16 x 16 multiply operation generates a 1.31 product that has a precision of 4.65661 x 10-10. 3.7.2 The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register: • OA: ACCA overflowed into guard bits • OB: ACCB overflowed into guard bits • SA: ACCA saturated (bit 31 overflow and saturation) or ACCA overflowed into guard bits and saturated (bit 39 overflow and saturation) • SB: ACCB saturated (bit 31 overflow and saturation) or ACCB overflowed into guard bits and saturated (bit 39 overflow and saturation) • OAB: Logical OR of OA and OB • SAB: Logical OR of SA and SB The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding Overflow Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1 register are set (refer to Section 7.0 “Interrupt Controller”). This allows the user application to take immediate action, for example, to correct system gain. The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and is saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, the SA and SB bits generate an arithmetic warning trap when saturation is disabled. Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 The Overflow and Saturation Status bits can optionally be viewed in the STATUS Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). Programmers can check one bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This is useful for complex number arithmetic, which typically uses both accumulators. The device supports three Saturation and Overflow modes: • Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. This condition is referred to as ‘super saturation’ and provides protection against erroneous data or unexpected algorithm problems (such as gain calculations). • Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. When this Saturation mode is in effect, the guard bits are not used, so the OA, OB or OAB bits are never set. • Bit 39 Catastrophic Overflow: The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remains set until cleared by the user application. No saturation operation is performed, and the accumulator is allowed to overflow, destroying its sign. If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. 3.7.3 ACCUMULATOR ‘WRITE BACK’ The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported: 3.7.3.1 Round Logic The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word is simply discarded. Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through 31 of the accumulator). • If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. • If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding operations, the value tends to be biased slightly positive. Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. In this case, the Least Significant bit (bit 16 of the accumulator) of ACCxH is examined: • If it is ‘1’, ACCxH is incremented. • If it is ‘0’, ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate. The SAC and SAC.R instructions store either a truncated (SAC), or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus, subject to data saturation (see Section 3.7.3.2 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator writeback operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. • W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction. • [W13] + = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write). 2009 Microchip Technology Inc. Preliminary DS70292D-page 35 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.7.3.2 Data Space Write Saturation 3.7.4 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These inputs are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. The barrel shifter can perform up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators or the X bus (to support multi-bit shifts of register or memory data). If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly: The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts. • For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. • For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. DS70292D-page 36 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.0 MEMORY ORGANIZATION Note: 4.1 This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 3. Data Memory” (DS70202) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution. User Memory Space FIGURE 4-1: Program Address Space The program address memory space of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4.6 “Interfacing Program and Data Memory Spaces”. User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory map for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 devices is shown in Figure 4-1. PROGRAM MEMORY MAP FOR dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, AND dsPIC33FJ128GPX02/X04 DEVICES dsPIC33FJ32GP302/304 dsPIC33FJ64GPX02/X04 dsPIC33FJ128GPX02/X04 GOTO Instruction Reset Address Interrupt Vector Table Reserved GOTO Instruction Reset Address Interrupt Vector Table Reserved GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table Alternate Vector Table Alternate Vector Table User Program Flash Memory (11264 instructions) User Program Flash Memory (22016 instructions) User Program Flash Memory (44032 instructions) 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 0x0057FE 0x005800 0x00ABFE 0x00AC00 Unimplemented (Read ‘0’s) Unimplemented 0x0157FE 0x015800 (Read ‘0’s) Unimplemented (Read ‘0’s) Configuration Memory Space 0x7FFFFE 0x800000 Reserved Reserved Reserved Device Configuration Registers Device Configuration Registers Device Configuration Registers Reserved Reserved Reserved DEVID (2) DEVID (2) DEVID (2) Reserved Reserved Reserved 0xF7FFFE 0xF80000 0xF80017 0xF80018 0xFEFFFE 0xFF0000 0xFF0002 0xFFFFFE Note: Memory areas are not shown to scale. 2009 Microchip Technology Inc. Preliminary DS70292D-page 37 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 4-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. FIGURE 4-2: msw Address least significant word most significant word 16 8 PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) DS70292D-page 38 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector Table”. PROGRAM MEMORY ORGANIZATION 23 0x000001 0x000003 0x000005 0x000007 INTERRUPT AND TRAP VECTORS Instruction Width Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.2 Data Address Space The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 CPU has a separate 16-bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-4. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility area (see Section 4.6.3 “Reading Data from Program Memory Using Program Space Visibility”). dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices implement up to 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte is returned. 4.2.1 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC® MCU devices and improve data space memory usage efficiency, the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] results in a value of Ws + 1 for byte operations and Ws + 2 for word operations. A data byte read, reads the complete word that contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address. 2009 Microchip Technology Inc. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. 4.2.3 DATA SPACE WIDTH The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. 4.2.2 All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the error occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault. SFR SPACE The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. Note: 4.2.4 The actual set of peripheral features and interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information. NEAR DATA SPACE The 8 Kbyte area between 0x0000 and 0x1FFF is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an address pointer. Preliminary DS70292D-page 39 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ32GP302/304 DEVICES WITH 4 KB RAM MSB Address MSB 2 Kbyte SFR Space LSB Address 16 bits LSB 0x0000 0x0000 SFR Space 0x07FF 0x0801 0x07FE 0x0800 X Data RAM (X) 0x0FFE 0x1000 0x0FFF 0x1001 4 Kbyte SRAM Space Y Data RAM (Y) 0x13FE 0x1400 0x13FF 0x1401 DMA RAM 0x17FF 0x1801 0x17FE 0x1800 0x8001 0x8000 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF DS70292D-page 40 6 Kbyte Near Data Space 0xFFFE Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJ128GP202/204 AND dsPIC33FJ64GP202/ 204 DEVICES WITH 8 KB RAM MSB Address MSB 2 Kbyte SFR Space LSB Address 16 bits LSB 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8 Kbyte Near Data Space X Data RAM (X) 8 Kbyte SRAM Space 0x17FF 0x1801 0x17FE 0x1800 Y Data RAM (Y) 0x1FFF 0x2001 0x27FF 0x2801 0x1FFE 0x2000 DMA RAM 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFE 0xFFFF 2009 Microchip Technology Inc. 0x27FE 0x2800 Preliminary DS70292D-page 41 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/ 804 DEVICES WITH 16 KB RAM MSB Address 16 bits MSB 2 Kbyte SFR Space LSB Address LSB 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 X Data RAM (X) 16 Kbyte SRAM Space 0x1FFF 0x1FFE 0x27FF 0x2801 0x27FE 0x2800 8 Kbyte Near Data Space Y Data RAM (Y) 0x3FFF 0x4001 0x47FF 0x4801 0x3FFE 0x4000 DMA RAM 0x8001 0x47FE 0x4800 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70292D-page 42 0xFFFE Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.2.5 X AND Y DATA SPACES 4.2.6 The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. This feature allows certain instructions to concurrently fetch two words from RAM, thereby enabling efficient execution of DSP algorithms such as Finite Impulse Response (FIR) filtering and Fast Fourier Transform (FFT). The X data space is used by all instructions and supports all addressing modes. X data space has separate read and write data buses. The X read data bus is the read data path for all instructions that view data space as combined X and Y address space. It is also the X data prefetch path for the dual operand DSP instructions (MAC class). The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. DMA RAM Every dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 device contains up to 2 Kbytes of dual ported DMA RAM located at the end of Y data space, and is part of Y data space. Memory locations in the DMA RAM space are accessible simultaneously by the CPU and the DMA controller module. DMA RAM is utilized by the DMA controller to store data to be transferred to various peripherals using DMA, as well as data transferred from various peripherals using DMA. The DMA RAM can be accessed by the DMA controller without having to steal cycles from the CPU. When the CPU and the DMA controller attempt to concurrently write to the same DMA RAM location, the hardware ensures that the CPU is given precedence in accessing the DMA RAM location. Therefore, the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU. Note: DMA RAM can be used for general purpose data storage if the DMA function is not required in an application. Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space. All data memory writes, including in DSP instructions, view data space as combined X and Y address space. The boundary between the X and Y data spaces is device-dependent and is not user-programmable. All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. 2009 Microchip Technology Inc. Preliminary DS70292D-page 43 CPU CORE REGISTERS MAP All Resets Preliminary 2009 Microchip Technology Inc. SFR Name SFR Addr WREG0 0000 Working Register 0 0000 WREG1 0002 Working Register 1 0000 WREG2 0004 Working Register 2 0000 WREG3 0006 Working Register 3 0000 WREG4 0008 Working Register 4 0000 WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 WREG7 000E Working Register 7 0000 WREG8 0010 Working Register 8 0000 WREG9 0012 Working Register 9 0000 WREG10 0014 Working Register 10 0000 WREG11 0016 Working Register 11 0000 WREG12 0018 Working Register 12 0000 WREG13 001A Working Register 13 0000 WREG14 001C Working Register 14 0000 WREG15 001E Working Register 15 0800 SPLIM 0020 Stack Pointer Limit Register xxxx ACCAL 0022 ACCAL xxxx ACCAH 0024 ACCAH ACCAU 0026 ACCBL 0028 ACCBL ACCBH 002A ACCBH ACCBU 002C PCL 002E PCH 0030 — — — — — — — — Program Counter High Byte Register 0000 TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register 0000 PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register 0000 RCOUNT 0036 Repeat Loop Counter Register xxxx DCOUNT 0038 DCOUNT<15:0> xxxx Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 xxxx ACCA<39> ACCAU xxxx xxxx xxxx ACCB<39> ACCBU xxxx Program Counter Low Word Register DOSTARTL 003A DOSTARTH 003C DOENDL 003E DOENDH 0040 — — — — — — — — SR 0042 OA OB SA SB OAB SAB DA DC CORCON 0044 — — — US EDT MODCON 0046 XMODEN YMODEN — — Legend: Bit 7 xxxx DOSTARTL<15:1> — — — — — — — — — — DL<2:0> BWM<3:0> x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — SATB 0 xxxx DOENDH IPL<2:0> SATA xxxx 00xx DOENDL<15:1> — 0 DOSTARTH<5:0> SATDW YWM<3:0> 00xx RA N OV Z C ACCSAT IPL3 PSV RND IF XWM<3:0> 0000 0020 0000 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 44 TABLE 4-1: SFR Name SFR Addr CPU CORE REGISTERS MAP (CONTINUED) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets XMODSRT 0048 XS<15:1> 0 xxxx XMODEND 004A XE<15:1> 1 xxxx YMODSRT 004C YS<15:1> 0 xxxx YMODEND 004E YE<15:1> 1 xxxx XBREV 0050 BREN DISICNT 0052 — Legend: XB<14:0> — Disable Interrupts Counter Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. xxxx xxxx Preliminary DS70292D-page 45 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2009 Microchip Technology Inc. TABLE 4-1: SFR Name CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 SFR Addr Bit 15 Bit 14 CNEN1 0060 CN15IE — CNEN2 0062 CNPU1 0068 CNPU2 006A Legend: Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 CN14IE CN13IE CN30IE CN29IE CN12IE CN11IE — — — CN7IE — CN27IE — — CN24IE CN23IE — — — CN7PUE CN6PUE — — CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE — CN30PUE CN29PUE — CN27PUE Bit 8 Bit 7 Bit 6 Bit 0 All Resets CN1IE CN0IE 0000 — CN16IE 0000 CN2PUE CN1PUE CN0PUE 0000 — — CN16PUE 0000 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 CN6IE CN5IE CN4IE CN3IE CN2IE CN22IE CN21IE — — — CN5PUE CN4PUE CN3PUE — — CN24PUE CN23PUE CN22PUE CN21PUE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 Preliminary SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 CNEN2 0062 — CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 CNPU1 0068 CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 CNPU2 006A Legend: CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 46 TABLE 4-2: SFR Name SFR Addr INTERRUPT CONTROLLER REGISTER MAP Bit 15 Bit 14 Bit 13 INTCON1 0080 NSTDIS OVAERR INTCON2 0082 ALTIVT DISI Bit 12 Bit 11 OVBERR COVAERR COVBERR Bit 10 Bit 9 Bit 8 OVATE OVBTE COVTE — — — — — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — 0000 INT1EP INT0EP 0000 IC1IF INT0IF 0000 SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — — — — — INT2EP All Resets Preliminary IFS0 0084 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF — INT1IF CNIF CMIF IFS2 0088 — DMA4IF PMPIF — — — — — — — — DMA3IF C1IF(1) C1RXIF(1) SPI2IF SPI2EIF 0000 IFS3 008A — RTCIF DMA5IF DCIIF DCIEIF — — — — — — — — — — — 0000 IFS4 008C DAC1LIF(2) DAC1RIF(2) — — — — — — — C1TXIF(1) DMA7IF DMA6IF CRCIF U2EIF U1EIF — 0000 IEC0 0094 — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE — INT1IE CNIE CMIE IEC2 0098 — DMA4IE PMPIE — — — — — — — — DMA3IE C1IE(1) C1RXIE(1) SPI2IE SPI2EIE 0000 IEC3 009A — RTCIE DMA5IE DCIIE DCIEIE — — — — — — — — — — — 0000 IEC4 009C DAC1LIE(2) DAC1RIE(2) — — — — — — — C1TXIE(1) DMA7IE DMA6IE CRCIE U2EIE U1EIE — IPC0 00A4 — IPC1 00A6 IPC2 00A8 IPC3 00AA — IPC4 00AC — IPC5 00AE IPC6 DMA1IE T1IP<2:0> — OC1IP<2:0> — — T2IP<2:0> — U1RXIP<2:0> — OC2IP<2:0> — SPI1IP<2:0> — CNIP<2:0> — 00B0 IPC7 MI2C1IF SI2C1IF MI2C1IE SI2C1IE 0000 0000 0000 IC1IP<2:0> — INT0IP<2:0> 4444 — IC2IP<2:0> — DMA0IP<2:0> 4444 — SPI1EIP<2:0> — T3IP<2:0> 4444 DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444 — CMIP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444 IC8IP<2:0> — IC7IP<2:0> — — INT1IP<2:0> 4404 — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 00B2 — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 IPC8 00B4 — C1IP<2:0>(1) — C1RXIP<2:0>(1) — SPI2IP<2:0> — SPI2EIP<2:0> 4444 IPC9 00B6 — — — — — — DMA3IP<2:0> IPC11 00BA — — — — — IPC14 00C0 — IPC15 00C2 — IPC16 00C4 — IPC17 00C6 — IPC19 00CA — INTTREG 00E0 — — — — DCIEIP<2:0> — — — — CRCIP<2:0> — — — DAC1LIP<2:0>(2) — — — — — — DMA4IP<2:0> — — — — RTCIP<2:0> — — U2EIP<2:0> — C1TXIP<2:0>(1) DAC1RIP<2:0>(2) — — — — — ILR<3:0>> DS70292D-page 47 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note Interrupts disabled on devices without ECAN™ modules. Interrupts disabled on devices without Audio DAC modules. 1: 2: — — — — — — PMPIP<2:0> — — — — — — — — — — DMA5IP<2:0> — — U1EIP<2:0> — — DMA7IP<2:0> — — — — — 0004 — — VECNUM<6:0> DCIIP<2:0> — — — 4000 0444 — DMA6IP<2:0> — 0440 4440 0444 — 4400 4444 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2009 Microchip Technology Inc. TABLE 4-4: SFR Name SFR Addr TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Preliminary TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 TMR2 0106 Timer2 Register xxxx TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx TMR3 010A Timer3 Register xxxx PR2 010C Period Register 2 FFFF PR3 010E Period Register 3 T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS<1:0> T32 — TCS — 0000 T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 TMR4 0114 Timer4 Register xxxx TMR5HLD 0116 Timer5 Holding Register (for 32-bit timer operations only) xxxx TMR5 0118 Timer5 Register xxxx PR4 011A Period Register 4 FFFF PR5 011C Period Register 5 T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS<1:0> T32 — TCS — 0000 T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets ICI<1:0> ICOV ICBNE ICM<2:0> ICI<1:0> ICOV ICBNE ICM<2:0> ICI<1:0> ICOV ICBNE ICM<2:0> ICI<1:0> ICOV ICBNE ICM<2:0> TABLE 4-6: SFR Name SFR Addr TON — TSIDL — — — — — — xxxx FFFF TGATE TCKPS<1:0> — TSYNC TCS — 0000 FFFF FFFF INPUT CAPTURE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 — — ICSIDL — — — — Bit 8 Bit 7 2009 Microchip Technology Inc. IC1BUF 0140 IC1CON 0142 IC2BUF 0144 IC2CON 0146 IC7BUF 0158 IC7CON 015A IC8BUF 015C IC8CON 015E Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bit 6 Bit 5 Input 1 Capture Register — ICTMR xxxx Input 2 Capture Register — — ICSIDL — — — — — ICTMR xxxx Input 7 Capture Register — — ICSIDL — — — — — ICTMR — ICSIDL — — — — — ICTMR 0000 xxxx Input 8Capture Register — 0000 0000 xxxx 0000 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 48 TABLE 4-5: SFR Name OUTPUT COMPARE REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 OC1RS 0180 Output Compare 1 Secondary Register OC1R 0182 Output Compare 1 Register OC1CON 0184 OC2RS 0186 Output Compare 2 Secondary Register OC2R 0188 Output Compare 2 Register OC2CON 018A OC3RS 018C Output Compare 3 Secondary Register OC3R 018E Output Compare 3 Register OC3CON 0190 OC4RS 0192 Output Compare 4 Secondary Register OC4R 0194 Output Compare 4 Register OC4CON 0196 Legend: — — — — — — — — OCSIDL OCSIDL OCSIDL OCSIDL — — — — — — — — — — — — — — — — — — — — — Bit 2 Bit 1 Bit 0 All Resets xxxx — OCFLT OCTSEL OCM<2:0> 0000 xxxx — OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx — — Bit 3 xxxx — — Bit 4 xxxx — — Bit 5 — OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx — — OCFLT OCTSEL OCM<2:0> 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Preliminary TABLE 4-8: I2C1 REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 I2C1RCV 0200 — — — — — — — — Receive Register 0000 I2C1TRN 0202 — — — — — — — — Transmit Register 00FF I2C1BRG 0204 — — — — — — — I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 I2C1ADD 020A — — — — — — Address Register 0000 I2C1MSK 020C — — — — — — Address Mask Register 0000 SFR Name Legend: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Baud Rate Generator Register All Resets 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-9: SFR Name Bit 7 SFR Addr UART1 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 WAKE LPBACK DS70292D-page 49 Bit 5 Bit 4 Bit 3 ABAUD URXINV BRGH ADDEN RIDLE PERR Bit 2 Bit 1 All Resets STSEL 0000 URXDA 0110 U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT U1TXREG 0224 — — — — — — — UTX8 UART Transmit Register xxxx U1RXREG 0226 — — — — — — — URX8 UART Received Register 0000 U1BRG 0228 Legend: URXISEL<1:0> Baud Rate Generator Prescaler x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. PDSEL<1:0> Bit 0 FERR OERR 0000 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2009 Microchip Technology Inc. TABLE 4-7: SFR Name SFR Addr UART2 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 WAKE LPBACK Bit 5 Bit 4 Bit 3 ABAUD URXINV BRGH ADDEN RIDLE PERR Bit 2 Bit 1 All Resets STSEL 0000 URXDA 0110 U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT U2TXREG 0234 — — — — — — — UTX8 UART Transmit Register xxxx U2RXREG 0236 — — — — — — — URX8 UART Receive Register 0000 U2BRG 0238 Legend: Bit 14 Bit 13 SPI1STAT 0240 SPIEN — SPISIDL — — — — SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — SPI1BUF 0248 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 — — CKE SSEN SPIROV — — CKP MSTEN — — — Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — SPITBF SPIRBF 0000 SPRE<2:0> — — PPRE<1:0> — FRMDLY — Preliminary SPI1 Transmit and Receive Buffer Register 0000 0000 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-12: SPI2 REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 SPI2STAT 0260 SPIEN — SPISIDL — — — — SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — SPI2BUF 0268 Legend: 0000 SPI1 REGISTER MAP Bit 15 SFR Name OERR Baud Rate Generator Prescaler SFR Addr Legend: FERR x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-11: SFR Name URXISEL<1:0> PDSEL<1:0> Bit 0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 — — CKE SSEN SPIROV — — CKP MSTEN — — — SPI2 Transmit and Receive Buffer Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — SPITBF SPIRBF 0000 SPRE<2:0> — — PPRE<1:0> — FRMDLY — 0000 0000 0000 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 50 TABLE 4-10: File Name Addr ADC1BUF0 0300 AD1CON1 0320 AD1CON2 0322 AD1CON3 0324 ADC1 REGISTER MAP FOR dsPIC33FJ64GP202/802, dsPIC33FJ128GP202/802 AND dsPIC33FJ32GP302 Bit 15 Bit 14 ADON — Bit 13 Bit 12 Bit 11 Bit 10 — AD12B FORM<1:0> VCFG<2:0> — — CSCNA CHPS<1:0> ADRC — — 0326 — — — 0328 CH0NB — — AD1PCFGL 032C — — — PCFG12 AD1CSSL 0330 — — — CSS12 CSS11 AD1CON4 0332 — — — — — Addr Preliminary ADC1BUF0 0300 AD1CON1 0320 AD1CON2 0322 AD1CON3 0324 — — Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — SIMSAM ASAM SAMP DONE BUFS BUFM ALTS CH123NB<1:0> CH123SB PCFG11 PCFG10 All Resets xxxx SSRC<2:0> — SMPI<3:0> ADCS<7:0> CH0SB<4:0> — — — CH0NA — — — 0000 0000 0000 — CH123NA<1:0> CH123SA 0000 PCFG1 PCFG0 0000 CSS1 CSS0 CH0SA<4:0> PCFG9 — — — PCFG5 PCFG4 PCFG3 PCFG2 CSS10 CSS9 — — — CSS5 CSS4 CSS3 CSS2 — — — — — — — — 0000 0000 0000 DMABL<2:0> ADC1 REGISTER MAP FOR dsPIC33FJ64GP204/804, dsPIC33FJ128GP204/804 AND dsPIC33FJ32GP304 Bit 15 Bit 14 ADON — Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 — AD12B FORM<1:0> — CSCNA CHPS<1:0> Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — SIMSAM ASAM SAMP DONE BUFM ALTS ADC Data Buffer 0 ADSIDL ADDMABM VCFG<2:0> — ADRC — — BUFS 0326 — — — AD1CHS0 0328 CH0NB — — AD1PCFGL 032C — — — PCFG12 AD1CSSL 0330 — — — CSS12 CSS11 AD1CON4 0332 — — — — — — — — SMPI<3:0> ADCS<7:0> CH123NB<1:0> CH123SB CH0SB<4:0> PCFG11 PCFG10 All Resets xxxx SSRC<2:0> SAMC<4:0> AD1CHS123 — — — CH0NA — — — 0000 0000 0000 — CH123NA<1:0> CH123SA CH0SA<4:0> 0000 0000 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 — — — — — — — — Bit 3 0000 0000 0000 DMABL<2:0> x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-15: SFR Name Bit 6 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-14: Legend: Bit 7 SAMC<4:0> AD1CHS0 File Name Bit 8 ADC Data Buffer 0 ADSIDL ADDMABM AD1CHS123 Legend: Bit 9 DAC1 REGISTER MAP FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804 SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 — RMVOEN — Bit 2 Bit 1 Bit 0 RITYPE RFULL REMPTY All Resets DS70292D-page 51 DAC1CON 03F0 DACEN — DACSIDL AMPON — — — FORM — DAC1STAT 03F2 LOEN — LMVOEN — LITYPE LFULL LEMPTY ROEN DAC1DFLT 03F4 DAC1DFLT<15:0> 0000 DAC1RDAT 03F6 DAC1RDAT<15:0> 0000 DAC1LDAT 03F8 DAC1LDAT<15:0> 0000 Legend: — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DACFDIV<6:0> — 0000 0000 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2009 Microchip Technology Inc. TABLE 4-13: File Name Addr DMA REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 — Bit 5 Bit 4 Bit 2 — — Bit 1 Bit 0 0380 CHEN SIZE DIR HALF NULLW — — — — DMA0REQ 0382 FORCE — — — — — — — — DMA0STA 0384 STA<15:0> 0000 DMA0STB 0386 STB<15:0> 0000 DMA0PAD 0388 PAD<15:0> DMA0CNT 038A DMA1CON DMA1REQ DMA1STA 0390 STA<15:0> 0000 DMA1STB 0392 STB<15:0> 0000 DMA1PAD 0394 PAD<15:0> DMA1CNT 0396 — — — — — 038C CHEN SIZE DIR HALF NULLW — — — — 038E FORCE — — — — — — — — — — — — — — MODE<1:0> All Resets DMA0CON — AMODE<1:0> Bit 3 IRQSEL<6:0> 0000 0000 0000 CNT<9:0> — AMODE<1:0> 0000 — — MODE<1:0> IRQSEL<6:0> 0000 0000 0000 CNT<9:0> 0000 Preliminary DMA2CON 0398 CHEN SIZE DIR HALF NULLW — — — — DMA2REQ 039A FORCE — — — — — — — — DMA2STA 039C STA<15:0> 0000 DMA2STB 039E STB<15:0> 0000 DMA2PAD 03A0 PAD<15:0> DMA2CNT 03A2 — — — — — — — AMODE<1:0> — — MODE<1:0> IRQSEL<6:0> 0000 CNT<9:0> DMA3CON 03A4 CHEN SIZE DIR HALF NULLW — — — — DMA3REQ 03A6 FORCE — — — — — — — — 0000 0000 — AMODE<1:0> 0000 — — MODE<1:0> IRQSEL<6:0> 0000 0000 DMA3STA 03A8 STA<15:0> 0000 DMA3STB 03AA STB<15:0> 0000 DMA3PAD 03AC PAD<15:0> DMA3CNT 03AE — — — — — — 0000 CNT<9:0> 0000 2009 Microchip Technology Inc. DMA4CON 03B0 CHEN SIZE DIR HALF NULLW — — — — DMA4REQ 03B2 FORCE — — — — — — — — DMA4STA 03B4 STA<15:0> 0000 DMA4STB 03B6 STB<15:0> 0000 DMA4PAD 03B8 PAD<15:0> DMA4CNT 03BA DMA5CON DMA5REQ DMA5STA 03C0 STA<15:0> 0000 DMA5STB 03C2 STB<15:0> 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — — — — — 03BC CHEN SIZE DIR HALF NULLW — — — — 03BE FORCE — — — — — — — — — AMODE<1:0> — — MODE<1:0> IRQSEL<6:0> 0000 0000 0000 CNT<9:0> — AMODE<1:0> 0000 — IRQSEL<6:0> — MODE<1:0> 0000 0000 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 52 TABLE 4-16: File Name Addr DMA5PAD 03C4 DMA5CNT DMA6CON DMA REGISTER MAP (CONTINUED) Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 03C6 — — — — — — 03C8 CHEN SIZE DIR HALF NULLW — — — DMA6REQ 03CA FORCE — — — — — — — DMA6STA 03CC STA<15:0> 0000 DMA6STB 03CE STB<15:0> 0000 DMA6PAD 03D0 PAD<15:0> DMA6CNT 03D2 PAD<15:0> — — — — — — 0000 CNT<9:0> — — AMODE<1:0> — 0000 — — MODE<1:0> IRQSEL<6:0> 0000 0000 0000 CNT<9:0> 0000 Preliminary DMA7CON 03D4 CHEN SIZE DIR HALF NULLW — — — — DMA7REQ 03D6 FORCE — — — — — — — — DMA7STA 03D8 STA<15:0> 0000 DMA7STB 03DA STB<15:0> 0000 DMA7PAD 03DC PAD<15:0> DMA7CNT 03DE DMACS0 03E0 DMACS1 03E2 DSADR 03E4 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — — — — — — — LSTCH<3:0> AMODE<1:0> — — MODE<1:0> IRQSEL<6:0> 0000 0000 0000 — CNT<9:0> PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 — — 0000 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 0000 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0000 DSADR<15:0> 0000 DS70292D-page 53 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2009 Microchip Technology Inc. TABLE 4-16: File Name ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1 (FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 C1CTRL1 0400 — — CSIDL ABAT — C1CTRL2 0402 — — — — — C1VEC 0404 — — — C1FCTRL 0406 C1FIFO 0408 — — C1INTF 040A — — TXBO C1INTE 040C — — — C1EC 040E DMABS<2:0> Bit 10 Bit 9 Bit 8 Bit 7 — — REQOP<2:0> — — — Bit 5 OPMODE<2:0> — FILHIT<4:0> — Bit 6 — — — — — — — EWARN IVRIF WAKIF ERRIF — — — — — IVRIE WAKIE ERRIE — — — — WAKFIL — — — C1FEN1 0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 All Resets — — WIN 0480 0000 0000 0000 FSA<4:0> TERRCNT<7:0> — Bit 0 FNRB<5:0> RXWAR — Bit 1 DNCNT<4:0> — TXWAR 0410 CANCAP Bit 2 ICODE<6:0> RXBP 0412 — — TXBP C1CFG1 Bit 3 — FBP<5:0> C1CFG2 Bit 4 0000 — FIFOIF RBOVIF RBIF TBIF — FIFOIE RBOVIE RBIE TBIE RERRCNT<7:0> — — — SEG2PH<2:0> FLTEN10 FLTEN9 SJW<1:0> SAM FLTEN7 FLTEN6 FLTEN8 SEG1PH<2:0> FLTEN5 FLTEN4 0000 PRSEG<2:0> FLTEN3 0000 0000 BRP<5:0> SEG2PHTS 0000 FLTEN2 FLTEN1 0000 FLTEN0 FFFF C1FMSKSEL1 0418 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000 C1FMSKSEL2 041A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000 Preliminary Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-18: File Name Addr ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 (FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 0400041E Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 See definition when WIN = x C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL0 0000 C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 RXFUL9 RXFUL8 0000 C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF0 0000 C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000 RXOVF8 RXFUL7 RXOVF7 RXFUL6 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 2009 Microchip Technology Inc. C1TR01CON 0430 TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI<1:0> TXEN0 TXABT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI<1:0> 0000 C1TR23CON 0432 TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI<1:0> TXEN2 TXABT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI<1:0> 0000 C1TR45CON 0434 TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI<1:0> TXEN4 TXABT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI<1:0> 0000 C1TR67CON 0436 TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI<1:0> TXEN6 TXABT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI<1:0> 0000 C1RXD 0440 Received Data Word xxxx C1TXD 0442 Transmit Data Word xxxx Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 54 TABLE 4-17: File Name ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1(FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 0400041E Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets See definition when WIN = x Preliminary DS70292D-page 55 C1BUFPNT1 0420 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000 C1BUFPNT2 0422 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000 C1BUFPNT3 0424 F11BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000 C1BUFPNT4 0426 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> 0000 C1RXM0SID 0430 SID<10:3> — EID<17:16> xxxx C1RXM0EID 0432 EID<15:8> C1RXM1SID 0434 SID<10:3> — EID<17:16> xxxx C1RXM1EID 0436 EID<15:8> C1RXM2SID 0438 SID<10:3> — EID<17:16> xxxx C1RXM2EID 043A EID<15:8> C1RXF0SID 0440 SID<10:3> — EID<17:16> xxxx C1RXF0EID 0442 EID<15:8> C1RXF1SID 0444 SID<10:3> — EID<17:16> xxxx C1RXF1EID 0446 EID<15:8> C1RXF2SID 0448 SID<10:3> — EID<17:16> xxxx C1RXF2EID 044A EID<15:8> C1RXF3SID 044C SID<10:3> — EID<17:16> xxxx C1RXF3EID 044E EID<15:8> C1RXF4SID 0450 SID<10:3> — EID<17:16> xxxx C1RXF4EID 0452 EID<15:8> C1RXF5SID 0454 SID<10:3> — EID<17:16> xxxx C1RXF5EID 0456 EID<15:8> C1RXF6SID 0458 SID<10:3> — EID<17:16> xxxx C1RXF6EID 045A EID<15:8> C1RXF7SID 045C SID<10:3> — EID<17:16> xxxx C1RXF7EID 045E EID<15:8> C1RXF8SID 0460 SID<10:3> — EID<17:16> xxxx C1RXF8EID 0462 EID<15:8> C1RXF9SID 0464 SID<10:3> — EID<17:16> xxxx — EID<17:16> xxxx — EID<17:16> xxxx C1RXF9EID 0466 EID<15:8> C1RXF10SID 0468 SID<10:3> C1RXF10EID 046A EID<15:8> C1RXF11SID 046C SID<10:3> Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. SID<2:0> — MIDE EID<7:0> SID<2:0> — SID<2:0> — SID<2:0> — SID<2:0> — SID<2:0> — SID<2:0> — SID<2:0> — SID<2:0> — SID<2:0> — SID<2:0> — SID<2:0> — SID<2:0> — SID<2:0> — SID<2:0> — MIDE xxxx EID<7:0> MIDE xxxx EID<7:0> EXIDE xxxx EID<7:0> EXIDE xxxx EID<7:0> EXIDE xxxx EID<7:0> EXIDE xxxx EID<7:0> EXIDE xxxx EID<7:0> EXIDE xxxx EID<7:0> EXIDE xxxx EID<7:0> EXIDE xxxx EID<7:0> EXIDE xxxx EID<7:0> EXIDE xxxx EID<7:0> EXIDE xxxx EID<7:0> EXIDE xxxx dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2009 Microchip Technology Inc. TABLE 4-19: File Name ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1(FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) (CONTINUED) Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 C1RXF11EID 046E EID<15:8> C1RXF12SID 0470 SID<10:3> C1RXF12EID 0472 EID<15:8> C1RXF13SID 0474 SID<10:3> C1RXF13EID 0476 EID<15:8> C1RXF14SID 0478 SID<10:3> C1RXF14EID 047A EID<15:8> C1RXF15SID 047C SID<10:3> 047E EID<15:8> C1RXF15EID Legend: Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EID<7:0> SID<2:0> — SID<2:0> — SID<2:0> — SID<2:0> — All Resets xxxx EXIDE — EID<17:16> xxxx — EID<17:16> xxxx — EID<17:16> xxxx — EID<17:16> xxxx EID<7:0> xxxx EXIDE EID<7:0> xxxx EXIDE EID<7:0> xxxx EXIDE EID<7:0> xxxx x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-20: SFR Name Bit 10 DCI REGISTER MAP Preliminary Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 COFSD UNFM CSDOM DJST — — — DCICON1 0280 DCIEN — DCISIDL — DLOOP CSCKD CSCKE DCICON2 0282 — — — — BLEN1 BLEN0 — DCICON3 0284 — — — — DCISTAT 0286 — — — — COFSG<3:0> — Bit 1 COFSM1 Bit 0 COFSM0 0000 0000 0000 0000 WS<3:0> 0000 0000 0000 0000 BCG<11:0> SLOT3 SLOT2 SLOT1 SLOT0 — — — Reset State 0000 0000 0000 0000 — ROV RFUL TUNF TMPTY 0000 0000 0000 0000 2009 Microchip Technology Inc. TSCON 0288 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 TSE7 TSE6 TSE5 TSE4 TSE3 TSE2 TSE1 TSE0 0000 0000 0000 0000 RSCON 028C RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 0000 0000 0000 0000 RXBUF0 0290 Receive Buffer 0 Data Register 0000 0000 0000 0000 RXBUF1 0292 Receive Buffer 1 Data Register 0000 0000 0000 0000 RXBUF2 0294 Receive Buffer 2 Data Register 0000 0000 0000 0000 RXBUF3 0296 Receive Buffer 3 Data Register 0000 0000 0000 0000 TXBUF0 0298 Transmit Buffer 0 Data Register 0000 0000 0000 0000 TXBUF1 029A Transmit Buffer 1 Data Register 0000 0000 0000 0000 TXBUF2 029C Transmit Buffer 2 Data Register 0000 0000 0000 0000 TXBUF3 029E Transmit Buffer 3 Data Register 0000 0000 0000 0000 Legend: — = unimplemented, read as ‘0’. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 56 TABLE 4-19: File Name Addr PERIPHERAL PIN SELECT INPUT REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 — — Bit 10 Bit 9 Bit 8 — — Bit 2 Bit 1 Bit 0 — — — All Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — — — — — — — — INT2R<4:0> 001F Preliminary RPINR0 0680 — — — RPINR1 0682 — — — RPINR3 0686 — — — T3CKR<4:0> — — — T2CKR<4:0> 1F1F RPINR4 0688 — — — T5CKR<4:0> — — — T4CKR<4:0> 1F1F RPINR7 068E — — — IC2R<4:0> — — — IC1R<4:0> 1F1F RPINR10 0694 — — — IC8R<4:0> — — — IC7R<4:0> 1F1F RPINR11 0696 — — — — — — OCFAR<4:0> 001F RPINR18 06A4 — — — U1CTSR<4:0> — — — U1RXR<4:0> 1F1F RPINR19 06A6 — — — U2CTSR<4:0> — — — U2RXR<4:0> 1F1F RPINR20 06A8 — — — SCK1R<4:0> — — — SDI1R<4:0> 1F1F RPINR21 06AA — — — — — — SS1R<4:0> 001F RPINR22 06AC — — — — — — SDI2R<4:0> 1F1F RPINR23 06AE — — — — — — SS2R<4:0> 001F RPINR24 06B0 — — — RPINR25 06B2 — — RPINR26(1) 06B4 — — Legend: Note 1: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register is present only for dsPIC33FJ128GP802/804 and dsPIC33FJ64GP802/804 INT1R<4:0> — — — — — — — — — — — SCK2R<4:0> — — — — — — — — — 1F00 — — — — — CSDIR<4:0> 1F1F — — — — — — COFSR<4:0> 001F — — — — — — C1RXR<4:0> 001F CSCKR<4:0> DS70292D-page 57 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2009 Microchip Technology Inc. TABLE 4-21: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 RPOR0 06C0 — — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Bit 7 Bit 6 Bit 5 RP1R<4:0> — — — RP0R<4:0> 0000 RPOR1 06C2 — — — RP3R<4:0> — — — RP2R<4:0> 0000 RPOR2 06C4 — — — RP5R<4:0> — — — RP4R<4:0> 0000 RPOR3 06C6 — — — RP7R<4:0> — — — RP6R<4:0> 0000 RPOR4 06C8 — — — RP9R<4:0> — — — RP8R<4:0> 0000 RPOR5 06CA — — — RP11R<4:0> — — — RP10R<4:0> 0000 RPOR6 06CC — — — RP13R<4:0> — — — RP12R<4:0> 0000 RPOR7 06CE — — — RP15R<4:0> — — — RP14R<4:0> 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-23: Preliminary PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 2009 Microchip Technology Inc. RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> 0000 RPOR1 06C2 — — — RP3R<4:0> — — — RP2R<4:0> 0000 RPOR2 06C4 — — — RP5R<4:0> — — — RP4R<4:0> 0000 RPOR3 06C6 — — — RP7R<4:0> — — — RP6R<4:0> 0000 RPOR4 06C8 — — — RP9R<4:0> — — — RP8R<4:0> 0000 RPOR5 06CA — — — RP11R<4:0> — — — RP10R<4:0> 0000 RPOR6 06CC — — — RP13R<4:0> — — — RP12R<4:0> 0000 RPOR7 06CE — — — RP15R<4:0> — — — RP14R<4:0> 0000 RPOR8 06D0 — — — RP17R<4:0> — — — RP16R<4:0> 0000 RPOR9 06D2 — — — RP19R<4:0> — — — RP18R<4:0> 0000 RPOR10 06D4 — — — RP21R<4:0> — — — RP20R<4:0> 0000 RPOR11 06D6 — — — RP23R<4:0> — — — RP22R<4:0> 0000 RPOR12 06D8 — — — RP25R<4:0> — — — RP24R<4:0> 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 58 TABLE 4-22: File Name PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 Addr Bit 15 Bit 14 Bit 13 PMCON 0600 PMPEN — PSIDL PMMODE 0602 BUSY PMADDR PMDOUT1 0604 ADDR15 IRQM<1:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ADRMUX<1:0> PTBEEN PTWREN PTRDEN INCM<1:0> MODE16 MODE<1:0> CS1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 0000 WAITB<1:0> WAITM<3:0> WAITE<1:0> ADDR<13:0> 0000 0000 Parallel Port Data Out Register 1 (Buffers 0 and 1) 0000 PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3) 0000 PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1) 0000 PMPDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3) PMAEN 060C — PTEN14 — — — — — — — — — — — — PMSTAT 060E IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E Legend: Preliminary Bit 15 Bit 14 Bit 13 PMCON 0600 PMPEN — PSIDL PMMODE 0602 BUSY PMDOUT1 0000 OB0E 0000 PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 Addr PMADDR OB1E — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-25: File Name 0000 PTEN<1:0> 0604 ADDR15 IRQM<1:0> Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ADRMUX<1:0> PTBEEN PTWREN PTRDEN INCM<1:0> MODE16 MODE<1:0> CS1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 0000 WAITB<1:0> WAITM<3:0> WAITE<1:0> ADDR<13:0> 0000 0000 Parallel Port Data Out Register 1 (Buffers 0 and 1) 0000 PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3) 0000 PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1) 0000 PMPDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3) 0000 PMAEN 060C — PTEN14 — — — PMSTAT 060E IBF IBOV — — IB3F Legend: PTEN<10:0> IB2F — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. IB1F IB0F OBE OBUF — 0000 — OB3E OB2E OB1E OB0E 0000 DS70292D-page 59 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2009 Microchip Technology Inc. TABLE 4-24: File Name Addr ALRMVAL 0620 ALCFGRPT 0622 RTCVAL 0624 RCFGCAL 0626 Legend: REAL-TIME CLOCK AND CALENDAR REGISTER MAP Bit 15 Bit 14 ALRMEN CHIME Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Alarm Value Register Window based on APTR<1:0> AMASK<3:0> xxxx ALRMPTR<1:0> ARPT<7:-0> 0000 RTCC Value Register Window based on RTCPTR<1:0> RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE All Resets xxxx RTCPTR<1:0> CAL<7:0> 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-27: CRC REGISTER MAP Addr Bit 15 Bit 14 Bit 13 CRCCON 0640 — — CSIDL CRCXOR 0642 X<15:0> 0000 CRCDAT 0644 CRC Data Input Register 0000 CRCWDAT 0646 CRC Result Register 0000 Preliminary Legend: Bit 11 Bit 10 Bit 9 Bit 8 VWORD<4:0> Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 CMCON 0630 CMIDL — C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN CVRCON 0632 — — — — — — — — Bit 5 Bit 4 CRCFUL CRCMPT — CRCGO Bit 3 Bit 2 Bit 1 Bit 0 PLEN<3:0> 0000 Bit 7 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets C2INV C1INV C2NEG C2POS C1NEG C1POS 0000 CVRR CVRSS Bit 6 Bit 5 C2OUT C1OUT CVREN CVROE CVR<3:0> 0000 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-29: File Name Bit 6 DUAL COMPARATOR REGISTER MAP Addr Legend: Bit 7 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-28: File Name Bit 12 All Resets File Name Addr PORTA REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 Bit 15 Bit 14 Bit 13 Bit 12 2009 Microchip Technology Inc. Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 — — — — Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 079F — RA4 RA3 RA2 RA1 RA0 xxxx Bit 6 TRISA 02C0 — — — — — PORTA 02C2 — — — — — — — — — — LATA 02C4 — — — — — — — — — — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx ODCA 02C6 — — — — — — — — — — — — — — — — 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 60 TABLE 4-26: File Name Addr PORTA REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISA 02C0 — — — — — TRISA10 TRISA9 TRISA8 TRISA7 — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 079F PORTA 02C2 — — — — — RA10 RA9 RA8 RA7 — — RA4 RA3 RA2 RA1 RA0 xxxx LATA 02C4 — — — — — LATA10 LATA9 LATA8 LATA7 — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx ODCA 02C6 — — — — — ODCA10 ODCA9 ODCA8 ODCA7 — — — — — — — 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-31: PORTB REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx ODCB 02CE — — — — ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 — — — — — 0000 File Name Preliminary Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-32: PORTC REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISC 02D0 — — — — — — TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 03FF PORTC 02D2 — — — — — — RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx LATC 02D4 — — — — — — LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx ODCC 02D6 — — — — — — ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 — — — 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. File Name DS70292D-page 61 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2009 Microchip Technology Inc. TABLE 4-30: SYSTEM CONTROL REGISTER MAP Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN 0300(2) Addr Bit 15 RCON 0740 TRAPR IOPUWR OSCCON 0742 — CLKDIV 0744 ROI PLLFBD 0746 — — OSCTUN 0748 — — — ACLKCON 074A — — SELACLK Legend: Note 1: 2: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. RCON register Reset values dependent on type of Reset. OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset. TABLE 4-34: File Name Addr Bit 14 Bit 13 File Name COSC<2:0> — DOZE<2:0> — NOSC<2:0> DOZEN FRCDIV<2:0> — — — — — — AOSCMD<1:0> PLLPOST<1:0> — — PLLPRE<4:0> 3040 PLLDIV<8:0> — — APSTSCLR<2:0> — — ASRCSEL — 0030 TUN<5:0> — — — — Bit 3 0000 — — 0000 Bit 2 Bit 1 Bit 0 All Resets SECURITY REGISTER MAP(1) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Preliminary BSRAM 0750 — — — — — — — — — — — — — IW_BSR IR_BSR RL_BSR 0000 SSRAM 0752 — — — — — — — — — — — — — IW_ SSR IR_SSR RL_SSR 0000 Legend: Note 1: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register is not present in devices with 4K RAM and 32K Flash memory. Bit 2 Bit 1 TABLE 4-35: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 NVMCON 0760 WR WREN WRERR — — — NVMKEY 0766 — — — — — — Legend: Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 — — — ERASE — — — Bit 4 Bit 3 — NVMOP<3:0> All Resets 0000 NVMKEY<7:0> 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2009 Microchip Technology Inc. TABLE 4-36: PMD REGISTER MAP Bit 0 All Resets C1MD AD1MD 0000 OC2MD OC1MD 0000 — 0000 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PMD1 0770 T5MD T4MD T3MD T2MD T1MD — — DCIMD I2C1MD U2MD U1MD SPI2MD SPI1MD — PMD2 0772 IC8MD IC7MD — — — — IC2MD IC1MD — — — — OC4MD OC3MD PMD3 0774 — — — — — CMPMD RTCCMD PMPMD CRCMD DAC1MD — — — — — Legend: Bit 0 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bit 1 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 62 TABLE 4-33: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.2.7 4.2.8 SOFTWARE STACK In addition to its use as a working register, the W15 register in the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6. For a PC push during any CALL instruction, the MSb of the PC is zeroextended before the push, ensuring that the MSb is always clear. Note: A PC push during exception processing concatenates the SRL register to the MSb of the PC prior to the push. The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to ‘0’ because all stack operations must be word aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap does not occur. The stack error trap occurs on a subsequent push operation. For example, to cause a stack error trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value 0x1FFE. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. FIGURE 4-6: Stack Grows Toward Higher Address 0x0000 CALL STACK FRAME 15 0 PC<15:0> 000000000 PC<22:16> <Free Word> W15 (before CALL) W15 (after CALL) The dsPIC33F product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled. See Table 4-1 for an overview of the BSRAM and SSRAM SFRs. 4.3 Instruction Addressing Modes The addressing modes shown in Table 4-37 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types. 4.3.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space. 4.3.2 MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 <function> Operand 2 where Operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions: • • • • • Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified 5-bit or 10-bit Literal Note: POP : [--W15] PUSH : [W15++] 2009 Microchip Technology Inc. DATA RAM PROTECTION FEATURE Preliminary Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. DS70292D-page 63 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 4-37: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset 4.3.3 The sum of Wn and a literal forms the EA. MOVE AND ACCUMULATOR INSTRUCTIONS 4.3.4 Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. Note: For the MOV instructions, the addressing mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared by both source and destination (but typically only used by one). In summary, the following addressing modes are supported by move and accumulator instructions: • • • • • • • • Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: DS70292D-page 64 The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred to as MAC instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables. The two-source operand prefetch registers must be members of the set {W8, W9, W10, W11}. For data reads, W8 and W9 are always directed to the X RAGU, and W10 and W11 are always directed to the Y AGU. The effective addresses generated (before and after modification) must, therefore, be valid addresses within X data space for W8 and W9 and Y data space for W10 and W11. Note: Register Indirect with Register Offset Addressing mode is available only for W9 (in X space) and W11 (in Y space). In summary, the following addressing modes are supported by the MAC class of instructions: • • • • • Register Indirect Register Indirect Post-Modified by 2 Register Indirect Post-Modified by 4 Register Indirect Post-Modified by 6 Register Indirect with Register Offset (Indexed) 4.3.5 Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. MAC INSTRUCTIONS OTHER INSTRUCTIONS Besides the addressing modes outlined previously, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.4 Modulo Addressing Modulo Addressing mode is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively. In general, any particular circular buffer can be configured to operate in only one direction as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing buffers), based upon the direction of the buffer. The only exception to the usage restrictions is for buffers that have a power-of-two length. As these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performed on both the lower and upper address boundaries). 4.4.1 The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes). 4.4.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register, MODCON<15:0>, contains enable flags as well as a W register field to specify the W Address registers. The XWM and YWM fields select the registers that operate with Modulo Addressing: • If XWM = 15, X RAGU and X WAGU Modulo Addressing is disabled. • If YWM = 15, Y AGU Modulo Addressing is disabled. The X Address Space Pointer W register (XWM), to which Modulo Addressing is to be applied, is stored in MODCON<3:0> (see Table 4-1). Modulo Addressing is enabled for X data space when XWM is set to any value other than ‘15’ and the XMODEN bit is set at MODCON<15>. The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied is stored in MODCON<7:4>. Modulo Addressing is enabled for Y data space when YWM is set to any value other than ‘15’ and the YMODEN bit is set at MODCON<14>. START AND END ADDRESS The Modulo Addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 4-1). Note: Y space Modulo Addressing EA calculations assume word-sized data (LSb of every EA is always clear). FIGURE 4-7: MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 MOV MOV MOV MOV MOV MOV #0x1100, W0 W0, XMODSRT #0x1163, W0 W0, MODEND #0x8001, W0 W0, MODCON MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 MOV W0, [W1++] AGAIN: INC W0, W0 ;set modulo start address ;set modulo end address ;enable W1, X AGU for modulo ;fill the 50 buffer locations ;fill the next location ;increment the fill value Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words 2009 Microchip Technology Inc. Preliminary DS70292D-page 65 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.4.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to: • The upper boundary addresses for incrementing buffers • The lower boundary addresses for decrementing buffers It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes can, therefore, jump beyond boundaries and still be adjusted correctly. Note: 4.5 The modulo corrected effective address is written back to the register only when PreModify or Post-Modify Addressing mode is used to compute the effective address. When an address offset (such as [W7 + W2]) is used, Modulo Address correction is performed but the contents of the register remain unchanged. Note: The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. All bit-reversed EA calculations assume word-sized data (LSb of every EA is always clear). The XB value is scaled accordingly to generate compatible (byte) addresses. When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or PostIncrement Addressing and word-sized data writes. It does not function for any other addressing mode or for byte-sized data, and normal addresses are generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address modifier (XB), and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as word-sized data is a requirement, the LSb of the EA is ignored (and always clear). Note: Bit-Reversed Addressing Bit-Reversed Addressing mode is intended to simplify data reordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only. 4.5.1 XB<14:0> is the Bit-Reversed Address modifier, or ‘pivot point,’ which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size. Modulo Addressing and Bit-Reversed Addressing should not be enabled together. If an application attempts to do so, Bit-Reversed Addressing assumes priority when active for the X WAGU and X WAGU, Modulo Addressing is disabled. However, Modulo Addressing continues to function in the X RAGU. If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-Reversed Addressing mode is enabled in any of these situations: • BWM bits (W register selection) in the MODCON register are any value other than ‘15’ (the stack cannot be accessed using Bit-Reversed Addressing) • The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment If the length of a bit-reversed buffer is M = 2N bytes, the last ‘N’ bits of the data buffer start address must be zeros. DS70292D-page 66 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point TABLE 4-38: XB = 0x0008 for a 16-Word Bit-Reversed Buffer BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 2009 Microchip Technology Inc. Preliminary DS70292D-page 67 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.6 4.6.1 Interfacing Program and Data Memory Spaces Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1). Aside from normal execution, the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 architecture provides two methods by which program space can be accessed during operation: For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. The application can only access the least significant word of the program word. TABLE 4-39: Table 4-39 and Figure 4-9 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, and D<15:0> refers to a data space word. PROGRAM SPACE ADDRESS CONSTRUCTION Access Space Access Type Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User Program Space Address <23> Program Space Visibility (Block Remap/Read) <22:16> <15> 0xx xxxx xxxx TBLPAG<7:0> 0xxx xxxx User <14:1> PC<22:1> 0 Configuration Note 1: ADDRESSING PROGRAM SPACE <0> 0 xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx 0 PSVPAG<7:0> 0 xxxx xxxx Data EA<14:0>(1) xxx xxxx xxxx xxxx Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. DS70292D-page 68 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 bits 16 bits 24 bits Select Program Space (Remapping) Visibility(1) 0 EA 1 0 PSVPAG 8 bits 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. 2009 Microchip Technology Inc. Preliminary DS70292D-page 69 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.6.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bitwide word address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. • TBLRDL (Table Read Low): - In Word mode, this instruction maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>). FIGURE 4-10: - In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. • TBLRDH (Table Read High): - In Word mode, this instruction maps the entire upper word of a program address (P<23:16>) to a data address. The ‘phantom’ byte (D<15:8>), is always ‘0’. - In Byte mode, this instruction maps the upper or lower byte of the program word to D<7:0> of the data address, in the TBLRDL instruction. The data is always ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1). In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user application and configuration spaces. When TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space. ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG 02 23 15 0 0x000000 23 16 8 0 00000000 00000000 0x020000 00000000 0x030000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W 0x800000 DS70292D-page 70 The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON<2>). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required. Although each data space address 8000h and higher maps directly into a corresponding program memory address (see Figure 4-11), only the lower 16 bits of the FIGURE 4-11: 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time. For operations that use PSV, and are executed inside a REPEAT loop, these instances require two instruction cycles in addition to the specified execution time of the instruction: • Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop allows the instruction using PSV to access data, to execute in a single cycle. PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space PSVPAG 02 23 15 Data Space 0 0x000000 0x0000 Data EA<14:0> 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory space... 0x8000 PSV Area 0x800000 2009 Microchip Technology Inc. Preliminary ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. DS70292D-page 71 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 72 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 5. Flash Programming” (DS70191) of the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in blocks or ‘rows’ of 64 instructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time. 5.1 The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in two ways: • In-Circuit Serial Programming™ (ICSP™) programming capability • Run-Time Self-Programming (RTSP) ICSP allows any of the following devices, dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04, to be serially programmed while in the end application circuit. This is done with two lines for programming clock and FIGURE 5-1: programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. Table Instructions and Flash Programming Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits <7:0> of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 5-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits <15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits <23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. ADDRESSING FOR TABLE REGISTERS 24 bits Using Program Counter Program Counter 0 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 bits User/Configuration Space Select 2009 Microchip Technology Inc. 16 bits 24-bit EA Preliminary Byte Select DS70292D-page 73 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 5.2 RTSP Operation 5.3 Programming Operations The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 30-12 shows typical erase and programming times. The 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the programming operation is finished. The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group of 64 boundary. EQUATION 5-1: The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions. All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row. The programming time depends on the FRC accuracy (see Table 30-19) and the value of the FRC Oscillator Tuning register (see Register 9-4). Use the following formula to calculate the minimum and maximum values for the Row Write Time, Page Erase Time and Word Write Cycle Time parameters (see Table 30-12). PROGRAMMING TIME T -------------------------------------------------------------------------------------------------------------------------7.37 MHz FRC Accuracy % FRC Tuning % For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN<5:0> bits (see Register 9-4) are set to ‘b111111, the Minimum Row Write Time is: 11064 Cycles T RW = ---------------------------------------------------------------------------------------------- = 1.435ms 7.37 MHz 1 + 0.05 1 – 0.00375 and, the Maximum Row Write Time is: 11064 Cycles T RW = ---------------------------------------------------------------------------------------------- = 1.586ms 7.37 MHz 1 – 0.05 1 – 0.00375 Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. 5.4 Control Registers Two SFRs are used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 5-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY (Register 5-2) is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section 5.3 “Programming Operations” for further details. DS70292D-page 74 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 5-1: R/SO-0 (1) WR NVMCON: FLASH MEMORY CONTROL REGISTER R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 — ERASE — — R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) NVMOP<3:0>(2) bit 7 bit 0 Legend: SO = Settable only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command 0 = Perform the program operation specified by NVMOP<3:0> on the next WR command bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Select bits(2) If ERASE = 1: 1111 = Memory bulk erase operation 1110 = Reserved 1101 = Erase General Segment 1100 = Erase Secure Segment 1011 = Reserved 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte If ERASE = 0: 1111 = No operation 1110 = Reserved 1101 = No operation 1100 = No operation 1011 = Reserved 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. 2009 Microchip Technology Inc. Preliminary DS70292D-page 75 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits DS70292D-page 76 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 5.4.1 4. PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 5. Programmers can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 5-1): a) Set the NVMOP bits (NVMCON<3:0>) to ‘0010’ to configure for block erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits. b) Write the starting address of the page to be erased into the TBLPAG and W registers. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit (NVMCON<15>). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. EXAMPLE 5-1: For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user application must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 5-3. ERASING A PROGRAM MEMORY PAGE ; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP 6. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 0x55 to NVMKEY. c) Write 0xAA to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR 2009 Microchip Technology Inc. ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ; Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority <7 for next 5 instructions Write the 55 key Write the AA key Start the erase sequence Insert two NOPs after the erase command is asserted Preliminary DS70292D-page 77 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch • • • ; 63rd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR DS70292D-page 78 ; Block all interrupts with priority <7 ; for next 5 instructions ; ; ; ; ; ; Write the 55 key Write the AA key Start the erase sequence Insert two NOPs after the erase command is asserted Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 6.0 RESETS Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 8. Reset” (DS70192) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Reset module combines all reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: • • • • • • • POR: Power-on Reset BOR: Brown-out Reset MCLR: Master Clear Pin Reset SWR: RESET Instruction WDTO: Watchdog Timer Reset CM: Configuration Mismatch Reset TRAPR: Trap Conflict Reset FIGURE 6-1: • IOPUWR: Illegal Condition Device Reset - Illegal Opcode Reset - Uninitialized W Register Reset - Security Reset A simplified block diagram of the Reset module is shown in Figure 6-1. Any active source of reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state and some are unaffected. Note: Refer to the specific peripheral section or Section 3.0 “CPU” of this manual for register Reset states. All types of device Reset sets a corresponding status bit in the RCON register to indicate the type of Reset (see Register 6-1). A POR clears all the bits, except for the POR bit (RCON<0>), that are set. The user application can set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software does not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset is meaningful. RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle BOR Internal Regulator SYSRST VDD VDD Rise Detect POR Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch 2009 Microchip Technology Inc. Preliminary DS70292D-page 79 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 RCON: RESET CONTROL REGISTER(1) REGISTER 6-1: R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR — — — — CM VREGS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred bit 13-10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Mismatch Flag bit 1 = A configuration mismatch Reset has occurred. 0 = A configuration mismatch Reset has NOT occurred bit 8 VREGS: Voltage Regulator Standby During Sleep bit 1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep bit 7 EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70292D-page 80 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 2009 Microchip Technology Inc. Preliminary DS70292D-page 81 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 6.1 System Reset 2. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 family of devices have two types of Reset: • Cold Reset • Warm Reset 3. A cold Reset is the result of a Power-on Reset (POR) or a Brown-out Reset (BOR). On a cold Reset, the FNOSC configuration bits in the FOSC device configuration register selects the device clock source. A warm Reset is the result of all other reset sources, including the RESET instruction. On warm Reset, the device will continue to operate from the current clock source as indicated by the Current Oscillator Selection (COSC<2:0>) bits in the Oscillator Control (OSCCON<14:12>) register. 4. The device is kept in a Reset state until the system power supplies have stabilized at appropriate levels and the oscillator clock is ready. The sequence in which this occurs is detailed below and is shown in Figure 6-2. 1. 5. POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay TPOR has elapsed. TABLE 6-1: 6. BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay TBOR has elapsed. The delay TBOR ensures that the voltage regulator output becomes stable. PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay TPWRT has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start generating clock cycles. Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in Table 6-1. Refer to Section 9.0 “Oscillator Configuration” for more information. When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay TFSCM elapsed. OSCILLATOR DELAY Oscillator Startup Delay Oscillator Startup Timer PLL Lock Time Total Delay FRC, FRCDIV16, FRCDIVN TOSCD — — TOSCD FRCPLL TOSCD — TLOCK TOSCD + TLOCK XT TOSCD TOST — TOSCD + TOST HS TOSCD TOST — TOSCD + TOST EC — — — — XTPLL TOSCD TOST TLOCK TOSCD + TOST + TLOCK HSPLL TOSCD TOST TLOCK TOSCD + TOST + TLOCK Oscillator Mode ECPLL — — TLOCK TLOCK SOSC TOSCD TOST — TOSCD + TOST TOSCD — — TOSCD LPRC Note 1: 2: 3: TOSCD = Oscillator Start-up Delay (1.1 s max for FRC, 70 s max for LPRC). Crystal Oscillator start-up times vary with crystal characteristics, load capacitance, etc. TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4 s for a 10 MHz crystal and TOST = 32 ms for a 32 kHz crystal. TLOCK = PLL lock time (1.5 ms nominal), if PLL is enabled. DS70292D-page 82 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 6-2: SYSTEM RESET TIMING VBOR Vbor VPOR VDD TPOR 1 POR Reset TBOR 2 BOR Reset 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 TFSCM FSCM 5 Reset Device Status Run Time Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay TPOR has elapsed. 2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output becomes stable. 3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay TPWRT has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start generating clock cycles. 4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in Table 6-1. Refer to Section 9.0 “Oscillator Configuration” for more information. 5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay TFSCM elapsed. 2009 Microchip Technology Inc. Preliminary DS70292D-page 83 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 6-2: OSCILLATOR DELAY Symbol Parameter Value VPOR POR threshold 1.8V nominal TPOR POR extension time 30 s maximum VBOR BOR threshold 2.5V nominal 100 s maximum TBOR BOR extension time TPWRT Programmable power-up time delay 0-128 ms nominal TFSCM Fail-Safe Clock Monitor Delay 900 s maximum Note: 6.2 When the device exits the Reset condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges, otherwise the device may not function correctly. The user application must ensure that the delay between the time power is first applied, and the time SYSRST becomes inactive, is long enough to get all operating parameters within specification. Power-on Reset (POR) A Power-on Reset (POR) circuit ensures the device is reset from power-on. The POR circuit is active until VDD crosses the VPOR threshold and the delay TPOR has elapsed. The delay TPOR ensures the internal device bias circuits become stable. The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR. Refer to Section 30.0 “Electrical Characteristics” for details. The POR status (POR) bit in the Reset Control (RCON<0>) register is set to indicate the Power-on Reset. DS70292D-page 84 6.2.1 Brown-out Reset (BOR) and Power-up timer (PWRT) The on-chip regulator has a Brown-out Reset (BOR) circuit that resets the device when the VDD is too low (VDD < VBOR) for proper device operation. The BOR circuit keeps the device in Reset until VDD crosses VBOR threshold and the delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output becomes stable. The BOR status (BOR) bit in the Reset Control (RCON<1>) register is set to indicate the Brown-out Reset. The device will not run at full speed after a BOR as the VDD should rise to acceptable levels for full-speed operation. The PWRT provides power-up time delay (TPWRT) to ensure that the system power supplies have stabilized at the appropriate levels for full-speed operation before the SYSRST is released. The power-up timer delay (TPWRT) is programmed by the Power-on Reset Timer Value Select (FPWRT<2:0>) bits in the POR Configuration (FPOR<2:0>) register, which provides eight settings (from 0 ms to 128 ms). Refer to Section 27.0 “Special Features” for further details. Figure 6-3 shows the typical brown-out scenarios. The reset delay (TBOR + TPWRT) is initiated each time VDD rises above the VBOR trip point Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 6-3: BROWN-OUT SITUATIONS VDD VBOR TBOR + TPWRT SYSRST VDD VBOR TBOR + TPWRT SYSRST VDD dips before PWRT expires VDD VBOR TBOR + TPWRT SYSRST 6.3 External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse-width will generate a Reset. Refer to Section 30.0 “Electrical Characteristics” for minimum pulse-width specifications. The External Reset (MCLR) Pin (EXTR) bit in the Reset Control (RCON) register is set to indicate the MCLR Reset. 6.3.0.1 EXTERNAL SUPERVISORY CIRCUIT Many systems have external supervisory circuits that generate reset signals to Reset multiple devices in the system. This external Reset signal can be directly connected to the MCLR pin to Reset the device when the rest of system is Reset. 6.3.0.2 INTERNAL SUPERVISORY CIRCUIT When using the internal power supervisory circuit to Reset the device, the external reset pin (MCLR) should be tied directly or resistively to VDD. In this case, the MCLR pin will not be used to generate a Reset. The external reset pin (MCLR) does not have an internal pull-up and must not be left unconnected. 6.4 Software RESET Instruction (SWR) Whenever the RESET instruction is executed, the device will assert SYSRST, placing the device in a special Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST is released at the next instruction cycle, and the reset vector fetch will commence. 2009 Microchip Technology Inc. The Software Reset (Instruction) Flag (SWR) bit in the Reset Control (RCON<6>) register is set to indicate the software Reset. 6.5 Watchdog Time-out Reset (WDTO) Whenever a Watchdog time-out occurs, the device will asynchronously assert SYSRST. The clock source will remain unchanged. A WDT time-out during Sleep or Idle mode will wake-up the processor, but will not reset the processor. The Watchdog Timer Time-out Flag (WDTO) bit in the Reset Control (RCON<4>) register is set to indicate the Watchdog Reset. Refer to Section 27.4 “Watchdog Timer (WDT)” for more information on Watchdog Reset. 6.6 Trap Conflict Reset If a lower-priority hard trap occurs while a higher-priority trap is being processed, a hard trap conflict Reset occurs. The hard traps include exceptions of priority level 13 through level 15, inclusive. The address error (level 13) and oscillator error (level 14) traps fall into this category. The Trap Reset Flag (TRAPR) bit in the Reset Control (RCON<15>) register is set to indicate the Trap Conflict Reset. Refer to Section 7.0 “Interrupt Controller” for more information on trap conflict Resets. Preliminary DS70292D-page 85 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 6.7 Configuration Mismatch Reset each program memory section to store the data values. The upper 8 bits should be programmed with 3Fh, which is an illegal opcode value. To maintain the integrity of the peripheral pin select control registers, they are constantly monitored with shadow registers in hardware. If an unexpected change in any of the registers occur (such as cell disturbances caused by ESD or other external events), a configuration mismatch Reset occurs. 6.8.0.2 Any attempts to use the uninitialized W register as an address pointer will Reset the device. The W register array (with the exception of W15) is cleared during all resets and is considered uninitialized until written to. The Configuration Mismatch Flag (CM) bit in the Reset Control (RCON<9>) register is set to indicate the configuration mismatch Reset. Refer to Section 11.0 “I/O Ports” for more information on the configuration mismatch Reset. Note: 6.8 6.8.0.3 The PFC occurs when the Program Counter is reloaded as a result of a Call, Jump, Computed Jump, Return, Return from Subroutine, or other form of branch instruction. Illegal Condition Device Reset The VFC occurs when the Program Counter is reloaded with an Interrupt or Trap vector. • Illegal Opcode Reset • Uninitialized W Register Reset • Security Reset Refer to Section 27.8 “Code Protection and CodeGuard™ Security” for more information on Security Reset. The Illegal Opcode or Uninitialized W Access Reset Flag (IOPUWR) bit in the Reset Control (RCON<14>) register is set to indicate the illegal condition device Reset. 6.9 Using the RCON Status Bits The user application can read the Reset Control (RCON) register after any device Reset to determine the cause of the reset. ILLEGAL OPCODE RESET A device Reset is generated if the device attempts to execute an illegal opcode value that is fetched from program memory. Note: The illegal opcode Reset function can prevent the device from executing program memory sections that are used to store constant data. To take advantage of the illegal opcode Reset, use only the lower 16 bits of TABLE 6-3: SECURITY RESET If a Program Flow Change (PFC) or Vector Flow Change (VFC) targets a restricted location in a protected segment (Boot and Secure Segment), that operation will cause a security Reset. The configuration mismatch feature and associated reset flag is not available on all devices. An illegal condition device Reset occurs due to the following sources: 6.8.0.1 UNINITIALIZED W REGISTER RESET The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. Table 6-3 provides a summary of the reset flag bit operation. RESET FLAG BIT OPERATION Flag Bit Set by: Cleared by: TRAPR (RCON<15>) Trap conflict event POR,BOR IOPWR (RCON<14>) Illegal opcode or uninitialized W register access or Security Reset POR,BOR CM (RCON<9>) Configuration Mismatch POR,BOR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET instruction POR,BOR WDTO (RCON<4>) WDT time-out PWRSAV instruction, CLRWDT instruction, POR,BOR SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR,BOR IDLE (RCON<2>) PWRSAV #IDLE instruction POR,BOR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — Note: All Reset flag bits can be set or cleared by user software. DS70292D-page 86 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 32. Interrupts (Part III)” (DS70214) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 CPU. The interrupt controller has the following features: • Up to eight processor exceptions and software traps • Eight user-selectable priority levels • Interrupt Vector Table (IVT) with up to 118 vectors • A unique vector for each interrupt or exception source • Fixed priority within a specified user priority level • Alternate Interrupt Vector Table (AIVT) for debug support • Fixed interrupt entry and return latencies 7.1 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices implement up to 53 unique interrupts and five nonmaskable traps. These are summarized in Table 7-1. 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports debugging by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT. 7.2 Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000. A GOTO instruction at the Reset address can redirect program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction. Interrupt Vector Table The Interrupt Vector Table (IVT), shown in Figure 7-1, resides in program memory, starting at location 000004h. The IVT contains 126 vectors consisting of eight nonmaskable trap vectors plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bitwide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority. For example, the interrupt associated with vector 0 takes priority over interrupts at any other vector address. 2009 Microchip Technology Inc. Preliminary DS70292D-page 87 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Decreasing Natural Order Priority FIGURE 7-1: Note 1: DS70292D-page 88 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Start of Code 0x000000 0x000002 0x000004 0x000014 0x00007C 0x00007E 0x000080 Interrupt Vector Table (IVT)(1) 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 Alternate Interrupt Vector Table (AIVT)(1) 0x00017C 0x00017E 0x000180 0x0001FE 0x000200 See Table 7-1 for the list of implemented interrupt vectors. Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 7-1: INTERRUPT VECTORS Vector Number IVT Address AIVT Address 0 1 2 3 4 5 6 7 0x000004 0x000006 0x000008 0x00000A 0x00000C 0x00000E 0x000010 0x000012 0x000104 0x000106 0x000108 0x00010A 0x00010C 0x00010E 0x000110 0x000112 Reserved Oscillator Failure Address Error Stack Error Math Error DMA Error Reserved Reserved 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 0x000014 0x000016 0x000018 0x00001A 0x00001C 0x00001E 0x000020 0x000022 0x000024 0x000026 0x000028 0x00002A 0x00002C 0x00002E 0x000030 0x000032 0x000034 0x000036 0x000038 0x00003A 0x00003C 0x00003E 0x000040 0x000042 0x000044 0x000046 0x000048 0x00004A 0x00004C 0x00004E 0x000050 0x000052 0x000054 0x000056 0x000058 0x00005A 0x00005C 0x00005E 0x000060 0x000114 0x000116 0x000118 0x00011A 0x00011C 0x00011E 0x000120 0x000122 0x000124 0x000126 0x000128 0x00012A 0x00012C 0x00012E 0x000130 0x000132 0x000134 0x000136 0x000138 0x00013A 0x00013C 0x00013E 0x000140 0x000142 0x000144 0x000146 0x000148 0x00014A 0x00014C 0x00014E 0x000150 0x000152 0x000154 0x000156 0x000158 0x00015A 0x00015C 0x00015E 0x000160 INT0 – External Interrupt 0 IC1 – Input Compare 1 OC1 – Output Compare 1 T1 – Timer1 DMA0 – DMA Channel 0 IC2 – Input Capture 2 OC2 – Output Compare 2 T2 – Timer2 T3 – Timer3 SPI1E – SPI1 Error SPI1 – SPI1 Transfer Done U1RX – UART1 Receiver U1TX – UART1 Transmitter ADC1 – ADC 1 DMA1 – DMA Channel 1 Reserved SI2C1 – I2C1 Slave Events MI2C1 – I2C1 Master Events CM – Comparator Interrupt CN – Change Notification Interrupt INT1 – External Interrupt 1 Reserved IC7 – Input Capture 7 IC8 – Input Capture 8 DMA2 – DMA Channel 2 OC3 – Output Compare 3 OC4 – Output Compare 4 T4 – Timer4 T5 – Timer5 INT2 – External Interrupt 2 U2RX – UART2 Receiver U2TX – UART2 Transmitter SPI2E – SPI2 Error SPI2 – SPI2 Transfer Done C1RX – ECAN1 RX Data Ready C1 – ECAN1 Event DMA3 – DMA Channel 3 Reserved Reserved 2009 Microchip Technology Inc. Interrupt Source Preliminary DS70292D-page 89 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Vector Number IVT Address AIVT Address 47 48 49 50 51 52 53 0x000062 0x000064 0x000066 0x000068 0x00006A 0x00006C 0x00006E 0x000162 0x000164 0x000166 0x000168 0x00016A 0x00016C 0x00016E Reserved Reserved Reserved Reserved Reserved Reserved PMP – Parallel Master Port 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 0x000070 0x000072 0x000074 0x000076 0x000078 0x00007A 0x00007C 0x00007E 0x000080 0x000082 0x000084 0x000086 0x000088 0x00008A 0x00008C 0x00008E 0x000090 0x000170 0x000172 0x000174 0x000176 0x000178 0x00017A 0x00017C 0x00017E 0x000180 0x000182 0x000184 0x000186 0x000188 0x00018A 0x00018C 0x00018E 0x000190 DMA – DMA Channel 4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DCIE – DCI Error DCI – DCI Transfer Done DMA5 – DMA Channel 5 RTCC – Real Time Clock 71 0x000092 0x000192 Reserved 72 73 74 75 76 77 78 79 80 81 0x000094 0x000096 0x000098 0x00009A 0x00009C 0x00009E 0x0000A0 0x0000A2 0x0000A4 0x0000A6 0x000194 0x000196 0x000198 0x00019A 0x00019C 0x00019E 0x0001A0 0x0001A2 0x0001A4 0x0001A6 Reserved U1E – UART1 Error U2E – UART2 Error CRC – CRC Generator Interrupt DMA6 – DMA Channel 6 DMA7 – DMA Channel 7 C1TX – ECAN1 TX Data Request Reserved Reserved Reserved 82 83 84 85 86 0x0000A8 0x0000AA 0x0000AC 0x0000AE 0x0000B0 0x0001A8 0x0001AA 0x0001AC 0x0001AE 0x0001B0 Reserved Reserved Reserved Reserved 87 0x0000B2 88-126 0x0000B4-0x0000FE DS70292D-page 90 Interrupt Source DAC1R – DAC1 Right Data Request 0x0001B2 DAC1L – DAC1 Left Data Request 0x0001B4-0x0001FE Reserved Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 7.3 Interrupt Control and Status Registers 7.3.4 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices implement a total of 30 registers for the interrupt controller: • • • • • • INTCON1 INTCON2 IFSx IECx IPCx INTTREG 7.3.1 INTCON1 AND INTCON2 IFSX The IFS registers maintain all of the interrupt request flags. Each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software. 7.3.3 The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. 7.3.5 INTTREG The INTTREG register contains the associated interrupt vector number and the new CPU interrupt priority level, which are latched into vector number (VECNUM<6:0>) and Interrupt level (ILR<3:0>) bit fields in the INTTREG register. The new interrupt priority level is the priority of the pending interrupt. Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table. 7.3.2 IPCX IECX The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are listed in Table 7-1. For example, the INT0 (External Interrupt 0) is shown as having vector number 8 and a natural order priority of 0. Thus, the INT0IF bit is found in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP bits in the first position of IPC0 (IPC0<2:0>). 7.3.6 STATUS/CONTROL REGISTERS Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality. • The CPU STATUS register, SR, contains the IPL<2:0> bits (SR<7:5>). These bits indicate the current CPU interrupt priority level. The user software can change the current CPU priority level by writing to the IPL bits. • The CORCON register contains the IPL3 bit which, together with IPL<2:0>, also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All Interrupt registers are described in Register 7-1 through Register 7-31 in the following pages. 2009 Microchip Technology Inc. Preliminary DS70292D-page 91 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0 R/W-0 R/W-0 IPL<2:0>(2,3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: For complete register details, see Register 3-1: “SR: CPU Status Register”. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1. 3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1. DS70292D-page 92 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1) U-0 — bit 15 U-0 — R/W-0 SATA bit 7 R/W-0 SATB R/W-0 US R/W-0 EDT R-0 R-0 DL<2:0> R-0 bit 8 Legend: R = Readable bit 0’ = Bit is cleared bit 3 U-0 — R/W-1 SATDW R/W-0 ACCSAT C = Clear only bit W = Writable bit ‘x = Bit is unknown R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less Note 1: For complete register details, see Register 3-2: “CORCON: Core Control Register”. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. 2009 Microchip Technology Inc. Preliminary DS70292D-page 93 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14 OVAERR: Accumulator A Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A bit 13 OVBERR: Accumulator B Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B bit 10 OVATE: Accumulator A Overflow Trap Enable bit 1 = Trap overflow of Accumulator A 0 = Trap disabled bit 9 OVBTE: Accumulator B Overflow Trap Enable bit 1 = Trap overflow of Accumulator B 0 = Trap disabled bit 8 COVTE: Catastrophic Overflow Trap Enable bit 1 = Trap on catastrophic overflow of Accumulator A or B enabled 0 = Trap disabled bit 7 SFTACERR: Shift Accumulator Error Status bit 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift bit 6 DIV0ERR: Arithmetic Error Status bit 1 = Math error trap was caused by a divide by zero 0 = Math error trap was not caused by a divide by zero bit 5 DMACERR: DMA Controller Error Status bit 1 = DMA controller error trap has occurred 0 = DMA controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred DS70292D-page 94 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. Preliminary DS70292D-page 95 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table 0 = Use standard (default) vector table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-3 Unimplemented: Read as ‘0’ bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge DS70292D-page 96 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 SPI1EIF: SPI1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred 2009 Microchip Technology Inc. Preliminary DS70292D-page 97 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70292D-page 98 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC8IF IC7IF — INT1IF CNIF CMIF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 DMA2IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 IC8IF: Input Capture Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 IC7IF: Input Capture Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred 2009 Microchip Technology Inc. Preliminary DS70292D-page 99 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) bit 2 CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70292D-page 100 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — DMA4IF PMPIF — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — R/W-0 R/W-0 DMA3IF C1IF (1) R/W-0 C1RXIF (1) R/W-0 R/W-0 SPI2IF SPI2EIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA4IF: DMA Channel 4 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-5 Unimplemented: Read as ‘0’ bit 4 DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 C1IF: ECAN1 Event Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: Interrupts disabled on devices without ECAN™ modules. 2009 Microchip Technology Inc. Preliminary DS70292D-page 101 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — RTCIF DMA5IF DCIIF DCIEIF — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock and Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 DCIIF: DCI Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 DCIEIF: DCI Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10-0 Unimplemented: Read as ‘0’ DS70292D-page 102 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 R/W-0 DAC1LIF(2) R/W-0 DAC1RIF (2) U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — C1TXIF(1) DMA7IF DMA6IF CRCIF U2EIF U1EIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DAC1LIF: DAC Left Channel Interrupt Flag Status bit(2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 DAC1RIF: DAC Right Channel Interrupt Flag Status bit(2) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-7 Unimplemented: Read as ‘0’ bit 6 C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit(1) 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 DMA7IF: DMA Channel 7 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 DMA6IF: DMA Channel 6 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U2EIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ Note 1: Interrupts disabled on devices without ECAN™ modules. 2: Interrupts disabled on devices without Audio DAC modules. 2009 Microchip Technology Inc. Preliminary DS70292D-page 103 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 SPI1IE: SPI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 SPI1EIE: SPI1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70292D-page 104 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Flag Status bit 1 = Interrupt request enabled 0 = Interrupt request not enabled 2009 Microchip Technology Inc. Preliminary DS70292D-page 105 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC8IE IC7IE — INT1IE CNIE CMIE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 IC8IE: Input Capture Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 IC7IE: Input Capture Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 Unimplemented: Read as ‘0’ bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70292D-page 106 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 2 CMIE: Comparator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled 2009 Microchip Technology Inc. Preliminary DS70292D-page 107 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — DMA4IE PMPIE — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DMA3IE C1IE(1) C1RXIE(1) SPI2IE SPI2EIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 PMPIE: Parallel Master Port Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12-5 Unimplemented: Read as ‘0’ bit 4 DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request has enabled bit 3 C1IE: ECAN1 Event Interrupt Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled x = Bit is unknown Note 1: Interrupts disabled on devices without ECAN™ modules. DS70292D-page 108 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — RTCIE DMA5IE DCIIE DCIEIE — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 DCIIE: DCI Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 DCIEIE: DCI Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. Preliminary x = Bit is unknown DS70292D-page 109 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 DAC1LIE(2) DAC1RIE(2) — — — — — — bit 15 bit 8 U-0 R/W-0 — C1TXIE (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 DMA7IE DMA6IE CRCIE U2EIE U1EIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 DAC1LIE: DAC Left Channel Interrupt Enable bit(2) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 14 DAC1RIE: DAC Right Channel Interrupt Enable bit(2) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13-7 Unimplemented: Read as ‘0’ bit 6 C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit(1) 1 = Interrupt request occurred 0 = Interrupt request not occurred bit 5 DMA7IE: DMA Channel 7 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 DMA6IE: DMA Channel 6 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 U2EIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ x = Bit is unknown Note 1: Interrupts disabled on devices without ECAN™ modules. 2: Interrupts disabled on devices without Audio DAC modules. DS70292D-page 110 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-15: U-0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-1 — R/W-0 R/W-0 T1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 INT0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2009 Microchip Technology Inc. Preliminary x = Bit is unknown DS70292D-page 111 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-16: U-0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-1 — R/W-0 R/W-0 T2IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC2IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC2IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70292D-page 112 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-17: U-0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-1 — R/W-0 R/W-0 U1RXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 SPI1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SPI1EIP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2009 Microchip Technology Inc. Preliminary x = Bit is unknown DS70292D-page 113 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 DMA1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 AD1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 U1TXIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70292D-page 114 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-19: U-0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-1 R/W-0 — R/W-0 CNIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 CMIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 MI2C1IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 SI2C1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CMIP<2:0>: Comparator Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2009 Microchip Technology Inc. Preliminary x = Bit is unknown DS70292D-page 115 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-20: U-0 IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 R/W-1 — R/W-0 R/W-0 IC8IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 IC7IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70292D-page 116 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-21: U-0 IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 R/W-1 — R/W-0 R/W-0 T4IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 OC3IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2009 Microchip Technology Inc. Preliminary DS70292D-page 117 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-22: U-0 IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 R/W-1 — R/W-0 R/W-0 U2TXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 U2RXIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 INT2IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T5IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70292D-page 118 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-23: U-0 IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 R/W-1 — R/W-0 C1IP<2:0> R/W-0 (1) U-0 R/W-1 — R/W-0 C1RXIP<2:0> R/W-0 (1) bit 15 bit 8 U-0 R/W-1 — R/W-0 SPI2IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 SPI2EIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 C1IP<2:0>: ECAN1 Event Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled x = Bit is unknown Note 1: Interrupts disabled on devices without ECAN™ modules. 2009 Microchip Technology Inc. Preliminary DS70292D-page 119 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 DMA3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70292D-page 120 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-25: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 DMA4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 PMPIP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA4IP<2:0>: DMA Channel 4 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 PMPIP<2:0>: Parallel Master Port Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. Preliminary DS70292D-page 121 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-26: U-0 IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 R/W-1 — R/W-0 R/W-0 DCIEIP<2:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 DCIEIP<2:0>: DCI Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ DS70292D-page 122 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-27: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 RTCIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 DMA5IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DCIIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Flag Status bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 DCIIP<2:0>: DCI Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2009 Microchip Technology Inc. Preliminary DS70292D-page 123 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-28: U-0 IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 R/W-1 — R/W-0 R/W-0 CRCIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 U2EIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 U1EIP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP<2:0>: CRC Generator Error Interrupt Flag Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2EIP<2:0>: UART2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70292D-page 124 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-29: U-0 IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17 U-0 — U-0 — — U-0 — U-0 R/W-1 — R/W-0 C1TXIP<2:0> R/W-0 (1) bit 15 bit 8 U-0 R/W-1 — R/W-0 DMA7IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 C1TXIP<2:0>: ECAN1 Transmit Data Request Interrupt Priority bits(1) 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 DMA7IP<2:0>: DMA Channel 7 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: Interrupts disabled on devices without ECAN™ modules. 2009 Microchip Technology Inc. Preliminary DS70292D-page 125 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-30: U-0 IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 R/W-1 R/W-0 R/W-0 DAC1LIP<2:0>(1) — U-0 R/W-0 R/W-0 R/W-0 DAC1RIP<2:0>(1) — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 DAC1LIP<2:0>: DAC Left Channel Interrupt Flag Status bit(1) 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 DAC1RIP<2:0>: DAC Right Channel Interrupt Flag Status bit(1) 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ x = Bit is unknown Note 1: Interrupts disabled on devices without Audio DAC modules. DS70292D-page 126 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-31: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 — R-0 R-0 R-0 R-0 R-0 VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 2009 Microchip Technology Inc. Preliminary x = Bit is unknown DS70292D-page 127 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 7.4 7.4.3 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source at initialization: 1. 2. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level depends on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources can be programmed to the same non-zero value. Note: 3. 4. At a device Reset, the IPCx registers are initialized such that all user interrupt sources are assigned to priority level 4. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register. 7.4.2 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR. 7.4.4 INTERRUPT DISABLE All user interrupts can be disabled using this procedure: 1. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to priority level 7 by inclusive ORing the value OEh with SRL. 2. To enable user interrupts, the POP instruction can be used to restore the previous SR value. Note: Only user interrupts with a priority level of 7 or lower can be disabled. Trap sources (level 8-level 15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. INTERRUPT SERVICE ROUTINE The method used to declare an ISR and initialize IVT with the correct vector address depends on programming language (C or assembler) and language development tool suite used to develop application. the the the the In general, the user application must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, the program re-enters the ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. DS70292D-page 128 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 8.0 DIRECT MEMORY ACCESS (DMA) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 38. Direct Memory Access (DMA) (Part III)” (DS70215) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. TABLE 8-1: Direct Memory Access (DMA) is a very efficient mechanism of copying data between peripheral SFRs (e.g., UART Receive register, Input Capture 1 buffer), and buffers or variables stored in RAM, with minimal CPU intervention. The DMA controller can automatically copy entire blocks of data without requiring the user software to read or write the peripheral Special Function Registers (SFRs) every time a peripheral interrupt occurs. The DMA controller uses a dedicated bus for data transfers and therefore, does not steal cycles from the code execution flow of the CPU. To exploit the DMA capability, the corresponding user buffers or variables must be located in DMA RAM. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 peripherals that can utilize DMA are listed in Table 8-1. DMA CHANNEL TO PERIPHERAL ASSOCIATIONS DMAxREQ Register IRQSEL<6:0> Bits DMAxPAD Register Values to Read from Peripheral DMAxPAD Register Values to Write to Peripheral INT0 – External Interrupt 0 0000000 — — IC1 – Input Capture 1 0000001 0x0140 (IC1BUF) — OC1 – Output Compare 1 Data 0000010 — 0x0182 (OC1R) OC1 – Output Compare 1 Secondary Data 0000010 — 0x0180 (OC1RS) IC2 – Input Capture 2 0000101 0x0144 (IC2BUF) — OC2 – Output Compare 2 Data 0000110 — 0x0188 (OC2R) OC2 – Output Compare 2 Secondary Data 0000110 — 0x0186 (OC2RS) TMR2 – Timer2 0000111 — — TMR3 – Timer3 0001000 — — Peripheral to DMA Association SPI1 – Transfer Done 0001010 0x0248 (SPI1BUF) 0x0248 (SPI1BUF) UART1RX – UART1 Receiver 0001011 0x0226 (U1RXREG) — UART1TX – UART1 Transmitter 0001100 — 0x0224 (U1TXREG) ADC1 – ADC1 convert done 0001101 0x0300 (ADC1BUF0) — UART2RX – UART2 Receiver 0011110 0x0236 (U2RXREG) — UART2TX – UART2 Transmitter 0011111 — 0x0234 (U2TXREG) SPI2 – Transfer Done 0100001 0x0268 (SPI2BUF) 0x0268 (SPI2BUF) ECAN1 – RX Data Ready 0100010 0x0440 (C1RXD) — PMP – Master Data Transfer 0101101 0x0608 (PMDIN1) 0x0608 (PMDIN1) ECAN1 – TX Data Request 1000110 — 0x0442 (C1TXD) DCI – Codec Transfer Done 0111100 0x0290 (RXBUF0) 0x0298 (TXBUF0) DAC1 – Right Data Output 1001110 — 0x03F6 (DAC1RDAT) DAC2 – Left Data Output 1001111 — 0x03F8 (DAC1LDAT) 2009 Microchip Technology Inc. Preliminary DS70292D-page 129 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 The DMA controller features eight identical data transfer channels. • Byte or word transfers • Fixed priority channel arbitration • Manual (software) or Automatic (peripheral DMA requests) transfer initiation • One-Shot or Auto-Repeat block transfer modes • Ping-Pong mode (automatic switch between two DPSRAM start addresses after each block transfer complete) • DMA request for each channel can be selected from any supported interrupt source • Debug support features Each channel has its own set of control and status registers. Each DMA channel can be configured to copy data either from buffers stored in dual port DMA RAM to peripheral SFRs, or from peripheral SFRs to buffers in DMA RAM. The DMA controller supports the following features: • Eight DMA channels • Register Indirect With Post-increment Addressing mode • Register Indirect Without Post-increment Addressing mode • Peripheral Indirect Addressing mode (peripheral generates destination address) • CPU interrupt after half or full block transfer complete FIGURE 8-1: For each DMA channel, a DMA interrupt request is generated when a block transfer is complete. Alternatively, an interrupt can be generated when half of the block has been filled. TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS Peripheral Indirect Address DMA Control DMA Controller DMA RAM SRAM DMA Ready Peripheral 3 DMA Channels PORT 1 PORT 2 SRAM X-Bus CPU DMA DMA DS Bus CPU Peripheral DS Bus CPU Note: CPU Non-DMA Ready Peripheral DMA DMA Ready Peripheral 1 CPU DMA DMA Ready Peripheral 2 CPU and DMA address buses are not shown for clarity. DS70292D-page 130 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 8.1 DMAC Registers Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7) contains the following registers: • A 16-bit DMA Channel Control register (DMAxCON) • A 16-bit DMA Channel IRQ Select register (DMAxREQ) • A 16-bit DMA RAM Primary Start Address register (DMAxSTA) • A 16-bit DMA RAM Secondary Start Address register (DMAxSTB) • A 16-bit DMA Peripheral Address register (DMAxPAD) • A 10-bit DMA Transfer Count register (DMAxCNT) The DMAxCON, DMAxREQ, DMAxPAD and DMAxCNT are all conventional read/write registers. Reads of DMAxSTA or DMAxSTB reads the contents of the DMA RAM Address register. Writes to DMAxSTA or DMAxSTB write to the registers. This allows the user to determine the DMA buffer pointer value (address) at any time. The interrupt flags (DMAxIF) are located in an IFSx register in the interrupt controller. The corresponding interrupt enable control bits (DMAxIE) are located in an IECx register in the interrupt controller, and the corresponding interrupt priority control bits (DMAxIP) are located in an IPCx register in the interrupt controller. An additional pair of status registers, DMACS0 and DMACS1, are common to all DMAC channels. DMACS0 contains the DMA RAM and SFR write collision flags, XWCOLx and PWCOLx, respectively. DMACS1 indicates DMA channel and Ping-Pong mode status. 2009 Microchip Technology Inc. Preliminary DS70292D-page 131 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 8-1: DMAxCON: DMA CHANNEL x CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CHEN SIZE DIR HALF NULLW — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 AMODE<1:0> U-0 U-0 — — R/W-0 R/W-0 MODE<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHEN: Channel Enable bit 1 = Channel enabled 0 = Channel disabled bit 14 SIZE: Data Transfer Size bit 1 = Byte 0 = Word bit 13 DIR: Transfer Direction bit (source/destination bus select) 1 = Read from DMA RAM address, write to peripheral address 0 = Read from peripheral address, write to DMA RAM address bit 12 HALF: Early Block Transfer Complete Interrupt Select bit 1 = Initiate block transfer complete interrupt when half of the data has been moved 0 = Initiate block transfer complete interrupt when all of the data has been moved bit 11 NULLW: Null Data Peripheral Write Mode Select bit 1 = Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear) 0 = Normal operation bit 10-6 Unimplemented: Read as ‘0’ bit 5-4 AMODE<1:0>: DMA Channel Operating Mode Select bits 11 = Reserved (acts as Peripheral Indirect Addressing mode) 10 = Peripheral Indirect Addressing mode 01 = Register Indirect without Post-Increment mode 00 = Register Indirect with Post-Increment mode bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer) 10 = Continuous, Ping-Pong modes enabled 01 = One-Shot, Ping-Pong modes disabled 00 = Continuous, Ping-Pong modes disabled DS70292D-page 132 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 8-2: R/W-0 FORCE (1) DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 IRQSEL6<6:0> R/W-0 R/W-0 R/W-0 (2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FORCE: Force DMA Transfer bit(1) 1 = Force a single DMA transfer (Manual mode) 0 = Automatic DMA transfer initiation by DMA request bit 14-7 Unimplemented: Read as ‘0’ bit 6-0 IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits(2) 0000000-1111111 = DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: Refer to Table 7-1 for a complete listing of IRQ numbers for all interrupt sources. 2009 Microchip Technology Inc. Preliminary DS70292D-page 133 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 8-3: R/W-0 DMAxSTA: DMA CHANNEL x RAM START ADDRESS REGISTER A(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown STA<15:0>: Primary DMA RAM Start Address bits (source or destination) Note 1: A read of this address register returns the current contents of the DMA RAM Address register, not the contents written to STA<15:0>. If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. REGISTER 8-4: R/W-0 DMAxSTB: DMA CHANNEL x RAM START ADDRESS REGISTER B(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown STB<15:0>: Secondary DMA RAM Start Address bits (source or destination) Note 1: A read of this address register returns the current contents of the DMA RAM Address register, not the contents written to STB<15:0>. If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. DS70292D-page 134 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 8-5: R/W-0 DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PAD<15:0>: Peripheral Address Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. REGISTER 8-6: DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 CNT<9:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 CNT<9:0>: DMA Transfer Count Register bits(2) x = Bit is unknown Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers = CNT<9:0> + 1. 2009 Microchip Technology Inc. Preliminary DS70292D-page 135 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PWCOL7: Channel 7 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 14 PWCOL6: Channel 6 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 13 PWCOL5: Channel 5 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 12 PWCOL4: Channel 4 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 11 PWCOL3: Channel 3 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 10 PWCOL2: Channel 2 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 9 PWCOL1: Channel 1 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 8 PWCOL0: Channel 0 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 7 XWCOL7: Channel 7 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 6 XWCOL6: Channel 6 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 5 XWCOL5: Channel 5 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 4 XWCOL4: Channel 4 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected DS70292D-page 136 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED) bit 3 XWCOL3: Channel 3 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 2 XWCOL2: Channel 2 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected 2009 Microchip Technology Inc. Preliminary DS70292D-page 137 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 8-8: DMACS1: DMA CONTROLLER STATUS REGISTER 1 U-0 U-0 U-0 U-0 — — — — R-1 R-1 R-1 R-1 LSTCH<3:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 LSTCH<3:0>: Last DMA Channel Active bits 1111 = No DMA transfer has occurred since system Reset 1110-1000 = Reserved 0111 = Last data transfer was by DMA Channel 7 0110 = Last data transfer was by DMA Channel 6 0101 = Last data transfer was by DMA Channel 5 0100 = Last data transfer was by DMA Channel 4 0011 = Last data transfer was by DMA Channel 3 0010 = Last data transfer was by DMA Channel 2 0001 = Last data transfer was by DMA Channel 1 0000 = Last data transfer was by DMA Channel 0 bit 7 PPST7: Channel 7 Ping-Pong Mode Status Flag bit 1 = DMA7STB register selected 0 = DMA7STA register selected bit 6 PPST6: Channel 6 Ping-Pong Mode Status Flag bit 1 = DMA6STB register selected 0 = DMA6STA register selected bit 5 PPST5: Channel 5 Ping-Pong Mode Status Flag bit 1 = DMA5STB register selected 0 = DMA5STA register selected bit 4 PPST4: Channel 4 Ping-Pong Mode Status Flag bit 1 = DMA4STB register selected 0 = DMA4STA register selected bit 3 PPST3: Channel 3 Ping-Pong Mode Status Flag bit 1 = DMA3STB register selected 0 = DMA3STA register selected bit 2 PPST2: Channel 2 Ping-Pong Mode Status Flag bit 1 = DMA2STB register selected 0 = DMA2STA register selected bit 1 PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMA1STB register selected 0 = DMA1STA register selected bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMA0STB register selected 0 = DMA0STA register selected DS70292D-page 138 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 8-9: R-0 DSADR: MOST RECENT DMA RAM ADDRESS R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits 2009 Microchip Technology Inc. Preliminary DS70292D-page 139 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 140 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 9.0 OSCILLATOR CONFIGURATION • External and internal oscillator options as clock sources • An on-chip Phase-Locked Loop (PLL) to scale the internal operating frequency to the required system clock frequency • An internal FRC oscillator that can also be used with the PLL, thereby allowing full-speed operation without any external clock generation hardware • Clock switching between various clock sources • Programmable clock postscaler for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures • A Clock Control register (OSCCON) • Non-volatile Configuration bits for main oscillator selection • An auxiliary crystal oscillator for Audio DAC Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 39. Oscillator (Part III)” (DS70216) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. A simplified diagram of the oscillator system is shown in Figure 9-1. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 oscillator system provides: FIGURE 9-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator POSCCLK R(2) S1 S1/S3 PLL FVCO(1) FRCDIV POSCMD<1:0> FRC Oscillator S2 XTPLL, HSPLL, ECPLL, FRCPLL S3 OSC2 DOZE<2:0> XT, HS, EC FRCDIVN S7 FCY DOZE OSC1 ÷ 2 FP FOSC FRCDIV<2:0> TUN<5:0> FRCDIV16 S6 ÷ 16 FRC LPRC Oscillator S0 LPRC Secondary Oscillator S5 SOSC SOSCO S4 LPOSCEN SOSCI Clock Fail S7 Clock Switch Reset WDT, PWRT, FSCM NOSC<2:0> FNOSC<2:0> Timer1 Auxiliary Oscillator POSCCLK FVCO(1) AOSCCLK ÷ N ACLK DAC AOSCMD<1:0> ASRCSEL Note SELACK APSTSCLR<2:0> 1: See Figure 9-2 for PLL details. 2: If the Oscillator is used with XT or HS modes, an extended parallel resistor with the value of 1 M must be connected. 2009 Microchip Technology Inc. Preliminary DS70292D-page 141 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 9.1 9.1.2 CPU Clocking System The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices provide seven system clock options: • • • • • • • Fast RC (FRC) Oscillator FRC Oscillator with Phase Locked Loop (PLL) Primary (XT, HS or EC) Oscillator Primary Oscillator with PLL Secondary (LP) Oscillator Low-Power RC (LPRC) Oscillator FRC Oscillator with postscaler 9.1.1 SYSTEM CLOCK SOURCES The Fast RC (FRC) internal oscillator runs at a nominal frequency of 7.37 MHz. User software can tune the FRC frequency. User software can optionally specify a factor (ranging from 1:2 to 1:256) by which the FRC clock frequency is divided. This factor is selected using the FRCDIV<2:0> (CLKDIV<10:8>) bits. The primary oscillator can use one of the following as its clock source: • Crystal (XT): Crystals and ceramic resonators in the range of 3 MHz to 10 MHz. The crystal is connected to the OSC1 and OSC2 pins. • High-Speed Crystal (HS): Crystals in the range of 10 MHz to 40 MHz. The crystal is connected to the OSC1 and OSC2 pins. • External Clock (EC): External clock signal is directly applied to the OSC1 pin. The secondary (LP) oscillator is designed for low power and uses a 32.768 kHz crystal or ceramic resonator. The LP oscillator uses the SOSCI and SOSCO pins. The Low-Power RC (LPRC) internal oscIllator runs at a nominal frequency of 32.768 kHz. It is also used as a reference clock by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip PLL to provide a wide range of output frequencies for device operation. PLL configuration is described in Section 9.1.4 “PLL Configuration”. The FRC frequency depends on the FRC accuracy (see Table 30-19) and the value of the FRC Oscillator Tuning register (see Register 9-4). DS70292D-page 142 SYSTEM CLOCK SELECTION The oscillator source used at a device Power-on Reset event is selected using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory. (Refer to Section 27.1 “Configuration Bits” for further details.) The Initial Oscillator Selection Configuration bits, FNOSC<2:0> (FOSCSEL<2:0>), and the Primary Oscillator Mode Select Configuration bits, POSCMD<1:0> (FOSC<1:0>), select the oscillator source that is used at a Power-on Reset. The FRC primary oscillator is the default (unprogrammed) selection. The Configuration bits allow users to choose among 12 different clock modes, shown in Table 9-1. The output of the oscillator (or the output of the PLL if a PLL mode has been selected) FOSC is divided by 2 to generate the device instruction clock (FCY) and peripheral clock time base (FP). FCY defines the operating speed of the device, and speeds up to 40 MHz are supported by the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 architecture. Instruction execution speed or device operating frequency, FCY, is given by: EQUATION 9-1: DEVICE OPERATING FREQUENCY FCY = FOSC/2 9.1.3 AUXILIARY OSCILLATOR The Auxiliary Oscillator (AOSC) can be used for peripherals that need to operate at a frequency unrelated to the system clock such as a Digital-to-Analog Converter (DAC). The Auxiliary Oscillator can use one of the following as its clock source: Crystal (XT): Crystal and ceramic resonators in the range of 3 MHz to 10 MHz. The crystal is connected to the SOCI and SOSCO pins. High-Speed Crystal (HS): Crystals in the range of 10 to 40 MHz. The crystal is connected to the SOSCI and SOSCO pins. External Clock (EC): External clock signal up to 64 MHz. The external clock signal is directly applied to SOSCI pin. Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 9.1.4 For a primary oscillator or FRC oscillator, output ‘FIN’, the PLL output ‘FOSC’ is given by: PLL CONFIGURATION The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in selecting the device operating speed. A block diagram of the PLL is shown in Figure 9-2. EQUATION 9-2: FOSC = FIN • The output of the primary oscillator or FRC, denoted as ‘FIN’, is divided down by a prescale factor (N1) of 2, 3, ... or 33 before being provided to the PLL’s Voltage Controlled Oscillator (VCO). The input to the VCO must be selected in the range of 0.8 MHz to 8 MHz. The prescale factor ‘N1’ is selected using the PLLPRE<4:0> bits (CLKDIV<4:0>). (N1M• N2) For example, suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL. • If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO input of 10/2 = 5 MHz, which is within the acceptable range of 0.8-8 MHz. • If PLLDIV<8:0> = 0x1E, then M = 32. This yields a VCO output of 5 x 32 = 160 MHz, which is within the 100-200 MHz ranged needed. • If PLLPOST<1:0> = 0, then N2 = 2. This provides a Fosc of 160/2 = 80 MHz. The resultant device operating speed is 80/2 = 40 MIPS. The PLL Feedback Divisor, selected using the PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M,’ by which the input to the VCO is multiplied. This factor must be selected such that the resulting VCO output frequency is in the range of 100 MHz to 200 MHz. The VCO output is further divided by a postscale factor ‘N2.’ This factor is selected using the PLLPOST<1:0> bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and must be selected such that the PLL output frequency (FOSC) is in the range of 12.5 MHz to 80 MHz, which generates device operating speeds of 6.25-40 MIPS. FIGURE 9-2: FOSC CALCULATION EQUATION 9-3: FCY = FOSC 2 = XT WITH PLL MODE EXAMPLE 1 10000000 • 32 ( ) = 40 MIPS 2•2 2 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 PLL BLOCK DIAGRAM FVCO 100-200 MHz Here(1) 0.8-8.0 MHz Here(1) Source (Crystal, External Clock or Internal RC) PLLPRE X VCO PLLPOST 12.5-80 MHz Here(1) FOSC PLLDIV N1 Divide by 2-33 M Divide by 2-513 N2 Divide by 2, 4, 8 Note 1: This frequency range must be satisfied at all times. 2009 Microchip Technology Inc. Preliminary DS70292D-page 143 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Note Fast RC Oscillator with Divide-by-N (FRCDIVN) Internal xx 111 1, 2 Fast RC Oscillator with Divide-by-16 (FRCDIV16) Internal xx 110 1 Low-Power RC Oscillator (LPRC) Internal xx 101 1 Secondary (Timer1) Oscillator (SOSC) Secondary xx 100 1 Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011 — Primary Oscillator (XT) with PLL (XTPLL) Primary 01 011 — Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1 Primary Oscillator (HS) Primary 10 010 — Primary Oscillator (XT) Primary 01 010 — Primary Oscillator (EC) Primary 00 010 1 Fast RC Oscillator with PLL (FRCPLL) Internal xx 001 1 Fast RC Oscillator (FRC) Internal xx 000 1 Note 1: 2: OSC2 pin function is determined by the OSCIOFNC Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device. DS70292D-page 144 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 OSCCON: OSCILLATOR CONTROL REGISTER(1) REGISTER 9-1: U-0 R-0 — R-0 R-0 COSC<2:0> U-0 R/W-y — R/W-y NOSC<2:0> R/W-y (2) bit 15 bit 8 R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0 CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 Legend: y = Value set from Configuration bits on POR C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only) 000 = Fast RC oscillator (FRC) 001 = Fast RC oscillator (FRC) with PLL 010 = Primary oscillator (XT, HS, EC) 011 = Primary oscillator (XT, HS, EC) with PLL 100 = Secondary oscillator (SOSC) 101 = Low-Power RC oscillator (LPRC) 110 = Fast RC oscillator (FRC) with Divide-by-16 111 = Fast RC oscillator (FRC) with Divide-by-n bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2) 000 = Fast RC oscillator (FRC) 001 = Fast RC oscillator (FRC) with PLL 010 = Primary oscillator (XT, HS, EC) 011 = Primary oscillator (XT, HS, EC) with PLL 100 = Secondary oscillator (SOSC) 101 = Low-Power RC oscillator (LPRC) 110 = Fast RC oscillator (FRC) with Divide-by-16 111 = Fast RC oscillator (FRC) with Divide-by-n bit 7 CLKLOCK: Clock Lock Enable bit If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01) 1 = Clock switching is disabled, system clock source is locked 0 = Clock switching is enabled, system clock source can be modified by clock switching bit 6 IOLOCK: Peripheral Pin Select Lock bit 1 = Peripherial pin select is locked, write to peripheral pin select registers not allowed 0 = Peripherial pin select is not locked, write to peripheral pin select registers allowed bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure Note 1: Writes to this register require an unlock sequence. Refer to Section 39. “Oscillator (Part III)” (DS70216) in the “dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip website) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 2009 Microchip Technology Inc. Preliminary DS70292D-page 145 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Writes to this register require an unlock sequence. Refer to Section 39. “Oscillator (Part III)” (DS70216) in the “dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip website) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. DS70292D-page 146 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 9-2: R/W-0 CLKDIV: CLOCK DIVISOR REGISTER R/W-0 ROI R/W-1 R/W-1 R/W-0 R/W-0 DOZEN(1) DOZE<2:0> R/W-0 R/W-0 FRCDIV<2:0> bit 15 bit 8 R/W-0 R/W-1 PLLPOST<1:0> U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 PLLPRE<4:0> bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clears the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits 000 = FCY/1 001 = FCY/2 010 = FCY/4 011 = FCY/8 (default) 100 = FCY/16 101 = FCY/32 110 = FCY/64 111 = FCY/128 bit 11 DOZEN: DOZE Mode Enable bit(1) 1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock/peripheral clock ratio forced to 1:1 bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 000 = FRC divide by 1 (default) 001 = FRC divide by 2 010 = FRC divide by 4 011 = FRC divide by 8 100 = FRC divide by 16 101 = FRC divide by 32 110 = FRC divide by 64 111 = FRC divide by 256 bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler) 00 = Output/2 01 = Output/4 (default) 10 = Reserved 11 = Output/8 bit 5 Unimplemented: Read as ‘0’ bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. 2009 Microchip Technology Inc. Preliminary DS70292D-page 147 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 DS70292D-page 148 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 9-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — R/W-0 R/W-0 R/W-0 — R/W-0 TUN<5:0> R/W-0 R/W-0 (1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Center frequency +11.625% (8.23 MHz) 011110 = Center frequency +11.25% (8.20 MHz) • • • 000001 = Center frequency +0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency -0.375% (7.345 MHz) • • • 100001 = Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz) x = Bit is unknown Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. 2009 Microchip Technology Inc. Preliminary DS70292D-page 149 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 9-5: ACLKCON: AUXILIARY CONTROL REGISTER U-0 U-0 R/W-0 — — SELACLK R/W-0 R/W-0 R/W-0 AOSCMD<1:0> R/W-0 R/W-0 APSTSCLR<2:0> bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 ASRCSEL — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider 1 = Auxiliary Oscillators provides the source clock for Auxiliary Clock Divider 0 = PLL output (Fvco) provides the source clock for the Auxiliary Clock Divider bit 12-11 AOSCMD<1:0>: Auxiliary Oscillator Mode 11 = EC External Clock Mode Select 10 = XT Oscillator Mode Select 01 = HS Oscillator Mode Select 00 = Auxiliary Oscillator Disabled bit 10-8 APSTSCLR<2:0>: Auxiliary Clock Output Divider 111 = divided by 1 110 = divided by 2 101 = divided by 4 100 = divided by 8 011 = divided by 16 010 = divided by 32 001 = divided by 64 000 = divided by 256 (default) bit 7 ASRCSEL: Select Reference Clock Source for Auxiliary Clock 1 = Primary Oscillator is the Clock Source 0 = Auxiliary Oscillator is the Clock Source bit 6-0 Unimplemented: Read as ‘0’ DS70292D-page 150 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 9.2 Clock Switching Operation 2. Applications are free to switch among any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 devices have a safeguard lock built into the switch process. Note: 9.2.1 Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMD<1:0> Configuration bits. While an application can switch to and from Primary Oscillator mode in software, it cannot switch among the different primary submodes without reprogramming the device. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF (OSCCON<3>) status bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware waits until the Oscillator Start-up Timer (OST) expires. If the new source is using the PLL, the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSC bit values are transferred to the COSC status bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are enabled) or LP (if LPOSCEN remains set). 3. 4. 5. 6. ENABLING CLOCK SWITCHING To enable clock switching, the FCKSM1 Configuration bit in the Configuration register must be programmed to ‘0’. (Refer to Section 27.1 “Configuration Bits” for further details.) If the FCKSM1 Configuration bit is unprogrammed (‘1’), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting. Note 1: The processor continues to execute code throughout the clock switching sequence. Timing-sensitive code should not be executed during this time. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: Refer to Section 39. “Oscillator (Part III)” (DS70216) in the “dsPIC33F/ PIC24H Family Reference Manual” for details. The NOSC control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSC bits (OSCCON<14:12>) reflect the clock source selected by the FNOSC Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at ‘0’ at all times. 9.2.2 OSCILLATOR SWITCHING SEQUENCE Performing sequence: 1. 2. 3. 4. 5. a clock switch requires this basic If desired, read the COSC bits (OSCCON<14:12>) to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSC control bits (OSCCON<10:8>) for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit (OSCCON<0>) to initiate the oscillator switch. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. 2009 Microchip Technology Inc. 9.3 Fail-Safe Clock Monitor (FSCM) The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by programming. If the FSCM function is enabled, the LPRC internal oscillator runs at all times (except during Sleep mode) and is not subject to control by the Watchdog Timer. In the event of an oscillator failure, the FSCM generates a clock failure trap event and switches the system clock over to the FRC oscillator. Then the application program can either attempt to restart the oscillator or execute a controlled shutdown. The trap can be treated as a warm Reset by simply loading the Reset address into the oscillator fail trap vector. If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. Preliminary DS70292D-page 151 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 152 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 10.0 POWER-SAVING FEATURES 10.2 Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 9. Watchdog Timer and Power-Saving Modes” (DS70196) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices provide the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 devices can manage power consumption in four ways: • • • • Clock frequency Instruction-based Sleep and Idle modes Software-controlled Doze mode Selective peripheral control in software Combinations of these methods can be used to selectively tailor an application’s power consumption while still maintaining critical application features, such as timing-sensitive communications. 10.1 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution. Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembler syntax of the PWRSAV instruction is shown in Example 10-1. Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to wake up. 10.2.1 SLEEP MODE The following occur in Sleep mode: • The system clock source is shut down. If an on-chip oscillator is used, it is turned off. • The device current consumption is reduced to a minimum, provided that no I/O pin is sourcing current. • The Fail-Safe Clock Monitor does not operate, since the system clock source is disabled. • The LPRC clock continues to run in Sleep mode if the WDT is enabled. • The WDT, if enabled, is automatically cleared prior to entering Sleep mode. • Some device features or peripherals can continue to operate. This includes items such as the input change notification on the I/O ports, or peripherals that use an external clock input. • Any peripheral that requires the system clock source for its operation is disabled. The device wakes up from Sleep mode on any of these events: Clock Frequency and Clock Switching dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices allow a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or highprecision oscillators by simply changing the NOSC bits (OSCCON<10:8>). The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 9.0 “Oscillator Configuration”. EXAMPLE 10-1: Instruction-Based Power-Saving Modes • Any interrupt source that is individually enabled • Any form of device Reset • A WDT time-out On wake-up from Sleep mode, the processor restarts with the same clock source that was active when Sleep mode was entered. PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE PWRSAV #IDLE_MODE ; Put the device into SLEEP mode ; Put the device into IDLE mode 2009 Microchip Technology Inc. Preliminary DS70292D-page 153 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 10.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.4 “Peripheral Module Disable”). • If the WDT or FSCM is enabled, the LPRC also remains active. The device wakes from Idle mode on any of these events: Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE<2:0> bits (CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default setting. Programs can use Doze mode to selectively reduce power consumption in event-driven applications. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the CPU idles, waiting for something to invoke an interrupt routine. An automatic return to full-speed CPU operation on interrupts can be enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. On wake-up from Idle mode, the clock is reapplied to the CPU and instruction execution will begin (2-4 clock cycles later), starting with the instruction following the PWRSAV instruction, or the first instruction in the ISR. For example, suppose the device is operating at 20 MIPS and the ECAN module has been configured for 500 kbps based on this device operating speed. If the device is placed in Doze mode with a clock frequency ratio of 1:4, the ECAN module continues to communicate at the required bit rate of 500 kbps, but the CPU now starts executing instructions at a frequency of 5 MIPS. 10.2.3 10.4 • Any interrupt that is individually enabled • Any device Reset • A WDT time-out INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS Any interrupt that coincides with the execution of a PWRSAV instruction is held off until entry into Sleep or Idle mode has completed. The device then wakes up from Sleep or Idle mode. 10.3 Doze Mode The preferred strategies for reducing power consumption are changing clock speed and invoking one of the power-saving modes. In some circumstances, this cannot be practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed can introduce communication errors, while using a power-saving mode can stop communications completely. The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral are also disabled, so writes to those registers do not have effect and read values are invalid. A peripheral module is enabled only if both the associated bit in the PMD register is cleared and the peripheral is supported by the specific dsPIC® DSC variant. If the peripheral is present in the device, it is enabled in the PMD register by default. Note: Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed, while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. DS70292D-page 154 Peripheral Module Disable Preliminary If a PMD bit is set, the corresponding module is disabled after a delay of one instruction cycle. Similarly, if a PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 T5MD bit 15 T4MD T3MD T2MD T1MD — — R/W-0 U2MD R/W-0 U1MD R/W-0 SPI2MD R/W-0 SPI1MD U-0 — R/W-0 C1MD R/W-0 I2C1MD R/W-0 DCIMD bit 8 R/W-0 AD1MD bit 7 bit 0 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set bit 15 T5MD: Timer5 Module Disable bit 1 = Timer5 module is disabled 0 = Timer5 module is enabled bit 14 T4MD: Timer4 Module Disable bit 1 = Timer4 module is disabled 0 = Timer4 module is enabled bit 13 T3MD: Timer3 Module Disable bit 1 = Timer3 module is disabled 0 = Timer3 module is enabled bit 12 T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled 0 = Timer2 module is enabled T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled 0 = Timer1 module is enabled Unimplemented: Read as ‘0’ bit 11 bit 10-9 bit 8 DCIMD: DCI Module Disable bit 1 = DCI module is disabled 0 = DCI module is enabled bit 7 I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled 0 = I2C1 module is enabled U2MD: UART2 Module Disable bit 1 = UART2 module is disabled 0 = UART2 module is enabled U1MD: UART1 Module Disable bit 1 = UART1 module is disabled 0 = UART1 module is enabled SPI2MD: SPI2 Module Disable bit 1 = SPI2 module is disabled 0 = SPI2 module is enabled bit 6 bit 5 bit 4 bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2 bit 1 Unimplemented: Read as ‘0’ C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled 2009 Microchip Technology Inc. U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Preliminary DS70292D-page 155 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 IC8MD IC7MD — — — — IC2MD IC1MD bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — OC4MD OC3MD OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 IC8MD: Input Capture 8 Module Disable bit 1 = Input Capture 8 module is disabled 0 = Input Capture 8 module is enabled bit 14 IC7MD: Input Capture 2 Module Disable bit 1 = Input Capture 7 module is disabled 0 = Input Capture 7 module is enabled bit 13-10 Unimplemented: Read as ‘0’ bit 9 IC2MD: Input Capture 2 Module Disable bit 1 = Input Capture 2 module is disabled 0 = Input Capture 2 module is enabled bit 8 IC1MD: Input Capture 1 Module Disable bit 1 = Input Capture 1 module is disabled 0 = Input Capture 1 module is enabled bit 7-4 Unimplemented: Read as ‘0’ bit 3 OC4MD: Output Compare 4 Module Disable bit 1 = Output Compare 4 module is disabled 0 = Output Compare 4 module is enabled bit 2 OC3MD: Output Compare 3 Module Disable bit 1 = Output Compare 3 module is disabled 0 = Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled DS70292D-page 156 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CMPMD RTCCMD PMPMD bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 CRCMD DAC1MD — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Comparator Module Disable bit 1 = Comparator module is disabled 0 = Comparator module is enabled bit 9 RTCCMD: RTCC Module Disable bit 1 = RTCC module is disabled 0 = RTCC module is enabled bit 8 PMPMD: PMP Module Disable bit 1 = PMP module is disabled 0 = PMP module is enabled bit 7 CRCMD: CRC Module Disable bit 1 = CRC module is disabled 0 = CRC module is enabled bit 6 DAC1MD: DAC1 Module Disable bit 1 = DAC1 module is disabled 0 = DAC1 module is enabled bit 5-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. Preliminary x = Bit is unknown DS70292D-page 157 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 158 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 11.0 I/O PORTS Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 10. I/O Ports” (DS70193) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. All of the device pins (except VDD, VSS, MCLR and OSC1/CLKI) are shared among the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. 11.1 Parallel I/O (PIO) Ports Generally a parallel I/O port that shares a pin with a peripheral is subservient to the peripheral. The peripheral’s output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port FIGURE 11-1: has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through,” in which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure 11-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin can be read, but the output driver for the parallel port bit is disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin can be driven by a port. All port pins have three registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch. Reads from the port (PORTx) read the port pins, while writes to the port pins write the latch. Any bit and its associated data and control registers that are not valid for a particular device is disabled. This means the corresponding LATx and TRISx registers and the port pin are read as zeros. When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Peripheral Output Data 0 PIO Module Read TRIS 1 Output Enable Output Data 0 Data Bus D WR TRIS CK Q I/O Pin TRIS Latch D WR LAT + WR Port Q CK Data Latch Read LAT Input Data Read Port 2009 Microchip Technology Inc. Preliminary DS70292D-page 159 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 11.2 Open-Drain Configuration 11.4 In addition to the PORT, LAT and TRIS registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired 5V tolerant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. Refer to “Pin Diagrams” for the available pins and their functionality. 11.3 Configuring Analog Port Pins The AD1PCFGL and TRIS registers control the operation of the analog-to-digital (A/D) port pins. The port pins that are to function as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) is converted. The AD1PCFGL register has a default value of 0x0000; therefore, all pins that share ANx functions are analog (not digital) by default. When the PORT register is read, all pins configured as analog input channels are read as cleared (a low level). Pins configured as digital inputs do not convert an analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. EXAMPLE 11-1: MOV MOV NOP btss 0xFF00, W0 W0, TRISBB PORTB, #13 DS70292D-page 160 I/O Port Write/Read Timing One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be an NOP, as shown in Example 11-1. 11.5 Input Change Notification The input change notification function of the I/O ports allows the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-ofstates even in Sleep mode, when the clocks are disabled. Depending on the device pin count, up to 21 external signals (CNx pin) can be selected (enabled) for generating an interrupt request on a change-ofstate. Four control registers are associated with the CN module. The CNEN1 and CNEN2 registers contain the interrupt enable control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. Each CN pin also has a weak pull-up connected to it. The pull-ups act as a current source connected to the pin, and eliminate the need for external resistors when push-button or keypad devices are connected. The pull-ups are enabled separately using the CNPU1 and CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. PORT WRITE/READ EXAMPLE ; ; ; ; Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs Delay 1 cycle Next Instruction Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 11.6 Peripheral Pin Select 11.6.2.1 Peripheral pin select configuration enables peripheral set selection and placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The peripheral pin select configuration feature operates over a fixed subset of digital I/O pins. Programmers can independently map the input and/or output of most digital peripherals to any one of these I/O pins. Peripheral pin select is performed in software, and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping, once it has been established. 11.6.1 The peripheral pin select feature is used with a range of up to 26 pins. The number of available pins depends on the particular device and its pin count. Pins that support the peripheral pin select feature include the designation “RPn” in their full pin designation, where “RP” designates a remappable peripheral and “n” is the remappable pin number. 11.6.2 The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it is mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 11-1 through Register 11-16). Each register contains sets of 5-bit fields, with each set associated with one of the remappable peripherals. Programming a given peripheral’s bit field with an appropriate 5-bit value maps the RPn pin with that value to that peripheral. For any given device, the valid range of values for any bit field corresponds to the maximum number of peripheral pin selections supported by the device. Figure 11-2 illustrates remappable pin selection for U1RX input. Note: AVAILABLE PINS Input Mapping For input mapping only, the Peripheral Pin Select (PPS) functionality does not have priority over the TRISx settings. Therefore, when configuring the RPx pin for input, the corresponding bit in the TRISx register must also be configured for input (i.e., set to ‘1’). FIGURE 11-2: CONTROLLING PERIPHERAL PIN SELECT Peripheral pin select features are controlled through two sets of special function registers: one to map peripheral inputs, and one to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or output is being mapped. REMAPPABLE MUX INPUT FOR U1RX U1RXR<4:0> 0 RP0 1 RP1 2 U1RX input to peripheral RP2 25 RP 25 2009 Microchip Technology Inc. Preliminary DS70292D-page 161 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) TABLE 11-1: Function Name Register Configuration Bits INT1 RPINR0 INT1R<4:0> External Interrupt 2 INT2 RPINR1 INT2R<4:0> Timer2 External Clock T2CK RPINR3 T2CKR<4:0> Input Name External Interrupt 1 Timer3 External Clock T3CK RPINR3 T3CKR<4:0> Timer4 External Clock T4CK RPINR4 T4CKR<4:0> Timer5 External Clock T5CK RPINR4 T5CKR<4:0> Input Capture 1 IC1 RPINR7 IC1R<4:0> Input Capture 2 IC2 RPINR7 IC2R<4:0> Input Capture 7 IC7 RPINR10 IC7R<4:0> IC8 RPINR10 IC8R<4:0> OCFA RPINR11 OCFAR<4:0> Input Capture 8 Output Compare Fault A UART1 Receive UART1 Clear To Send UART2 Receive U1RX RPINR18 U1RXR<4:0> U1CTS RPINR18 U1CTSR<4:0> U2RX RPINR19 U2RXR<4:0> U2CTS RPINR19 U2CTSR<4:0> SPI1 Data Input SDI1 RPINR20 SDI1R<4:0> SPI1 Clock Input SCK1 RPINR20 SCK1R<4:0> SS1 RPINR21 SS1R<4:0> SPI2 Data Input SDI2 RPINR22 SDI2R<4:0> SPI2 Clock Input SCK2 RPINR22 SCK2R<4:0> SPI2 Slave Select Input SS2 RPINR23 SS2R<4:0> DCI Serial Data Input CSDI RPINR24 CSDIR<4:0> UART2 Clear To Send SPI1 Slave Select Input DCI Serial Clock Input CSCK RPINR24 CSCKR<4:0> DCI Frame Sync Input COFS RPINR25 COFSR<4:0> ECAN1 Receive CIRX RPINR26 CIRXR<4:0> Note 1: Unless otherwise noted, all inputs use Schmitt input buffers. DS70292D-page 162 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 11.6.2.2 Output Mapping FIGURE 11-3: In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Like the RPINRx registers, each register contains sets of 5-bit fields, with each set associated with one RPn pin (see Register 11-17 through Register 11-29). The value of the bit field corresponds to one of the peripherals, and that peripheral’s output is mapped to the pin (see Table 11-2 and Figure 11-3). MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPn RPnR<4:0> default 0 U1TX Output enable 3 U1RTS Output enable 4 Output Enable The list of peripherals for output mapping also includes a null value of ‘00000’ because of the mapping technique. This permits any given pin to remain unconnected from the output of any of the pin selectable peripherals. OC4 Output 21 default 0 U1TX Output 3 U1RTS Output 4 RPn Output Data OC4 Output TABLE 11-2: 21 OUTPUT SELECTION FOR REMAPPABLE PIN (RPn) Function RPnR<4:0> Output Name NULL 00000 RPn tied to default port pin C1OUT 00001 RPn tied to Comparator1 Output C2OUT 00010 RPn tied to Comparator2 Output U1TX 00011 RPn tied to UART1 Transmit U1RTS 00100 RPn tied to UART1 Ready To Send U2TX 00101 RPn tied to UART2 Transmit U2RTS 00110 RPn tied to UART2 Ready To Send SDO1 00111 RPn tied to SPI1 Data Output SCK1 01000 RPn tied to SPI1 Clock Output SS1 01001 RPn tied to SPI1 Slave Select Output SDO2 01010 RPn tied to SPI2 Data Output SCK2 01011 RPn tied to SPI2 Clock Output SS2 01100 RPn tied to SPI2 Slave Select Output CSDO 01101 RPn tied to DCI Serial Data Output CSCK 01110 RPn tied to DCI Serial Clock Output COFS 01111 RPn tied to DCI Frame Sync Output C1TX 10000 RPn tied to ECAN1 Transmit OC1 10010 RPn tied to Output Compare 1 OC2 10011 RPn tied to Output Compare 2 OC3 10100 RPn tied to Output Compare 3 OC4 10101 RPn tied to Output Compare 4 2009 Microchip Technology Inc. Preliminary DS70292D-page 163 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 11.6.3 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. dsPIC33F devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • Continuous state monitoring • Configuration bit pin select lock 11.6.3.1 Control Register Lock To set or clear IOLOCK, a specific command sequence must be executed: Write 0x46 to OSCCON<7:0>. Write 0x57 to OSCCON<7:0>. Clear (or set) IOLOCK as a single operation. Note: Continuous State Monitoring In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a configuration mismatch Reset is triggered. 11.6.3.3 Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON<6>). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. 1. 2. 3. 11.6.3.2 Configuration Bit Pin Select Lock As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (FOSC<IOL1WAY>) configuration bit blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure does not execute, and the peripheral pin select control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. MPLAB® C30 provides built-in C language functions for unlocking the OSCCON register: __builtin_write_OSCCONL(value) __builtin_write_OSCCONH(value) See MPLAB Help for more information. Unlike the similar sequence with the oscillator’s LOCK bit, IOLOCK remains in one state until changed. This allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. DS70292D-page 164 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 11.7 Peripheral Pin Select Registers The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 family of devices implement 33 registers for remappable peripheral configuration: • 16 Input Remappable Peripheral Registers: - RPINR0-RPINR1, RPINR3-RPINR4, RPINR7, RPINR10-RPINR11 and PRINR18-RPINR26 • 13 Output Remappable Peripheral Registers: - RPOR0-RPOR12 Note: Input and Output Register values can only be changed if the IOLOCK bit (OSCCON<6>) is set to ‘0’. See Section 11.6.3.1 “Control Register Lock” for a specific command sequence. REGISTER 11-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 INT1R<4:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. Preliminary DS70292D-page 165 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 INT2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70292D-page 166 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T3CKR<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T2CKR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 2009 Microchip Technology Inc. Preliminary DS70292D-page 167 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-4: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T5CKR<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T4CKR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T5CKR<4:0>: Assign Timer5 External Clock (T5CK) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 T4CKR<4:0>: Assign Timer4 External Clock (T4CK) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70292D-page 168 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC2R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC2R<4:0>: Assign Input Capture 2 (IC2) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25. • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 2009 Microchip Technology Inc. Preliminary x = Bit is unknown DS70292D-page 169 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-6: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC8R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC7R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC8R<4:0>: Assign Input Capture 8 (IC8) to the corresponding pin RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding pin RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70292D-page 170 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-7: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OCFAR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign Output Compare A (OCFA) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 2009 Microchip Technology Inc. Preliminary DS70292D-page 171 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-8: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1RXR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U1CTSR<4:0>: Assign UART1 Clear to Send (U1CTS) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70292D-page 172 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-9: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U2CTSR<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U2RXR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U2CTSR<4:0>: Assign UART2 Clear to Send (U2CTS) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 U2RXR<4:0>: Assign UART2 Receive (U2RX) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 2009 Microchip Technology Inc. Preliminary DS70292D-page 173 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-10: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SCK1R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SDI1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 SCK1R<4:0>: Assign SPI1 Clock Input (SCK1) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70292D-page 174 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-11: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SS1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select Input (SS1) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 2009 Microchip Technology Inc. Preliminary DS70292D-page 175 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-12: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SCK2R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SDI2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 SCK2R<4:0>: Assign SPI2 Clock Input (SCK2) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70292D-page 176 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-13: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SS2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS2R<4:0>: Assign SPI2 Slave Select Input (SS2) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 2009 Microchip Technology Inc. Preliminary DS70292D-page 177 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-14: RPINR24: PERIPHERAL PIN SELECT INPUT REGISTER 24 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CSCKR<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CSDIR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 CSCKR<4:0>: Assign DCI Serial Clock Input (CSCK) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 4-0 CSDIR<4:0>: Assign DCI Serial Data Input (CSDI) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70292D-page 178 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-15: RPINR25: PERIPHERAL PIN SELECT INPUT REGISTER 25 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 COFSR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 COFSR<4:0>: Assign DCI Frame Sync Input (COFS) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 REGISTER 11-16: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 C1RXR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 C1RXR<4:0>: Assign ECAN1Receive (C1RX) to the corresponding RPn pin 11111 = Input tied to VSS 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 Note 1: This register is disabled on devices without ECAN™ module. 2009 Microchip Technology Inc. Preliminary DS70292D-page 179 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-17: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP1R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP0R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table 11-2 for peripheral function numbers) REGISTER 11-18: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP3R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 11-2 for peripheral function numbers) DS70292D-page 180 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-19: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP5R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP4R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table 11-2 for peripheral function numbers) REGISTER 11-20: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP7R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP6R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 11-2 for peripheral function numbers) 2009 Microchip Technology Inc. Preliminary DS70292D-page 181 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-21: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP9R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP8R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table 11-2 for peripheral function numbers) REGISTER 11-22: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP11R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP10R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 11-2 for peripheral function numbers) DS70292D-page 182 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-23: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP13R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP12R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table 11-2 for peripheral function numbers) REGISTER 11-24: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP15R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP14R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 11-2 for peripheral function numbers) 2009 Microchip Technology Inc. Preliminary DS70292D-page 183 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-25: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8(1) U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP17R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP16R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP16R<4:0>: Peripheral Output Function is Assigned to RP16 Output Pin bits (see Table 11-2 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. REGISTER 11-26: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9(1) U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP19R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP18R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table 11-2 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. DS70292D-page 184 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-27: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10(1) U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP21R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP20R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP21R<4:0>: Peripheral Output Function is Assigned to RP21 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table 11-2 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. REGISTER 11-28: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11(1) U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP23R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP22R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 11-2 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. 2009 Microchip Technology Inc. Preliminary DS70292D-page 185 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 11-29: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12(1) U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP25R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP24R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP25R<4:0>: Peripheral Output Function is Assigned to RP25 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 11-2 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. DS70292D-page 186 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 12.0 TIMER1 The unique features of Timer1 allow it to be used for Real-Time Clock (RTC) applications. A block diagram of Timer1 is shown in Figure 12-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 11. Timers” (DS70205) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). The Timer1 module can operate in one of the following modes: • • • • In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous and Asynchronous Counter modes, the input clock is derived from the external clock input at the T1CK pin. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Timer modes are determined by the following bits: • Timer Clock Source Control bit (TCS): T1CON<1> • Timer Synchronization Control bit (TSYNC): T1CON<2> • Timer Gate Control bit (TGATE): T1CON<6> The Timer1 module is a 16-bit timer, which can serve as the time counter for the real-time clock, or operate as a free-running interval timer/counter. Timer control bit setting for different operating modes are given in the Table 12-1. The Timer1 module has the following unique features over other timers: TABLE 12-1: • Can be operated from the low power 32 kHz crystal oscillator available on the device • Can be operated in Asynchronous Counter mode from an external clock source. • The external clock input (T1CK) can optionally be synchronized to the internal device clock and the clock synchronization is performed after the prescaler. FIGURE 12-1: Timer mode Gated Timer mode Synchronous Counter mode Asynchronous Counter mode Mode TIMER MODE SETTINGS TCS TGATE TSYNC Timer 0 0 x Gated timer 0 1 x Synchronous counter 1 x 1 Asynchronous counter 1 x 0 16-BIT TIMER1 MODULE BLOCK DIAGRAM Falling Edge Detect Gate Sync 1 Set T1IF flag 0 FCY Prescaler (/n) 10 00 TCKPS<1:0> TMR1 Reset TGATE 1 SOSCO/ T1CK x1 Prescaler (/n) Sync TSYNC TCKPS<1:0> SOSCI Comparator 0 Equal TGATE TCS PR1 LPOSCEN(1) Note 1: Refer to Section 9.0 “Oscillator Configuration” for information on enabling the secondary oscillator. 2009 Microchip Technology Inc. Preliminary DS70292D-page 187 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> U-0 R/W-0 R/W-0 U-0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When T1CS = 1: This bit is ignored. When T1CS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = External clock from pin T1CK (on the rising edge) 0 = Internal clock (FCY) bit 0 Unimplemented: Read as ‘0’ DS70292D-page 188 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 13.0 TIMER2/3 AND TIMER4/5 FEATURE • A Type B timer can be concatenated with a Type C timer to form a 32-bit timer • The external clock input (TxCK) is always synchronized to the internal device clock and the clock synchronization is performed after the prescaler. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 11. Timers” (DS70205) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). A block diagram of the Type B timer is shown in Figure 13-1. Timer3 and Timer5 are Type C timers with the following specific features: • A Type C timer can be concatenated with a Type B timer to form a 32-bit timer • At least one Type C timer has the ability to trigger an A/D conversion. • The external clock input (TxCK) is always synchronized to the internal device clock and the clock synchronization is performed before the prescaler 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. A block diagram of the Type C timer is shown in Figure 13-2. Timer2 and Timer4 are Type B timers with the following specific features: FIGURE 13-1: TYPE B TIMER BLOCK DIAGRAM (x = 2 or 4) Gate Sync FCY Falling Edge Detect Sync Reset TMRx 00 TCKPS<1:0> TGATE x1 Comparator TxCK TCKPS<1:0> Set TxIF flag 0 10 Prescaler (/n) Prescaler (/n) 1 Equal TGATE TCS PRx FIGURE 13-2: TYPE C TIMER BLOCK DIAGRAM (x = 3 or 5) Gate Sync FCY Falling Edge Detect Prescaler (/n) 1 0 10 00 Set TxIF flag TMRx Reset TGATE TCKPS<1:0> Sync Prescaler (/n) x1 Comparator TxCK TCKPS<1:0> ADC SOC Trigger TGATE TCS 2009 Microchip Technology Inc. Equal Preliminary PRx DS70292D-page 189 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 The Timer2/3 and Timer4/5 modules can operate in one of the following modes: • Timer mode • Gated Timer mode • Synchronous Counter mode In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous Counter mode, the input clock is derived from the external clock input at TxCK pin. For interrupt control, the combined 32-bit timer uses the interrupt enable, interrupt flag and interrupt priority control bits of the Type C timer. The interrupt control and status bits for the Type B timer are ignored during 32-bit timer operation. The Type B and Type C timers that can be combined to form a 32-bit timer are listed in Table 13-2. TABLE 13-2: The timer modes are determined by the following bits: TYPE B Timer (lsw) TYPE C Timer (msw) Timer2 Timer3 Timer4 Timer5 • TCS (TxCON<1>): Timer Clock Source Control bit • TGATE (TxCON<6>): Timer Gate Control bit Timer control bit settings for different operating modes are given in the Table 13-1. TABLE 13-1: TIMER MODE SETTINGS Mode TCS TGATE Timer 0 0 Gated timer 0 1 Synchronous counter 1 x 13.1 3. 4. 5. 6. 1. 2. 16-Bit Operation Clear the T32 bit corresponding to that timer. Select the timer prescaler ratio using the TCKPS<1:0> bits. Set the Clock and Gating modes using the TCS and TGATE bits. Load the timer period value into the PRx register. If interrupts are required, set the interrupt enable bit, TxIE. Use the priority bits, TxIP<2:0>, to set the interrupt priority. Set the TON bit. Note: 13.2 A block diagram representation of the 32-bit timer module is shown in Figure 13-3. The 32-bit timer module can operate in one of the following modes: • Timer mode • Gated Timer mode • Synchronous Counter mode To configure the features of Timer2/3 or Timer4/5 for 32-bit operation: To configure any of the timers for individual 16-bit operation: 1. 2. 32-BIT TIMER Only Timer2 and Timer3 can trigger a DMA data transfer. 3. 4. 5. 6. Set the T32 control bit. Select the prescaler ratio for Timer2 or Timer4 using the TCKPS<1:0> bits. Set the Clock and Gating modes using the corresponding TCS and TGATE bits. Load the timer period value. PR3 or PR5 contains the most significant word of the value, while PR2 or PR4 contains the least significant word. If interrupts are required, set the interrupt enable bits, T3IE or T5IE. Use the priority bits, T3IP<2:0> or T5IP<2:0> to set the interrupt priority. While Timer2 or Timer4 controls the timer, the interrupt appears as a Timer3 or Timer5 interrupt. Set the corresponding TON bit. The timer value at any point is stored in the register pair, TMR3:TMR2 or TMR5:TMR4, which always contains the most significant word of the count, while TMR2 or TMR4 contains the least significant word. 32-Bit Operation A 32-bit timer module can be formed by combining a Type B and a Type C 16-bit timer module. For 32-bit timer operation, the T32 control bit in the Type B Timer Control (TxCON<3>) register must be set. The Type C timer holds the most significant word (msw) and the Type B timer holds the least significant word (lsw) for 32-bit operation. When configured for 32-bit operation, only the Type B Timer Control (TxCON) register bits are required for setup and control. Type C timer control register bits are ignored (except TSIDL bit). DS70292D-page 190 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 13-3: 32-BIT TIMER BLOCK DIAGRAM Falling Edge Detect Gate Sync 1 Set TyIF Flag PRy PRx 0 Equal Comparator FCY Prescaler (/n) lsw 00 TCKPS<1:0> Prescaler (/n) TGATE 10 Sync TMRx msw Reset ADC SOC trigger TMRy x1 TxCK TMRyHLD TCKPS<1:0> TGATE TCS Data Bus <15:0> Note 1: ADC trigger is available only on TMR3:TMR2 and TMR5:TMR2 32-bit timers 2: Timer x is a Type B Timer (x = 2 and 4) 3: Timer y is a Type C Timer (y = 3 and 5) 2009 Microchip Technology Inc. Preliminary DS70292D-page 191 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 13-1: TxCON: TIMER CONTROL REGISTER (x = 2 or 4, y = 3 or 5) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> R/W-0 U-0 R/W-0 U-0 T32 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timerx On bit When T32 = 1 (in 32-bit Timer mode): 1 = Starts 32-bit TMRx:TMRy timer pair 0 = Stops 32-bit TMRx:TMRy timer pair When T32 = 0 (in 16-bit Timer mode): 1 = Starts 16-bit timer 0 = Stops 16-bit timer bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue timer operation when device enters Idle mode 0 = Continue timer operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 T32: 32-bit Timerx Mode Select bit 1 = TMRx and TMRy form a 32-bit timer 0 = TMRx and TMRy form separate 16-bit timer bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit 1 = External clock from TxCK pin 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ DS70292D-page 192 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 13-2: R/W-0 TxCON: TIMER CONTROL REGISTER (x = 3 OR 5) U-0 TON(2) R/W-0 — TSIDL U-0 U-0 U-0 U-0 U-0 — — — — — (1) bit 15 bit 8 U-0 R/W-0 (2) — TGATE R/W-0 R/W-0 TCKPS<1:0> (2) U-0 — U-0 — R/W-0 (2) TCS bit 7 U-0 — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(2) 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue timer operation when device enters Idle mode 0 = Continue timer operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit(2) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits(2) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit(2) 1 = External clock from TxCK pin 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ x = Bit is unknown Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, these bits have no effect. 2009 Microchip Technology Inc. Preliminary DS70292D-page 193 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 194 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 14.0 INPUT CAPTURE - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin 2. Capture timer value on every edge (rising and falling) 3. Prescaler Capture Event modes: - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 12. Input Capture” (DS70198) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). Each input capture channel can select one of two 16bit timers (Timer2 or Timer3) for the time base. The selected timer can use either an internal or external clock. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. Other operational features include: • Device wake-up from capture pin during CPU Sleep and Idle modes • Interrupt on input capture event • 4-word FIFO buffer for capture values - Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled • Use of input capture to provide additional sources of external interrupts The input capture module is useful in applications requiring frequency (period) and pulse measurement. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices support up to four input capture channels. The input capture module captures the 16-bit value of the selected Time Base register when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: 1. Note: Simple Capture Event modes: FIGURE 14-1: Only IC1 and IC2 can trigger a DMA data transfer. If DMA data transfers are required, the FIFO buffer size must be set to ‘1’ (ICI<1:0> = 00) INPUT CAPTURE BLOCK DIAGRAM ICM<2:0> Prescaler Mode (16th Rising Edge) Prescaler Mode (4th Rising Edge) 101 TMR2 TMR3 100 ICTMR Rising Edge Mode ICx pin 011 CaptureEvent Falling Edge Mode 010 To CPU FIFO CONTROL ICxBUF FIFO Edge Detection Mode ICI<1:0> 001 ICM<2:0> Set Flag ICxIF (In IFSx Register) /N Sleep/Idle Wake-up Mode 001 111 Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel. 2009 Microchip Technology Inc. Preliminary DS70292D-page 195 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 14.1 Input Capture Registers REGISTER 14-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER (x = 1, 2, 7 OR 8) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — ICSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 ICTMR R/W-0 ICI<1:0> R-0, HC R-0, HC ICOV ICBNE R/W-0 R/W-0 R/W-0 ICM<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 ICTMR: Input Capture Timer Select bits 1 = TMR2 contents are captured on capture event 0 = TMR3 contents are captured on capture event bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture Mode Select bits 111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (Rising edge detect only, all other control bits are not applicable.) 110 = Unused (module disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge (rising and falling) (ICI<1:0> bits do not control interrupt generation for this mode.) 000 = Input capture module turned off DS70292D-page 196 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 15.0 OUTPUT COMPARE The Output Compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the compare register value. The Output Compare module generates either a single output pulse or a sequence of output pulses, by changing the state of the output pin on the compare match events. The Output Compare module can also generate interrupts on compare match events. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 13. Output Compare” (DS70209) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). The Output Compare module has multiple operating modes: • • • • • • • 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 15-1: Active-Low One-Shot mode Active-High One-Shot mode Toggle mode Delayed One-Shot mode Continuous Pulse mode PWM mode without fault protection PWM mode with fault protection OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF OCxRS Output Logic OCxR 3 OCM<2:0> Mode Select Comparator 0 16 1 0 OCx Output Enable OCFA 1 16 TMR2 TMR3 2009 Microchip Technology Inc. OCTSEL S Q R TMR2 Rollover TMR3 Rollover Preliminary DS70292D-page 197 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 15.1 Output Compare Modes Note 1: Only OC1 and OC2 can trigger a DMA data transfer. Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Table 15-1 lists the different bit settings for the Output Compare modes. Figure 15-2 illustrates the output compare operation for various modes. The user application must disable the associated timer when writing to the output compare control registers to avoid malfunctions. TABLE 15-1: 2: See Section 13. “Output Compare” in the “dsPIC33F/PIC24H Family Reference Manual” (DS70209) for OCxR and OCxRS register restrictions. OUTPUT COMPARE MODES OCM<2:0> Mode OCx Pin Initial State 000 Module Disabled 001 010 Active-Low One-Shot Active-High One-Shot 011 100 Toggle Mode Delayed One-Shot 101 110 Continuous Pulse mode 0 PWM mode without fault 0, if OCxR is zero protection 1, if OCxR is non-zero PWM mode with fault protection 0, if OCxR is zero 1, if OCxR is non-zero 111 FIGURE 15-2: Controlled by GPIO register 0 1 Current output is maintained 0 OCx Interrupt Generation — OCx Rising edge OCx Falling edge OCx Rising and Falling edge OCx Falling edge OCx Falling edge No interrupt OCFA Falling edge for OC1 to OC4 OUTPUT COMPARE OPERATION Output Compare Mode enabled Timer is reset on period match OCxRS TMRy OCxR Active-Low One-Shot (OCM = 001) Active-High One-Shot (OCM = 010) Toggle Mode (OCM = 011) Delayed One-Shot (OCM = 100) Continuous Pulse Mode (OCM = 101) PWM Mode (OCM = 110 or 111) DS70292D-page 198 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 15-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2, 3 OR 4) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0 HC R/W-0 — — — OCFLT OCTSEL R/W-0 R/W-0 R/W-0 OCM<2:0> bit 7 bit 0 Legend: HC = Cleared in Hardware HS = Set in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Stop Output Compare in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-5 Unimplemented: Read as ‘0’ bit 4 OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred (This bit is only used when OCM<2:0> = 111.) bit 3 OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for Compare x 0 = Timer2 is the clock source for Compare x bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx, Fault pin enabled 110 = PWM mode on OCx, Fault pin disabled 101 = Initialize OCx pin low, generate continuous output pulses on OCx pin 100 = Initialize OCx pin low, generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled 2009 Microchip Technology Inc. Preliminary DS70292D-page 199 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 200 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 16.0 SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 18. Serial Peripheral Interface (SPI)” (DS70206) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 16-1: The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices can be serial EEPROMs, shift registers, display drivers, analog-to-digital converters, etc. The SPI module is compatible with SPI and SIOP from Motorola®. Each SPI module consists of a 16-bit shift register, SPIxSR (where x = 1 or 2), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module. Additionally, a status register, SPIxSTAT, indicates status conditions. The serial interface consists of 4 pins: • • • • SDIx (serial data input) SDOx (serial data output) SCKx (shift clock input or output) SSx (active-low slave select). In Master mode operation, SCK is a clock output. In Slave mode, it is a clock input. SPI MODULE BLOCK DIAGRAM SCKx 1:1 to 1:8 Secondary Prescaler 1:1/4/16/64 Primary Prescaler FCY SSx Sync Control Select Edge Control Clock SPIxCON1<1:0> Shift Control SPIxCON1<4:2> SDOx Enable Master Clock bit 0 SDIx SPIxSR Transfer Transfer SPIxRXB SPIxTXB SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus 2009 Microchip Technology Inc. Preliminary DS70292D-page 201 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0 — SPIROV — — — — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPIxBUF register 0 = No overflow has occurred bit 5-2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. DS70292D-page 202 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 (3) CKP SSEN R/W-0 R/W-0 MSTEN R/W-0 SPRE<2:0> R/W-0 R/W-0 (2) R/W-0 PPRE<1:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled, pin functions as I/O 0 = Internal SPI clock is enabled bit 11 DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. bit 8 CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) bit 7 SSEN: Slave Select Enable bit (Slave mode)(3) 1 = SSx pin used for Slave mode 0 = SSx pin not used by module. Pin controlled by port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: Do not set both Primary and Secondary prescalers to the value of 1:1. 3: This bit must be cleared when FRMEN = 1. 2009 Microchip Technology Inc. Preliminary DS70292D-page 203 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: Do not set both Primary and Secondary prescalers to the value of 1:1. 3: This bit must be cleared when FRMEN = 1. DS70292D-page 204 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) 0 = Framed SPIx support disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) bit 13 FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: Read as ‘0’ This bit must not be set to ‘1’ by the user application. 2009 Microchip Technology Inc. Preliminary DS70292D-page 205 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 206 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 17.0 INTER-INTEGRATED CIRCUIT™ (I2C™) 17.1 Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 19. Inter-Integrated Circuit™ (I2C™)” (DS70195) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Inter-Integrated Circuit (I2C) module provides complete hardware support for both Slave and MultiMaster modes of the I2C serial communication standard, with a 16-bit interface. The I2C module has a 2-pin interface: • The SCLx pin is clock. • The SDAx pin is data. The I2C module offers the following key features: • I2C interface supporting both Master and Slave modes of operation. • I2C Slave mode supports 7 and 10-bit address. • I2C Master mode supports 7 and 10-bit address. • I2C Port allows bidirectional transfers between master and slaves. • Serial clock synchronization for I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control). • I2C supports multi-master operation, detects bus collision and arbitrates accordingly. 2009 Microchip Technology Inc. Operating Modes The hardware fully implements all the master and slave functions of the I2C Standard and Fast mode specifications, as well as 7 and 10-bit addressing. The I2C module can operate either as a slave or a master on an I2C bus. The following types of I2C operation are supported: • • • I2C slave operation with 7-bit address I2C slave operation with 10-bit address I2C master operation with 7- or 10-bit address For details about the communication sequence in each of these modes, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip website (www.microchip.com) for the latest dsPIC33F Family Reference Manual chapters. 17.2 I2C Registers I2CxCON and I2CxSTAT are control and status registers, respectively. The I2CxCON register is readable and writable. The lower six bits of I2CxSTAT are read-only. The remaining bits of the I2CSTAT are read/write: • I2CxRSR is the shift register used for shifting data internal to the module and the user application has no access to it. • I2CxRCV is the receive buffer and the register to which data bytes are written, or from which data bytes are read. • I2CxTRN is the transmit register to which bytes are written during a transmit operation. • The I2CxADD register holds the slave address. • A status bit, ADD10, indicates 10-bit Address mode. • The I2CxBRG acts as the Baud Rate Generator (BRG) reload value. In receive operations, I2CxRSR and I2CxRCV together form a double-buffered receiver. When I2CxRSR receives a complete byte, it is transferred to I2CxRCV, and an interrupt pulse is generated. Preliminary DS70292D-page 207 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 17-1: I2C™ BLOCK DIAGRAM (X = 1) Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read Shift Clock Reload Control Write BRG Down Counter I2CxBRG Read TCY/2 DS70292D-page 208 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Set in hardware HC = Cleared in hardware -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module. All I2C™ pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters an Idle mode 0 = Continue module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave transmission. bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI mode is enabled; all addresses Acknowledged 0 = IPMI mode disabled bit 10 A10M: 10-bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled bit 8 SMEN: SMbus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMbus specification 0 = Disable SMbus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching 2009 Microchip Technology Inc. Preliminary DS70292D-page 209 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence 0 = Acknowledge sequence not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte 0 = Receive sequence not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence 0 = Stop condition not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence 0 = Repeated Start condition not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 = Start condition not in progress DS70292D-page 210 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 U-0 U-0 R/C-0 HS R-0 HSC R-0 HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0 HS R/C-0 HS R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC R-0 HSC R-0 HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ C = Clear only bit R = Readable bit W = Writable bit HS = Set in hardware HSC = Hardware set/cleared -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C™ master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware set or clear at end of slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. 2009 Microchip Technology Inc. Preliminary DS70292D-page 211 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates data transfer is output from slave 0 = Write – indicates data transfer is input to slave Hardware set or clear after reception of I 2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70292D-page 212 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSKx: Mask for Address Bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position 2009 Microchip Technology Inc. Preliminary DS70292D-page 213 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 214 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 17. UART” (DS70188) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and also includes an IrDA® encoder and decoder. FIGURE 18-1: The primary features of the UART module are: • Full-Duplex, 8- or 9-bit Data Transmission through the UxTX and UxRX pins • Even, Odd or No Parity Options (for 8-bit data) • One or two stop bits • Hardware flow control option with UxCTS and UxRTS pins • Fully integrated Baud Rate Generator with 16-bit prescaler • Baud rates ranging from 10 Mbps to 38 bps at 40 MIPS • 4-deep First-In First-Out (FIFO) Transmit Data buffer • 4-deep FIFO Receive Data buffer • Parity, framing and buffer overrun error detection • Support for 9-bit mode with Address Detect (9th bit = 1) • Transmit and Receive interrupts • A separate interrupt for all UART error conditions • Loopback mode for diagnostic support • Support for sync and break characters • Support for automatic baud rate detection • IrDA® encoder and decoder logic • 16x baud clock output for IrDA® support A simplified block diagram of the UART module is shown in Figure 18-1. The UART module consists of these key hardware elements: • Baud Rate Generator • Asynchronous Transmitter • Asynchronous Receiver UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® BCLK Hardware Flow Control UxRTS UxCTS UART Receiver UxRX UART Transmitter UxTX Note 1: Both UART1 and UART2 can trigger a DMA data transfer. 2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e., UTXISEL<1:0> = 00 and URXISEL<1:0> = 00). 2009 Microchip Technology Inc. Preliminary DS70292D-page 215 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 UARTEN(1) — USIDL IREN(2) RTSMD — R/W-0 R/W-0 UEN<1:0> bit 15 bit 8 R/W-0 HC R/W-0 R/W-0 HC R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH R/W-0 R/W-0 PDSEL<1:0> R/W-0 STSEL bit 7 bit 0 Legend: HC = Hardware cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA® encoder and decoder enabled 0 = IrDA® encoder and decoder disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin in Simplex mode 0 = UxRTS pin in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by port latches bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit 1 = UARTx continues to sample the UxRX pin; interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = No wake-up enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h) before other data; cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). DS70292D-page 216 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). 2009 Microchip Technology Inc. Preliminary DS70292D-page 217 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0 R-1 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 URXISEL<1:0> R/W-0 R-1 R-0 R-0 R/C-0 R-0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Clear only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: Transmit Polarity Inversion bit If IREN = 0: 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ If IREN = 1: 1 = IrDA® encoded UxTX Idle state is ‘1’ 0 = IrDA® encoded UxTX Idle state is ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission disabled or completed bit 10 UTXEN: Transmit Enable bit(1) 1 = Transmit enabled, UxTX pin controlled by UARTx 0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by port bit 9 UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer. Receive buffer has one or more characters. Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. DS70292D-page 218 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect 0 = Address Detect mode disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (read/clear only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1 0 transition) resets the receiver buffer and the UxRSR to the empty state. bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. 2009 Microchip Technology Inc. Preliminary DS70292D-page 219 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 220 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 19.0 ENHANCED CAN (ECAN™) MODULE Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 21. Enhanced Controller Area Network (ECAN™)” (DS70185) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 19.1 Overview The Enhanced Controller Area Network (ECAN™) module is a serial interface, useful for communicating with other CAN modules or microcontroller devices. This interface/protocol was designed to allow communications within noisy environments. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices contain up to two ECAN modules. The ECAN module is a communication controller implementing the CAN 2.0 A/B protocol, as defined in the BOSCH CAN specification. The module supports CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active versions of the protocol. The module implementation is a full CAN system. The CAN specification is not covered within this data sheet. The reader can refer to the BOSCH CAN specification for further details. The module features are as follows: • Implementation of the CAN protocol, CAN 1.2, CAN 2.0A and CAN 2.0B • Standard and extended data frames • 0-8 bytes data length • Programmable bit rate up to 1 Mbit/sec • Automatic response to remote transmission requests • Up to eight transmit buffers with application specified prioritization and abort capability (each buffer can contain up to 8 bytes of data) • Up to 32 receive buffers (each buffer can contain up to 8 bytes of data) • Up to 16 full (standard/extended identifier) acceptance filters • Three full acceptance filter masks • DeviceNet™ addressing support • Programmable wake-up functionality with integrated low-pass filter 2009 Microchip Technology Inc. • Programmable Loopback mode supports self-test operation • Signaling via interrupt capabilities for all CAN receiver and transmitter error states • Programmable clock source • Programmable link to input capture module (IC2 for CAN1) for time-stamping and network synchronization • Low-power Sleep and Idle mode The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus. Messages are transmitted by first loading the appropriate data registers. Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against filters to see if it should be received and stored in one of the receive registers. 19.2 Frame Types The ECAN module transmits various types of frames which include data messages, or remote transmission requests initiated by the user, as other frames that are automatically generated for control purposes. The following frame types are supported: • Standard Data Frame: A standard data frame is generated by a node when the node wishes to transmit data. It includes an 11bit Standard Identifier (SID), but not an 18-bit Extended Identifier (EID). • Extended Data Frame: An extended data frame is similar to a standard data frame, but includes an extended identifier as well. • Remote Frame: It is possible for a destination node to request the data from the source. For this purpose, the destination node sends a remote frame with an identifier that matches the identifier of the required data frame. The appropriate data source node sends a data frame as a response to this remote request. • Error Frame: An error frame is generated by any node that detects a bus error. An error frame consists of two fields: an error flag field and an error delimiter field. • Overload Frame: An overload frame can be generated by a node as a result of two conditions. First, the node detects a dominant bit during interframe space which is an illegal condition. Second, due to internal conditions, the node is not yet able to start reception of the next message. A node can generate a maximum of 2 sequential overload frames to delay the start of the next message. • Interframe Space: Interframe space separates a proceeding frame (of whatever type) from a following data or remote frame. Preliminary DS70292D-page 221 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 19-1: ECAN™ MODULE BLOCK DIAGRAM RxF15 Filter RxF14 Filter RxF13 Filter RxF12 Filter DMA Controller RxF11 Filter RxF10 Filter RxF9 Filter RxF8 Filter TRB7 Tx/Rx Buffer Control Register RxF7 Filter TRB6 Tx/Rx Buffer Control Register RxF6 Filter TRB5 Tx/Rx Buffer Control Register RxF5 Filter TRB4 Tx/Rx Buffer Control Register RxF4 Filter TRB3 Tx/Rx Buffer Control Register RxF3 Filter TRB2 Tx/Rx Buffer Control Register RxF2 Filter RxM2 Mask TRB1 Tx/Rx Buffer Control Register RxF1 Filter RxM1 Mask TRB0 Tx/Rx Buffer Control Register RxF0 Filter RxM0 Mask Transmit Byte Sequencer Message Assembly Buffer Control Configuration Logic CPU Bus CAN Protocol Engine Interrupts C1Tx DS70292D-page 222 C1Rx Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 19.3 Modes of Operation The ECAN module can operate in one of several operation modes selected by the user. These modes include: • • • • • • Note: Initialization mode Disable mode Normal Operation mode Listen Only mode Listen All Messages mode Loopback mode Modes are requested by setting the REQOP<2:0> bits (CiCTRL1<10:8>). Entry into a mode is Acknowledged by monitoring the OPMODE<2:0> bits (CiCTRL1<7:5>). The module does not change the mode and the OPMODE bits until a change in mode is acceptable, generally during bus Idle time, which is defined as at least 11 consecutive recessive bits. 19.3.1 INITIALIZATION MODE In the Initialization mode, the module does not transmit or receive. The error counters are cleared and the interrupt flags remain unchanged. The user application has access to Configuration registers that are access restricted in other modes. The module protects the user from accidentally violating the CAN protocol through programming errors. All registers which control the configuration of the module can not be modified while the module is on-line. The ECAN module is not allowed to enter the Configuration mode while a transmission is taking place. The Configuration mode serves as a lock to protect the following registers: • • • • • All Module Control registers Baud Rate and Interrupt Configuration registers Bus Timing registers Identifier Acceptance Filter registers Identifier Acceptance Mask registers 19.3.2 19.3.3 DISABLE MODE If the REQOP<2:0> bits (CiCTRL1<10:8>) = 001, the module enters the Module Disable mode. If the module is active, the module waits for 11 recessive bits on the CAN bus, detect that condition as an Idle bus, then accept the module disable command. When the OPMODE<2:0> bits (CiCTRL1<7:5>) = 001, that indicates whether the module successfully went into Module Disable mode. The I/O pins reverts to normal I/O function when the module is in the Module Disable mode. Typically, if the ECAN module is allowed to transmit in a particular mode of operation and a transmission is requested immediately after the ECAN module has been placed in that mode of operation, the module waits for 11 consecutive recessive bits on the bus before starting transmission. If the user switches to Disable mode within this 11-bit period, then this transmission is aborted and the corresponding TXABT bit is set and TXREQ bit is cleared. NORMAL OPERATION MODE Normal Operation mode is selected when REQOP<2:0> = 000. In this mode, the module is activated and the I/O pins assumes the CAN bus functions. The module transmits and receive CAN bus messages via the CiTX and CiRX pins. 19.3.4 LISTEN ONLY MODE If the Listen Only mode is activated, the module on the CAN bus is passive. The transmitter buffers revert to the port I/O function. The receive pins remain inputs. For the receiver, no error flags or Acknowledge signals are sent. The error counters are deactivated in this state. The Listen Only mode can be used for detecting the baud rate on the CAN bus. To use this, it is necessary that there are at least two further nodes that communicate with each other. 19.3.5 In Disable mode, the module does not transmit or receive. The module has the ability to set the WAKIF bit due to bus activity, however, any pending interrupts remains and the error counters retains their value. 2009 Microchip Technology Inc. The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2<14>) enables or disables the filter. LISTEN ALL MESSAGES MODE The module can be set to ignore all errors and receive any message. The Listen All Messages mode is activated by setting REQOP<2:0> = ‘111’. In this mode, the data which is in the message assembly buffer, until the time an error occurred, is copied in the receive buffer and can be read via the CPU interface. 19.3.6 LOOPBACK MODE If the Loopback mode is activated, the module connects the internal transmit signal to the internal receive signal at the module boundary. The transmit and receive pins revert to their port I/O function. Preliminary DS70292D-page 223 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-1: U-0 — bit 15 R-1 CiCTRL1: ECAN™ CONTROL REGISTER 1 U-0 — R/W-0 CSIDL R/W-0 ABAT r-0 — R/W-1 R-0 OPMODE<2:0> Legend: R = Readable bit -n = Value at POR bit 12 bit 11 bit 10-8 bit 7-5 bit 4 bit 3 bit 2-1 bit 0 R/W-0 bit 8 R-0 U-0 — R/W-0 CANCAP U-0 — bit 7 bit 15-14 bit 13 R/W-0 REQOP<2:0> r = Bit is reserved W = Writable bit ‘1’ = Bit is set U-0 — R/W-0 WIN bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode ABAT: Abort All Pending Transmissions bit 1 = Signal all transmit buffers to abort transmission. 0 = Module will clear this bit when all transmissions are aborted Reserved: Do not use REQOP<2:0>: Request Operation Mode bits 000 = Set Normal Operation mode 001 = Set Disable mode 010 = Set Loopback mode 011 = Set Listen Only Mode 100 = Set Configuration mode 101 = Reserved 110 = Reserved 111 = Set Listen All Messages mode OPMODE<2:0>: Operation Mode bits 000 = Module is in Normal Operation mode 001 = Module is in Disable mode 010 = Module is in Loopback mode 011 = Module is in Listen Only mode 100 = Module is in Configuration mode 101 = Reserved 110 = Reserved 111 = Module is in Listen All Messages mode Unimplemented: Read as ‘0’ CANCAP: CAN Message Receive Timer Capture Event Enable bit 1 = Enable input capture based on CAN message receive 0 = Disable CAN capture Unimplemented: Read as ‘0’ WIN: SFR Map Window Select bit 1 = Use filter window 0 = Use buffer window DS70292D-page 224 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-2: CiCTRL2: ECAN™ CONTROL REGISTER 2 U-0 — bit 15 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — R-0 R-0 R-0 DNCNT<4:0> R-0 R-0 bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up to data byte 3, bit 6 with EID<17> • • • 00001 = Compare up to data byte 1, bit 7 with EID<0> 00000 = Do not compare data bytes 2009 Microchip Technology Inc. Preliminary DS70292D-page 225 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-3: CiVEC: ECAN™ INTERRUPT CODE REGISTER U-0 — bit 15 U-0 — U-0 — R-1 U-0 — R-0 R-0 R-0 FILHIT<4:0> R-0 bit 8 R-0 R-0 R-0 ICODE<6:0> R-0 R-0 bit 7 bit 7 bit 6-0 R-0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 R-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ FILHIT<4:0>: Filter Hit Number bits 10000-11111 = Reserved 01111 = Filter 15 • • • 00001 = Filter 1 00000 = Filter 0 Unimplemented: Read as ‘0’ ICODE<6:0>: Interrupt Flag Code bits 1000101-1111111 = Reserved 1000100 = FIFO almost full interrupt 1000011 = Receiver overflow interrupt 1000010 = Wake-up interrupt 1000001 = Error interrupt 1000000 = No interrupt • • • 0010000-0111111 = Reserved 0001111 = RB15 buffer Interrupt • • • 0001001 = RB9 buffer interrupt 0001000 = RB8 buffer interrupt 0000111 = TRB7 buffer interrupt 0000110 = TRB6 buffer interrupt 0000101 = TRB5 buffer interrupt 0000100 = TRB4 buffer interrupt 0000011 = TRB3 buffer interrupt 0000010 = TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt DS70292D-page 226 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-4: R/W-0 CiFCTRL: ECAN™ FIFO CONTROL REGISTER R/W-0 DMABS<2:0> R/W-0 U-0 — U-0 — U-0 — U-0 — U-0 — bit 15 bit 8 U-0 — U-0 — U-0 — R/W-0 R/W-0 R/W-0 FSA<4:0> R/W-0 R/W-0 bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-5 bit 4-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in DMA RAM 101 = 24 buffers in DMA RAM 100 = 16 buffers in DMA RAM 011 = 12 buffers in DMA RAM 010 = 8 buffers in DMA RAM 001 = 6 buffers in DMA RAM 000 = 4 buffers in DMA RAM Unimplemented: Read as ‘0’ FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = Read buffer RB31 11110 = Read buffer RB30 • • • 00001 = Tx/Rx buffer TRB1 00000 = Tx/Rx buffer TRB0 2009 Microchip Technology Inc. Preliminary DS70292D-page 227 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-5: CiFIFO: ECAN™ FIFO STATUS REGISTER U-0 — bit 15 U-0 — U-0 — U-0 — R-0 R-0 R-0 R-0 FBP<5:0> R-0 bit 8 R-0 R-0 R-0 R-0 FNRB<5:0> R-0 bit 7 bit 7-6 bit 5-0 R-0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-8 R-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ FBP<5:0>: FIFO Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB1 buffer 000000 = TRB0 buffer Unimplemented: Read as ‘0’ FNRB<5:0>: FIFO Next Read Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB1 buffer 000000 = TRB0 buffer DS70292D-page 228 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-6: CiINTF: ECAN™ INTERRUPT FLAG REGISTER U-0 — bit 15 U-0 — R-0 TXBO R-0 TXBP R-0 RXBP R-0 TXWAR R-0 RXWAR R-0 EWARN bit 8 R/C-0 IVRIF bit 7 R/C-0 WAKIF R/C-0 ERRIF U-0 — R/C-0 FIFOIF R/C-0 RBOVIF R/C-0 RBIF R/C-0 TBIF bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ TXBO: Transmitter in Error State Bus Off bit 1 = Transmitter is in Bus Off state 0 = Transmitter is not in Bus Off state TXBP: Transmitter in Error State Bus Passive bit 1 = Transmitter is in Bus Passive state 0 = Transmitter is not in Bus Passive state RXBP: Receiver in Error State Bus Passive bit 1 = Receiver is in Bus Passive state 0 = Receiver is not in Bus Passive state TXWAR: Transmitter in Error State Warning bit 1 = Transmitter is in Error Warning state 0 = Transmitter is not in Error Warning state RXWAR: Receiver in Error State Warning bit 1 = Receiver is in Error Warning state 0 = Receiver is not in Error Warning state EWARN: Transmitter or Receiver in Error State Warning bit 1 = Transmitter or Receiver is in Error State Warning state 0 = Transmitter or Receiver is not in Error State Warning state IVRIF: Invalid Message Received Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred WAKIF: Bus Wake-up Activity Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred ERRIF: Error Interrupt Flag bit (multiple sources in CiINTF<13:8> register) 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred Unimplemented: Read as ‘0’ FIFOIF: FIFO Almost Full Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred RBOVIF: RX Buffer Overflow Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred RBIF: RX Buffer Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred TBIF: TX Buffer Interrupt Flag bit 1 = Interrupt Request has occurred 0 = Interrupt Request has not occurred 2009 Microchip Technology Inc. Preliminary DS70292D-page 229 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-7: U-0 — bit 15 U-0 — R/W-0 WAKIE Legend: R = Readable bit -n = Value at POR bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 IVRIE bit 7 bit 15-8 bit 7 CiINTE: ECAN™ INTERRUPT ENABLE REGISTER R/W-0 ERRIE R/W-0 — R/W-0 FIFOIE R/W-0 RBOVIE R/W-0 RBIE R/W-0 TBIE bit 0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ IVRIE: Invalid Message Received Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled WAKIE: Bus Wake-up Activity Interrupt Flag bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled ERRIE: Error Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled Unimplemented: Read as ‘0’ FIFOIE: FIFO Almost Full Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled RBOVIE: RX Buffer Overflow Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled RBIE: RX Buffer Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled TBIE: TX Buffer Interrupt Enable bit 1 = Interrupt Request Enabled 0 = Interrupt Request not enabled DS70292D-page 230 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-8: R-0 CiEC: ECAN™ TRANSMIT/RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 TERRCNT<7:0> R-0 R-0 R-0 bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 RERRCNT<7:0> R-0 R-0 R-0 bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown TERRCNT<7:0>: Transmit Error Count bits RERRCNT<7:0>: Receive Error Count bits REGISTER 19-9: U-0 — bit 15 CiCFG1: ECAN™ BAUD RATE CONFIGURATION REGISTER 1 U-0 — Legend: R = Readable bit -n = Value at POR bit 5-0 U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 R/W-0 SJW<1:0> bit 7 bit 15-8 bit 7-6 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 BRP<5:0> R/W-0 R/W-0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ SJW<1:0>: Synchronization Jump Width bits 11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ BRP<5:0>: Baud Rate Prescaler bits 11 1111 = TQ = 2 x 64 x 1/FCAN • • • 00 0010 = TQ = 2 x 3 x 1/FCAN 00 0001 = TQ = 2 x 2 x 1/FCAN 00 0000 = TQ = 2 x 1 x 1/FCAN 2009 Microchip Technology Inc. Preliminary DS70292D-page 231 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-10: CiCFG2: ECAN™ BAUD RATE CONFIGURATION REGISTER 2 U-0 — bit 15 R/W-x WAKFIL R/W-x SAM bit 7 bit 6 bit 5-3 bit 2-0 U-0 — R/W-x R/W-x SEG2PH<2:0> R/W-x R/W-x R/W-x SEG1PH<2:0> R/W-x R/W-x R/W-x PRSEG<2:0> R/W-x bit 0 Legend: R = Readable bit -n = Value at POR bit 13-11 bit 10-8 U-0 — bit 8 R/W-x SEG2PHTS bit 7 bit 15 bit 14 U-0 — W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ WAKFIL: Select CAN bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up Unimplemented: Read as ‘0’ SEG2PH<2:0>: Phase Segment 2 bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of SEG1PH bits or Information Processing Time (IPT), whichever is greater SAM: Sample of the CAN bus Line bit 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point SEG1PH<2:0>: Phase Segment 1 bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ PRSEG<2:0>: Propagation Time Segment bits 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ DS70292D-page 232 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-11: CiFEN1: ECAN™ ACCEPTANCE FILTER ENABLE REGISTER R/W-1 FLTEN15 bit 15 R/W-1 FLTEN14 R/W-1 FLTEN13 R/W-1 FLTEN12 R/W-1 FLTEN11 R/W-1 FLTEN10 R/W-1 FLTEN9 R/W-1 FLTEN8 bit 8 R/W-1 FLTEN7 bit 7 R/W-1 FLTEN6 R/W-1 FLTEN5 R/W-1 FLTEN4 R/W-1 FLTEN3 R/W-1 FLTEN2 R/W-1 FLTEN1 R/W-1 FLTEN0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown FLTENn: Enable Filter n to Accept Messages bits 1 = Enable Filter n 0 = Disable Filter n REGISTER 19-12: CiBUFPNT1: ECAN™ FILTER 0-3 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 F3BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F2BP<3:0> R/W-0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 F1BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F0BP<3:0> R/W-0 bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 bit 7-4 bit 3-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown F3BP<3:0>: RX Buffer mask for Filter 3 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 F2BP<3:0>: RX Buffer mask for Filter 2 (same values as bit 15-12) F1BP<3:0>: RX Buffer mask for Filter 1 (same values as bit 15-12) F0BP<3:0>: RX Buffer mask for Filter 0 (same values as bit 15-12) 2009 Microchip Technology Inc. Preliminary DS70292D-page 233 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-13: CiBUFPNT2: ECAN™ FILTER 4-7 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 F7BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F6BP<3:0> R/W-0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 F5BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F4BP<3:0> R/W-0 bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 bit 7-4 bit 3-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown F7BP<3:0>: RX Buffer mask for Filter 7 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 F6BP<3:0>: RX Buffer mask for Filter 6 (same values as bit 15-12) F5BP<3:0>: RX Buffer mask for Filter 5 (same values as bit 15-12) F4BP<3:0>: RX Buffer mask for Filter 4 (same values as bit 15-12) REGISTER 19-14: CiBUFPNT3: ECAN™ FILTER 8-11 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 F11BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F10BP<3:0> R/W-0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 F9BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F8BP<3:0> R/W-0 bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 bit 7-4 bit 3-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown F11BP<3:0>: RX Buffer mask for Filter 11 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 F10BP<3:0>: RX Buffer mask for Filter 10 (same values as bit 15-12) F9BP<3:0>: RX Buffer mask for Filter 9 (same values as bit 15-12) F8BP<3:0>: RX Buffer mask for Filter 8 (same values as bit 15-12) DS70292D-page 234 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-15: CiBUFPNT4: ECAN™ FILTER 12-15 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 F15BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F14BP<3:0> R/W-0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 F13BP<3:0> R/W-0 R/W-0 R/W-0 R/W-0 F12BP<3:0> R/W-0 bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-8 bit 7-4 bit 3-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown F15BP<3:0>: RX Buffer mask for Filter 15 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 F14BP<3:0>: RX Buffer mask for Filter 14 (same values as bit 15-12) F13BP<3:0>: RX Buffer mask for Filter 13 (same values as bit 15-12) F12BP<3:0>: RX Buffer mask for Filter 12 (same values as bit 15-12) 2009 Microchip Technology Inc. Preliminary DS70292D-page 235 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-16: CiRXFnSID: ECAN™ ACCEPTANCE FILTER STANDARD IDENTIFIER REGISTER n (n = 0-15) R/W-x SID10 bit 15 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 8 R/W-x SID2 bit 7 R/W-x SID1 R/W-x SID0 U-0 — R/W-x EXIDE U-0 — R/W-x EID17 R/W-x EID16 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4 bit 3 bit 2 bit 1-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown SID<10:0>: Standard Identifier bits 1 = Message address bit SIDx must be ‘1’ to match filter 0 = Message address bit SIDx must be ‘0’ to match filter Unimplemented: Read as ‘0’ EXIDE: Extended Identifier Enable bit If MIDE = 1 then: 1 = Match only messages with extended identifier addresses 0 = Match only messages with standard identifier addresses If MIDE = 0 then: Ignore EXIDE bit. Unimplemented: Read as ‘0’ EID<17:16>: Extended Identifier bits 1 = Message address bit EIDx must be ‘1’ to match filter 0 = Message address bit EIDx must be ‘0’ to match filter DS70292D-page 236 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-17: CiRXFnEID: ECAN™ ACCEPTANCE FILTER EXTENDED IDENTIFIER REGISTER n (n = 0-15) R/W-x EID15 bit 15 R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 8 R/W-x EID7 bit 7 R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown EID<15:0>: Extended Identifier bits 1 = Message address bit EIDx must be ‘1’ to match filter 0 = Message address bit EIDx must be ‘0’ to match filter REGISTER 19-18: CiFMSKSEL1: ECAN™ FILTER 7-0 MASK SELECTION REGISTER R/W-0 R/W-0 F7MSK<1:0> bit 15 R/W-0 R/W-0 F6MSK<1:0> R/W-0 R/W-0 F5MSK<1:0> R/W-0 R/W-0 F4MSK<1:0> bit 8 R/W-0 R/W-0 F3MSK<1:0> bit 7 R/W-0 R/W-0 F2MSK<1:0> R/W-0 R/W-0 F1MSK<1:0> R/W-0 R/W-0 F0MSK<1:0> bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-12 bit 11-10 bit 9-8 bit 7-6 bit 5-4 bit 3-2 bit 1-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown F7MSK<1:0>: Mask Source for Filter 7 bit 11 = No mask 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask F6MSK<1:0>: Mask Source for Filter 6 bit (same values as bit 15-14) F5MSK<1:0>: Mask Source for Filter 5 bit (same values as bit 15-14) F4MSK<1:0>: Mask Source for Filter 4 bit (same values as bit 15-14) F3MSK<1:0>: Mask Source for Filter 3 bit (same values as bit 15-14) F2MSK<1:0>: Mask Source for Filter 2 bit (same values as bit 15-14) F1MSK<1:0>: Mask Source for Filter 1 bit (same values as bit 15-14) F0MSK<1:0>: Mask Source for Filter 0 bit (same values as bit 15-14) 2009 Microchip Technology Inc. Preliminary DS70292D-page 237 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-19: CiFMSKSEL2: ECAN™ FILTER 15-8 MASK SELECTION REGISTER R/W-0 R/W-0 F15MSK<1:0> bit 15 R/W-0 R/W-0 F14MSK<1:0> R/W-0 R/W-0 F13MSK<1:0> R/W-0 R/W-0 F12MSK<1:0> bit 8 R/W-0 R/W-0 F11MSK<1:0> bit 7 R/W-0 R/W-0 F10MSK<1:0> R/W-0 R/W-0 F9MSK<1:0> R/W-0 R/W-0 F8MSK<1:0> bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-12 bit 11-10 bit 9-8 bit 7-6 bit 5-4 bit 3-2 bit 1-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown F15MSK<1:0>: Mask Source for Filter 15 bit 11 = No mask 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask F14MSK<1:0>: Mask Source for Filter 14 bit (same values as bit 15-14) F13MSK<1:0>: Mask Source for Filter 13 bit (same values as bit 15-14) F12MSK<1:0>: Mask Source for Filter 12 bit (same values as bit 15-14) F11MSK<1:0>: Mask Source for Filter 11 bit (same values as bit 15-14) F10MSK<1:0>: Mask Source for Filter 10 bit (same values as bit 15-14) F9MSK<1:0>: Mask Source for Filter 9 bit (same values as bit 15-14) F8MSK<1:0>: Mask Source for Filter 8 bit (same values as bit 15-14) DS70292D-page 238 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-20: CiRXMnSID: ECAN™ ACCEPTANCE FILTER MASK STANDARD IDENTIFIER REGISTER n (n = 0-2) R/W-x SID10 bit 15 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 8 R/W-x SID2 bit 7 R/W-x SID1 R/W-x SID0 U-0 — R/W-x MIDE U-0 — R/W-x EID17 R/W-x EID16 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4 bit 3 bit 2 bit 1-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown SID<10:0>: Standard Identifier bits 1 = Include bit SIDx in filter comparison 0 = Bit SIDx is don’t care in filter comparison Unimplemented: Read as ‘0’ MIDE: Identifier Receive Mode bit 1 = Match only message types (standard or extended address) that correspond to EXIDE bit in filter 0 = Match either standard or extended address message if filters match (i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID)) Unimplemented: Read as ‘0’ EID<17:16>: Extended Identifier bits 1 = Include bit EIDx in filter comparison 0 = Bit EIDx is don’t care in filter comparison REGISTER 19-21: CiRXMnEID: ECAN™ ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER REGISTER n (n = 0-2) R/W-x EID15 bit 15 R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 8 R/W-x EID7 bit 7 R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown EID<15:0>: Extended Identifier bits 1 = Include bit EIDx in filter comparison 0 = Bit EIDx is don’t care in filter comparison 2009 Microchip Technology Inc. Preliminary DS70292D-page 239 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-22: CiRXFUL1: ECAN™ RECEIVE BUFFER FULL REGISTER 1 R/C-0 RXFUL15 bit 15 R/C-0 RXFUL14 R/C-0 RXFUL13 R/C-0 RXFUL12 R/C-0 RXFUL11 R/C-0 RXFUL10 R/C-0 RXFUL9 R/C-0 RXFUL8 bit 8 R/C-0 RXFUL7 bit 7 R/C-0 RXFUL6 R/C-0 RXFUL5 R/C-0 RXFUL4 R/C-0 RXFUL3 R/C-0 RXFUL2 R/C-0 RXFUL1 R/C-0 RXFUL0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown RXFUL<15:0>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty REGISTER 19-23: CiRXFUL2: ECAN™ RECEIVE BUFFER FULL REGISTER 2 R/C-0 RXFUL31 bit 15 R/C-0 RXFUL30 R/C-0 RXFUL29 R/C-0 RXFUL28 R/C-0 RXFUL27 R/C-0 RXFUL26 R/C-0 RXFUL25 R/C-0 RXFUL24 bit 8 R/C-0 RXFUL23 bit 7 R/C-0 RXFUL22 R/C-0 RXFUL21 R/C-0 RXFUL20 R/C-0 RXFUL19 R/C-0 RXFUL18 R/C-0 RXFUL17 R/C-0 RXFUL16 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown RXFUL<31:16>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty DS70292D-page 240 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-24: CiRXOVF1: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 1 R/C-0 RXOVF15 bit 15 R/C-0 RXOVF14 R/C-0 RXOVF13 R/C-0 RXOVF12 R/C-0 RXOVF11 R/C-0 RXOVF10 R/C-0 RXOVF9 R/C-0 RXOVF8 bit 8 R/C-0 RXOVF7 bit 7 R/C-0 RXOVF6 R/C-0 RXOVF5 R/C-0 RXOVF4 R/C-0 RXOVF3 R/C-0 RXOVF2 R/C-0 RXOVF1 R/C-0 RXOVF0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown RXOVF<15:0>: Receive Buffer n Overflow bits 1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition REGISTER 19-25: CiRXOVF2: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 2 R/C-0 RXOVF31 bit 15 R/C-0 RXOVF30 R/C-0 RXOVF29 R/C-0 RXOVF28 R/C-0 RXOVF27 R/C-0 RXOVF26 R/C-0 RXOVF25 R/C-0 RXOVF24 bit 8 R/C-0 RXOVF23 bit 7 R/C-0 RXOVF22 R/C-0 RXOVF21 R/C-0 RXOVF20 R/C-0 RXOVF19 R/C-0 RXOVF18 R/C-0 RXOVF17 R/C-0 RXOVF16 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown RXOVF<31:16>: Receive Buffer n Overflow bits 1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition 2009 Microchip Technology Inc. Preliminary DS70292D-page 241 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 19-26: CiTRmnCON: ECAN™ Tx/Rx BUFFER m CONTROL REGISTER (m = 0,2,4,6; n = 1,3,5,7) R/W-0 TXENn bit 15 R-0 TXABTn R/W-0 TXENm bit 7 R-0 TXABTm(1) Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 R-0 TXLARBn R-0 TXERRn R-0 R-0 TXLARBm(1) TXERRm(1) R/W-0 TXREQn R/W-0 RTRENn R/W-0 R/W-0 TXnPRI<1:0> bit 8 R/W-0 TXREQm R/W-0 RTRENm R/W-0 R/W-0 TXmPRI<1:0> bit 0 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown See Definition for Bits 7-0, Controls Buffer n TXENm: TX/RX Buffer Selection bit 1 = Buffer TRBn is a transmit buffer 0 = Buffer TRBn is a receive buffer TXABTm: Message Aborted bit(1) 1 = Message was aborted 0 = Message completed transmission successfully TXLARBm: Message Lost Arbitration bit(1) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent TXERRm: Error Detected During Transmission bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent TXREQm: Message Send Request bit 1 = Requests that a message be sent. The bit automatically clears when the message is successfully sent 0 = Clearing the bit to ‘0’ while set requests a message abort RTRENm: Auto-Remote Transmit Enable bit 1 = When a remote transmit is received, TXREQ will be set 0 = When a remote transmit is received, TXREQ will be unaffected TXmPRI<1:0>: Message Transmission Priority bits 11 = Highest message priority 10 = High intermediate message priority 01 = Low intermediate message priority 00 = Lowest message priority Note 1: This bit is cleared when TXREQ is set. Note: The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM. DS70292D-page 242 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 19.4 ECAN Message Buffers ECAN Message Buffers are part of DMA RAM Memory. They are not ECAN special function registers. The user application must directly write into the DMA RAM area that is configured for ECAN Message Buffers. The location and size of the buffer area is defined by the user application. BUFFER 19-1: ECAN™ MESSAGE BUFFER WORD 0 U-0 — bit 15 U-0 — U-0 — R/W-x SID10 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 bit 8 R/W-x SID5 bit 7 R/W-x SID4 R/W-x SID3 R/W-x SID2 R/W-x SID1 R/W-x SID0 R/W-x SRR R/W-x IDE bit 0 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ SID<10:0>: Standard Identifier bits SRR: Substitute Remote Request bit 1 = Message will request remote transmission 0 = Normal message IDE: Extended Identifier bit 1 = Message will transmit extended identifier 0 = Message will transmit standard identifier BUFFER 19-2: ECAN™ MESSAGE BUFFER WORD 1 U-0 — bit 15 U-0 — U-0 — U-0 — R/W-x EID17 R/W-x EID16 R/W-x EID15 R/W-x EID14 bit 8 R/W-x EID13 bit 7 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 R/W-x EID7 R/W-x EID6 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-12 bit 11-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ EID<17:6>: Extended Identifier bits 2009 Microchip Technology Inc. Preliminary DS70292D-page 243 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 ( BUFFER 19-3: R/W-x EID5 bit 15 U-0 — ECAN™ MESSAGE BUFFER WORD 2 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 R/W-x RTR R/W-x RB1 bit 8 U-0 — U-0 — R/W-x RB0 R/W-x DLC3 R/W-x DLC2 R/W-x DLC1 R/W-x DLC0 bit 0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9 bit 8 bit 7-5 bit 4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown EID<5:0>: Extended Identifier bits RTR: Remote Transmission Request bit 1 = Message will request remote transmission 0 = Normal message RB1: Reserved Bit 1 User must set this bit to ‘0’ per CAN protocol. Unimplemented: Read as ‘0’ RB0: Reserved Bit 0 User must set this bit to ‘0’ per CAN protocol. DLC<3:0>: Data Length Code bits BUFFER 19-4: R/W-x ECAN™ MESSAGE BUFFER WORD 3 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 1 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Byte 1<15:8>: ECAN™ Message Byte 0 Byte 0<7:0>: ECAN Message Byte 1 DS70292D-page 244 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 BUFFER 19-5: R/W-x ECAN™ MESSAGE BUFFER WORD 4 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 3 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Byte 3<15:8>: ECAN™ Message Byte 3 Byte 2<7:0>: ECAN Message Byte 2 BUFFER 19-6: R/W-x ECAN™ MESSAGE BUFFER WORD 5 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 5 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 4 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Byte 5<15:8>: ECAN™ Message Byte 5 Byte 4<7:0>: ECAN Message Byte 4 2009 Microchip Technology Inc. Preliminary DS70292D-page 245 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 BUFFER 19-7: R/W-x ECAN™ MESSAGE BUFFER WORD 6 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 7 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 6 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Byte 7<15:8>: ECAN™ Message Byte 7 Byte 6<7:0>: ECAN Message Byte 6 BUFFER 19-8: ECAN™ MESSAGE BUFFER WORD 7 U-0 — bit 15 U-0 — U-0 — U-0 — U-0 — R/W-x R/W-x R/W-x FILHIT<4:0>(1) R/W-x R/W-x bit 8 U-0 — U-0 — U-0 — U-0 — U-0 — bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-0 U-0 — W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ FILHIT<4:0>: Filter Hit Code bits(1) Encodes number of filter that resulted in writing this buffer. Unimplemented: Read as ‘0’ Note 1: Only written by module for receive buffers, unused for transmit buffers. DS70292D-page 246 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 20.0 DATA CONVERTER INTERFACE (DCI) MODULE 20.1 The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 Data Converter Interface (DCI) module allows simple interfacing of devices, such as audio coder/decoders (Codecs), ADC and D/A converters. The following interfaces are supported: Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 20. Data Converter Interface (DCI)” (DS70288) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). • Framed Synchronous Serial Transfer (Single or Multi-Channel) • Inter-IC Sound (I2S) Interface • AC-Link Compliant mode • The DCI module provides the following general features: • Programmable word size up to 16 bits • Supports up to 16 time slots, for a maximum frame size of 256 bits • Data buffering for up to 4 samples without CPU overhead 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 20-1: Module Introduction DCI MODULE BLOCK DIAGRAM BCG Control bits SCKD FOSC/4 Sample Rate CSCK Generator FSD Word Size Selection bits Frame Length Selection bits 16-bit Data Bus DCI Mode Selection bits Frame Synchronization Generator COFS Receive Buffer Registers w/Shadow DCI Buffer Control Unit 15 Transmit Buffer Registers w/Shadow 0 DCI Shift Register CSDI CSDO 2009 Microchip Technology Inc. Preliminary DS70292D-page 247 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 20-1: DCICON1: DCI CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 DCIEN — DCISIDL — DLOOP CSCKD CSCKE COFSD bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 UNFM CSDOM DJST — — — R/W-0 R/W-0 COFSM<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DCIEN: DCI Module Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 DCISIDL: DCI Stop in Idle Control bit 1 = Module will halt in CPU Idle mode 0 = Module will continue to operate in CPU Idle mode bit 12 Unimplemented: Read as ‘0’ bit 11 DLOOP: Digital Loopback Mode Control bit 1 = Digital Loopback mode is enabled. CSDI and CSDO pins internally connected. 0 = Digital Loopback mode is disabled bit 10 CSCKD: Sample Clock Direction Control bit 1 = CSCK pin is an input when DCI module is enabled 0 = CSCK pin is an output when DCI module is enabled bit 9 CSCKE: Sample Clock Edge Control bit 1 = Data changes on serial clock falling edge, sampled on serial clock rising edge 0 = Data changes on serial clock rising edge, sampled on serial clock falling edge bit 8 COFSD: Frame Synchronization Direction Control bit 1 = COFS pin is an input when DCI module is enabled 0 = COFS pin is an output when DCI module is enabled bit 7 UNFM: Underflow Mode bit 1 = Transmit last value written to the transmit registers on a transmit underflow 0 = Transmit ‘0’s on a transmit underflow bit 6 CSDOM: Serial Data Output Mode bit 1 = CSDO pin will be tri-stated during disabled transmit time slots 0 = CSDO pin drives ‘0’s during disabled transmit time slots bit 5 DJST: DCI Data Justification Control bit 1 = Data transmission/reception is begun during the same serial clock cycle as the frame synchronization pulse 0 = Data transmission/reception is begun one serial clock cycle after frame synchronization pulse bit 4-2 Unimplemented: Read as ‘0’ bit 1-0 COFSM<1:0>: Frame Sync Mode bits 11 = 20-bit AC-Link mode 10 = 16-bit AC-Link mode 01 = I2S Frame Sync mode 00 = Multi-Channel Frame Sync mode DS70292D-page 248 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 20-2: DCICON2: DCI CONTROL REGISTER 2 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 U-0 R/W-0 — COFSG3 BLEN<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 — COFSG<2:0> R/W-0 R/W-0 R/W-0 WS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-10 BLEN<1:0>: Buffer Length Control bits 11 = Four data words will be buffered between interrupts 10 = Three data words will be buffered between interrupts 01 = Two data words will be buffered between interrupts 00 = One data word will be buffered between interrupts bit 9 Unimplemented: Read as ‘0’ bit 8-5 COFSG<3:0>: Frame Sync Generator Control bits 1111 = Data frame has 16 words • • • 0010 = Data frame has 3 words 0001 = Data frame has 2 words 0000 = Data frame has 1 word bit 4 Unimplemented: Read as ‘0’ bit 3-0 WS<3:0>: DCI Data Word Size bits 1111 = Data word size is 16 bits • • • 0100 = Data word size is 5 bits 0011 = Data word size is 4 bits 0010 = Invalid Selection. Do not use. Unexpected results may occur. 0001 = Invalid Selection. Do not use. Unexpected results may occur. 0000 = Invalid Selection. Do not use. Unexpected results may occur. 2009 Microchip Technology Inc. Preliminary x = Bit is unknown DS70292D-page 249 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 20-3: DCICON3: DCI CONTROL REGISTER 3 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 BCG<11:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BCG<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 BCG<11:0>: DCI Bit Clock Generator Control bits DS70292D-page 250 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 20-4: DCISTAT: DCI STATUS REGISTER U-0 U-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 SLOT<3:0> bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ROV RFUL TUNF TMPTY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SLOT<3:0>: DCI Slot Status bits 1111 = Slot 15 is currently active • • • 0010 = Slot 2 is currently active 0001 = Slot 1 is currently active 0000 = Slot 0 is currently active bit 7-4 Unimplemented: Read as ‘0’ bit 3 ROV: Receive Overflow Status bit 1 = A receive overflow has occurred for at least one receive register 0 = A receive overflow has not occurred bit 2 RFUL: Receive Buffer Full Status bit 1 = New data is available in the receive registers 0 = The receive registers have old data bit 1 TUNF: Transmit Buffer Underflow Status bit 1 = A transmit underflow has occurred for at least one transmit register 0 = A transmit underflow has not occurred bit 0 TMPTY: Transmit Buffer Empty Status bit 1 = The transmit registers are empty 0 = The transmit registers are not empty 2009 Microchip Technology Inc. Preliminary x = Bit is unknown DS70292D-page 251 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 20-5: RSCON: DCI RECEIVE SLOT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown RSE<15:0>: Receive Slot Enable bits 1 = CSDI data is received during the individual time slot n 0 = CSDI data is ignored during the individual time slot n REGISTER 20-6: TSCON: DCI TRANSMIT SLOT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TSE7 TSE6 TSE5 TSE4 TSE3 TSE2 TSE1 TSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown TSE<15:0>: Transmit Slot Enable Control bits 1 = Transmit buffer contents are sent during the individual time slot n 0 = CSDO pin is tri-stated or driven to logic ‘0’, during the individual time slot, depending on the state of the CSDOM bit DS70292D-page 252 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 21.0 10-BIT/12-BIT ANALOG-TODIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 16. Analog-to-Digital Converter (ADC)” (DS70183) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). Depending on the particular device pinout, the ADC can have up to 13 analog input pins, designated AN0 through AN12. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs can be shared with other analog input pins. The actual number of analog input pins and external voltage reference input configuration depends on the specific device. Block diagrams of the ADC module are shown in Figure 21-1 and Figure 21-2. 21.2 The following configuration steps should be performed. 1. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices have up to 13 ADC input channels. The AD12B bit (AD1CON1<10>) allows each of the ADC modules to be configured by the user as either a 10-bit, 4-sample/hold ADC (default configuration) or a 12-bit, 1-sample/hold ADC. Note: 21.1 The ADC module needs to be disabled before modifying the AD12B bit. Key Features 2. The 10-bit ADC configuration has the following key features: • • • • • • • • • • Successive Approximation (SAR) conversion Conversion speeds of up to 1.1 Msps Up to 13 analog input pins External voltage reference input pins Simultaneous sampling of up to four analog input pins Automatic Channel Scan mode Selectable conversion trigger source Selectable Buffer Fill modes Four result alignment options (signed/unsigned, fractional/integer) Operation during CPU Sleep and Idle modes The 12-bit ADC configuration supports all the above features, except: • In the 12-bit configuration, conversion speeds of up to 500 ksps are supported • There is only one sample/hold amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported. 2009 Microchip Technology Inc. ADC Initialization Configure the ADC module: a) Select port pins as analog inputs (AD1PCFGH<15:0> or AD1PCFGL<15:0>) b) Select voltage reference source to match expected range on analog inputs (AD1CON2<15:13>) c) Select the analog conversion clock to match desired data rate with processor clock (AD1CON3<7:0>) d) Determine how many S/H channels are used (AD1CON2<9:8> and AD1PCFGH<15:0> or AD1PCFGL<15:0>) e) Select the appropriate sample/conversion sequence (AD1CON1<7:5> and AD1CON3<12:8>) f) Select how conversion results are presented in the buffer (AD1CON1<9:8>) g) Turn on ADC module (AD1CON1<15>) Configure ADC interrupt (if required): a) Clear the AD1IF bit b) Select ADC interrupt priority 21.3 ADC and DMA If more than one conversion result needs to be buffered before triggering an interrupt, DMA data transfers can be used. ADC1 can trigger a DMA data transfer. If ADC1 is selected as the DMA IRQ source, a DMA transfer occurs when the AD1IF bit gets set as a result of an ADC1 sample conversion sequence. The SMPI<3:0> bits (AD1CON2<5:2>) are used to select how often the DMA RAM buffer pointer is incremented. The ADDMABM bit (AD1CON1<12>) determines how the conversion results are filled in the DMA RAM buffer area being used for ADC. If this bit is set, DMA buffers are written in the order of conversion. The module provides an address to the DMA channel that is the same as the address used for the non-DMA standalone buffer. If the ADDMABM bit is cleared, then DMA buffers are written in Scatter/Gather mode. The module provides a scatter/gather address to the DMA channel, based on the index of the analog input and the size of the DMA buffer. Preliminary DS70292D-page 253 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 21-1: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ32GP304, dsPIC33FJ64GP204/804 AND dsPIC33FJ128GP204/804 DEVICES AN0 AN12 S/H0 CHANNEL SCAN + CH0SA<4:0> CH0 CH0SB<4:0> - CSCNA AN1 VREFL CH0NA CH0NB AN0 (1) VREFL+(1)AVDD VREFL- AVSS AN3 S/H1 + - CH123SA CH123SB CH1(2) AN6 VCFG<2:0> AN9 VREFL VREFH VREFL CH123NA CH123NB SAR ADC ADC1BUF0 AN1 AN4 S/H2 + CH123SA CH123SB CH2(2) - AN7 AN10 VREFL CH123NA CH123NB AN2 AN5 S/H3 + CH123SA CH123SB CH3(2) - AN8 AN11 VREFL CH123NA CH123NB Alternate Input Selection Note 1: 2: VREF+, VREF- inputs can be multiplexed with other analog inputs. Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. DS70292D-page 254 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 21-2: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ32GP302, dsPIC33FJ64GP202/802 AND dsPIC33FJ128GP202/802 DEVICES AN0 AN12 S/H0 CHANNEL SCAN + CH0SA<4:0> CH0 CH0SB<4:0> - CSCNA AN1 VREFL CH0NA CH0NB AN0 (1) VREFL+(1)AVDD VREFL- AVSS AN3 S/H1 + - CH123SA CH123SB CH1(2) VCFG<2:0> AN9 VREFL VREFH VREFL CH123NA CH123NB SAR ADC ADC1BUF0 AN1 AN4 S/H2 + CH123SA CH123SB - CH2(2) AN10 VREFL CH123NA CH123NB AN2 AN5 S/H3 + CH123SA CH123SB CH3(2) - AN11 VREFL CH123NA CH123NB Alternate Input Selection Note 1: 2: VREF+, VREF- inputs can be multiplexed with other analog inputs. Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. 2009 Microchip Technology Inc. Preliminary DS70292D-page 255 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 21-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM AD1CON3<15> ADC Internal RC Clock(2) 0 TAD AD1CON3<5:0> 1 6 TOSC(1) X2 TCY ADC Conversion Clock Multiplier 1, 2, 3, 4, 5,..., 64 Note 1: Refer to Figure 8-2 for the derivation of Fosc when the PLL is enabled. If the PLL is not used, Fosc is equal to the clock source frequency. Tosc = 1/Fosc. 2: See the ADC electrical characteristics for the exact RC clock value. DS70292D-page 256 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 21-1: AD1CON1: ADC1 CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 ADON — ADSIDL ADDMABM — AD12B R/W-0 R/W-0 FORM<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 SSRC<2:0> U-0 R/W-0 R/W-0 R/W-0 HC,HS R/C-0 HC, HS — SIMSAM ASAM SAMP DONE bit 7 bit 0 Legend: HC = Cleared by hardware HS = Set by hardware C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: ADC Operating Mode bit 1 = ADC module is operating 0 = ADC is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 ADDMABM: DMA Buffer Build Mode bit 1 = DMA buffers are written in the order of conversion. The module provides an address to the DMA channel that is the same as the address used for the non-DMA stand-alone buffer 0 = DMA buffers are written in Scatter/Gather mode. The module provides a scatter/gather address to the DMA channel, based on the index of the analog input and the size of the DMA buffer bit 11 Unimplemented: Read as ‘0’ bit 10 AD12B: 10-Bit or 12-Bit Operation Mode bit 1 = 12-bit, 1-channel ADC operation 0 = 10-bit, 4-channel ADC operation bit 9-8 FORM<1:0>: Data Output Format bits For 10-bit operation: 11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s =.NOT.d<9>) 10 = Fractional (DOUT = dddd dddd dd00 0000) 01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>) 00 = Integer (DOUT = 0000 00dd dddd dddd) For 12-bit operation: 11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d<11>) 10 = Fractional (DOUT = dddd dddd dddd 0000) 01 = Signed Integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d<11>) 00 = Integer (DOUT = 0000 dddd dddd dddd) bit 7-5 SSRC<2:0>: Sample Clock Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 101 = Reserved 100 = GP timer (Timer5 for ADC1) compare ends sampling and starts conversion 011 = Reserved 010 = GP timer (Timer3 for ADC1) compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing sample bit ends sampling and starts conversion bit 4 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. Preliminary DS70292D-page 257 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 21-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ 1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01) 0 = Samples multiple channels individually in sequence bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion. SAMP bit is auto-set 0 = Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit 1 = ADC sample/hold amplifiers are sampling 0 = ADC sample/hold amplifiers are holding If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC 000, automatically cleared by hardware to end sampling and start conversion. bit 0 DONE: ADC Conversion Status bit 1 = ADC conversion cycle is completed. 0 = ADC conversion not started or in progress Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. DS70292D-page 258 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 21-2: R/W-0 AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 VCFG<2:0> U-0 U-0 R/W-0 — — CSCNA R/W-0 R/W-0 CHPS<1:0> bit 15 bit 8 R-0 U-0 BUFS — R/W-0 R/W-0 R/W-0 R/W-0 SMPI<3:0> R/W-0 R/W-0 BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown VCFG<2:0>: Converter Voltage Reference Configuration bits 000 001 010 011 1xx ADREF+ ADREF- AVDD External VREF+ AVDD External VREF+ AVDD AVSS AVSS External VREFExternal VREFAvss bit 12-11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Scan Input Selections for CH0+ during Sample A bit 1 = Scan inputs 0 = Do not scan inputs bit 9-8 CHPS<1:0>: Selects Channels Utilized bits When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’ 1x = Converts CH0, CH1, CH2 and CH3 01 = Converts CH0 and CH1 00 = Converts CH0 bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1) 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF bit 6 Unimplemented: Read as ‘0’ bit 5-2 SMPI<3:0>: Selects Increment Rate for DMA Addresses bits or number of sample/conversion operations per interrupt 1111 = Increments the DMA address or generates interrupt after completion of every 16th sample/ conversion operation 1110 = Increments the DMA address or generates interrupt after completion of every 15th sample/ conversion operation • • • 0001 = Increments the DMA address after completion of every 2nd sample/conversion operation 0000 = Increments the DMA address after completion of every sample/conversion operation bit 1 BUFM: Buffer Fill Mode Select bit 1 = Starts buffer filling at address 0x0 on first interrupt and 0x8 on next interrupt 0 = Always starts filling buffer at address 0x0 bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A 2009 Microchip Technology Inc. Preliminary DS70292D-page 259 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 21-3: R/W-0 AD1CON3: ADC1 CONTROL REGISTER 3 U-0 ADRC — U-0 R/W-0 R/W-0 — R/W-0 SAMC<4:0> R/W-0 R/W-0 (1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS<7:0> R/W-0 R/W-0 R/W-0 (2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system clock bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 SAMC<4:0>: Auto Sample Time bits(1) 11111 = 31 TAD • • • 00001 = 1 TAD 00000 = 0 TAD bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2) 11111111 = Reserved • • • • 01000000 = Reserved 00111111 = TCY · (ADCS<7:0> + 1) = 64 · TCY = TAD • • • 00000010 = TCY · (ADCS<7:0> + 1) = 3 · TCY = TAD 00000001 = TCY · (ADCS<7:0> + 1) = 2 · TCY = TAD 00000000 = TCY · (ADCS<7:0> + 1) = 1 · TCY = TAD x = Bit is unknown Note 1: This bit only used if AD1CON1<7:5> (SSRC<2:0>) = 111. 2: This bit is not used if AD1CON3<15> (ADRC) = 1. DS70292D-page 260 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 21-4: AD1CON4: ADC1 CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 DMABL<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits 111 = Allocates 128 words of buffer to each analog input 110 = Allocates 64 words of buffer to each analog input 101 = Allocates 32 words of buffer to each analog input 100 = Allocates 16 words of buffer to each analog input 011 = Allocates 8 words of buffer to each analog input 010 = Allocates 4 words of buffer to each analog input 001 = Allocates 2 words of buffer to each analog input 000 = Allocates 1 word of buffer to each analog input 2009 Microchip Technology Inc. Preliminary DS70292D-page 261 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 21-5: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 CH123NB<1:0> R/W-0 CH123SB bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 CH123NA<1:0> R/W-0 CH123SA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as ‘0’ 11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8(1) 0x = CH1, CH2, CH3 negative input is VREF- bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’ 1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 bit 7-3 Unimplemented: Read as ‘0’ bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as ‘0’ 11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8(1) 0x = CH1, CH2, CH3 negative input is VREF- bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’ 1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 Note 1: This bit setting is Reserved in dsPIC33FJ128GPX02, dsPIC33FJ64GPX02 and dsPIC33FJGPX02 (28pin) devices. DS70292D-page 262 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 21-6: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER R/W-0 U-0 U-0 CH0NB — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SB<4:0> bit 15 bit 8 R/W-0 U-0 U-0 CH0NA — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SA<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit Same definition as bit 7. bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits 01100 = Channel 0 positive input is AN12 01011 = Channel 0 positive input is AN11 • • • 01000 = Channel 0 positive input is AN8(1) 00111 = Channel 0 positive input is AN7(1) 00110 = Channel 0 positive input is AN6(1) • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREF- bit 6-5 Unimplemented: Read as ‘0’ bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits 01100 = Channel 0 positive input is AN12 01011 = Channel 0 positive input is AN11 • • • 01000 = Channel 0 positive input is AN8(1) 00111 = Channel 0 positive input is AN7(1) 00110 = Channel 0 positive input is AN6(1) • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 Note 1: x = Bit is unknown These bit settings (AN6, AN7 and AN8) are reserved on dsPIC33FJ128GPX02, dsPIC33FJ64GPX02 and dsPIC33FJ32GPX02 (28-pin) devices. 2009 Microchip Technology Inc. Preliminary DS70292D-page 263 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 21-7: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CSS12 CSS11 CSS10 CSS9 CSS8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 CSS<11:0>: ADC Input Scan Selection bits 1 = Select ANx for input scan 0 = Skip ANx for input scan x = Bit is unknown Note 1: On devices without 13 analog inputs, all AD1CSSL bits can be selected by the user application. However, inputs selected for scan without a corresponding input on device converts VREFL. 2: CSSx = ANx, where x = 0 through 12. REGISTER 21-8: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW(1,2,3) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-0 PCFG<12:0>: ADC Port Configuration Control bits 1 = Port pin in Digital mode, port read input enabled, ADC input multiplexor connected to AVSS 0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage Note 1: On devices without 13 analog inputs, all PCFG bits are R/W by user software. However, the PCFG bits are ignored on ports without a corresponding input on device. 2: PCFGx = ANx, where x = 0 through 12. 3: PCFGx bits have no effect if ADC module is disabled by setting ADxMD bit in the PMDx Register. In this case all port pins multiplexed with ANx will be in Digital mode. DS70292D-page 264 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 22.0 AUDIO DIGITAL-TO-ANALOG CONVERTER (DAC) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 33. Audio Digital-toAnalog Converter (DAC)”, (DS70211) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Audio Digital-to-Analog Converter (DAC) module is a 16-bit Delta-Sigma signal converter designed for audio applications. It has two output channels, left and right to support stereo applications. Each DAC output channel provides three voltage outputs, positive DAC output, negative DAC output, and the midpoint voltage output for the dsPIC33FJ64GP804 and dsPIC33FJ128GP804 devices. The dsPIC33FJ64GP802 and dsPIC33FJ128GP802 devices provide positive DAC output and negative DAC output voltages. 22.1 • • • • • • • • • • • Key Features Note: 22.3 The DAC module is designed specifically for audio applications and is not recommended for control type applications. DAC Output Format The DAC output data stream can be in a two’s complement signed number format or as an unsigned number format. The Audio DAC module features the ability to accept the 16-bit input data in a two’s complement signed number format or as an unsigned number format. The data formatting is controlled by the Data Format Control (FORM<8>) bit in the DAC1CON register. The supported formats are: If the FORM bit is configured for “Unsigned data” then the user input data yields the following behavior: • • • • 0xFFFF = most positive output voltage 0x8000 = mid point output voltage 0x7FFF = a value just below the midpoint 0x0000 = minimum output voltage If the FORM bit is configured for “signed data” then the user input data yields the following behavior: • • • • DAC Module Operation The functional block diagram of the Audio DAC module is shown in Figure 22-1. The Audio DAC module provides a 4-deep data input FIFO buffer for each output channel. If the DMA module and/or the processor cannot provide output data in a timely manner, and the FIFO becomes empty, the DAC accepts data from the DAC Default Data register (DACDFLT). This safety feature is useful for industrial control applications where 2009 Microchip Technology Inc. The digital interpolator up-samples the input signals, where the over-sampling ratio is 256x which creates data points between the user supplied data points. The interpolator also includes processing by digital filters to provide “noise shaping” to move the converter noise above 20 kHz (upper limit of the pass band). The output of the interpolator drives the SigmaDelta modulator. The serial data bit stream from the Sigma-Delta modulator is processed by the reconstruction filter. The differential outputs of the reconstruction filter are amplified by Op Amps to provide the required peak-to-peak voltage swing. • 1 = Signed (two’s complement) • 0 = Unsigned 16-bit resolution (14-bit accuracy) Second-Order Digital Delta-Sigma Modulator 256 X Over-Sampling Ratio 128-Tap FIR Current-Steering Analog Reconstruction Filter 100 ksps Maximum Sampling Rate User controllable Sample Clock Input Frequency 45 kHz max Differential Analog Outputs Signal-To-Noise: 90 dB 4-deep input Buffer 16-bit Processor I/O, and DMA interfaces 22.2 the DAC output controls an important processor or machinery. The DACDFLT register should be initialized with a “safe” output value. Often the safe output value is either the midpoint value (0x8000) or a zero value (0x0000). 0x7FFF = most positive output voltage 0x0000 = mid point output voltage 0xFFFF = value just below the midpoint 0x8000 = minimum output voltage The Audio DAC provides an analog output proportional to the digital input value. The maximum 100,000 samples per second (100 ksps) update rate provides good quality audio reproduction. Preliminary DS70292D-page 265 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 22.4 DAC Clock The DAC clock signal clocks the internal logic of the Audio DAC module. The data sample rate of the Audio DAC is an integer division of the rate of the DAC clock. The DAC clock is generated via a clock divider circuit that accepts an auxiliary clock from the auxiliary oscillator. FIGURE 22-1: The divisor ratio is programmed by clock divider bits (DACFDIV<6:0>) in the DAC Control register (DAC1CON). The resulting DAC clock must not exceed 25.6 MHz. If lower sample rates are to be used, then the DAC filter clock frequency may be reduced to reduce power consumption. The DAC clock frequency is 256 times the sampling frequency. BLOCK DIAGRAM OF AUDIO DIGITAL-TO-ANALOG (DAC) CONVERTER Right Channel DAC1RM DAC1RDAT D/A Amp DAC1RP DAC1RN 16-bit Data Bus Note 1 ACLK CONTROL DACFDIV<6:0> CLK DIV DACDFLT DAC1LM D/A Amp DAC1LP DAC1LN DAC1LDAT Note 1 Left Channel Note 1: FIGURE 22-2: If DAC1RDAT and DAC1LDAT are empty, data will be taken from the DACDFLT register. AUDIO DAC OUTPUT FOR RAMP INPUT (UNSIGNED) 0xFFFF DAC input Count (DAC1RDAT) 0x0000 VDACH VDACM Positive DAC Output (DAC1RP) VDACL VDACH VDACM Negative DAC Output (DAC1RN) VDACL Note: VOD+ = VDACH – VDACL, VOD- = VDACL – VDACH; refer to Audio DAC Module Specifications, Table 30-42, for typical values. DS70292D-page 266 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 22-1: DAC1CON: DAC CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 DACEN — DACSIDL AMPON — — — FORM bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 DACFDIV<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DACEN: DAC1 Enable bit 1 = Enables module 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 DACSIDL: Stop in Ideal Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 AMPON: Enable Analog Output Amplifier in Sleep Mode/Stop-in Idle Mode 1 = Analog Output Amplifier is enabled during Sleep Mode/Stop-in Idle mode 0 = Analog Output Amplifier is disabled during Sleep Mode/Stop-in Idle mode bit 11-9 Unimplemented: Read as ‘0’ bit 8 FORM: Data Format Select bit 1 = Signed integer 0 = Unsigned integer bit 7 Unimplemented: Read as ‘0’ bit 6-0 DACFDIV<6:0>: DAC Clock Divider 1111111 = Divide input clock by 128 • • • 0000101 = Divide input clock by 6 (default) • • • 0000010 = Divide input clock by 3 0000001 = Divide input clock by 2 0000000 = Divide input clock by 1 (no divide) 2009 Microchip Technology Inc. Preliminary DS70292D-page 267 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 22-2: DAC1STAT: DAC STATUS REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R-0 R-0 LOEN — LMVOEN — — LITYPE LFULL LEMPTY bit 15 bit 8 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R-0 R-0 ROEN — RMVOEN — — RITYPE RFULL REMPTY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 LOEN: Left Channel DAC output enable 1 = Positive and negative DAC outputs are enabled. 0 = DAC outputs are disabled. bit 14 Unimplemented: Read as ‘0’ bit 13 LMVOEN: Left Channel Midpoint DAC output voltage enable 1 = Midpoint DAC output is enabled. 0 = Midpoint output is disabled. bit 12-11 Unimplemented: Read as ‘0’ bit 10 LITYPE: Left Channel Type of Interrupt 1 = Interrupt if FIFO is EMPTY. 0 = Interrupt if FIFO is NOT FULL. bit 9 LFULL: Status, Left Channel Data input FIFO is FULL 1 = FIFO is Full. 0 = FIFO is not full. bit 8 LEMPTY: Status, Left Channel Data input FIFO is EMPTY 1 = FIFO is Empty. 0 = FIFO is not Empty. bit 7 ROEN: Right Channel DAC output enable 1 = Positive and negative DAC outputs are enabled. 0 = DAC outputs are disabled. bit 6 Unimplemented: Read as ‘0’ bit 5 RMVOEN: Right Channel Midpoint DAC output voltage enable 1 = Midpoint DAC output is enabled. 0 = Midpoint output is disabled. bit 4-3 Unimplemented: Read as ‘0’ bit 2 RITYPE: Right Channel Type of Interrupt 1 = Interrupt if FIFO is EMPTY. 0 = Interrupt if FIFO is NOT FULL. bit 1 RFULL: Status, Right Channel Data input FIFO is FULL 1 = FIFO is Full. 0 = FIFO is not full. bit 0 REMPTY: Status, Right Channel Data input FIFO is EMPTY 1 = FIFO is Empty. 0 = FIFO is not Empty. DS70292D-page 268 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 22-3: R/W-0 DAC1DFLT: DAC DEFAULT DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACDFLT<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACDFLT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown DACDFLT<15:0>: DAC Default Value REGISTER 22-4: R/W-0 DAC1LDAT: DAC LEFT DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACLDAT<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACLDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown DACLDAT<15:0>: Left Channel Data Port REGISTER 22-5: R/W-0 DAC1RDAT: DAC RIGHT DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACRDAT<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACRDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown DACRDAT<15:0>: Right Channel Data Port 2009 Microchip Technology Inc. Preliminary DS70292D-page 269 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 270 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 23.0 COMPARATOR MODULE Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 34. Comparator” (DS70212) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). The Comparator module provides a set of dual input comparators. The inputs to the comparator can be configured to use any one of the four pin inputs (C1IN+, C1IN-, C2IN+ and C2IN-) as well as the Comparator Voltage Reference Input (CVREF). Note: This peripheral contains output functions that may need to be configured by the peripheral pin select feature. For more information, see Section 11.6 “Peripheral Pin Select”. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 23-1: COMPARATOR I/O OPERATING MODES C1NEG C1IN+ C1IN- C1EN CMCON<6> C1INV VINC1OUT(1) C1POS C1IN+ CVREF C1 VIN+ C2NEG C2IN+ C2IN- C1OUTEN C2EN CMCON<7> C2INV VINC2OUT(1) C2POS C2IN+ CVREF C2 VIN+ C2OUTEN Note 1: This peripheral’s outputs must be assigned to an available RPn pin before use. Refer to Section 11.6 “Peripheral Pin Select” for more information. 2009 Microchip Technology Inc. Preliminary DS70292D-page 271 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 23-1: CMCON: COMPARATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CMIDL — C2EVT C1EVT C2EN C1EN R/W-0 R/W-0 C2OUTEN(1) C1OUTEN(2) bit 15 bit 8 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV C2NEG C2POS C1NEG C1POS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL: Stop in Idle Mode 1 = When device enters Idle mode, module does not generate interrupts. Module is still enabled. 0 = Continue normal module operation in Idle mode bit 14 Unimplemented: Read as ‘0’ bit 13 C2EVT: Comparator 2 Event 1 = Comparator output changed states 0 = Comparator output did not change states bit 12 C1EVT: Comparator 1 Event 1 = Comparator output changed states 0 = Comparator output did not change states bit 11 C2EN: Comparator 2 Enable 1 = Comparator is enabled 0 = Comparator is disabled bit 10 C1EN: Comparator 1 Enable 1 = Comparator is enabled 0 = Comparator is disabled bit 9 C2OUTEN: Comparator 2 Output Enable(1) 1 = Comparator output is driven on the output pad 0 = Comparator output is not driven on the output pad bit 8 C1OUTEN: Comparator 1 Output Enable(2) 1 = Comparator output is driven on the output pad 0 = Comparator output is not driven on the output pad bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 0 = C2 VIN+ > C2 VIN1 = C2 VIN+ < C2 VIN- Note 1: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPx pin. See Section 11.6 “Peripheral Pin Select” for more information. 2: If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPx pin. See Section 11.6 “Peripheral Pin Select” for more information. DS70292D-page 272 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 23-1: CMCON: COMPARATOR CONTROL REGISTER (CONTINUED) bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 0 = C1 VIN+ > C1 VIN1 = C1 VIN+ < C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 C2NEG: Comparator 2 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VINSee Figure 23-1 for the comparator modes. bit 2 C2POS: Comparator 2 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure 23-1 for the comparator modes. bit 1 C1NEG: Comparator 1 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VINSee Figure 23-1 for the comparator modes. bit 0 C1POS: Comparator 1 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure 23-1 for the comparator modes. Note 1: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPx pin. See Section 11.6 “Peripheral Pin Select” for more information. 2: If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPx pin. See Section 11.6 “Peripheral Pin Select” for more information. 2009 Microchip Technology Inc. Preliminary DS70292D-page 273 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 23.1 Comparator Voltage Reference 23.1.1 The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON<4>). CONFIGURING THE COMPARATOR VOLTAGE REFERENCE The settling time of the comparator voltage reference must be considered when changing the CVREF output. The voltage reference module is controlled through the CVRCON register (Register 23-2). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR3:CVR0), with one range offering finer resolution. VREF+ AVDD COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 CVRSRC CVRCON<3:0> CVR3 CVR2 CVR1 CVR0 FIGURE 23-2: 8R CVRSS = 0 R CVREN CVREFIN R 16-to-1 MUX R R 16 Steps R CVREF CVRCON<CVROE> R R CVRR VREFAVSS DS70292D-page 274 8R CVRSS = 1 CVRSS = 0 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 23-2: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS R/W-0 R/W-0 R/W-0 R/W-0 CVR<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ – VREF0 = Comparator reference source CVRSRC = AVDD – AVSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection 0 CVR<3:0> 15 bits When CVRR = 1: CVREF = (CVR<3:0>/ 24) (CVRSRC) When CVRR = 0: CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) (CVRSRC) 2009 Microchip Technology Inc. Preliminary DS70292D-page 275 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 276 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 24.0 REAL-TIME CLOCK AND CALENDAR (RTCC) • Time: hours, minutes, and seconds • 24-hour format (military time) • Calendar: weekday, date, month and year Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 37. Real-Time Clock and Calendar (RTCC)” of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). • Alarm configurable • Year range: 2000 to 2099 • Leap year correction • BCD format for compact firmware • Optimized for low-power operation • User calibration with auto-adjust • Calibration range: ±2.64 seconds error per month • Requirements: External 32.768 kHz clock crystal • Alarm pulse or seconds clock output on RTCC pin 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The RTCC module is intended for applications where accurate time must be maintained for extended periods of time with minimum to no intervention from the CPU. The RTCC module is optimized for low-power usage to provide extended battery lifetime while keeping track of time. This chapter discusses the Real-Time Clock and Calendar (RTCC) module, available on dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices, and its operation. The following are some of the key features of this module: FIGURE 24-1: The RTCC module is a 100-year clock and calendar with automatic leap year detection. The range of the clock is from 00:00:00 (midnight) on January 1, 2000 to 23:59:59 on December 31, 2099. The hours are available in 24-hour (military time) format. The clock provides a granularity of one second with half-second visibility to the user. RTCC BLOCK DIAGRAM RTCC Clock Domain 32.768 kHz Input from SOSC Oscillator CPU Clock Domain RCFGCAL RTCC Prescalers ALCFGRPT 0.5s RTCVAL RTCC Timer Alarm Event Comparator Compare Registers with Masks ALRMVAL Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE 2009 Microchip Technology Inc. Preliminary DS70292D-page 277 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 24.1 RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 24.1.1 By writing the ALRMVALH byte, the Alarm Pointer value, ALRMPTR<1:0> bits, decrement by one until they reach ‘00’. Once they reach ‘00’, the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed. TABLE 24-2: To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL<9:8>) to select the desired timer register pair (see Table 24-1). By writing the RTCVALH byte, the RTCC Pointer value, RTCPTR<1:0> bits, decrement by one until they reach ‘00’. Once they reach ‘00’, the MINUTES and SECONDS value will be accessible through RTCVALH and RTCVALL until the pointer value is manually changed. TABLE 24-1: RTCVAL REGISTER MAPPING ALRMPTR <1:0> RTCVAL<15:8> RTCVAL<7:0> 00 MINUTES SECONDS 01 WEEKDAY HOURS 10 MONTH DAY 11 — YEAR ALRMMIN ALRMSEC 01 ALRMWD ALRMHR 10 ALRMMNTH ALRMDAY 11 — — 24.1.2 This only applies to read operations and not write operations. WRITE LOCK In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RCFGCAL<13>) must be set (refer to Example 24-1). Note: To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL<13>) is kept clear at any other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed between the 55h/AA sequence and the setting of RTCWREN; therefore, it is recommended that code follow the procedure in Example 24-1. SETTING THE RTCWREN BIT #NVMKEY, W1 #0x55, W2 #0xAA, W3 W2, [W1] W3, [W1] RCFGCAL, #13 DS70292D-page 278 ALRMVAL<15:8> ALRMVAL<7:0> 00 Note: The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALCFGRPT<9:8>) to select the desired Alarm register pair (see Table 24-2). EXAMPLE 24-1: Alarm Value Register Window Considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the ALRMVALH or ALRMVALL bytes will decrement the ALRMPTR<1:0> value. The same applies to the RTCVALH or RTCVALL bytes with the RTCPTR<1:0> being decremented. RTCC Value Register Window RTCPTR <1:0> MOV MOV MOV MOV MOV BSET ALRMVAL REGISTER MAPPING REGISTER MAPPING ;move the address of NVMKEY into W1 ;start 55/AA sequence ;set the RTCWREN bit Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 RTCEN(2) — RTCWREN RTCSYNC HALFSEC(3) RTCOE R/W-0 R/W-0 RTCPTR<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple bit 11 HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 10 RTCOE: RTCC Output Enable bit 1 = RTCC output enabled 0 = RTCC output disabled bit 9-8 RTCPTR<1:0>: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers; the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL<15:8>: 00 = MINUTES 01 = WEEKDAY 10 = MONTH 11 = Reserved RTCVAL<7:0>: 00 = SECONDS 01 = HOURS 10 = DAY 11 = YEAR Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN = 1. 3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. 2009 Microchip Technology Inc. Preliminary DS70292D-page 279 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-1: bit 7-0 RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute • • • 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute • • • 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN = 1. 3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. DS70292D-page 280 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers x = Bit is unknown Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set. 2009 Microchip Technology Inc. Preliminary DS70292D-page 281 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 ALRMEN CHIME R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMASK<3:0> R/W-0 ALRMPTR<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and CHIME = 0) 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit 1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every 4 years) 101x = Reserved – do not use 11xx = Reserved – do not use bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers; the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL<15:8>: 00 = ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = Unimplemented ALRMVAL<7:0>: 00 = ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = Unimplemented bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times • • • 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1. DS70292D-page 282 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-4: RTCVAL (WHEN RTCPTR<1:0> = 11): YEAR VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN<3:0> R/W-x R/W-x YRONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit; contains a value from 0 to 9 bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit; contains a value from 0 to 9 Note 1: A write to the YEAR register is only allowed when RTCWREN = 1. REGISTER 24-5: RTCVAL (WHEN RTCPTR<1:0> = 10): MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R-x — — — MTHTEN0 R-x R-x R-x R-x MTHONE<3:0> bit 15 bit 8 U-0 U-0 — — R/W-x R/W-x R/W-x DAYTEN<1:0> R/W-x R/W-x R/W-x DAYONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1 bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit; contains a value from 0 to 9 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3 bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN = 1. 2009 Microchip Technology Inc. Preliminary DS70292D-page 283 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-6: RTCVAL (WHEN RTCPTR<1:0> = 01): WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 — — — — — R/W-x R/W-x R/W-x WDAY<2:0> bit 15 bit 8 U-0 U-0 — — R/W-x R/W-x R/W-x HRTEN<1:0> R/W-x R/W-x R/W-x HRONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2 bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN = 1. REGISTER 24-7: U-0 RTCVAL (WHEN RTCPTR<1:0> = 00): MINUTES AND SECONDS VALUE REGISTER R/W-x — R/W-x R/W-x R/W-x MINTEN<2:0> R/W-x R/W-x R/W-x MINONE<3:0> bit 15 bit 8 U-0 R/W-x — R/W-x R/W-x R/W-x SECTEN<2:0> R/W-x R/W-x R/W-x SECONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5 bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9 bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5 bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; contains a value from 0 to 9 DS70292D-page 284 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-8: ALRMVAL (WHEN ALRMPTR<1:0> = 10): ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x — — — MTHTEN0 R/W-x R/W-x R/W-x R/W-x MTHONE<3:0> bit 15 bit 8 U-0 U-0 — — R/W-x R/W-x R/W-x R/W-x DAYTEN<1:0> R/W-x R/W-x DAYONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1 bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit; contains a value from 0 to 9 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3 bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN = 1. REGISTER 24-9: ALRMVAL (WHEN ALRMPTR<1:0> = 01): ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 — — R/W-x R/W-x R/W-x HRTEN<1:0> R/W-x R/W-x R/W-x HRONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2 bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN = 1. 2009 Microchip Technology Inc. Preliminary DS70292D-page 285 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-10: ALRMVAL (WHEN ALRMPTR<1:0> = 00): ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x — R/W-x R/W-x R/W-x MINTEN<2:0> R/W-x R/W-x R/W-x MINONE<3:0> bit 15 bit 8 U-0 R/W-x — R/W-x R/W-x R/W-x SECTEN<2:0> R/W-x R/W-x R/W-x SECONE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5 bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9 bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5 bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; contains a value from 0 to 9 DS70292D-page 286 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 25.0 PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR 25.1 The module implements a software configurable CRC generator. The terms of the polynomial and its length can be programmed using the CRCXOR (X<15:1>) bits and the CRCCON (PLEN<3:0>) bits, respectively. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 36. Programmable Cyclic Redundancy Check (CRC)” (DS70298) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). EQUATION 25-1: x 16 CRC EQUATION +x 12 5 +x +1 To program this polynomial into the CRC generator, the CRC register bits should be set as shown in Table 25-1. TABLE 25-1: 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. EXAMPLE CRC SETUP Bit Name Bit Value PLEN<3:0> 1111 X<15:1> 000100000010000 For the value of X<15:1>, the 12th bit and the 5th bit are set to ‘1’, as required by the CRC equation. The 0th bit required by the CRC equation is always XORed. For a 16-bit polynomial, the 16th bit is also always assumed to be XORed; therefore, the X<15:1> bits do not have the 0th bit or the 16th bit. The programmable CRC generator offers the following features: • User-programmable polynomial CRC equation • Interrupt output • Data FIFO FIGURE 25-1: Overview The topology of a standard CRC generator is shown in Figure 25-2. CRC SHIFTER DETAILS PLEN<3:0> 0 1 2 15 CRC Shift Register Hold XOR DOUT OUT IN BIT 0 p_clk X1 0 1 Hold OUT IN BIT 1 p_clk X2 Hold 0 1 OUT IN BIT 2 X3 X15 0 0 1 1 p_clk Hold OUT IN BIT 15 p_clk CRC Read Bus CRC Write Bus 2009 Microchip Technology Inc. Preliminary DS70292D-page 287 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1 FIGURE 25-2: XOR D Q D Q D Q D Q D Q SDOx BIT 0 BIT 4 BIT 5 BIT 12 BIT 15 p_clk p_clk p_clk p_clk p_clk CRC Read Bus CRC Write Bus 25.2 25.2.1 User Interface To empty words already written into a FIFO, the CRCGO bit must be set to ‘1’ and the CRC shifter allowed to run until the CRCMPT bit is set. DATA INTERFACE To start serial shifting, a ‘1’ must be written to the CRCGO bit. The module incorporates a FIFO that is 8 deep when PLEN (PLEN<3:0>) > 7, and 16 deep, otherwise. The data for which the CRC is to be calculated must first be written into the FIFO. The smallest data element that can be written into the FIFO is one byte. For example, if PLEN = 5, then the size of the data is PLEN + 1 = 6. The data must be written as follows: If a word is written when the CRCFUL bit is set, the VWORD Pointer will roll over to 0. The hardware will then behave as if the FIFO is empty. However, the condition to generate an interrupt will not be met; therefore, no interrupt will be generated (See Section 25.2.2 “Interrupt Operation”). At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done. data[5:0] = crc_input[5:0] data[7:6] = ‘bxx Once data is written into the CRCWDAT MSb (as defined by PLEN), the value of VWORD (VWORD<4:0>) increments by one. The serial shifter starts shifting data into the CRC engine when CRCGO = 1 and VWORD > 0. When the MSb is shifted out, VWORD decrements by one. The serial shifter continues shifting until the VWORD reaches 0. Therefore, for a given value of PLEN, it will take (PLEN + 1) * VWORD number of clock cycles to complete the CRC calculations. When VWORD reaches 8 (or 16), the CRCFUL bit will be set. When VWORD reaches 0, the CRCMPT bit will be set. To continually feed data into the CRC engine, the recommended mode of operation is to initially “prime” the FIFO with a sufficient number of words so no interrupt is generated before the next word can be written. Once that is done, start the CRC by setting the CRCGO bit to ‘1’. From that point onward, the VWORD bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO. DS70292D-page 288 Also, to get the correct CRC reading, it will be necessary to wait for the CRCMPT bit to go high before reading the CRCWDAT register. 25.2.2 INTERRUPT OPERATION When the VWORD4:VWORD0 bits make a transition from a value of ‘1’ to ‘0’, an interrupt will be generated. 25.3 25.3.1 Operation in Power Save Modes SLEEP MODE If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes. 25.3.2 IDLE MODE To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into the mode. If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available. Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 25.4 Registers The CRC module provides the following registers: • CRC Control Register • CRC XOR Polynomial Register REGISTER 25-1: CRCCON: CRC CONTROL REGISTER U-0 U-0 R/W-0 — — CSIDL R-0 R-0 R-0 R-0 R-0 VWORD<4:0> bit 15 bit 8 R-0 R-1 U-0 R/W-0 CRCFUL CRCMPT — CRCGO R/W-0 R/W-0 R/W-0 R/W-0 PLEN<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-8 VWORD<4:0>: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<3:0> is greater than 7, or 16 when PLEN<3:0> is less than or equal to 7. bit 7 CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: FIFO Empty bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 Unimplemented: Read as ‘0’ bit 4 CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = Turn off CRC serial shifter after FIFO is empty bit 3-0 PLEN<3:0>: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. 2009 Microchip Technology Inc. Preliminary DS70292D-page 289 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 25-2: R/W-0 CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — X<7:1> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 X<15:1>: XOR of Polynomial Term Xn Enable bits bit 0 Unimplemented: Read as ‘0’ DS70292D-page 290 Preliminary x = Bit is unknown 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 26.0 PARALLEL MASTER PORT (PMP) devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP is highly configurable. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 35. Parallel Master Port (PMP)” (DS70299) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Parallel Master Port (PMP) module is a parallel 8-bit I/O module, specifically designed to communicate with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory FIGURE 26-1: Key features of the PMP module include: • Fully multiplexed address/data mode • Demultiplexed or partially multiplexed address/ data mode - up to 11 address lines with single chip select - up to 12 address lines without chip select • One Chip Select Line • Programmable Strobe Options - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe • Address Auto-Increment/Auto-Decrement • Programmable Address/Data Multiplexing • Programmable Polarity on Control Signals • Legacy Parallel Slave Port Support • Enhanced Parallel Slave Support - Address Support - 4-Byte Deep Auto-Incrementing Buffer • Programmable Wait States • Selectable Input Voltage Levels PMP MODULE OVERVIEW Address Bus Data Bus dsPIC33F Parallel Master Port PMA<0> PMALL Control Lines PMA<1> PMALH Up to 11-Bit Address EEPROM PMA<10:2>(1) PMA<14> PMCS1 PMBE PMRD PMRD/PMWR PMWR PMENB Microcontroller PMD<7:0> PMA<7:0> PMA<10:8> LCD FIFO Buffer 8-Bit Data Note 1: 28-pin devices do not have PMA<10:2>. 2009 Microchip Technology Inc. Preliminary DS70292D-page 291 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-1: PMCON: PARALLEL PORT CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN bit 15 bit 8 R/W-0 R/W-0 R/W-0(1) U-0 R/W-0(1) R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP — CS1P BEP WRSP RDSP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PMPEN: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed bit 14 Unimplemented: Read as ‘0’ bit 13 PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits(1) 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on PMA<10:8> 00 = Address and data appear on separate pins bit 10 PTBEEN: Byte Enable Port Enable bit (16-bit Master mode) 1 = PMBE port enabled 0 = PMBE port disabled bit 9 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled bit 8 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled bit 7-6 CSF1:CSF0: Chip Select Function bits 11 = Reserved 10 = PMCS1 functions as chip select 0x = PMCS1 functions as address bit 14 bit 5 ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 Unimplemented: Read as ‘0’ bit 3 CS1P: Chip Select 1 Polarity bit(1) 1 = Active-high (PMCS1/PMCS1) 0 = Active-low (PMCS1/PMCS1) bit 2 BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) Note 1: These bits have no effect when their corresponding pins are used as address lines. DS70292D-page 292 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 1 WRSP: Write Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE<9:8> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master mode 1 (PMMODE<9:8> = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. 2009 Microchip Technology Inc. Preliminary DS70292D-page 293 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-2: R-0 PMMODE: PARALLEL PORT MODE REGISTER R/W-0 BUSY R/W-0 IRQM<1:0> R/W-0 R/W-0 INCM<1:0> R/W-0 R/W-0 MODE16 R/W-0 MODE<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 WAITB<1:0>(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAITE<1:0>(1) WAITM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy (not useful when the processor stall is active) 0 = Port is not busy bit 14-13 IRQM<1:0>: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = No interrupt generated, processor stall activated 01 = Interrupt generated at the end of the read/write cycle 00 = No interrupt generated bit 12-11 INCM<1:0>: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only) 10 = Decrement ADDR<10:0> by 1 every read/write cycle 01 = Increment ADDR<10:0> by 1 every read/write cycle 00 = No increment or decrement of address bit 10 MODE16: 8-Bit/16-Bit Mode bit 1 = 16-bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers 0 = 8-bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer bit 9-8 MODE<1:0>: Parallel Port Mode Select bits 11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>) 10 = Master mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>) 01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD<7:0>) bit 7-6 WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits(1) 11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY 10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY 01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY 00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY bit 5-2 WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TCY • • • 0001 = Wait of additional 1 TCY 0000 = No additional wait cycles (operation forced into one TCY) bit 1-0 WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits(1) 11 = Wait of 4 TCY 10 = Wait of 3 TCY 01 = Wait of 2 TCY 00 = Wait of 1 TCY Note 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000. DS70292D-page 294 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-3: PMADDR: PARALLEL PORT ADDRESS REGISTER R/W-0 R/W-0 ADDR15 CS1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADDR15: Parallel Port Destination Address bits bit 14 CS1: Chip Select 1 bit 1 = Chip select 1 is active 0 = Chip select 1 is inactive bit 13-0 ADDR13:ADDR0: Parallel Port Destination Address bits REGISTER 26-4: U-0 PMAEN: PARALLEL PORT ENABLE REGISTER R/W-0 — x = Bit is unknown PTEN14 U-0 — U-0 U-0 — R/W-0 R/W-0 R/W-0 PTEN<10:8>(1) — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<7:2>(1) R/W-0 PTEN<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 PTEN14: PMCS1 Strobe Enable bit 1 = PMA14 functions as either PMA<14> bit or PMCS1 0 = PMA14 pin functions as port I/O bit 13-11 Unimplemented: Read as ‘0’ bit 10-2 PTEN<10:2>: PMP Address Port Enable bits(1) 1 = PMA<10:2> function as PMP address lines 0 = PMA<10:2> function as port I/O bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O Note 1: Devices with 28 pins do not have PMA<10:2>. 2009 Microchip Technology Inc. Preliminary DS70292D-page 295 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-5: PMSTAT: PARALLEL PORT STATUS REGISTER R-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F bit 15 bit 8 R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Set bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register occurred (must be cleared in software) 0 = No overflow occurred bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 IB3F:IB0F: Input Buffer x Status Full bits 1 = Input buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input buffer does not contain any unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bits 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 OB3E:OB0E: Output Buffer x Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted DS70292D-page 296 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers x = Bit is unknown Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set. 2009 Microchip Technology Inc. Preliminary DS70292D-page 297 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 298 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 27.0 SPECIAL FEATURES 27.1 Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location 0xF80000. The individual Configuration bit descriptions for the Configuration registers are shown in Table 27-2. Note that address 0xF80000 is beyond the user program memory space. It belongs to the configuration memory space (0x800000-0xFFFFFF), which can only be accessed using table reads and table writes. To prevent inadvertent configuration changes during code execution, all programmable Configuration bits are write-once. After a bit is initially programmed during a power cycle, it cannot be written to again. Changing a device configuration requires that power to the device be cycled. The Device Configuration register map is shown in Table 27-1. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • • • • • • Flexible configuration Watchdog Timer (WDT) Code Protection and CodeGuard™ Security JTAG Boundary Scan Interface In-Circuit Serial Programming™ (ICSP™) In-Circuit emulation TABLE 27-1: Address DEVICE CONFIGURATION REGISTER MAP Name Bit 7 0xF80000 FBS 0xF80002 FSS(1) Bit 5 Bit 4 RBS<1:0> — — RSS<1:0> — — — — — — IESO — 0xF80004 FGS 0xF80006 FOSCSEL Bit 6 — Bit 3 — 0xF8000A FWDT FWDTEN WINDIS — WDTPRE 0xF8000E FICD Reserved(3) JTAGEN GWRP FNOSC<2:0> — OSCIOFNC POSCMD<1:0> WDTPOST<3:0> ALTI2C — — — 0xF80010 FUID0 User Unit ID Byte 0 0xF80012 FUID1 User Unit ID Byte 1 0xF80014 FUID2 User Unit ID Byte 2 0xF80016 FUID3 User Unit ID Byte 3 Legend: Note 1: 2: 3: SWRP GSS<1:0> — IOL1WAY Bit 0 BWRP SSS<2:0> — FCKSM<1:0> Reserved(2) Bit 1 BSS<2:0> 0xF80008 FOSC 0xF8000C FPOR Bit 2 FPWRT<2:0> — ICS<1:0> — = unimplemented bit, read as ‘0’. This Configuration register is not available and reads as 0xFF on dsPIC33FJ32GP302/304 devices. These bits are reserved and always read as ‘1’. These bits are reserved for use by development tools and must be programmed as ‘1’. 2009 Microchip Technology Inc. Preliminary DS70292D-page 299 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 27-2: dsPIC CONFIGURATION BITS DESCRIPTION Bit Field Register Description BWRP FBS Boot Segment Program Flash Write Protection 1 = Boot segment can be written 0 = Boot segment is write-protected BSS<2:0> FBS Boot Segment Program Flash Code Protection Size X11 = No Boot program Flash segment Boot space is 1K Instruction Words (except interrupt vectors) 110 = Standard security; boot program Flash segment ends at 0x0007FE 010 = High security; boot program Flash segment ends at 0x0007FE Boot space is 4K Instruction Words (except interrupt vectors) 101 = Standard security; boot program Flash segment, ends at 0x001FFE 001 = High security; boot program Flash segment ends at 0x001FFE Boot space is 8K Instruction Words (except interrupt vectors) 100 = Standard security; boot program Flash segment ends at 0x003FFE 000 = High security; boot program Flash segment ends at 0x003FFE RBS<1:0>(1) FBS SWRP(1) FSS(1) Secure Segment Program Flash Write-Protect bit 1 = Secure Segment can bet written 0 = Secure Segment is write-protected SSS<2:0>(1) FSS(1) Secure Segment Program Flash Code Protection Size (Secure segment is not implemented on 32K devices) X11 = No Secure program flash segment Boot Segment RAM Code Protection Size 11 = No Boot RAM defined 10 = Boot RAM is 128 bytes 01 = Boot RAM is 256 bytes 00 = Boot RAM is 1024 bytes Secure space is 4K IW less BS 110 = Standard security; secure program flash segment starts at End of BS, ends at 0x001FFE 010 = High security; secure program flash segment starts at End of BS, ends at 0x001FFE Secure space is 8K IW less BS 101 = Standard security; secure program flash segment starts at End of BS, ends at 0x003FFE 001 = High security; secure program flash segment starts at End of BS, ends at 0x003FFE Secure space is 16K IW less BS 100 = Standard security; secure program flash segment starts at End of BS, ends at 007FFEh 000 = High security; secure program flash segment starts at End of BS, ends at 0x007FFE RSS<1:0>(1) FSS(1) Secure Segment RAM Code Protection 11 = No Secure RAM defined 10 = Secure RAM is 256 Bytes less BS RAM 01 = Secure RAM is 2048 Bytes less BS RAM 00 = Secure RAM is 4096 Bytes less BS RAM Note 1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices. DS70292D-page 300 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 27-2: dsPIC CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register Description GSS<1:0> FGS General Segment Code-Protect bit 11 = User program memory is not code-protected 10 = Standard security 0x = High security GWRP FGS General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO FOSCSEL Two-speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source FNOSC<2:0> FOSCSEL Initial Oscillator Source Selection bits 111 = Internal Fast RC (FRC) oscillator with postscaler 110 = Internal Fast RC (FRC) oscillator with divide-by-16 101 = LPRC oscillator 100 = Secondary (LP) oscillator 011 = Primary (XT, HS, EC) oscillator with PLL 010 = Primary (XT, HS, EC) oscillator 001 = Internal Fast RC (FRC) oscillator with PLL 000 = FRC oscillator FCKSM<1:0> FOSC Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled IOL1WAY FOSC Peripheral pin select configuration 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations OSCIOFNC FOSC OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin POSCMD<1:0> FOSC Primary Oscillator Mode Select bits 11 = Primary oscillator disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode FWDTEN FWDT Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register has no effect.) 0 = Watchdog Timer enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) WINDIS FWDT Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode WDTPRE FWDT Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 Note 1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices. 2009 Microchip Technology Inc. Preliminary DS70292D-page 301 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 27-2: dsPIC CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register Description WDTPOST<3:0> FWDT Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 FPWRT<2:0> FPOR Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT = Disabled ALTI2C FPOR Alternate I2C™ pins 1 = I2C mapped to SDA1/SCL1 pins 0 = I2C mapped to ASDA1/ASCL1 pins JTAGEN FICD JTAG Enable bit 1 = JTAG enabled 0 = JTAG disabled ICS<1:0> FICD ICD Communication Channel Select bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use Note 1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices. DS70292D-page 302 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 27.2 On-Chip Voltage Regulator 27.3 BOR: Brown-out Reset All of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The Brown-out Reset (BOR) module is based on an internal voltage reference circuit that monitors the regulated supply voltage VCAP/VDDCORE. The main purpose of the BOR module is to generate a device Reset when a brown-out condition occurs. Brown-out conditions are generally caused by glitches on the AC mains (for example, missing portions of the AC cycle waveform due to bad power transmission lines, or voltage sags due to excessive current draw when a large inductive load is turned on). The regulator provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR (less than 5 Ohms) capacitor (such as tantalum or ceramic) must be connected to the VCAP/VDDCORE pin (Figure 27-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Table 30-13 located in Section 30.1 “DC Characteristics”. A BOR generates a Reset pulse, which resets the device. The BOR selects the clock source, based on the device Configuration bit values (FNOSC<2:0> and POSCMD<1:0>). Note: It is important for the low-ESR capacitor to be placed as close as possible to the VCAP/VDDCORE pin. On a POR, it takes approximately 20 s for the on-chip voltage regulator to generate an output voltage. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down. FIGURE 27-1: If an oscillator mode is selected, the BOR activates the Oscillator Start-up Timer (OST). The system clock is held until OST expires. If the PLL is used, the clock is held until the LOCK bit (OSCCON<5>) is ‘1’. Concurrently, the PWRT time-out (TPWRT) is applied before the internal Reset is released. If TPWRT = 0 and a crystal oscillator is being used, then a nominal delay of TFSCM = 100 is applied. The total delay in this case is TFSCM. The BOR Status bit (RCON<1>) is set to indicate that a BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold voltage. CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1) 3.3V dsPIC33F VDD VCAP/VDDCORE CEFC VSS Note 1: These are typical operating voltages. Refer to Section TABLE 30-13: “Internal Voltage Regulator Specifications” located in Section 30.1 “DC Characteristics” for the full operating ranges of VDD and VCAP/ VDDCORE. 2: It is important for the low-ESR capacitor to be placed as close as possible to the VCAP/VDDCORE pin. 2009 Microchip Technology Inc. Preliminary DS70292D-page 303 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 27.4 Watchdog Timer (WDT) 27.4.2 For dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 27.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit. With a 32 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPOST<3:0> Configuration bits (FWDT<3:0>), which allow the selection of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution Note: SLEEP AND IDLE MODES If the WDT is enabled, it continues to run during Sleep or Idle modes. When the WDT time-out occurs, the device wakes the device and code execution continues from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON<3,2>) needs to be cleared in software after the device wakes up. 27.4.3 ENABLING WDT The WDT is enabled or disabled by the FWDTEN Configuration bit in the FWDT Configuration register. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user application to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. Note: If the WINDIS bit (FWDT<6>) is cleared, the CLRWDT instruction should be executed by the application software only during the last 1/4 of the WDT period. This CLRWDT window can be determined by using a timer. If a CLRWDT instruction is executed before this window, a WDT Reset occurs. The WDT flag bit, WDTO (RCON<4>), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. FIGURE 27-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle WDTPRE WDTPOST<3:0> WDT Wake-up SWDTEN FWDTEN RS Prescaler (divide by N1) LPRC Clock 1 RS Postscaler (divide by N2) 0 WINDIS WDT Reset WDT Window Select CLRWDT Instruction DS70292D-page 304 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 27.5 JTAG Interface 27.8 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices implement a JTAG interface, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on this interface is provided in future revisions of the document. Note: 27.6 Refer to Section 24. “Programming and Diagnostics” (DS70207) of the “dsPIC33F/PIC24H Family Reference Manual” for further information on usage, configuration and operation of the JTAG interface. In-Circuit Serial Programming The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices can be serially programmed while in the end application circuit. This is done with two lines for clock and data and three other lines for power, ground and the programming sequence. Serial programming allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. Serial programming also allows the most recent firmware or a custom firmware to be programmed. Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for details about In-Circuit Serial Programming (ICSP). Code Protection and CodeGuard™ Security The dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 devices offer advanced implementation of CodeGuard Security that supports BS, SS and GS while, the dsPIC33FJ32GP302/304 devices offer the intermediate level of CodeGuard Security that supports only BS and GS. CodeGuard Security enables multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip. This feature helps protect individual Intellectual Property in collaborative system designs. When coupled with software encryption libraries, CodeGuard Security can be used to securely update Flash even when multiple IPs reside on the single chip. The code protection features vary depending on the actual dsPIC33F implemented. The following sections provide an overview of these features. Secure segment and RAM protection is implemented on the dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 devices. The dsPIC33FJ32GP302/304 devices do not support secure segment and RAM protection. Note: Any of the three pairs of programming clock/data pins can be used: Refer to Section 23. “CodeGuard™ Security” (DS70199) of the “dsPIC33F/ PIC24H Family Reference Manual” for further information on usage, configuration and operation of CodeGuard Security. • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 27.7 In-Circuit Debugger When MPLAB® ICD 2 is selected as a debugger, the incircuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pin functions. Any of the three pairs of debugging clock/data pins can be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS, PGC, PGD and the PGECx and PGEDx pin pairs. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. 2009 Microchip Technology Inc. Preliminary DS70292D-page 305 CODE FLASH SECURITY SEGMENT SIZES FOR 32 KB DEVICES CONFIG BITS BSS<2:0> = x11 0K VS = 256 IW SSS<2:0> = x11 0K GS = 11008 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x0057FEh 0x0157FEh BSS<2:0> = x10 1K VS = 256 IW BS = 768 IW GS = 10240 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x0057FEh 0x0157FEh BSS<2:0> = x01 4K VS = 256 IW BS = 3840 IW GS = 7168 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x0057FEh 0x0157FEh BSS<2:0> = x00 8K VS = 256 IW BS = 7936 IW GS = 3072 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x0057FEh 0x0157FEh Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 306 TABLE 27-3: CODE FLASH SECURITY SEGMENT SIZES FOR 64 KB DEVICES CONFIG BITS BSS<2:0> = x11 0K VS = 256 IW SSS<2:0> = x11 0K GS = 21760 IW VS = 256 IW SSS<2:0> = x10 SS = 3840 IW Preliminary 4K GS = 17920 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh BSS<2:0> = x10 1K VS = 256 IW BS = 768 IW GS = 20992 IW SSS<2:0> = x01 SS = 7936 IW 8K GS = 13824 IW VS = 256 IW DS70292D-page 307 SSS<2:0> = x00 16K SS = 16128 IW GS = 5632 IW VS = 256 IW BS = 3840 IW GS = 17920 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh BSS<2:0> = x00 8K VS = 256 IW BS = 7936 IW GS = 13824 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x0157FEh 0x0157FEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh VS = 256 IW BS = 768 IW SS = 3072 IW GS = 17920 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh VS = 256 IW BS = 3840 IW GS = 17920 IW 0x0157FEh 0x0157FEh VS = 256 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh BSS<2:0> = x01 4K VS = 256 IW BS = 768 IW SS = 7168 IW GS = 13824 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh VS = 256 IW BS = 7936 IW GS = 13824 IW 0x0157FEh VS = 256 IW BS = 3840 IW SS = 4096 IW GS = 13824 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW BS = 7936 IW GS = 13824 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x0157FEh 0x0157FEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW BS = 768 IW SS = 15360 IW GS = 5632 IW 0x0157FEh VS = 256 IW BS = 3840 IW SS = 12288 IW GS = 5632 IW 0x0157FEh VS = 256 IW BS = 7936 IW SS = 8192 IW GS = 5632 IW 0x0157FEh dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2009 Microchip Technology Inc. TABLE 27-4: CODE FLASH SECURITY SEGMENT SIZES FOR 128 KB DEVICES CONFIG BITS BSS<2:0> = x11 0K VS = 256 IW SSS<2:0> = x11 0K GS = 43776 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h BSS<2:0> = x10 1K VS = 256 IW BS = 768 IW GS = 43008 IW 0x0157FEh VS = 256 IW SSS<2:0> = x10 SS = 3840 IW Preliminary 4K GS = 39936 IW VS = 256 IW SSS<2:0> = x01 SS = 7936 IW 8K GS = 35840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 2009 Microchip Technology Inc. SSS<2:0> = x00 16K SS = 16128 IW GS = 27648 IW VS = 256 IW BS = 3840 IW GS = 39936 IW 0x0157FEh VS = 256 IW BS = 768 IW SS = 3072 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h VS = 256 IW BS = 3840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x0157FEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h BS = 768 IW SS = 7168 IW GS = 35840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 3840 IW SS = 4096 IW GS = 35840 IW 0x0157FEh VS = 256 IW BS = 768 IW SS = 15360 IW GS = 27648 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 7936 IW GS = 35840 IW VS = 256 IW BS = 7936 IW BS = 3840 IW SS = 12288 IW GS = 27648 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW BS = 7936 IW GS = 35840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh 0x0157FEh VS = 256 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh GS = 35840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h VS = 256 IW BSS<2:0> = x00 8K 0x0157FEh GS = 39936 IW GS = 39936 IW 0x0157FEh VS = 256 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h BSS<2:0> = x01 4K VS = 256 IW BS = 7936 IW SS = 8192 IW GS = 27648 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 308 TABLE 27-5: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 28.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. The dsPIC33F instruction set is identical to that of the dsPIC30F. Most instructions are a single program memory word (24 bits). Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into five basic categories: • • • • • Word or byte-oriented operations Bit-oriented operations Literal operations DSP operations Control operations Table 28-1 shows the general symbols used in describing the instructions. The dsPIC33F instruction set summary in Table 28-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand, which is typically a register ‘Wb’ without any address modifier • The second source operand, which is typically a register ‘Ws’ with or without an address modifier • The destination of the result, which is typically a register ‘Wd’ with or without an address modifier Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’) The literal instructions that involve data movement can use some of the following operands: • A literal value to be loaded into a W register or file register (specified by ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand, which is a register ‘Wb’ without any address modifier • The second source operand, which is a literal value • The destination of the result (only if not the same as the first source operand), which is typically a register ‘Wd’ with or without an address modifier The MAC class of DSP instructions can use some of the following operands: • The accumulator (A or B) to be used (required operand) • The W registers to be used as the two operands • The X and Y address space prefetch operations • The X and Y address space prefetch destinations • The accumulator write back destination The other DSP instructions do not involve any multiplication and can include: • The accumulator to be used (required) • The source or destination operand (designated as Wso or Wdo, respectively) with or without an address modifier • The amount of shift specified by a W register ‘Wn’ or a literal value The control instructions can use some of the following operands: However, word or byte-oriented file register instructions have two operands: • A program memory address • The mode of the table read and table write instructions • The file register specified by the value ‘f’ • The destination, which could be either the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ 2009 Microchip Technology Inc. Preliminary DS70292D-page 309 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Most instructions are a single word. Certain doubleword instructions are designed to provide all the required information in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it executes as a NOP. The double-word instructions execute in two instruction cycles. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (uncondi- TABLE 28-1: tional/computed branch), indirect CALL/GOTO, all table reads and writes and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. Note: For more details on the instruction set, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157). SYMBOLS USED IN OPCODE DESCRIPTIONS Field #text Description Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” {} Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator write back destination address register {W13, [W13]+ = 2} bit4 4-bit bit selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0x0000...0x1FFF} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’ None Field does not require an entry, can be blank OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0...W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) Wm*Wm Multiplicand and Multiplier working register pair for Square instructions {W4 * W4,W5 * W5,W6 * W6,W7 * W7} DS70292D-page 310 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Wm*Wn Description Multiplicand and Multiplier working register pair for DSP instructions {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 working registers {W0...W15} Wnd One of 16 destination working registers {W0...W15} Wns One of 16 source working registers {W0...W15} WREG W0 (working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X data space prefetch address register for DSP instructions {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none} Wxd X data space prefetch destination register for DSP instructions {W4...W7} Wy Y data space prefetch address register for DSP instructions {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Wyd Y data space prefetch destination register for DSP instructions {W4...W7} 2009 Microchip Technology Inc. Preliminary DS70292D-page 311 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: Base Instr # 1 2 3 4 5 6 7 8 9 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG Assembly Syntax Description # of # of Words Cycles Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z OA,OB,SA,SB ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if greater than or equal 1 1 (2) None BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None BRA GT,Expr Branch if greater than 1 1 (2) None BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None BRA LE,Expr Branch if less than or equal 1 1 (2) None BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None BRA LT,Expr Branch if less than 1 1 (2) None BRA LTU,Expr Branch if unsigned less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None DS70292D-page 312 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: Base Instr # 10 11 12 13 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSC BTSS BTST BTSTS Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 (2 or 3) None BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z lit23 Call subroutine 2 2 None 14 CALL CALL CALL Wn Call indirect subroutine 1 2 None 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB Clear Watchdog Timer 1 1 WDTO,Sleep 16 CLRWDT CLRWDT 17 COM COM f f=f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow (Wb – Ws – C) 1 1 C,DC,N,OV,Z 18 19 20 CP CP0 CPB 21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1 (2 or 3) None 22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1 (2 or 3) None 23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1 (2 or 3) None 24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if 1 1 (2 or 3) None 25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C 26 DEC DEC f f=f–1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z DEC2 f f=f–2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None 27 28 DEC2 DISI 2009 Microchip Technology Inc. Preliminary DS70292D-page 313 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: Base Instr # 29 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DIV Assembly Syntax # of # of Words Cycles Description Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV None 30 DIVF DIVF 31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None Wm,Wn 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None INC f f=f+1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z INC2 f f=f+2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z 39 40 41 INC INC2 IOR INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 43 LNK LNK #lit14 Link Frame Pointer 1 1 None 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd , AWB Multiply and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 N,Z MOV f,WREG Move f to WREG 1 1 N,Z MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N,Z Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None Prefetch and store accumulator 1 1 None 45 46 MAC MOV MOV.D MOV.D 47 MOVSAC MOVSAC DS70292D-page 314 Acc,Wx,Wxd,Wy,Wyd,AWB Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: Base Instr # 48 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MPY Assembly Syntax Description # of # of Words Cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd , AWB Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5) 1 1 None 52 53 54 NEG NOP POP MUL f W3:W2 = f * WREG 1 1 None NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f=f+1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z NOP No Operation 1 1 None NOPR No Operation 1 1 None None POP f Pop f from Top-of-Stack (TOS) 1 1 POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd + 1) 1 2 None Pop Shadow Registers 1 1 All f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None Push Shadow Registers 1 1 None Go into Sleep or Idle mode 1 1 WDTO,Sleep POP.S 55 PUSH PUSH PUSH.S 56 PWRSAV PWRSAV 57 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None None 58 REPEAT #lit1 59 RESET RESET Software device Reset 1 1 60 RETFIE RETFIE Return from interrupt 1 3 (2) None 61 RETLW RETLW Return with literal in Wn 1 3 (2) None 62 RETURN RETURN Return from Subroutine 1 3 (2) None 63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z 64 65 66 RLNC RRC RRNC #lit10,Wn RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 2009 Microchip Technology Inc. Preliminary DS70292D-page 315 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: Base Instr # 67 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic SAC Assembly Syntax Description # of # of Words Cycles Status Flags Affected SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None 68 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z 69 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f – WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z C,DC,N,OV,Z 70 71 72 73 74 75 76 SFTAC SL SUB SUBB SUBR SUBBR SWAP SUBB f f = f – WREG – (C) 1 1 SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 SUBR f f = WREG – f 1 1 C,DC,N,OV,Z C,DC,N,OV,Z SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 SWAP.b Wn Wn = nibble swap Wn 1 1 None SWAP Wn Wn = byte swap Wn 1 1 None None 77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None 79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 81 ULNK ULNK Unlink Frame Pointer 1 1 None 82 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N 83 ZE DS70292D-page 316 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 29.0 DEVELOPMENT SUPPORT 29.1 The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers - MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. 2009 Microchip Technology Inc. Preliminary DS70292D-page 317 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 29.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 29.3 HI-TECH C for Various Device Families For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. 29.4 29.5 • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 29.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS70292D-page 318 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 29.7 MPLAB SIM Software Simulator 29.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 29.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 2009 Microchip Technology Inc. MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 29.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. Preliminary DS70292D-page 319 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 29.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 29.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. 29.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS70292D-page 320 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 30.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 electrical characteristics. Additional information is provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 family are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(4) .................................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(4) .................................................. -0.3V to +5.6V Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(4) ......................................... -0.3V to (VDD + 0.3V) Voltage on VCAP/VDDCORE with respect to VSS ....................................................................................... 2.25V to 2.75V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin(2) ...........................................................................................................................250 mA Maximum output current sunk by any I/O pin(3) ........................................................................................................4 mA Maximum output current sourced by any I/O pin(3) ...................................................................................................4 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports(2)...............................................................................................................200 mA Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods can affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGECx and PGEDx pins, which are able to sink/source 12 mA. 4: See the “Pin Diagrams” section for 5V tolerant pins. 2009 Microchip Technology Inc. Preliminary DS70292D-page 321 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 30.1 DC Characteristics TABLE 30-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic TABLE 30-2: VDD Range (in Volts) Temp Range (in °C) dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 3.0-3.6V -40°C to +85°C 40 3.0-3.6V -40°C to +125°C 40 THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Operating Junction Temperature Range TJ -40 — +140 °C Operating Ambient Temperature Range TA -40 — +125 °C Industrial Temperature Devices Extended Temperature Devices Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD – IOH) PD PINT + PI/O W PDMAX (TJ – TA)/JA W I/O Pin Power Dissipation: I/O = ({VDD – VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol JA JA JA JA JA Package Thermal Resistance, 44-pin QFN Package Thermal Resistance, 44-pin TFQP Package Thermal Resistance, 28-pin SPDIP Package Thermal Resistance, 28-pin SOIC Package Thermal Resistance, 28-pin QFN-S Note 1: Typ Max Unit Notes 30 — °C/W 1 40 — °C/W 1 45 — °C/W 1 50 — °C/W 1 30 — °C/W 1 Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS70292D-page 322 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions Operating Voltage DC10 Supply Voltage VDD — 3.0 — 3.6 V DC12 VDR RAM Data Retention Voltage(2) 1.8 — — V — V — Voltage(4) DC16 VPOR VDD Start to ensure internal Power-on Reset signal — — VSS DC17 SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.03 — — DC18 VCORE VDD Core(3) Internal regulator voltage 2.25 — 2.75 Note 1: 2: 3: 4: Industrial and Extended V/ms 0-3.0V in 0.1s V Voltage is dependent on load, temperature and VDD Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. This is the limit to which VDD can be lowered without losing RAM data. These parameters are characterized but not tested in manufacturing. VDD voltage must remain at VSS for a minimum of 200 µs to ensure POR. 2009 Microchip Technology Inc. Preliminary DS70292D-page 323 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC20d 19 30 mA -40°C DC20a 19 30 mA +25°C DC20b 19 30 mA +85°C DC20c 19 35 mA +125°C DC21d 29 40 mA -40°C DC21a 29 40 mA +25°C DC21b 28 45 mA +85°C DC21c 28 45 mA +125°C DC22d 33 50 mA -40°C DC22a 33 50 mA +25°C DC22b 33 55 mA +85°C DC22c 33 55 mA +125°C DC23d 47 70 mA -40°C DC23a 48 70 mA +25°C DC23b 48 70 mA +85°C DC23c 48 70 mA +125°C DC24d 60 90 mA -40°C DC24a 60 90 mA +25°C DC24b 60 90 mA +85°C 60 90 mA +125°C DC24c Note 1: 2: 3.3V 10 MIPS 3.3V 16 MIPS 3.3V 20 MIPS 3.3V 30 MIPS 3.3V 40 MIPS Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits are all zeroed). DS70292D-page 324 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Idle Current (IIDLE): Core OFF Clock ON Base Current(2) DC40d 4 25 mA -40°C DC40a 4 25 mA +25°C DC40b 4 25 mA +85°C DC40c 4 25 mA +125°C DC41d 6 25 mA -40°C DC41a 6 25 mA +25°C DC41b 6 25 mA +85°C DC41c 6 25 mA +125°C DC42d 9 25 mA -40°C DC42a 9 25 mA +25°C DC42b 9 25 mA +85°C DC42c 9 25 mA +125°C DC43a 16 25 mA +25°C DC43d 16 25 mA -40°C DC43b 16 25 mA +85°C DC43c 16 25 mA +125°C DC44d 18 25 mA -40°C DC44a 18 25 mA +25°C DC44b 19 25 mA +85°C 19 25 mA +125°C DC44c Note 1: 2: 3.3V 10 MIPS 3.3V 16 MIPS 3.3V 20 MIPS 3.3V 30 MIPS 3.3V 40 MIPS Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS. 2009 Microchip Technology Inc. Preliminary DS70292D-page 325 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units 500 A Conditions Power-Down Current (IPD)(2) DC60d 24 -40°C DC60a 28 500 A +25°C DC60b 124 750 A +85°C DC60c 350 1000 A +125°C DC61d 8 13 A -40°C DC61a 10 15 A +25°C DC61b 12 20 A +85°C 13 25 A +125°C DC61c Note 1: 2: 3: 4: 3.3V Base Power-Down Current(3,4) 3.3V Watchdog Timer Current: IWDT(3) Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off and VREGS (RCON<8>) = 1. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. These currents are measured on the device containing the most memory in this family. TABLE 30-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Doze Ratio Units DC73a 42 50 1:2 mA DC73f 23 30 1:64 mA DC73g 23 30 1:128 mA DC70a 42 50 1:2 mA DC70f 26 30 1:64 mA DC70g 25 30 1:128 mA DC71a 41 50 1:2 mA DC71f 25 30 1:64 mA DC71g 24 30 1:128 mA DC72a 42 50 1:2 mA DC72f 26 30 1:64 mA DC72g 25 30 1:128 mA Note 1: Conditions -40°C 3.3V 40 MIPS +25°C 3.3V 40 MIPS +85°C 3.3V 40 MIPS +125°C 3.3V 40 MIPS Data in the Typical column is at 3.3V, 25°C unless otherwise stated. DS70292D-page 326 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage DI10 I/O pins VSS — 0.2 VDD V DI11 PMP pins VSS — 0.15 VDD V PMPTTL = 1 DI15 MCLR VSS — 0.2 VDD V DI16 I/O Pins with OSC1 or SOSCI VSS — 0.2 VDD V DI18 I/O Pins with SDAx, SCLx VSS — 0.3 VDD V SMbus disabled DI19 I/O Pins with SDAx, SCLx VSS — 0.2 VDD V SMbus enabled 0.7 VDD 0.7 VDD 0.24 VDD + 0.8 — — — VDD 5.5 VDD V V V 0.24 VDD + 0.8 — 5.5 V 50 250 400 A VDD = 3.3V, VPIN = VSS VIH Input High Voltage I/O Pins Not 5V Tolerant(4) I/O Pins 5V Tolerant(4) I/O Pins Not 5V Tolerant with PMP(4) I/O Pins 5V Tolerant with PMP(4) DI20 DI21 ICNPU CNx Pull-up Current IIL Input Leakage Current(2)(3) DI30 DI50 I/O pins 5V Tolerant(4) — — ±2 A VSS VPIN VDD, Pin at high-impedance DI51 I/O Pins Not 5V Tolerant(4) — — ±1 A VSS VPIN VDD, Pin at high-impedance, 40°C TA +85°C DI51a I/O Pins Not 5V Tolerant(4) — — ±2 A Shared with external reference pins, 40°C TA +85°C DI51b I/O Pins Not 5V Tolerant(4) — — ±3.5 A VSS VPIN VDD, Pin at high-impedance, -40°C TA +125°C DI51c I/O Pins Not 5V Tolerant(4) — — ±8 A Analog pins shared with external reference pins, -40°C TA +125°C DI55 MCLR — — ±2 A VSS VPIN VDD DI56 OSC1 — — ±2 A VSS VPIN VDD, XT and HS modes Note 1: 2: 3: 4: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. Negative current is defined as current sourced by the pin. See “Pin Diagrams” for the 5V tolerant I/O pins. 2009 Microchip Technology Inc. Preliminary DS70292D-page 327 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. VOL DO10 DO16 VOH Characteristic Min Typ Max Units Conditions I/O ports — — 0.4 V IOL = 2 mA, VDD = 3.3V OSC2/CLKO — — 0.4 V IOL = 2 mA, VDD = 3.3V Output Low Voltage Output High Voltage DO20 I/O ports 2.40 — — V IOH = -2.3 mA, VDD = 3.3V DO26 OSC2/CLKO 2.41 — — V IOH = -1.3 mA, VDD = 3.3V TABLE 30-11: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Characteristic Min(1) Typ Max(1) Units Conditions BOR Event on VDD transition high-to-low BOR event is tied to VDD core voltage decrease 2.40 — 2.55 V — BO10 VBOR Note 1: Parameters are for design guidance only and are not tested in manufacturing. DS70292D-page 328 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions Program Flash Memory D130a EP Cell Endurance 10,000 — — D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VPEW VDD for Self-Timed Write VMIN — 3.6 V VMIN = Minimum operating voltage D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated D135 IDDP Supply Current during Programming — 10 — mA D136a TRW Row Write Time 1.32 — 1.74 ms TRW = 11064 FRC cycles, TA = +85°C, See Note 2 D136b TRW Row Write Time 1.28 — 1.79 ms TRW = 11064 FRC cycles, TA = +125°C, See Note 2 D137a TPE Page Erase Time 20.1 — 26.5 ms TPE = 168517 FRC cycles, TA = +85°C, See Note 2 D137b TPE Page Erase Time 19.5 — 27.3 ms TPE = 168517 FRC cycles, TA = +125°C, See Note 2 D138a TWW Word Write Cycle Time 42.3 — 55.9 µs TWW = 355 FRC cycles, TA = +85°C, See Note 2 D138b TWW Word Write Cycle Time 41.1 — 57.6 µs TWW = 355 FRC cycles, TA = +125°C, See Note 2 Note 1: 2: E/W -40C to +125C Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max). This parameter depends on the FRC accuracy (see Table 30-19) and the value of the FRC Oscillator Tuning register (see Register 9-4). For complete details on calculating the Minimum and Maximum time see Section 5.3 “Programming Operations”. TABLE 30-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated): Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param No. Symbol CEFC Characteristics External Filter Capacitor Value 2009 Microchip Technology Inc. Min Typ Max Units 4.7 10 — F Preliminary Comments Capacitor must be low series resistance (< 5 Ohms) DS70292D-page 329 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 30.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 AC characteristics and timing parameters. TABLE 30-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Operating voltage VDD range as described in Section 30.0 “Electrical Characteristics”. AC CHARACTERISTICS FIGURE 30-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 CL Pin RL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSC2 15 pF for OSC2 output VSS TABLE 30-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. Characteristic Min Typ Max Units Conditions DO50 COSCO OSC2/SOSCO pin — — 15 pF In XT and HS modes when external clock is used to drive OSC1 DO56 CIO All I/O pins and OSC2 — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode DS70292D-page 330 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS25 OS30 OS31 OS31 CLKO OS41 OS40 TABLE 30-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. OS10 Symbol FIN OS20 TOSC Characteristic Min Typ(1) Max Units External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) DC — 40 MHz EC Oscillator Crystal Frequency 3.5 10 — — — 10 40 33 MHz MHz kHz XT HS SOSC TOSC = 1/FOSC 12.5 — DC ns Time(2) Conditions OS25 TCY Instruction Cycle 25 — DC ns OS30 TosL, TosH External Clock in (OSC1) High or Low Time 0.375 x TOSC — 0.625 x TOSC ns EC OS31 TosR, TosF External Clock in (OSC1) Rise or Fall Time — — 20 ns EC OS40 TckR CLKO Rise Time(3) — 5.2 — ns — OS41 TckF CLKO Fall Time(3) — 5.2 — ns — OS42 GM External Oscillator Transconductance(4) 14 16 18 mA/V Note 1: 2: 3: 4: VDD = 3.3V TA = +25ºC Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing. 2009 Microchip Technology Inc. Preliminary DS70292D-page 331 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min Typ(1) Max Units Conditions OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 0.8 — 8 MHz ECPLL, HSPLL, XTPLL modes OS51 FSYS On-Chip VCO System Frequency 100 — 200 MHz — OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 mS — OS53 DCLK CLKO Stability (Jitter) -3 0.5 3 % Note 1: Measured over 100 ms period Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 30-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min Typ Max Units Conditions Internal FRC Accuracy @ 7.3728 MHz(1,2) F20a FRC -2 — +2 % -40°C TA +85°C VDD = 3.0-3.6V F20b FRC -5 — +5 % -40°C TA +125°C VDD = 3.0-3.6V Note 1: 2: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift. FRC is set to initial frequency of 7.37 MHz (±2%) at 25°C. TABLE 30-19: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min Typ Max Units Conditions LPRC @ 32.768 kHz(1) F21a LPRC -20 ±6 +20 % -40°C TA +85°C VDD = 3.0-3.6V F21b LPRC -70 — +70 % -40°C TA +125°C VDD = 3.0-3.6V Note 1: Change of LPRC frequency as VDD changes. DS70292D-page 332 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-3: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 30-1 for load conditions. TABLE 30-20: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Typ(1) Max Units Conditions — 10 25 ns — DO31 TIOR DO32 TIOF Port Output Fall Time — 10 25 ns — DI35 TINP INTx Pin High or Low Time (output) 20 — — ns — TRBP CNx High or Low Time (input) 2 — — TCY — DI40 Note 1: Port Output Rise Time Min Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2009 Microchip Technology Inc. Preliminary DS70292D-page 333 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-4: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR SY11 PWRT Time-out OSC Time-out SY30 Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay DS70292D-page 334 Note: Refer to Figure 30-1 for load conditions. Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param Symbol No. Min Typ(2) Max Characteristic(1) Units Conditions SY10 TMCL MCLR Pulse-Width (low) 2 — — s -40°C to +85°C SY11 TPWRT Power-up Timer Period — 2 4 8 16 32 64 128 — ms -40°C to +85°C User programmable SY12 TPOR Power-on Reset Delay 3 10 30 s -40°C to +85°C SY13 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset 0.68 0.72 1.2 s SY20 TWDT1 Watchdog Timer Time-out Period — — — — See Section 27.4 “Watchdog Timer (WDT)” and LPRC specification F21 (Table 30-19) SY30 TOST Oscillator Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 s -40°C to +85°C Note 1: 2: These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2009 Microchip Technology Inc. Preliminary DS70292D-page 335 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-5: TIMER1, 2, 3 AND 4 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 OS60 Tx20 TMRx Note: Refer to Figure 30-1 for load conditions. TABLE 30-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. TA10 TA11 TA15 Symbol TTXH TTXL TTXP Characteristic TxCK High Time TxCK Low Time Min Typ Max Units Conditions Synchronous, no prescaler 0.5 TCY + 20 — — ns Must also meet parameter TA15 Synchronous, with prescaler 10 — — ns Asynchronous 10 — — ns Synchronous, no prescaler 0.5 TCY + 20 — — ns Synchronous, with prescaler 10 — — ns Asynchronous 10 — — ns TCY + 40 — — ns Synchronous, with prescaler Greater of: 20 ns or (TCY + 40)/N — — — Asynchronous 20 — — ns — DC — 50 kHz — 0.5 TCY — 1.5 TCY — — TxCK Input Period Synchronous, no prescaler OS60 Ft1 TA20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Note 1: SOSCI/T1CK Oscillator Input frequency Range (oscillator enabled by setting bit TCS (T1CON<1>)) Must also meet parameter TA15 — N = prescale value (1, 8, 64, 256) Timer1 is a Type A. DS70292D-page 336 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-23: TIMER2 AND TIMER4 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. TB10 TB11 TB15 TB20 Symbol TtxH TtxL TtxP TCKEXTMRL Characteristic TxCK High Time TxCK Low Time TxCK Input Period Min Typ Max Units Conditions Synchronous, no prescaler 0.5 TCY + 20 — — ns Must also meet parameter TB15 Synchronous, with prescaler 10 — — ns Synchronous, no prescaler 0.5 TCY + 20 — — ns Synchronous, with prescaler 10 — — ns Synchronous, no prescaler TCY + 40 — — ns Synchronous, with prescaler Greater of: 20 ns or (TCY + 40)/N — 1.5 TCY — Delay from External TxCK Clock Edge to Timer Increment 0.5 TCY Must also meet parameter TB15 N = prescale value (1, 8, 64, 256) — TABLE 30-24: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min Typ Max Units Conditions TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet parameter TC15 TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet parameter TC15 TC15 TtxP TxCK Input Period Synchronous, no prescaler TCY + 40 — — ns N = prescale value (1, 8, 64, 256) — 1.5 TCY — Synchronous, with prescaler TC20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment 2009 Microchip Technology Inc. Greater of: 20 ns or (TCY + 40)/N 0.5 TCY Preliminary — DS70292D-page 337 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 30-1 for load conditions. TABLE 30-25: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol IC10 TccL ICx Input Low Time IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Characteristic(1) No Prescaler Min Max Units Conditions 0.5 TCY + 20 — ns — With Prescaler No Prescaler 10 — ns 0.5 TCY + 20 — ns With Prescaler Note 1: 10 — ns (TCY + 40)/N — ns — N = prescale value (1, 4, 16) These parameters are characterized but not tested in manufacturing. FIGURE 30-7: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC10 OC11 Note: Refer to Figure 30-1 for load conditions. TABLE 30-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Characteristic(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min Typ Max Units Conditions OC10 TccF OCx Output Fall Time — — — ns See parameter D032 OC11 TccR OCx Output Rise Time — — — ns See parameter D031 Note 1: These parameters are characterized but not tested in manufacturing. DS70292D-page 338 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-8: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 OCx TABLE 30-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ Max Units Conditions OC15 TFD Fault Input to PWM I/O Change — — 50 ns — OC20 TFLT Fault Input Pulse-Width 50 — — ns — Note 1: These parameters are characterized but not tested in manufacturing. 2009 Microchip Technology Inc. Preliminary DS70292D-page 339 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-9: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP31 SDIx LSb SP30 MSb In LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 30-1 for load conditions. TABLE 30-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions SP10 TscL SCKx Output Low Time TCY/2 — — ns See Note 3 SP11 TscH SCKx Output High Time TCY/2 — — ns See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See parameter D032 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See parameter D031 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter D032 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter D031 and Note 4 SP35 TscH2doV, TscL2doV SDOx Data Output Valid after SCKx Edge — 6 20 ns — SP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 23 — — ns — SP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 30 — — ns — Note 1: 2: 3: 4: These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS70292D-page 340 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-10: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKX (CKP = 1) SP35 SP40 SDIX LSb Bit 14 - - - - - -1 MSb SDOX SP30,SP31 MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 30-1 for load conditions. TABLE 30-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units — — ns Conditions TscL SCKx Output Low Time(3) TCY/2 SP11 TscH SCKx Output High Time(3) TCY/2 — — ns See Note 3 SP20 TscF SCKx Output Fall Time(4) — — — ns See parameter D032 and Note 4 SP21 TscR SCKx Output Rise Time(4) — — — ns See parameter D031 and Note 4 SP30 TdoF SDOx Data Output Fall Time(4) — — — ns See parameter D032 and Note 4 SP31 TdoR SDOx Data Output Rise Time(4) — — — ns See parameter D031 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — 6 20 ns — SP36 TdoV2sc, SDOx Data Output Setup to TdoV2scL First SCKx Edge 30 — — ns — SP40 TdiV2scH, Setup Time of SDIx Data TdiV2scL Input to SCKx Edge 23 — — ns — SP41 TscH2diL, TscL2diL 30 — — ns — SP10 Note 1: 2: 3: 4: Hold Time of SDIx Data Input to SCKx Edge See Note 3 These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. 2009 Microchip Technology Inc. Preliminary DS70292D-page 341 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-11: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX Bit 14 - - - -1 MSb In LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions. TABLE 30-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions SP70 TscL SCKx Input Low Time 30 — — ns — SP71 TscH SCKx Input High Time 30 — — ns — SP72 TscF SCKx Input Fall Time(3) — 10 25 ns See Note 3 SP73 TscR SCKx Input Rise Time(3) — 10 25 ns See Note 3 (3) SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter D032 and Note 3 SP31 TdoR SDOx Data Output Rise Time(3) — — — ns See parameter D031 and Note 3 SP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — — 30 ns — SP40 TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge 20 — — ns — SP41 TscH2diL, TscL2diL 20 — — ns — SP50 TssL2scH, SSx to SCKx or SCKx Input TssL2scL 120 — — ns — SP51 TssH2doZ SSx to SDOx Output High-Impedance(3) 10 — 50 ns See Note 3 SP52 TscH2ssH SSx after SCKx Edge TscL2ssH 1.5 TCY + 40 — — ns — Note 1: 2: 3: Hold Time of SDIx Data Input to SCKx Edge These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Assumes 50 pF load on all SPIx pins. DS70292D-page 342 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-12: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDI SDIx MSb In SP51 Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions. 2009 Microchip Technology Inc. Preliminary DS70292D-page 343 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions SP70 TscL SCKx Input Low Time 30 — — ns — SP71 TscH SCKx Input High Time 30 — — ns — — 10 25 ns See Note 3 — 10 25 ns See Note 3 — — — ns See parameter D032 and Note 3 — — — ns See parameter D031 and Note 3 Time(3) SP72 TscF SCKx Input Fall SP73 TscR SCKx Input Rise Time(3) Time(3) SP30 TdoF SDOx Data Output Fall SP31 TdoR SDOx Data Output Rise Time(3) SP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — — 30 ns — SP40 TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge 20 — — ns — SP41 TscH2diL, Hold Time of SDIx Data Input TscL2diL to SCKx Edge 20 — — ns — SP50 TssL2scH, SSx to SCKx or SCKx TssL2scL Input 120 — — ns — SP51 TssH2doZ SSx to SDOX Output High-Impedance(4) 10 — 50 ns — SP52 TscH2ssH SSx after SCKx Edge TscL2ssH 1.5 TCY + 40 — — ns See Note 4 SP60 TssL2doV SDOx Data Output Valid after SSx Edge — — 50 ns — Note 1: 2: 3: 4: These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS70292D-page 344 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-13: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 30-1 for load conditions. FIGURE 30-14: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 30-1 for load conditions. 2009 Microchip Technology Inc. Preliminary DS70292D-page 345 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No. IM10 Min(1) Max Units Conditions TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — s — 400 kHz mode TCY/2 (BRG + 1) — s — mode(2) TCY/2 (BRG + 1) — s — Clock High Time 100 kHz mode TCY/2 (BRG + 1) — s — 400 kHz mode TCY/2 (BRG + 1) — s — 1 MHz mode(2) TCY/2 (BRG + 1) — s — 300 ns Characteristic 1 MHz IM11 THI:SCL IM20 TF:SCL SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode(2) IM21 TR:SCL IM25 SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode TSU:DAT Data Input Setup Time IM26 THD:DAT Data Input Hold Time IM30 TSU:STA IM31 Start Condition Setup Time THD:STA Start Condition Hold Time IM33 TSU:STO Stop Condition Setup Time IM34 THD:STO Stop Condition Hold Time IM40 TAA:SCL Output Valid From Clock TBF:SDA Bus Free Time 300 ns — 100 ns — 1000 ns 20 + 0.1 CB 300 ns 1 MHz mode(2) — 300 ns 100 kHz mode 250 — ns 400 kHz mode 100 — ns 1 MHz mode(2) 40 — ns 100 kHz mode 0 — s 400 kHz mode 0 0.9 s 1 MHz mode(2) 0.2 — s 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s 100 kHz mode TCY/2 (BRG + 1) — s 400 kHz mode TCY/2 (BRG + 1) — s 1 MHz mode(2) TCY/2 (BRG + 1) — s CB is specified to be from 10 to 400 pF — — Only relevant for Repeated Start condition After this period the first clock pulse is generated — 100 kHz mode TCY/2 (BRG + 1) — ns 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode(2) TCY/2 (BRG + 1) — ns 100 kHz mode — 3500 ns — 400 kHz mode — 1000 ns — mode(2) — 400 ns — 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s 1 MHz mode(2) 0.5 — s Time the bus must be free before a new transmission can start 1 MHz IM45 20 + 0.1 CB — CB is specified to be from 10 to 400 pF — IM50 CB Bus Capacitive Loading — 400 pF — IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 3 Note 1: 2: 3: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip website (www.microchip.com) for the latest dsPIC33F Family Reference Manual chapters. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). Typical value for this parameter is 130 ns. DS70292D-page 346 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-15: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition FIGURE 30-16: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out 2009 Microchip Technology Inc. Preliminary DS70292D-page 347 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol IS10 IS11 IS20 IS21 IS25 IS26 IS30 IS31 IS33 IS34 TLO:SCL Clock Low Time THI:SCL TF:SCL TR:SCL IS45 IS50 Note 1: Clock High Time SDAx and SCLx Fall Time SDAx and SCLx Rise Time TSU:DAT Data Input Setup Time THD:DAT Data Input Hold Time TSU:STA Start Condition Setup Time THD:STA Start Condition Hold Time TSU:STO Stop Condition Setup Time THD:ST O IS40 Characteristic Stop Condition Hold Time TAA:SCL Output Valid From Clock TBF:SDA Bus Free Time CB Min Max Units 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) — 100 ns 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) — 300 ns 100 kHz mode 250 — ns 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns 100 kHz mode 0 — s 400 kHz mode 0 0.9 s 1 MHz mode(1) 0 0.3 s 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s 1 MHz mode(1) 0.25 — s 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s 1 MHz mode(1) 0.25 — s 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s 1 MHz mode(1) 0.6 — s 100 kHz mode 4000 — ns 400 kHz mode 600 — ns 1 MHz mode(1) 250 100 kHz mode 0 3500 ns 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns 100 kHz mode 4.7 — s — — CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF — — Only relevant for Repeated Start condition After this period, the first clock pulse is generated — — ns 400 kHz mode 1.3 — s 1 MHz mode(1) 0.5 — s — 400 pF Bus Capacitive Loading Conditions — Time the bus must be free before a new transmission can start — Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS70292D-page 348 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-17: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CS10 CS21 CS20 CS20 CS21 CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CSDO 70 CS50 High-Z LSb MSb CS30 CSDI High-Z CS31 LSb In MSb In CS40 CS41 Note: Refer to Figure 30-1 for load conditions. 2009 Microchip Technology Inc. Preliminary DS70292D-page 349 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-34: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. CS10 Symbol TCSCKL Characteristic(1) Min Typ(2) Max Units Conditions TCY/2 + 20 — — ns — 30 — — ns — TCY/2 + 20 — — ns — CSCK Output High Time(3) (CSCK pin is an output) 30 — — ns — CSCK Input Low Time (CSCK pin is an input) CSCK Output Low Time(3) (CSCK pin is an output) CS11 TCSCKH CSCK Input High Time (CSCK pin is an input) CS20 TCSCKF CSCK Output Fall Time(4) (CSCK pin is an output) — 10 25 ns — CS21 TCSCKR CSCK Output Rise Time(4) (CSCK pin is an output) — 10 25 ns — CS30 TCSDOF CSDO Data Output Fall Time(4) — 10 25 ns — CS31 TCSDOR CSDO Data Output Rise Time(4) — 10 25 ns — CS35 TDV Clock Edge to CSDO Data Valid — — 10 ns — CS36 TDIV Clock Edge to CSDO Tri-Stated 10 — 20 ns — CS40 TCSDI Setup Time of CSDI Data Input to CSCK Edge (CSCK pin is input or output) 20 — — ns — CS41 THCSDI Hold Time of CSDI Data Input to CSCK Edge (CSCK pin is input or output) 20 — — ns — CS50 TCOFSF COFS Fall Time (COFS pin is output) — 10 25 ns Note 1 CS51 TCOFSR COFS Rise Time (COFS pin is output) — 10 25 ns Note 1 CS55 TSCOFS Setup Time of COFS Data Input to CSCK Edge (COFS pin is input) 20 — — ns — CS56 THCOFS Hold Time of COFS Data Input to CSCK Edge (COFS pin is input) 20 — — ns — Note 1: 2: 3: 4: These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all DCI pins. DS70292D-page 350 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-18: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 CS71 CS70 CS72 SYNC (COFS) CS75 CS76 CS80 SDOx (CSDO) LSb MSb LSb CS76 SDIx (CSDI) CS75 MSb In CS65 CS66 2009 Microchip Technology Inc. Preliminary DS70292D-page 351 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-35: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1,2) Min Typ(3) Max Units Conditions CS60 TBCLKL BIT_CLK Low Time 36 40.7 45 ns — CS61 TBCLKH BIT_CLK High Time 36 40.7 45 ns — CS62 TBCLK BIT_CLK Period — 81.4 — ns CS65 TSACL Input Setup Time to Falling Edge of BIT_CLK — — 10 ns — CS66 THACL Input Hold Time from Falling Edge of BIT_CLK — — 10 ns — CS70 TSYNCLO SYNC Data Output Low Time — 19.5 — s Note 1 CS71 TSYNCHI SYNC Data Output High Time — 1.3 — s Note 1 CS72 TSYNC SYNC Data Output Period — 20.8 — s Note 1 CS75 TRACL Rise Time, SYNC, SDATA_OUT — — 30 ns CLOAD = 50 pF, VDD = 3V CS76 TFACL Fall Time, SYNC, SDATA_OUT — — 30 ns CLOAD = 50 pF, VDD = 3V CS80 TOVDACL Output Valid Delay from Rising Edge of BIT_CLK — — 15 ns — Note 1: 2: 3: These parameters are characterized but not tested in manufacturing. These values assume BIT_CLK frequency is 12.288 MHz. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70292D-page 352 Preliminary Bit clock is input 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-19: CiTx Pin (output) ECAN™ MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CiRx Pin (input) CA20 TABLE 30-36: ECAN™ MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions CA10 TioF Port Output Fall Time — — — ns See parameter D032 CA11 TioR Port Output Rise Time — — — ns See parameter D031 CA20 Tcwf Pulse-Width to Trigger CAN Wake-up Filter 120 ns — Note 1: 2: These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2009 Microchip Technology Inc. Preliminary DS70292D-page 353 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-37: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ Max. Units Lesser of VDD + 0.3 or 3.6 V VSS + 0.3 V Conditions Device Supply AD01 AVDD Module VDD Supply AD02 AVSS Module VSS Supply AD05 VREFH Reference Voltage High Greater of VDD – 0.3 or 3.0 — VSS – 0.3 — — — Reference Inputs AD05a AD06 VREFL Reference Voltage Low AD06a AVSS + 2.7 — AVDD V See Note 1 3.0 — 3.6 V VREFH = AVDD VREFL = AVSS = 0 AVSS — AVDD – 2.7 V See Note 1 0 — 0 V VREFH = AVDD VREFL = AVSS = 0 AD07 VREF Absolute Reference Voltage 2.7 — 3.6 V VREF = VREFH - VREFL AD08 IREF Current Drain — — 10 A ADC off AD09 IAD Operating Current — 7.0 9.0 mA — 2.7 3.2 mA ADC operating in 10-bit mode, see Note 1 ADC operating in 12-bit mode, see Note 1 Analog Input AD12 VINH Input Voltage Range VINH VINL — VREFH V This voltage reflects Sample and Hold Channels 0, 1, 2, and 3 (CH0-CH3), positive input AD13 VINL Input Voltage Range VINL VREFL — AVSS + 1V V This voltage reflects Sample and Hold Channels 0, 1, 2, and 3 (CH0-CH3), negative input AD17 RIN Recommended Impedance of Analog Voltage Source — — — — 200 200 10-bit ADC 12-bit ADC Note 1: These parameters are not characterized or tested in manufacturing. DS70292D-page 354 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-38: ADC MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions ADC Accuracy (12-bit Mode) – Measurements with external VREF+/VREFAD20a Nr Resolution 12 data bits bits AD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD22a DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD23a GERR Gain Error 1.25 3.4 10 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD24a EOFF Offset Error -0.2 0.9 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD25a — Monotonicity — — — — Guaranteed ADC Accuracy (12-bit Mode) – Measurements with internal VREF+/VREFAD20a Nr Resolution AD21a INL Integral Nonlinearity -2 12 data bits bits — +2 LSb VINL = AVSS = 0V, AVDD = 3.6V >-1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6V 2 10.5 20 LSb VINL = AVSS = 0V, AVDD = 3.6V AD22a DNL Differential Nonlinearity AD23a GERR Gain Error AD24a EOFF Offset Error 2 3.8 10 LSb AD25a — Monotonicity — — — — AD30a THD Total Harmonic Distortion AD31a SINAD Signal to Noise and Distortion AD32a SFDR AD33a AD34a VINL = AVSS = 0V, AVDD = 3.6V Guaranteed Dynamic Performance (12-bit Mode) — — -75 dB — 68.5 69.5 — dB — Spurious Free Dynamic Range 80 — — dB — FNYQ Input Signal Bandwidth — — 250 kHz — ENOB Effective Number of Bits 11.09 11.3 — bits — 2009 Microchip Technology Inc. Preliminary DS70292D-page 355 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-39: ADC MODULE SPECIFICATIONS (10-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions ADC Accuracy (10-bit Mode) – Measurements with external VREF+/VREFAD20b Nr Resolution 10 data bits bits AD21b INL Integral Nonlinearity -1.5 — +1.5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD22b DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD23b GERR Gain Error 0.4 3 6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD24b EOFF Offset Error 0.2 2 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD25b — Monotonicity — — — — Guaranteed ADC Accuracy (10-bit Mode) – Measurements with internal VREF+/VREFAD20b Nr Resolution AD21b INL Integral Nonlinearity -1 10 data bits — +1 bits LSb VINL = AVSS = 0V, AVDD = 3.6V AD22b DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6V AD23b GERR Gain Error 3 7 15 LSb VINL = AVSS = 0V, AVDD = 3.6V AD24b EOFF Offset Error 1.5 3 7 LSb AD25b — Monotonicity — — — — AD30b THD Total Harmonic Distortion — — -64 dB — AD31b SINAD Signal to Noise and Distortion 57 58.5 — dB — AD32b SFDR Spurious Free Dynamic Range 72 — — dB — AD33b FNYQ Input Signal Bandwidth — — 550 kHz — AD34b ENOB Effective Number of Bits 9.16 9.4 — bits — VINL = AVSS = 0V, AVDD = 3.6V Guaranteed Dynamic Performance (10-bit Mode) DS70292D-page 356 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-20: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 TSAMP AD55 DONE AD1IF 1 2 3 4 5 6 7 8 9 1 – Software sets AD1CON. SAMP to start sampling. 4 – Sampling ends, conversion sequence starts. 2 – Sampling starts after discharge period. TSAMP is described in Section 28. “Analog-to-Digital Converter (ADC) without DMA” (DS70210) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F Family Reference Manual sections. 5 – Convert bit 11. 3 – Software clears AD1CON. SAMP to start conversion. 2009 Microchip Technology Inc. Preliminary 6 – Convert bit 10. 7 – Convert bit 1. 8 – Convert bit 0. 9 – One TAD for end of conversion. DS70292D-page 357 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-40: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ(2) Max. Units Conditions Clock Parameters(1) AD50 TAD ADC Clock Period AD51 tRC ADC Internal RC Oscillator Period 117.6 — — ns — — 250 — ns — Conversion Rate AD55 tCONV Conversion Time — 14 TAD ns — AD56 FCNV Throughput Rate — — 500 ksps — AD57 TSAMP Sample Time 3 TAD — — — — Timing Parameters AD60 tPCS Conversion Start from Sample Trigger(2) 2 TAD — 3 TAD — Auto convert trigger not selected AD61 tPSS Sample Start from Setting Sample (SAMP) bit(2) 2 TAD — 3 TAD — — AD62 tCSS Conversion Completion to Sample Start (ASAM = 1)(2) — 0.5 TAD — — — AD63 tDPU Time to Stabilize Analog Stage from ADC Off to ADC On(2,3) — — 20 s — Note 1: 2: 3: Because the sample caps eventually loses charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures. These parameters are characterized but not tested in manufacturing. The tDPU is the time required for the ADC module to stabilize at the appropriate level when the module is turned on (AD1CON1<ADON>=’1’). During this time, the ADC result is indeterminate. DS70292D-page 358 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-21: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 TSAMP AD55 AD55 DONE AD1IF 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets AD1CON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 28. “Analog-to-Digital Converter (ADC) without DMA” (DS70210) in the “dsPIC33F/PIC24H Family Reference Manual”. 3 – Software clears AD1CON. SAMP to start conversion. 4 – Sampling ends, conversion sequence starts. 5 – Convert bit 9. 6 – Convert bit 8. 7 – Convert bit 0. 8 – One TAD for end of conversion. FIGURE 30-22: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Set ADON Execution SAMP TSAMP AD55 TSAMP AD55 AD55 AD1IF DONE 1 2 3 4 5 6 7 3 4 5 1 – Software sets AD1CON. ADON to start AD operation. 4 – Convert bit 8. 2 – Sampling starts after discharge period. TSAMP is described in Section 28. “Analog-to-Digital Converter (ADC) without DMA” (DS70210) in the “dsPIC33F/PIC24H Family Reference Manual'. – Convert bit 9. 3 5 – Convert bit 0. 6 8 6 – One TAD for end of conversion. 7 – Begin conversion of next channel. 8 – Sample for time specified by SAMC<4:0>. 2009 Microchip Technology Inc. Preliminary DS70292D-page 359 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-41: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C T A +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Typ(2) Min. Max. Units Conditions Clock Parameters(1) AD50 TAD ADC Clock Period AD51 tRC ADC Internal RC Oscillator Period 76 — — ns — — 250 — ns — Conversion Rate AD55 tCONV Conversion Time — 12 TAD — — — AD56 FCNV Throughput Rate — — 1.1 Msps — AD57 TSAMP Sample Time 2 TAD — — — — Timing Parameters AD60 tPCS Conversion Start from Sample Trigger(2) 2 TAD — 3 TAD — AD61 tPSS Sample Start from Setting Sample (SAMP) bit(2) 2 TAD — 3 TAD — — AD62 tCSS Conversion Completion to Sample Start (ASAM = 1)(2) — 0.5 TAD — — — AD63 tDPU Time to Stabilize Analog Stage from ADC Off to ADC On(2,3) — — 20 s — Note 1: 2: 3: Auto-Convert Trigger not selected Because the sample caps eventually loses charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures. These parameters are characterized but not tested in manufacturing. The tDPU is the time required for the ADC module to stabilize at the appropriate level when the module is turned on (AD1CON1<ADON>=’1’). During this time, the ADC result is indeterminate. TABLE 30-42: AUDIO DAC MODULE SPECIFICATIONS AC/DC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param No. Min. Symbol Characteristic Typ Max. Units Conditions Clock Parameters DA01 VOD+ Positive Output Differential Voltage 1 1.15 2 V VOD+ = VDACH – VDACL See Note 1, 2 DA02 VOD- Negative Output Differential Voltage -2 -1.15 -1 V VOD- = VDACL – VDACH See Note 1, 2 DA03 VRES Resolution — 16 — bits — DA04 GERR Gain Error — 3.1 — % — DA08 FDAC Clock frequency — — 25.6 MHz — DA09 FSAMP Sample Rate 0 — 100 kHz DA10 FINPUT Input data frequency 0 — 45 kHz DA11 TINIT Initialization period 1024 — — Clks Time before first sample DA12 SNR Signal-to-Noise Ratio — 61 Note 1: 2: dB — Sampling frequency = 100 kHz Sampling frequency = 96 kHz Measured VDACH and VDACL output with respect to VSS, with no load and FORM bit (DACXCON<8>) = 0. This parameter is tested at -40°C TA 85°C only. DS70292D-page 360 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-43: COMPARATOR TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions 300 TRESP Response Time(1,2) — 150 400 ns — 301 TMC2OV Comparator Mode Change to Output Valid(1) — — 10 s — Note 1: 2: Parameters are characterized but not tested. Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. 2009 Microchip Technology Inc. Preliminary DS70292D-page 361 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-44: COMPARATOR MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Symbol D300 VIOFF Characteristic Input Offset Voltage(1) (1) D301 VICM Input Common Mode Voltage D302 CMRR Common Mode Rejection Ratio (1) Note 1: Min. Typ Max. Units Conditions — ±10 — mV — 0 — AVDD-1.5V V — -54 — — dB — Parameters are characterized but not tested. TABLE 30-45: COMPARATOR REFERENCE VOLTAGE SETTLING TIME SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. VR310 Note 1: Symbol TSET Characteristic Settling Time(1) Min. Typ Max. Units Conditions — — 10 s — Settling time measured while CVRR = 1 and CVR3:CVR0 bits transition from ‘0000’ to ‘1111’. TABLE 30-46: COMPARATOR REFERENCE VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Symbol VRD310 CVRES VRD311 CVRAA VRD312 CVRUR DS70292D-page 362 Characteristic Resolution Min. Typ Max. Units Conditions CVRSRC/24 — CVRSRC/32 LSb — Absolute Accuracy — — 0.5 LSb — Unit Resistor Value (R) — 2k — — Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-23: PARALLEL SLAVE PORT TIMING DIAGRAM CS RD WR PS4 PMD<7:0> PS1 PS3 PS2 TABLE 30-47: PARALLEL SLAVE PORT TIME SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions PS1 TdtV2wrH Data in Valid before WR or CS Inactive (setup time) 20 — — ns — PS2 TwrH2dtI WR or CS Inactive to Data-In Invalid (hold time) 20 — — ns — PS3 TrdL2dtV RD and CS to Active Data-Out Valid — — 80 ns — PS4 TrdH2dtI RD Active or CS Inactive to Data-Out Invalid 10 — 30 ns — 2009 Microchip Technology Inc. Preliminary DS70292D-page 363 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-24: PARALLEL MASTER PORT READ TIMING DIAGRAM P1 P2 P3 P4 P1 P2 P3 P4 P1 P2 System Clock PMA<13:8> Address PMD<7:0> Data Address <7:0> PM6 PM2 PM7 PM3 PMRD PM5 PMWR PMALL/PMALH PM1 PMCS1 TABLE 30-48: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Characteristic Min. Typ Max. Units Conditions PM1 PMALL/PMALH Pulse-Width — 0.5 TCY — ns — PM2 Address Out Valid to PMALL/PMALH Invalid (address setup time) — 0.75 TCY — ns — PM3 PMALL/PMALH Invalid to Address Out Invalid (address hold time) — 0.25 TCY — ns — PM5 PMRD Pulse-Width — 0.5 TCY — ns — PM6 PMRD or PMENB Active to Data In Valid (data setup time) — — — ns — PM7 PMRD or PMENB Inactive to Data In Invalid (data hold time) — — — ns — DS70292D-page 364 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-25: PARALLEL MASTER PORT WRITE TIMING DIAGRAM P1 P2 P3 P4 P1 P2 P3 P4 P1 P2 System Clock PMA<13:8> Address Address <7:0> PMD<7:0> Data Data PM12 PM13 PMRD PMWR PM11 PMALL/PMALH PM16 PMCS1 TABLE 30-49: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Characteristic Min. Typ Max. Units Conditions PM11 PMWR Pulse-Width — 0.5 TCY — ns — PM12 Data Out Valid before PMWR or PMENB goes Inactive (data setup time) — — — ns — PM13 PMWR or PMEMB Invalid to Data Out Invalid (data hold time) — — — ns — PM16 PMCSx Pulse-Width TCY - 5 — — ns — 2009 Microchip Technology Inc. Preliminary DS70292D-page 365 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 366 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 31.0 HIGH TEMPERATURE ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 electrical characteristics for devices operating in an ambient temperature range of -40°C to +140°C. Note: Programming of the Flash memory is not allowed above 125°C. The specifications between -40°C to +140°C are identical to those shown in Section 30.0 “Electrical Characteristics” for operation between -40°C to +125°C, with the exception of the parameters listed in this section. Parameters in this section begin with an H, which denotes High temperature. For example, parameter DC10 in Section 30.0 “Electrical Characteristics” is the Industrial and Extended temperature equivalent of HDC10. Absolute maximum ratings for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 high temperature devices are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias(4) .........................................................................................................-40°C to +140°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(5) .................................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(5) ....................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(5) .................................................... -0.3V to 5.6V Voltage on VCAP/VDDCORE with respect to VSS ....................................................................................... 2.25V to 2.75V Maximum current out of VSS pin .............................................................................................................................60 mA Maximum current into VDD pin(2) .............................................................................................................................60 mA Maximum junction temperature............................................................................................................................. +145°C Maximum output current sunk by any I/O pin(3) ........................................................................................................1 mA Maximum output current sourced by any I/O pin(3) ...................................................................................................1 mA Maximum current sunk by all ports combined ........................................................................................................10 mA Maximum current sourced by all ports combined(2) ................................................................................................10 mA Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods can affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2). 3: Unlike devices at 125°C and below, the specifications in this section also apply to the CLKOUT, VREF+, VREF-, SCLx, SDAx, PGCx, and PGDx pins. 4: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 hours. Any design in which the total operating time from 125°C to 150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. 5: Refer to the “Pin Diagrams” section for 5V tolerant pins. 2009 Microchip Technology Inc. Preliminary DS70292D-page 367 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 31.1 High Temperature DC Characteristics TABLE 31-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic TABLE 31-2: VDD Range (in Volts) Temperature Range (in °C) dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 3.0V to 3.6V -40°C to +140°C 20 THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +145 °C Operating Ambient Temperature Range TA -40 — +140 °C High Temperature Devices Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD - IOH) PD PINT + PI/O W PDMAX (TJ - TA)/JA W I/O Pin Power Dissipation: I/O = ({VDD - VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation TABLE 31-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +140°C for High Temperature DC CHARACTERISTICS Parameter No. Symbol Characteristic Min Typ Max Units 3.0 3.3 3.6 V Conditions Operating Voltage HDC10 Supply Voltage — VDD TABLE 31-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +140°C for High Temperature DC CHARACTERISTICS Parameter No. -40°C to +140°C Typical Max Units Conditions Power-Down Current (IPD) HDC60e 250 2000 A +140°C 3.3V Base Power-Down Current(1,3) HDC61c 3 5 A +140°C 3.3V Watchdog Timer Current: IWDT(2,4) Note 1: 2: 3: 4: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off, and VREGS (RCON<8>) = 1. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. These currents are measured on the device containing the most memory in this family. These parameters are characterized, but are not tested in manufacturing. DS70292D-page 368 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-5: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +140°C for High Temperature DC CHARACTERISTICS Parameter No. Typical(1) Max Doze Ratio Units HDC72a 39 45 1:2 mA HDC72f 18 25 1:64 mA 18 25 1:128 mA HDC72g Note 1: +140°C 3.3V 20 MIPS Parameters with Doze ratios of 1:2 and 1:64 are characterized, but are not tested in manufacturing. TABLE 31-6: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +140°C for High Temperature DC CHARACTERISTICS Param No. Conditions Symbol Characteristic Min Typ Max Units Conditions Output Low Voltage VOL HDO10 I/O ports — — 0.4 V IOL = 1 mA, VDD = 3.3V HDO16 OSC2/CLKO — — 0.4 V IOL = 1 mA, VDD = 3.3V Output High Voltage VOH HDO20 I/O ports 2.40 — — V IOH = -1 mA, VDD = 3.3V HDO26 OSC2/CLKO 2.41 — — V IOH = -1 mA, VDD = 3.3V TABLE 31-7: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param Symbol No. Characteristic(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +140°C for High Temperature Min Typ Max Units Conditions 10,000 — — E/W -40C to +140C(2) 20 — — Year 1000 E/W cycles or less and no other specifications are violated Program Flash Memory HD130 EP Cell Endurance HD134 TRETD Characteristic Retention Note 1: 2: These parameters are assured by design, but are not characterized or tested in manufacturing. Programming of the Flash memory is not allowed above 125°C. 2009 Microchip Technology Inc. Preliminary DS70292D-page 369 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 31.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 AC characteristics and timing parameters for high temperature devices. However, all AC timing specifications in this section are the same as those in Section 30.2 “AC Characteristics and Timing Parameters”, with the exception of the parameters listed in this section. Parameters in this section begin with an H, which denotes High temperature. For example, parameter OS53 in Section 30.2 “AC Characteristics and Timing Parameters” is the Industrial and Extended temperature equivalent of HOS53. TABLE 31-8: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS FIGURE 31-1: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +140°C for High Temperature Operating voltage VDD range as described in Table 31-1. LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 CL Pin RL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSC2 15 pF for OSC2 output VSS TABLE 31-9: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +140°C for High Temperature Param No. Symbol Characteristic CLKO Stability (Jitter)(1) Min Typ Max Units -5 0.5 5 % HOS53 DCLK Note 1: These parameters are characterized, but are not tested in manufacturing. DS70292D-page 370 Preliminary Conditions Measured over 100 ms period 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-10: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +140°C for High Temperature Param No. Characteristic(1) Symbol Min Typ Max Units Conditions HSP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — 10 25 ns — HSP40 TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge 28 — — ns — HSP41 TscH2diL, TscL2diL 35 — — ns — Note 1: These parameters are characterized but not tested in manufacturing. Hold Time of SDIx Data Input to SCKx Edge TABLE 31-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +140°C for High Temperature Param No. Characteristic(1) Symbol Min Typ Max Units Conditions HSP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — 10 25 ns — HSP36 TdoV2sc, TdoV2scL 35 — — ns — HSP40 TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge 28 — — ns — HSP41 TscH2diL, TscL2diL 35 — — ns — Note 1: SDOx Data Output Setup to First SCKx Edge Hold Time of SDIx Data Input to SCKx Edge These parameters are characterized but not tested in manufacturing. 2009 Microchip Technology Inc. Preliminary DS70292D-page 371 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +140°C for High Temperature Param No. Symbol Characteristic(1) Min Typ Max Units Conditions HSP35 TscH2doV, TscL2doV SDOx Data Output Valid after SCKx Edge — — 35 ns — HSP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 25 — — ns — HSP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 25 — — ns — HSP51 TssH2doZ SSx to SDOx Output High-Impedance 15 — 55 ns Note 1: 2: See Note 2 These parameters are characterized but not tested in manufacturing. Assumes 50 pF load on all SPIx pins. TABLE 31-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +140°C for High Temperature Characteristic(1) Min Typ Max Units Conditions HSP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — — 35 ns — HSP40 TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge 25 — — ns — HSP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 25 — — ns — HSP51 TssH2doZ SSx to SDOX Output High-Impedance 15 — 55 ns HSP60 TssL2doV SDOx Data Output Valid after SSx Edge — — 55 ns Note 1: 2: These parameters are characterized but not tested in manufacturing. Assumes 50 pF load on all SPIx pins. DS70292D-page 372 Preliminary See Note 2 — 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-14: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +140°C for High Temperature Characteristic Min Typ Max Units 600 50 A A Conditions Reference Inputs HAD08 Note 1: 2: Current Drain IREF — — 250 — ADC operating, See Note 1 ADC off, See Note 1 These parameters are not characterized or tested in manufacturing. These parameters are characterized, but are not tested in manufacturing. TABLE 31-15: ADC MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +140°C for High Temperature Param No. Symbol Characteristic Min Typ Max Units Conditions ADC Accuracy (12-bit Mode) – Measurements with External VREF+/VREF-(1) HAD20a Nr Resolution 12 data bits HAD21a INL Integral Nonlinearity HAD22a DNL Differential Nonlinearity HAD23a GERR HAD24a EOFF bits — -2 — +2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V > -1 — <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V Gain Error -2 — 10 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V Offset Error -3 — 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V ADC Accuracy (12-bit Mode) – Measurements with Internal VREF+/VREF-(1) HAD20a Nr Resolution 12 data bits HAD21a INL Integral Nonlinearity HAD22a DNL Differential Nonlinearity HAD23a GERR HAD24a EOFF bits — -2 — +2 LSb VINL = AVSS = 0V, AVDD = 3.6V > -1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6V Gain Error 2 — 20 LSb VINL = AVSS = 0V, AVDD = 3.6V Offset Error 2 — 10 LSb VINL = AVSS = 0V, AVDD = 3.6V Dynamic Performance (12-bit Mode) Input Signal Bandwidth HAD33a FNYQ Note 1: 2: These parameters are characterized, but are tested at 20 ksps only. These parameters are characterized by similarity, but are not tested in manufacturing. 2009 Microchip Technology Inc. — — Preliminary 200 (2) kHz — DS70292D-page 373 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-16: ADC MODULE SPECIFICATIONS (10-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +140°C for High Temperature Param No. Symbol Characteristic Min Typ Max Units Conditions ADC Accuracy (10-bit Mode) – Measurements with External VREF+/VREF-(1) HAD20b Nr Resolution HAD21b INL Integral Nonlinearity 10 data bits HAD22b DNL Differential Nonlinearity HAD23b GERR HAD24b EOFF bits — -3 — 3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V > -1 — <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V Gain Error -5 — 6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V Offset Error -1 — 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V ADC Accuracy (10-bit Mode) – Measurements with Internal VREF+/VREF-(1) HAD20b Nr Resolution HAD21b INL Integral Nonlinearity 10 data bits HAD22b DNL Differential Nonlinearity HAD23b GERR Gain Error HAD24b EOFF Offset Error bits — -2 — 2 LSb VINL = AVSS = 0V, AVDD = 3.6V > -1 — <1 LSb VINL = AVSS = 0V, AVDD = 3.6V -5 — 15 LSb VINL = AVSS = 0V, AVDD = 3.6V -1.5 — 7 LSb VINL = AVSS = 0V, AVDD = 3.6V Dynamic Performance (10-bit Mode)(2) HAD33b FNYQ Note 1: 2: These parameters are characterized, but are tested at 20 ksps only. These parameters are characterized by similarity, but are not tested in manufacturing. DS70292D-page 374 Input Signal Bandwidth — — Preliminary 400 kHz — 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-17: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +140°C for High Temperature Param No. Symbol Characteristic Min Typ Max Units Conditions — — ns — — 400 Ksps — Clock Parameters HAD50 TAD (1) ADC Clock Period 147 Conversion Rate HAD56 Note 1: FCNV Throughput Rate(1) — These parameters are characterized but not tested in manufacturing. TABLE 31-18: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C TA +140°C for High Temperature Param No. Symbol Characteristic Min Typ Max Units Conditions — ns — 800 Ksps — Clock Parameters HAD50 TAD ADC Clock Period(1) 104 — Conversion Rate Throughput Rate(1) — — HAD56 FCNV Note 1: These parameters are characterized but not tested in manufacturing. 2009 Microchip Technology Inc. Preliminary DS70292D-page 375 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 376 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 32.0 PACKAGING INFORMATION 28-Lead SPDIP Example dsPIC33FJ32GP 302-E/SP e3 0730235 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC (.300”) Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN dsPIC33FJ32GP 302-E/SO e3 0730235 28-Lead QFN-S Example XXXXXXXX XXXXXXXX YYWWNNN 33FJ32GP 302EMM e3 0730235 44-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN dsPIC 33FJ32GP304 -E/ML e3 0730235 Example 44-Lead TQFP dsPIC 33FJ32GP304 -I/PT e3 0730235 XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. 2009 Microchip Technology Inc. Preliminary DS70292D-page 377 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 32.1 Package Details 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .335 Molded Package Width E1 .240 .285 .295 Overall Length D 1.345 1.365 1.400 Tip to Seating Plane L .110 .130 .150 Lead Thickness c .008 .010 .015 b1 .040 .050 .070 b .014 .018 .022 eB – – Upper Lead Width Lower Lead Width Overall Row Spacing § .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-070B DS70292D-page 378 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e b h α A2 A h c φ L A1 Units Dimension Limits Number of Pins β L1 MILLMETERS MIN N NOM MAX 28 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.30 Overall Width E Molded Package Width E1 7.50 BSC Overall Length D 17.90 BSC 2.65 10.30 BSC Chamfer (optional) h 0.25 – 0.75 Foot Length L 0.40 – 1.27 Footprint L1 1.40 REF Foot Angle Top φ 0° – 8° Lead Thickness c 0.18 – 0.33 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-052B 2009 Microchip Technology Inc. Preliminary DS70292D-page 379 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 28-Lead Plastic Quad Flat, No Lead Package (MM) – 6x6x0.9 mm Body [QFN-S] with 0.40 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E2 E b 2 2 1 1 K N N L NOTE 1 TOP VIEW BOTTOM VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E Exposed Pad Width E2 Overall Length D Exposed Pad Length D2 3.65 3.70 4.70 b 0.23 0.38 0.43 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Contact Width 6.00 BSC 3.65 3.70 4.70 6.00 BSC Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-124B DS70292D-page 380 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 !! "# $%& ' ( ) !! *+ + ( , ! " # $% &"' "" ($ ) % *++&&&! !+ $ 2009 Microchip Technology Inc. Preliminary DS70292D-page 381 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 44 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E Exposed Pad Width E2 Overall Length D Exposed Pad Length D2 6.30 6.45 6.80 b 0.25 0.30 0.38 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Contact Width 8.00 BSC 6.30 6.45 6.80 8.00 BSC Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-103B DS70292D-page 382 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 )) , !! "# $& ! " # $% &"' "" ($ ) % *++&&&! !+ $ 2009 Microchip Technology Inc. Preliminary DS70292D-page 383 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 )) , -(+ . - /// !! "# !! $- & ! " # $% &"' "" ($ ) % *++&&&! !+ $ D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 6 " !" 7! " 8#!. )7%" 772 2 8 8 89 : 7%( 9, < = = 3 3 3 = 3 3 > 3 %%($ $"" % )) 7 7 7 I 9, @% ;5/ 2 ? 3? ? 2 5/ 9, 7 5/ %%($@% 2 5/ %%($7 5/ 7% $"" 7%@% % ) % ) 5 ! = . 3 D ? ? ? E ? ? ? , (,"#%-) # !, '.# !#" . %& % / !) " " 0"1!, !" "%2% #%! %)" #" " %)" #" "" -%3!! "% !" % 243 5/* 5"!" - ,#" && # " 2* ) !" '#"#& # ') ) ! # "" DS70292D-page 384 Preliminary & />5 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 )) , -(+ . - /// !! "# !! $- & ! " # $% &"' "" ($ ) % *++&&&! !+ $ 2009 Microchip Technology Inc. Preliminary DS70292D-page 385 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 386 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 APPENDIX A: REVISION HISTORY Revision A (September 2007) Initial release of this document. Revision B (March 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. In addition, redundant information was removed that is now available in the respective chapters of the dsPIC33F/PIC24H Family Reference Manual, which can be obtained from the Microchip website (www.microchip.com). The major changes are referenced by their respective section in the following table. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-Bit Digital Signal Controllers” Note 1 added to all pin diagrams (see “Pin Diagrams”). Section 1.0 “Device Overview” Updated parameters PMA0, PMA1, and PMD0 through PMPD7 (Table 1-1). Section 6.0 “Interrupt Controller” IFS0-IFSO4 changed to IFSX (see Section 6.3.2 “IFSx”). Add External Interrupts column and Note 3 to the “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” table. IEC0-IEC4 changed to IECX (see Section 6.3.3 “IECx”). IPC0-IPC19 changed to IPCx (see Section 6.3.4 “IPCx”). Section 7.0 “Direct Memory Access (DMA)” Updated parameter PMP (see Table 7-1). Section 8.0 “Oscillator Configuration” Updated the third clock source item (External Clock) in Section 8.1.1 “System Clock Sources”. Updated TUN<5:0> (OSCTUN<5:0>) bit description (see Register 8-4). Section 20.0 “10-Bit/12-Bit Analog-to-Digital Added Note 2 to Figure 20-3. Converter (ADC1)” Section 26.0 “Special Features” Added Note 2 to Figure 26-1. Added Note after second paragraph in Section 26.2 “On-Chip Voltage Regulator”. Section 29.0 “Electrical Characteristics” Updated Max MIPS for temperature range of -40ºC to +125ºC in Table 29-1. Updated typical values in Thermal Packaging Characteristics in Table 29-3. Added parameters DI11 and DI12 to Table 29-9. Updated minimum values for parameters D136 (TRW) and D137 (TPE) and removed typical values in Table 29-12. Added Extended temperature range to Table 29-13. Updated parameter AD63 and added Note 3 to Table 29-40 and Table 29-41. 2009 Microchip Technology Inc. Preliminary DS70292D-page 387 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Revision C (May 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: • Changed all instances of OSCI to OSC1 and OSCO to OSC2 • Changed all instances of VDDCORE and VDDCORE/ VCAP to VCAP/VDDCORE The other changes are referenced by their respective section in the following table. TABLE A-2: MAJOR SECTION UPDATES Section Name High-Performance, 16-Bit Digital Signal Controllers Update Description Updated all pin diagrams to denote the pin voltage tolerance (see “Pin Diagrams”). Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which references pin connections to VSS. Section 1.0 “Device Overview” Updated AVDD in the PINOUT I/O Descriptions (see Table 1-1). Added Peripheral Pin Select (PPS) capability column to Pinout I/O Descriptions (see Table 1-1). Section 2.0 “Guidelines for Getting Started with 16-Bit Digital Signal Controllers” Added new section to the data sheet that provides guidelines on getting started with 16-bit Digital Signal Controllers. Section 3.0 “CPU” Updated CPU Core Block Diagram with a connection from the DSP Engine to the Y Data Bus (see Figure 3-1). Vertically extended the X and Y Data Bus lines in the DSP Engine Block Diagram (see Figure 3-3). Section 4.0 “Memory Organization” Updated Reset value for CORCON in the CPU Core Register Map (see Table 4-1). Updated the Reset values for IPC14 and IPC15 and removed the FLTA1IE bit (IEC3) from the Interrupt Controller Register Map (see Table 4-4). Updated bit locations for RPINR25 in the Peripheral Pin Select Input Register Map (see Table 4-21). Updated the Reset value for CLKDIV in the System Control Register Map (see Table 4-33). Section 5.0 “Flash Program Memory” Updated Section 5.3 “Programming Operations” with programming time formula. Section 9.0 “Oscillator Configuration” Updated the Oscillator System Diagram and added Note 2 (see Figure 9-1). Added Note 1 and Note 2 to the OSCON register (see Register 9-1). Updated default bit values for DOZE<2:0> and FRCDIV<2:0> in the Clock Divisor (CLKDIV) Register (see Register 9-2). Added a paragraph regarding FRC accuracy at the end of Section 9.1.1 “System Clock Sources”. Added Note 3 to Section 9.2.2 “Oscillator Switching Sequence”. Added Note 1 to the FRC Oscillator Tuning (OSCTUN) Register (see Register 9-4). DS70292D-page 388 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section 10.0 “Power-Saving Features” Added the following registers: Section 11.0 “I/O Ports” Removed Table 11-1 and added reference to pin diagrams for I/O pin availability and functionality. • PMD1: Peripheral Module Disable Control Register 1 (Register 10-1) • PMD2: Peripheral Module Disable Control Register 2 (Register 10-2) • PMD3: Peripheral Module Disable Control Register 3 (Register 10-3) Added paragraph on ADPCFG register default values to Section 11.3 “Configuring Analog Port Pins”. Added Note box regarding PPS functionality with input mapping to Section 11.6.2.1 “Input Mapping”. Section 16.0 “Serial Peripheral Interface (SPI)” Added Note 2 and 3 to the SPIxCON1 register (see Register 16-2). Section 18.0 “Universal Updated the Notes in the UxMode register (see Register 18-1). Asynchronous Receiver Transmitter Updated the UTXINV bit settings in the UxSTA register and added Note 1 (UART)” (see Register 18-2). Section 19.0 “Enhanced CAN (ECAN™) Module” Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved (see Register 19-1). Section 21.0 “10-Bit/12-Bit Analogto-Digital Converter (ADC)” Replaced the ADC1 Module Block Diagrams with new diagrams (see Figure 21-1 and Figure 21-2). Updated bit values for ADCS<7:0> and added Notes 1 and 2 to the ADC1 Control Register 3 (AD1CON3) (see Register 21-3). Added Note 2 to the ADC1 Input Scan Select Register Low (AD1CSSL) (see Register 21-7). Added Note 2 to the ADC1 Port Configuration Register Low (AD1PCFGL) (see Register 21-8). Section 22.0 “Audio Digital-toAnalog Converter (DAC)” Updated the midpoint voltage in the last sentence of the first paragraph. Section 23.0 “Comparator Module” Updated the Comparator Voltage Reference Block Diagram (see Figure 23-2). Section 24.0 “Real-Time Clock and Calendar (RTCC)” Updated the minimum positive adjust value for CAL<7:0> in the RTCC Calibration and Configuration (RCFGCAL) Register (see Register 24-1). Section 27.0 “Special Features” Added Note 1 to the Device Configuration Register Map (see Table 27-1). Updated the voltage swing values in the last sentence of the last paragraph in Section 22.3 “DAC Output Format”. Updated Note 1 in the dsPIC33F Configuration Bits Description (see Table 27-2). 2009 Microchip Technology Inc. Preliminary DS70292D-page 389 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 30.0 “Electrical Characteristics” Update Description Updated Typical values for Thermal Packaging Characteristics (see Table 30-3). Updated Min and Max values for parameter DC12 (RAM Data Retention Voltage) and added Note 4 (see Table 30-4). Updated Power-Down Current Max values for parameters DC60b and DC60c (see Table 30-7). Updated Characteristics for I/O Pin Input Specifications and added parameter DI21 (see Table 30-9). Updated Program Memory values for parameters 136, 137, and 138 (renamed to 136a, 137a, and 138a), added parameters 136b, 137b, and 138b, and added Note 2 (see Table 30-12). Added parameter OS42 (GM) to the External Clock Timing Requirements (see Table 30-16). Updated Watchdog Timer Time-out Period parameter SY20 (see Table 30-21). Updated the IREF Current Drain parameter AD08 (see Table 30-37). Updated parameters AD30a, AD31a, AD32a, AD33a, and AD34a (see Table 30-38) Updated parameters AD30b, AD31b, AD32b, AD33b, and AD34b (see Table 30-39) DS70292D-page 390 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Revision D (November 2009) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-3: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-Bit Digital Signal Controllers” Added information on high temperature operation (see “Operating Range:”). Section 11.0 “I/O Ports” Changed the reference to digital-only pins to 5V tolerant pins in the second paragraph of Section 11.2 “Open-Drain Configuration”. Section 18.0 “Universal Asynchronous Receiver Transmitter (UART)” Updated the two baud rate range features to: 10 Mbps to 38 bps at 40 MIPS. Section 21.0 “10-Bit/12-Bit Analog-toDigital Converter (ADC)” Updated the ADC block diagrams (see Figure 21-1 and Figure 21-2). Section 22.0 “Audio Digital-to-Analog Converter (DAC)” Removed last sentence of the first paragraph in the section. Added a shaded note to Section 22.2 “DAC Module Operation”. Updated Figure 22-2: “Audio DAC Output for Ramp Input (Unsigned)”. Section 27.0 “Special Features” Updated the second paragraph and removed the fourth paragraph in Section 27.1 “Configuration Bits”. Updated the Device Configuration Register Map (see Table 27-1). Section 30.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings for high temperature and added Note 4. Removed parameters DI26, DI28, and DI29 from the I/O Pin Input Specifications (see Table 30-9). Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics (see Figure 30-12). Removed Table 30-43: Audio DAC Module Specifications. Original contents were updated and combined with Table 30-42 of the same name. Section 31.0 “High Temperature Electrical Characteristics” Added new chapter with high temperature specifications. “Product Identification System” Added the “H” definition for high temperature. 2009 Microchip Technology Inc. Preliminary DS70292D-page 391 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 392 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 INDEX A CPU A/D Converter ................................................................... 253 DMA .......................................................................... 253 Initialization ............................................................... 253 Key Features............................................................. 253 AC Characteristics .................................................... 332, 372 ADC Module.............................................................. 375 ADC Module (10-bit Mode) ....................................... 376 ADC Module (12-bit Mode) ....................................... 375 Internal RC Accuracy ................................................ 334 Load Conditions ................................................ 332, 372 ADC Module ADC11 Register Map .................................................. 51 Alternate Interrupt Vector Table (AIVT) .............................. 87 Arithmetic Logic Unit (ALU)................................................. 32 Assembler MPASM Assembler................................................... 320 B Barrel Shifter ....................................................................... 36 Bit-Reversed Addressing .................................................... 66 Example ...................................................................... 67 Implementation ........................................................... 66 Sequence Table (16-Entry)......................................... 67 Block Diagrams 16-bit Timer1 Module ................................................ 187 A/D Module ....................................................... 254, 255 Connections for On-Chip Voltage Regulator............. 305 DCI Module ............................................................... 247 Device Clock ..................................................... 141, 143 DSP Engine ................................................................ 33 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 ......................... 16 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 CPU Core........ 26 ECAN Module ........................................................... 222 Input Capture ............................................................ 195 Output Compare ....................................................... 197 PLL............................................................................ 143 Reset System.............................................................. 79 Shared Port Structure ............................................... 159 SPI ............................................................................ 201 Timer2 (16-bit) .......................................................... 189 Timer2/3 (32-bit) ....................................................... 191 UART ........................................................................ 215 Watchdog Timer (WDT) ............................................ 306 C C Compilers Hi-Tech C.................................................................. 320 MPLAB C .................................................................. 320 Clock Switching................................................................. 151 Enabling .................................................................... 151 Sequence.................................................................. 151 Code Examples Erasing a Program Memory Page............................... 77 Initiating a Programming Sequence............................ 78 Loading Write Buffers ................................................. 78 Port Write/Read ........................................................ 160 PWRSAV Instruction Syntax..................................... 153 Code Protection ........................................................ 301, 307 Comparator Module .......................................................... 265 Configuration Bits.............................................................. 301 Configuration Register Map .............................................. 301 Configuring Analog Port Pins ............................................ 160 2009 Microchip Technology Inc. Control Register.......................................................... 28 CPU Clocking System ...................................................... 142 PLL Configuration..................................................... 143 Selection................................................................... 142 Sources .................................................................... 142 Customer Change Notification Service............................. 401 Customer Notification Service .......................................... 401 Customer Support............................................................. 401 D Data Accumulators and Adder/Subtracter .......................... 34 Data Space Write Saturation ...................................... 36 Overflow and Saturation ............................................. 34 Round Logic ............................................................... 35 Write Back .................................................................. 35 Data Address Space........................................................... 39 Alignment.................................................................... 39 Memory Map for dsPIC33FJ128GP202/204 and dsPIC33FJ64GP202/204 Devices with 8 KB RAM ................................................... 41 Memory Map for dsPIC33FJ128GP802/804 and dsPIC33FJ64GP802/804 Devices with 16 KB RAM ................................................. 42 Memory Map for dsPIC33FJ32GP302/304 Devices with 4 KB RAM...................................... 40 Near Data Space ........................................................ 39 Software Stack ........................................................... 63 Width .......................................................................... 39 Data Converter Interface (DCI) Module ............................ 247 DC Characteristics............................................................ 324 Doze Current (IDOZE)................................................ 371 High Temperature..................................................... 370 I/O Pin Input Specifications ...................................... 329 I/O Pin Output........................................................... 371 I/O Pin Output Specifications.................................... 330 Idle Current (IDOZE) .................................................. 328 Idle Current (IIDLE) .................................................... 327 Operating Current (IDD) ............................................ 326 Operating MIPS vs. Voltage ..................................... 370 Power-Down Current (IPD)........................................ 328 Power-down Current (IPD) ........................................ 370 Program Memory.............................................. 331, 371 Temperature and Voltage......................................... 370 Temperature and Voltage Specifications.................. 325 Thermal Operating Conditions.................................. 370 DCI Introduction............................................................... 247 DCI Module Register Map .............................................................. 56 Demonstration/Development Boards, Evaluation Kits, and Starter Kits......................................................... 322 Development Support ....................................................... 319 DMA Module DMA Register Map ..................................................... 52 DMAC Registers ............................................................... 131 DMAxCNT ................................................................ 131 DMAxCON................................................................ 131 DMAxPAD ................................................................ 131 DMAxREQ ................................................................ 131 DMAxSTA ................................................................. 131 DMAxSTB ................................................................. 131 Doze Mode ....................................................................... 154 DSP Engine ........................................................................ 32 Multiplier ..................................................................... 34 Preliminary DS70292D-page 393 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 E ECAN Module CiBUFPNT1 register ................................................. 233 CiBUFPNT2 register ................................................. 234 CiBUFPNT3 register ................................................. 234 CiBUFPNT4 register ................................................. 235 CiCFG1 register ........................................................ 231 CiCFG2 register ........................................................ 232 CiCTRL1 register ...................................................... 224 CiCTRL2 register ...................................................... 225 CiEC register............................................................. 231 CiFCTRL register ...................................................... 227 CiFEN1 register ........................................................ 233 CiFIFO register ......................................................... 228 CiFMSKSEL1 register ............................................... 237 CiFMSKSEL2 register ............................................... 238 CiINTE register ......................................................... 230 CiINTF register.......................................................... 229 CiRXFnEID register .................................................. 237 CiRXFnSID register .................................................. 236 CiRXFUL1 register .................................................... 240 CiRXFUL2 register .................................................... 240 CiRXMnEID register.................................................. 239 CiRXMnSID register.................................................. 239 CiRXOVF1 register ................................................... 241 CiRXOVF2 register ................................................... 241 CiTRmnCON register ................................................ 242 CiVEC register .......................................................... 226 ECAN1 Register Map (C1CTRL1.WIN = 0 or 1) ......... 54 ECAN1 Register Map (C1CTRL1.WIN = 0) ................ 54 ECAN1 Register Map (C1CTRL1.WIN = 1) ................ 55 Frame Types ............................................................. 221 Modes of Operation .................................................. 223 Overview ................................................................... 221 ECAN Registers Acceptance Filter Enable Register (CiFEN1)............ 233 Acceptance Filter Extended Identifier Register n (CiRXFnEID) ..................................................... 237 Acceptance Filter Mask Extended Identifier Register n (CiRXMnEID) .................................................... 239 Acceptance Filter Mask Standard Identifier Register n (CiRXMnSID) .................................................... 239 Acceptance Filter Standard Identifier Register n (CiRXFnSID)................................................................. 236 Baud Rate Configuration Register 1 (CiCFG1) ......... 231 Baud Rate Configuration Register 2 (CiCFG2) ......... 232 Control Register 1 (CiCTRL1) ................................... 224 Control Register 2 (CiCTRL2) ................................... 225 FIFO Control Register (CiFCTRL) ............................ 227 FIFO Status Register (CiFIFO) ................................. 228 Filter 0-3 Buffer Pointer Register (CiBUFPNT1) ....... 233 Filter 12-15 Buffer Pointer Register (CiBUFPNT4) ... 235 Filter 15-8 Mask Selection Register (CiFMSKSEL2). 238 Filter 4-7 Buffer Pointer Register (CiBUFPNT2) ....... 234 Filter 7-0 Mask Selection Register (CiFMSKSEL1)... 237 Filter 8-11 Buffer Pointer Register (CiBUFPNT3) ..... 234 Interrupt Code Register (CiVEC) .............................. 226 Interrupt Enable Register (CiINTE) ........................... 230 Interrupt Flag Register (CiINTF) ............................... 229 Receive Buffer Full Register 1 (CiRXFUL1).............. 240 Receive Buffer Full Register 2 (CiRXFUL2).............. 240 Receive Buffer Overflow Register 2 (CiRXOVF2)..... 241 Receive Overflow Register (CiRXOVF1) .................. 241 ECAN Transmit/Receive Error Count Register (CiEC) ..... 231 DS70292D-page 394 ECAN TX/RX Buffer m Control Register (CiTRmnCON) .. 242 Electrical Characteristics .................................................. 323 AC..................................................................... 332, 372 Enhanced CAN Module .................................................... 221 Equations Device Operating Frequency .................................... 142 Errata .................................................................................. 14 F Flash Program Memory ...................................................... 73 Control Registers ........................................................ 74 Operations .................................................................. 74 Programming Algorithm .............................................. 77 RTSP Operation ......................................................... 74 Table Instructions ....................................................... 73 Flexible Configuration ....................................................... 301 H High Temperature Electrical Characteristics .................... 369 I I/O Ports............................................................................ 159 Parallel I/O (PIO) ...................................................... 159 Write/Read Timing .................................................... 160 I2C Operating Modes ...................................................... 207 Registers .................................................................. 207 In-Circuit Debugger........................................................... 307 In-Circuit Emulation .......................................................... 301 In-Circuit Serial Programming (ICSP)....................... 301, 307 Input Capture .................................................................... 195 Registers .................................................................. 196 Input Change Notification ................................................. 160 Instruction Addressing Modes ............................................ 63 File Register Instructions ............................................ 63 Fundamental Modes Supported ................................. 64 MAC Instructions ........................................................ 64 MCU Instructions ........................................................ 63 Move and Accumulator Instructions............................ 64 Other Instructions ....................................................... 64 Instruction Set Overview................................................................... 314 Summary .................................................................. 311 Instruction-Based Power-Saving Modes........................... 153 Idle ............................................................................ 154 Sleep ........................................................................ 153 Internal RC Oscillator Use with WDT........................................................... 306 Internet Address ............................................................... 401 Interrupt Control and Status Registers ............................... 91 IECx ............................................................................ 91 IFSx ............................................................................ 91 INTCON1 .................................................................... 91 INTCON2 .................................................................... 91 IPCx ............................................................................ 91 Interrupt Setup Procedures............................................... 128 Initialization ............................................................... 128 Interrupt Disable ....................................................... 128 Interrupt Service Routine .......................................... 128 Trap Service Routine ................................................ 128 Interrupt Vector Table (IVT) ................................................ 87 Interrupts Coincident with Power Save Instructions ......... 154 J JTAG Boundary Scan Interface ........................................ 301 JTAG Interface.................................................................. 307 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 M R Memory Organization.......................................................... 37 Microchip Internet Web Site .............................................. 401 Modes of Operation Disable ...................................................................... 223 Initialization ............................................................... 223 Listen All Messages .................................................. 223 Listen Only ................................................................ 223 Loopback .................................................................. 223 Normal Operation...................................................... 223 Modulo Addressing ............................................................. 65 Applicability ................................................................. 66 Operation Example ..................................................... 65 Start and End Address................................................ 65 W Address Register Selection .................................... 65 MPLAB ASM30 Assembler, Linker, Librarian ................... 320 MPLAB ICD 3 In-Circuit Debugger System ...................... 321 MPLAB Integrated Development Environment Software .. 319 MPLAB PM3 Device Programmer .................................... 322 MPLAB REAL ICE In-Circuit Emulator System................. 321 MPLINK Object Linker/MPLIB Object Librarian ................ 320 Reader Response............................................................. 402 Register Map CRC............................................................................ 60 Dual Comparator ........................................................ 60 Parallel Master/Slave Port .......................................... 59 Real-Time Clock and Calendar .................................. 60 Registers AD1CHS0 (ADC1 Input Channel 0 Select................ 263 AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 262 AD1CON1 (ADC1 Control 1) .................................... 257 AD1CON2 (ADC1 Control 2) .................................... 259 AD1CON3 (ADC1 Control 3) .................................... 260 AD1CON4 (ADC1 Control 4) .................................... 261 AD1CSSL (ADC1 Input Scan Select Low) ............... 264 AD1PCFGL (ADC1 Port Configuration Low) ............ 264 CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer) .......... 233 CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer) .......... 234 CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer) ........ 234 CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer) ...... 235 CiCFG1 (ECAN Baud Rate Configuration 1)............ 231 CiCFG2 (ECAN Baud Rate Configuration 2)............ 232 CiCTRL1 (ECAN Control 1) ...................................... 224 CiCTRL2 (ECAN Control 2) ...................................... 225 CiEC (ECAN Transmit/Receive Error Count) ........... 231 CiFCTRL (ECAN FIFO Control) ............................... 227 CiFEN1 (ECAN Acceptance Filter Enable)............... 233 CiFIFO (ECAN FIFO Status) .................................... 228 CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection) .... 237, 238 CiINTE (ECAN Interrupt Enable) .............................. 230 CiINTF (ECAN Interrupt Flag) .................................. 229 CiRXFnEID (ECAN Acceptance Filter n Extended Identifier) .......................................... 237 CiRXFnSID (ECAN Acceptance Filter n Standard Identifier) ........................................... 236 CiRXFUL1 (ECAN Receive Buffer Full 1)................. 240 CiRXFUL2 (ECAN Receive Buffer Full 2)................. 240 CiRXMnEID (ECAN Acceptance Filter Mask n Extended Identifier) .......................................... 239 CiRXMnSID (ECAN Acceptance Filter Mask n Standard Identifier) ........................................... 239 CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 241 CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 241 CiTRBnSID (ECAN Buffer n Standard Identifier)..... 243, 244, 246 CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 242 CiVEC (ECAN Interrupt Code) ................................. 226 CLKDIV (Clock Divisor) ............................................ 147 CORCON (Core Control) ...................................... 30, 93 DCICON1 (DCI Control 1) ........................................ 248 DCICON2 (DCI Control 2) ........................................ 249 DCICON3 (DCI Control 3) ........................................ 250 DCISTAT (DCI Status) ............................................. 251 DMACS0 (DMA Controller Status 0) ........................ 136 DMACS1 (DMA Controller Status 1) ........................ 138 DMAxCNT (DMA Channel x Transfer Count) ........... 135 DMAxCON (DMA Channel x Control)....................... 132 DMAxPAD (DMA Channel x Peripheral Address) .... 135 DMAxREQ (DMA Channel x IRQ Select) ................. 133 DMAxSTA (DMA Channel x RAM Start Address A) . 134 DMAxSTB (DMA Channel x RAM Start Address B) . 134 DSADR (Most Recent DMA RAM Address) ............. 139 I2CxCON (I2Cx Control)........................................... 209 I2CxMSK (I2Cx Slave Mode Address Mask)............ 213 I2CxSTAT (I2Cx Status) ........................................... 211 N NVM Module Register Map............................................................... 62 O Open-Drain Configuration ................................................. 160 Output Compare ............................................................... 197 P Packaging ......................................................................... 379 Details ....................................................................... 380 Marking ..................................................................... 379 Peripheral Module Disable (PMD) .................................... 154 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express............................................ 322 PICkit 3 In-Circuit Debugger/Programmer and PICkit 3 Debug Express............................................ 321 Pinout I/O Descriptions (table) ............................................ 17 PMD Module Register Map............................................................... 62 PORTA Register Map......................................................... 60, 61 PORTB Register Map............................................................... 61 Power-on Reset (POR) ....................................................... 84 Power-Saving Features .................................................... 153 Clock Frequency and Switching................................ 153 Program Address Space ..................................................... 37 Construction................................................................ 68 Data Access from Program Memory Using Program Space Visibility........................... 71 Data Access from Program Memory Using Table Instructions ..................................... 70 Data Access from, Address Generation...................... 69 Memory Map ............................................................... 37 Table Read Instructions TBLRDH ............................................................. 70 TBLRDL .............................................................. 70 Visibility Operation ...................................................... 71 Program Memory Interrupt Vector ........................................................... 38 Organization................................................................ 38 Reset Vector ............................................................... 38 2009 Microchip Technology Inc. Preliminary DS70292D-page 395 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 IFS0 (Interrupt Flag Status 0) ............................. 97, 104 IFS1 (Interrupt Flag Status 1) ............................. 99, 106 IFS2 (Interrupt Flag Status 2) ........................... 101, 108 IFS3 (Interrupt Flag Status 3) ........................... 102, 109 IFS4 (Interrupt Flag Status 4) ........................... 103, 110 INTCON1 (Interrupt Control 1) .................................... 94 INTCON2 (Interrupt Control 2) .................................... 96 INTTREG Interrupt Control and Status Register....... 127 IPC0 (Interrupt Priority Control 0) ............................. 111 IPC1 (Interrupt Priority Control 1) ............................. 112 IPC11 (Interrupt Priority Control 11) ......................... 121 IPC14 (Interrupt Priority Control 14) ......................... 122 IPC15 (Interrupt Priority Control 15) ......................... 123 IPC16 (Interrupt Priority Control 16) ......................... 124 IPC17 (Interrupt Priority Control 17) ......................... 125 IPC18 (Interrupt Priority Control 18) ......................... 126 IPC2 (Interrupt Priority Control 2) ............................. 113 IPC3 (Interrupt Priority Control 3) ............................. 114 IPC4 (Interrupt Priority Control 4) ............................. 115 IPC5 (Interrupt Priority Control 5) ............................. 116 IPC6 (Interrupt Priority Control 6) ............................. 117 IPC7 (Interrupt Priority Control 7) ............................. 118 IPC8 (Interrupt Priority Control 8) ............................. 119 IPC9 (Interrupt Priority Control 9) ............................. 120 NVMCON (Flash Memory Control) ............................. 75 NVMKEY (Nonvolatile Memory Key) .......................... 76 OCxCON (Output Compare x Control) ..................... 199 OSCCON (Oscillator Control) ................................... 145 OSCTUN (FRC Oscillator Tuning) ............................ 149 PLLFBD (PLL Feedback Divisor) .............................. 148 PMD1 (Peripheral Module Disable Control Register 1)............................................ 155 PMD2 (Peripheral Module Disable Control Register 2)............................................ 156 PMD3 (Peripheral Module Disable Control Register 3)............................................ 157 PxTCON (PWM Time Base Control)......... 267, 268, 269 RCON (Reset Control) ................................................ 80 RSCON (DCI Receive Slot Control).......................... 252 SPIxCON1 (SPIx Control 1) ...................................... 203 SPIxCON2 (SPIx Control 2) ...................................... 205 SPIxSTAT (SPIx Status and Control) ....................... 202 SR (CPU Status) ................................................... 28, 92 T1CON (Timer1 Control)........................................... 188 TCxCON (Input Capture x Control) ........................... 196 TSCON (DCI Transmit Slot Control) ......................... 252 TxCON (Type B Time Base Control) ........................ 192 TyCON (Type C Time Base Control) ........................ 193 UxMODE (UARTx Mode) .......................................... 216 UxSTA (UARTx Status and Control) ......................... 218 Reset Illegal Opcode ....................................................... 79, 86 Trap Conflict.......................................................... 85, 86 Uninitialized W Register ........................................ 79, 86 Reset Sequence.................................................................. 87 Resets ................................................................................. 79 S Serial Peripheral Interface (SPI) ....................................... 201 Software Reset Instruction (SWR) ...................................... 85 Software Simulator (MPLAB SIM)..................................... 321 Software Stack Pointer, Frame Pointer CALL Stack Frame...................................................... 63 Special Features of the CPU............................................. 301 SPI Module SPI1 Register Map ...................................................... 50 Symbols Used in Opcode Descriptions............................. 312 DS70292D-page 396 System Control Register Map .............................................................. 62 T Temperature and Voltage Specifications AC..................................................................... 332, 372 Timer1............................................................................... 187 Timer2/3............................................................................ 189 Timing Characteristics CLKO and I/O ........................................................... 335 Timing Diagrams 10-bit A/D Conversion (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)... 361 10-bit A/D Conversion (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)...................................... 361 12-bit A/D Conversion (ASAM = 0, SSRC<2:0> = 000)........................ 359 Brown-out Situations................................................... 85 DCI AC-Link Mode.................................................... 353 DCI Multi -Channel, I2S Modes................................. 351 ECAN I/O .................................................................. 355 External Clock........................................................... 333 I2Cx Bus Data (Master Mode) .................................. 347 I2Cx Bus Data (Slave Mode) .................................... 349 I2Cx Bus Start/Stop Bits (Master Mode)................... 347 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 349 Input Capture (CAPx) ............................................... 340 OC/PWM................................................................... 341 Output Compare (OCx)............................................. 340 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ......................................... 336 SPIx Master Mode (CKE = 0) ................................... 342 SPIx Master Mode (CKE = 1) ................................... 343 SPIx Slave Mode (CKE = 0) ..................................... 344 SPIx Slave Mode (CKE = 1) ..................................... 345 Timer1, 2 and 3 External Clock ................................ 338 Timing Requirements ADC Conversion (10-bit mode)................................. 377 ADC Conversion (12-bit Mode)................................. 377 CLKO and I/O ........................................................... 335 DCI AC-Link Mode.................................................... 354 DCI Multi-Channel, I2S Modes.................................. 352 External Clock........................................................... 333 Input Capture ............................................................ 340 SPIx Master Mode (CKE = 0) ................................... 373 SPIx Module Master Mode (CKE = 1) ...................... 373 SPIx Module Slave Mode (CKE = 0) ........................ 374 SPIx Module Slave Mode (CKE = 1) ........................ 374 Timing Specifications 10-bit A/D Conversion Requirements ....................... 362 12-bit A/D Conversion Requirements ....................... 360 CAN I/O Requirements ............................................. 355 I2Cx Bus Data Requirements (Master Mode)........... 348 I2Cx Bus Data Requirements (Slave Mode)............. 350 Output Compare Requirements................................ 340 PLL Clock ......................................................... 334, 372 QEI External Clock Requirements ............................ 339 QEI Index Pulse Requirements ................................ 342 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ................................................... 337 Simple OC/PWM Mode Requirements ..................... 341 SPIx Master Mode (CKE = 0) Requirements............ 342 SPIx Master Mode (CKE = 1) Requirements............ 343 SPIx Slave Mode (CKE = 0) Requirements.............. 344 SPIx Slave Mode (CKE = 1) Requirements.............. 346 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Timer1 External Clock Requirements ....................... 338 Timer2 External Clock Requirements ....................... 339 Timer3 External Clock Requirements ....................... 339 U UART Module UART1 Register Map............................................ 49, 50 Universal Asynchronous Receiver Transmitter (UART).... 215 Using the RCON Status Bits ............................................... 86 V Voltage Regulator (On-Chip) ............................................ 305 W Watchdog Time-out Reset (WDTR) .................................... 85 Watchdog Timer (WDT) ............................................ 301, 306 Programming Considerations ................................... 306 WWW Address.................................................................. 401 WWW, On-Line Support ..................................................... 14 2009 Microchip Technology Inc. Preliminary DS70292D-page 397 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292D-page 398 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers receives e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com, click on Customer Change Notification and follow the registration instructions. 2009 Microchip Technology Inc. Preliminary DS70292D-page 399 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Data Sheet Literature Number: DS70292D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70292D-page 400 Preliminary 2009 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 32 GP3 02 T E / SP - XXX Examples: a) dsPIC33FJ32GP302-E/SP: General Purpose dsPIC33, 32 KB program memory, 28-pin, Extended temperature, SPDIP package. Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture: 33 = 16-bit Digital Signal Controller Flash Memory Family: FJ = Flash program memory, 3.3V Product Group: GP2 GP3 GP8 = = = General Purpose family General Purpose family General Purpose family Pin Count: 02 04 = = 28-pin 44-pin Temperature Range: I E H = = = -40C to+85C (Industrial) -40C to+125C (Extended) -40C to+140C (High) Package: SP SO ML MM PT = = = = = Skinny Plastic Dual In-Line - 300 mil body (SPDIP) Plastic Small Outline - Wide - 300 mil body (SOIC) Plastic Quad, No Lead Package - 8x8 mm body (QFN) Plastic Quad, No Lead Package - 6x6x0.9 mm body (QFN-S) Plastic Thin Quad Flatpack - 10x10x1 mm body (TQFP) 2009 Microchip Technology Inc. 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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microchip: dsPIC33FJ128GP202-E/MM dsPIC33FJ128GP202-I/MM dsPIC33FJ128GP202T-I/MM dsPIC33FJ128GP206-E/PT dsPIC33FJ128GP306-E/PT dsPIC33FJ128GP310-E/PT dsPIC33FJ128GP310T-I/PF dsPIC33FJ128GP310T-I/PT dsPIC33FJ128GP706-E/PT dsPIC33FJ128GP708-E/PT dsPIC33FJ128GP710-E/PF dsPIC33FJ128GP710-E/PT dsPIC33FJ128GP802-E/MM dsPIC33FJ128GP802-I/MM dsPIC33FJ128GP802T-I/MM dsPIC33FJ32GP302-E/MM dsPIC33FJ64GP802T-I/MM dsPIC33FJ32GP302-I/MM dsPIC33FJ64GP802-I/MM dsPIC33FJ64GP802-E/MM dsPIC33FJ32GP302T-I/MM dsPIC33FJ64GP202T-I/MM dsPIC33FJ64GP202-I/MM dsPIC33FJ128GP310-E/PF dsPIC33FJ64GP202-E/MM dsPIC33FJ128GP202-E/SO dsPIC33FJ128GP202-E/SP dsPIC33FJ128GP202-I/SO dsPIC33FJ128GP202-I/SP dsPIC33FJ128GP202T-I/SO dsPIC33FJ128GP204-E/ML dsPIC33FJ128GP204-E/PT dsPIC33FJ128GP204-I/ML dsPIC33FJ128GP204-I/PT dsPIC33FJ128GP204T-I/ML dsPIC33FJ128GP204T-I/PT dsPIC33FJ128GP802-E/SO dsPIC33FJ128GP802-E/SP dsPIC33FJ128GP802-I/SO dsPIC33FJ128GP802-I/SP dsPIC33FJ128GP802T-I/SO dsPIC33FJ128GP804-E/ML dsPIC33FJ128GP804-E/PT dsPIC33FJ128GP804-I/ML dsPIC33FJ128GP804-I/PT dsPIC33FJ128GP804T-I/ML dsPIC33FJ128GP804T-I/PT dsPIC33FJ32GP302-E/SO dsPIC33FJ32GP302-E/SP dsPIC33FJ32GP302-I/SO dsPIC33FJ32GP302-I/SP dsPIC33FJ32GP302T-I/SO dsPIC33FJ32GP304-E/ML dsPIC33FJ32GP304-E/PT dsPIC33FJ32GP304-I/ML dsPIC33FJ32GP304-I/PT dsPIC33FJ32GP304T-I/ML dsPIC33FJ32GP304T-I/PT dsPIC33FJ64GP202-E/SO dsPIC33FJ64GP202-E/SP dsPIC33FJ64GP202-I/SO dsPIC33FJ64GP202-I/SP dsPIC33FJ64GP202T-I/SO dsPIC33FJ64GP204-E/ML dsPIC33FJ64GP204-E/PT dsPIC33FJ64GP204-I/ML dsPIC33FJ64GP204-I/PT dsPIC33FJ64GP204T-I/ML dsPIC33FJ64GP204T-I/PT dsPIC33FJ64GP802-E/SO dsPIC33FJ64GP802-E/SP dsPIC33FJ64GP802-I/SO dsPIC33FJ64GP802-I/SP dsPIC33FJ64GP802T-I/SO dsPIC33FJ64GP804-E/ML dsPIC33FJ64GP804-E/PT dsPIC33FJ64GP804-I/ML dsPIC33FJ64GP804-I/PT dsPIC33FJ64GP804T-I/ML dsPIC33FJ64GP804T-I/PT dsPIC33FJ128GP206A-I/PT dsPIC33FJ128GP206AT-I/PT dsPIC33FJ128GP306AT-I/PT dsPIC33FJ128GP310A-E/PF dsPIC33FJ128GP310AT-I/PF dsPIC33FJ128GP310AT-I/PT dsPIC33FJ128GP706A-E/PT dsPIC33FJ128GP706ATI/PT dsPIC33FJ128GP708A-E/PT dsPIC33FJ128GP708AT-I/PT dsPIC33FJ128GP710A-E/PT dsPIC33FJ128GP710AT-I/PF dsPIC33FJ128GP710AT-I/PT dsPIC33FJ128GP804-H/PT DSPIC33FJ128GP202-E/SO DSPIC33FJ128GP202-E/SP DSPIC33FJ128GP202-I/SO DSPIC33FJ128GP202-I/SP DSPIC33FJ128GP202T-I/SO DSPIC33FJ128GP204-E/ML