MC74HCT245A Octal 3−State Noninverting Bus Transceiver with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS The MC74HCT245A is identical in pinout to the LS245. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The MC74HCT245A is a 3−state noninverting transceiver that is used for 2−way asynchronous communication between data buses. The device has an active−low Output Enable pin, which is used to place the I/O ports into high−impedance states. The Direction control determines whether data flows from A to B or from B to A. http://onsemi.com PDIP−20 N SUFFIX CASE 738 1 Features • • • • • • • • Output Drive Capability: 15 LSTTL Loads TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 V to 5.5 V Low Input Current: 1.0 mA In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 304 FETs or 76 Equivalent Gates Pb−Free Packages are Available A1 A2 A DATA PORT A3 A4 A5 A6 A7 A8 DIRECTION OUTPUT ENABLE 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 1 1 TSSOP−20 DT SUFFIX CASE 948E 1 B1 B2 B3 B4 B5 B DATA PORT SOEIAJ−20 F SUFFIX CASE 967 1 B6 B7 B8 PIN ASSIGNMENT PIN 20 = VCC PIN 10 = GND 19 SOIC−20W DW SUFFIX CASE 751D Figure 1. Logic Diagram DIRECTION 1 20 VCC A1 2 19 OUTPUT ENABLE A2 3 18 B1 Value Units A3 4 17 B2 Internal Gate Count* 76 ea A4 5 16 B3 Internal Gate Propagation Delay 1.0 ns 6 15 B4 5.0 mW A5 Internal Gate Power Dissipation 0.005 pJ A6 7 14 B5 A7 8 13 B6 FUNCTION TABLE A8 9 12 B7 Control Inputs GND 10 11 B8 Design Criteria Speed Power Product *Equivalent to a two−input NAND gate. Output Enable Direction L L Operation Data Transmitted from Bus B to Bus A L H Data Transmitted from Bus A to Bus B X Buses Isolated (High−Impedance State) H X = Don’t Care © Semiconductor Components Industries, LLC, 2007 January, 2007 − Rev. 10 1 ORDERING INFORMATION See detailed ordering, shipping information, and marking information in the package dimensions section on page 6 of this data sheet. Publication Order Number: MC74HCT245A/D MC74HCT245A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit – 0.5 to + 7.0 V VCC DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 35 mA ICC DC Supply Current, VCC and GND Pins ± 75 mA PD Power Dissipation in Still Air, PDIP† SOIC Package† TSSOP Package† 750 500 450 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Secs (PDIP, SOIC, SSOP or TSSOP Package) _C 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min Max Unit 4.5 5.5 V 0 VCC V – 55 + 125 _C 0 500 ns DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) http://onsemi.com 2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. MC74HCT245A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V – 55 to 25_C v 85_C v 125_C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 mA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 mA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| v 20 mA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V Vin = VIH or VIL |Iout| v 6.0 mA 4.5 3.98 3.84 3.7 Vin = VIH or VIL |Iout| v 20 mA 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 Vin = VIH or VIL |Iout| v 6.0 mA 4.5 0.26 0.33 0.4 VOL Maximum Low−Level Output Voltage V Iin Maximum Input Leakage Current Vin = VCC or GND, Pins 1 or 19 5.5 ± 0.1 ± 1.0 ± 1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 5.5 4.0 40 160 mA IOZ Maximum Three−State Leakage Current Output in High−Impedance State Vin = VIL or VIH Vout = VCC or GND, I/O Pins 5.5 ± 0.5 ± 5.0 ± 10 mA Additional Quiescent Supply Current Vin = 2.4 V, Any One Input Vin = VCC or GND, Other Inputs lout = 0 mA DICC ≥ −55_C 25_C to 125_C 2.9 2.4 5.5 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter – 55 to 25_C v 85_C v 125_C Unit tPLH, tPHL Maximum Propagation Delay, A to B or B to A (Figures 2 and 4) 22 28 33 ns tPLZ, tPHZ Maximum Propagation Delay, Direction or Output Enable to A or B (Figures 3 and 5) 30 36 42 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to A or 8 (Figures 3 and 5) 30 36 42 ns tTLH, tTHL Maximum Output Transition Time. any Output (Figures 2 and 4) 12 15 18 ns Cin Maximum Input Capacitance (Pin 1 or 19) 10 10 10 pF Cout Maximum Three−State I/O Capacitance, (I/O in High−Impedance State) 15 15 15 pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD 97 Power Dissipation Capacitance (Per Enabled Output)* pF * Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). http://onsemi.com 3 MC74HCT245A SWITCHING WAVEFORMS INPUT A OR B OUTPUT B OR A tr tf 3.0 V 2.7 V 1.3 V 0.3 V tPLH tPHL 90% 1.3 V 10% GND tTHL tTLH Figure 2. DIRECTION 1.3 V OUTPUT ENABLE 1.3 V 3.0 V 1.3 V GND 3.0 V A OR B tPZL 1.3 V tPZH A OR B GND tPLZ tPHZ 1.3 V HIGH IMPEDANCE 10% VOL 90% VOH HIGH IMPEDANCE Figure 3. TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST C L* *Includes all probe and jig capacitance 1 kW C L* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 4. Figure 5. Test Circuit http://onsemi.com 4 MC74HCT245A A1 2 18 A2 3 17 A3 A4 OUTPUT ENABLE B6 B7 9 11 DIRECTION B5 8 12 A8 B DATA PORT 7 13 A7 B4 6 14 A6 B3 5 15 A5 B2 4 16 A DATA PORT B1 1 19 Figure 6. Expanded Logic Diagram http://onsemi.com 5 B8 MC74HCT245A ORDERING INFORMATION Device Shipping † Package MC74HCT245AN PDIP−20 MC74HCT245ANG PDIP−20 (Pb−Free) MC74HCT245ADW SOIC−20 MC74HCT245ADWG SOIC−20 (Pb−Free) MC74HCT245ADWR2 SOIC−20 MC74HCT245ADWR2G SOIC−20 (Pb−Free) MC74HCT245ADT TSSOP−20* MC74HCT245ADTG TSSOP−20* MC74HCT245ADTR2 TSSOP−20* MC74HCT245ADTR2G TSSOP−20* MC74HCT245AFELG SOEIAJ−20 (Pb−Free) 18 Units / Rail 38 Units / Rail 1000 / Tape & Reel 75 Units / Rail 2500 / Tape & Reel 2000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *These packages are inherently Pb−Free. MARKING DIAGRAMS PDIP−20 SOIC−20W 20 20 HCT245A AWLYYWWG MC74HCT245AN AWLYYWWG 1 1 TSSOP−20 SOEIAJ−20 20 20 HCT 245A ALYWG G 74HCT245A AWLYWWG 1 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) http://onsemi.com 6 MC74HCT245A PACKAGE DIMENSIONS PDIP−20 N SUFFIX PLASTIC DIP PACKAGE CASE 738−03 ISSUE E −A− 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C −T− K SEATING PLANE M N E G F J D 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) M T A M T B M M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 SOIC−20W DW SUFFIX CASE 751D−05 ISSUE G 20 11 X 45 _ h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q A B M D 18X e A1 SEATING PLANE C T http://onsemi.com 7 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74HCT245A PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X 0.10 (0.004) S L/2 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K REF 20 M T U S V K K1 S J J1 11 B L SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING DIM A B C D F G H J J1 K K1 L M PLANE SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 8 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HCT245A PACKAGE DIMENSIONS SOEIAJ−20 M SUFFIX CASE 967−01 ISSUE A 20 LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D VIEW P e A c DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). M 0.10 (0.004) MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 −−− 0.81 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 −−− 0.032 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 9 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC74HCT245A/D