Data Sheet 2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit nanoDAC, SPI Interface in LFCSP and SC70 AD5601/AD5611/AD5621 FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS GND AD5601/AD5611/AD5621 POWER-ON RESET REF(+) 12-/10-/8-BIT DAC DAC REGISTER INPUT CONTROL LOGIC OUTPUT BUFFER POWER-DOWN CONTROL LOGIC VOUT RESISTOR NETWORK SYNC SCLK SDIN Figure 1. Table 1. Related Devices Part Number AD5641 Description 2.7 V to 5.5 V, <100 µA, 14-bit nanoDAC in SC70 and LFCSP packages They also provide software-selectable output loads while in power-down mode. The parts are put into power-down mode over the serial interface. Voltage level setting Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION The AD5601/AD5611/AD5621, members of the nanoDAC® family, are single, 8-/10-/12-bit, buffered voltage output DACs that operate from a single 2.7 V to 5.5 V supply, consuming typically 75 µA at 5 V. The parts come in tiny LFCSP and SC70 packages. Their on-chip precision output amplifier allows railto-rail output swing to be achieved. The AD5601/AD5611/ AD5621 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards. The reference for the AD5601/AD5611/AD5621 is derived from the power supply inputs and, therefore, gives the widest dynamic output range. The parts incorporate a power-on reset circuit, which ensures that the DAC output powers up to 0 V and remains there until a valid write to the device takes place. The AD5601/AD5611/AD5621 contain a power-down feature that reduces current consumption to typically 0.2 µA at 3 V. Rev. G VDD 06853-001 6-lead SC70 and LFCSP packages Micropower operation: 100 µA maximum at 5 V Power-down typically to 0.2 µA at 3 V 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to 0 V with brownout detection 3 power-down functions Low power serial interface with Schmitt-triggered inputs On-chip output buffer amplifier, rail-to-rail operation SYNC interrupt facility Minimized zero-code error AD5601 buffered 8-bit DAC B version: ±0.5 LSB INL AD5611 buffered 10-bit DAC B version: ±0.5 LSB INL A version: ±4 LSB INL AD5621 buffered 12-bit DAC B version: ±1 LSB INL A version: ±6 LSB INL The low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. The combination of small package and low power makes these nanoDAC devices ideal for level-setting requirements, such as generating bias or control voltages in space-constrained and power-sensitive applications. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. Available in 6-lead LFCSP and SC70 packages. Low power, single-supply operation. The AD5601/ AD5611/AD5621 operate from a single 2.7 V to 5.5 V supply with a maximum current consumption of 100 µA, making them ideal for battery-powered applications. The on-chip output buffer amplifier allows the output of the DAC to swing rail-to-rail with a typical slew rate of 0.5 V/µs. Reference is derived from the power supply. High speed serial interface with clock speeds up to 30 MHz. Designed for very low power consumption. The interface powers up only during a write cycle. Power-down capability. When powered down, the DAC typically consumes 0.2 µA at 3 V. Power-on reset with brownout detection. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5601/AD5611/AD5621 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Amplifier ........................................................................ 14 Applications ....................................................................................... 1 Serial Interface ............................................................................ 14 General Description ......................................................................... 1 Input Shift Register .................................................................... 14 Functional Block Diagram .............................................................. 1 SYNC Interrupt .......................................................................... 14 Product Highlights ........................................................................... 1 Power-On Reset .......................................................................... 16 Revision History ............................................................................... 2 Power-Down Modes .................................................................. 16 Specifications..................................................................................... 3 Microprocessor Interfacing ....................................................... 16 Timing Characteristics ................................................................ 4 Applications..................................................................................... 18 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Choosing a Reference as Power Supply for the AD5601/AD5611/AD5621 ....................................................... 18 Pin Configuration and Function Descriptions ............................. 6 Bipolar Operation Using the AD5601/AD5611/AD5621 ..... 18 Typical Performance Characteristics ............................................. 7 Using the AD5601/AD5611/AD5621 with a Galvanically Isolated Interface ........................................................................ 19 Terminology .................................................................................... 13 Theory of Operation ...................................................................... 14 DAC Section ................................................................................ 14 Resistor String ............................................................................. 14 Power Supply Bypassing and Grounding ................................ 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 21 REVISION HISTORY 6/13—Rev. F to Rev. G Change to Ordering Guide ............................................................ 21 2/12—Rev. E to Rev. F Added 6-Lead LFCSP ......................................................... Universal Changes to Features Section, General Description Section, Table 1, and Product Highlights Section ....................................... 1 Changes to Table 4 ............................................................................ 5 Added Figure 4; Renumbered Sequentially .................................. 6 Changes to Table 5 ............................................................................ 6 Changes to Choosing a Reference as Power Supply for the AD5601/AD5611/AD5621 Section .............................................. 18 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 21 7/10—Rev. D to Rev. E Changes to Figure 1 .......................................................................... 1 5/08—Rev. C to Rev. D Changes to General Description Section ...................................... 1 Changes to Table 2 ............................................................................ 3 Changes to Choosing a Reference as Power Supply for the AD5601/AD5611/AD5621 Section .............................................. 18 Changes to Ordering Guide .......................................................... 20 12/07—Rev. B to Rev. C Changes to Features ..........................................................................1 Changes to Table 2.............................................................................3 Changes to AD5601/AD5611/AD5621 to ADSP-2101 Interface Section ............................................................................. 16 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 7/05—Rev. A to Rev. B Changes to Figure 48...................................................................... 17 Changes to Galvanically Isolated Interface Section ................... 19 Changes to Figure 52...................................................................... 19 3/05—Rev. 0 to Rev. A Changes to Timing Characteristics .................................................4 Changes to Absolute Maximum Ratings ........................................5 Changes to Full Scale Error Section ................................................7 Changes to Figure 20...................................................................... 10 Changes to Theory of Operation.................................................. 14 Changes to Power Down Modes .................................................. 15 1/05—Revision 0: Initial Version Rev. G | Page 2 of 24 Data Sheet AD5601/AD5611/AD5621 SPECIFICATIONS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Temperature range for A/B grades is −40°C to +125°C, typical at 25°C. Table 2. Parameter STATIC PERFORMANCE AD5601 Resolution Relative Accuracy 1 (INL) Differential Nonlinearity (DNL) AD5611 Resolution Relative Accuracy1 (INL) Differential Nonlinearity (DNL) AD5621 Resolution Relative Accuracy1 (INL) Differential Nonlinearity (DNL) Zero-Code Error Full-Scale Error Offset Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient OUTPUT CHARACTERISTICS 2 Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Min B Grade Typ Max Unit Test Conditions/Comments ±0.5 ±0.5 Bits LSB LSB Guaranteed monotonic by design ±4 ±0.5 ±0.5 ±0.5 Bits LSB LSB Guaranteed monotonic by design ±6 ±0.5 10 ±1 ±0.5 10 10 12 0.5 ±0.5 ±0.063 ±0.0004 5.0 2.0 0 6 0.5 470 1000 120 2 0.5 ±0.5 ±0.063 ±0.0004 5.0 2.0 ±10 ±0.037 VDD 10 0 6 0.5 470 1000 120 2 5 0.2 15 0.5 ±10 ±0.037 VDD 10 5 0.2 15 0.5 ±2 1.8 1.4 ±2 0.8 0.6 3 0.8 0.6 3 Rev. G | Page 3 of 24 Bits LSB LSB mV mV mV %FSR µV/°C ppm FSR/°C V µs V/µs pF pF nV/√Hz µV nV-s nV-s mA Ω 1.8 1.4 Input Low Voltage, VINL Pin Input Capacitance Min 8 Output Noise Spectral Density Noise Digital-to-Analog Glitch Impulse Digital Feedthrough Short-Circuit Current DC Output Impedance LOGIC INPUTS Input Current 3 Input High Voltage, VINH A Grade Typ Max µA V V V V pF Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register Code ¼ scale to ¾ scale RL = ∞ RL = 2 kΩ DAC code = midscale,1 kHz DAC code = midscale, 0.1 Hz to 10 kHz bandwidth 1 LSB change around major carry VDD = 3 V/5 V VDD = 4.7 V to 5.5 V VDD = 2.7 V to 3.6 V VDD = 4.7 V to 5.5 V VDD = 2.7 V to 3.6 V AD5601/AD5611/AD5621 Parameter POWER REQUIREMENTS VDD IDD for Normal Mode Min 2 3 A Grade Typ Max 2.7 VDD = ±4.5 V to ±5.5 V VDD = ±2.7 V to ±3.6 V IDD for All Power-Down Modes VDD = ±4.5 V to ±5.5 V VDD = ±2.7 V to ±3.6 V POWER EFFICIENCY IOUT/IDD 1 Data Sheet 5.5 Min B Grade Typ Max Test Conditions/Comments 5.5 V 100 90 µA µA 0.5 0.2 0.5 0.2 µA µA All digital inputs at 0 V or VDD DAC active and excluding load current VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND 96 96 % ILOAD = 2 mA and VDD = ±5 V 75 60 2.7 Unit 100 90 75 60 Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252. Guaranteed by design and characterization, not production tested. Total current flowing into all pins. TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2. Table 3. Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 2 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK falling edge ignored All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency is 30 MHz. t4 t2 t1 t9 SCLK t8 t3 t7 SYNC t6 t5 SDIN D15 D14 D2 D1 Figure 2. Timing Diagram Rev. G | Page 4 of 24 D0 D15 D14 06853-002 1 Limit 1 33 5 5 10 5 4.5 0 20 13 Data Sheet AD5601/AD5611/AD5621 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND Digital Input Voltage to GND VOUT to GND Operating Temperature Range Industrial (A/B Grades) Storage Temperature Range Maximum Junction Temperature SC70 Package θJA Thermal Impedance θJC Thermal Impedance LFCSP Package θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD (Human Body Model) Rating −0.3 V to +7.0 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +125°C −65°C to +160°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 433.34°C/W 149.47°C/W 95°C/W 215°C 220°C 2.0 kV Rev. G | Page 5 of 24 AD5601/AD5611/AD5621 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SDIN 3 TOP VIEW (Not to Scale) 6 5 4 SCLK 2 AD5601/ AD5611/ AD5621 SDIN 3 TOP VIEW (Not to Scale) VDD 1 VOUT GND VDD 6 VOUT 5 GND 4 SYNC NOTES: 1. CONNECT THE EXPOSED PAD TO GND. Figure 3. 6-Lead SC70 Pin Configuration 06853-053 SCLK 2 AD5601/ AD5611/ AD5621 06853-003 SYNC 1 Figure 4. 6-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions SC70 Pin No. 1 LFCSP Pin No. 4 Mnemonic SYNC 2 2 SCLK 3 3 SDIN 4 1 VDD 5 6 5 6 GND VOUT EP Description Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the clocks that follow. The DAC is updated following the 16th clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND. Ground. Ground reference point for all circuitry on the AD5601/AD5611/AD5621. Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. Exposed Pad. Connect to GND. Rev. G | Page 6 of 24 Data Sheet AD5601/AD5611/AD5621 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 2.5 VDD = VREF = 5V TA = 25°C TOTAL UNADJUSTED ERROR (LSB) 0.5 INL ERROR (LSB) VDD = VREF = 5V TA = 25°C 2.0 0 –0.5 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 1064 1564 2064 2564 3064 3564 DAC CODE 4064 –2.5 64 564 Figure 5. Typical AD5621 INL 3564 4064 0.6 VDD = VREF = 5V TA = 25°C TOTAL UNADJUSTED ERROR (LSB) VDD = VREF = 5V TA = 25°C 0.3 0.2 INL ERROR (LSB) 3064 Figure 8. AD5621 Total Unadjusted Error (TUE) 0.5 0.4 2064 2564 1564 DAC CODE 1064 06853-007 564 06853-004 –2.0 –1.0 64 0.1 0 –0.1 –0.2 –0.3 0.4 0.2 0 –0.2 –0.4 116 216 316 416 516 616 DAC CODE 716 816 916 –0.6 16 06853-005 –0.5 16 0.100 0.20 VDD = VREF = 5V TA = 25°C TOTAL UNADJUSTED ERROR (LSB) 0.025 0 –0.025 –0.050 316 416 516 616 DAC CODE 716 816 916 VDD = VREF = 5V TA = 25°C 0.15 0.10 0.05 0 –0.05 –0.10 4 54 104 154 DAC CODE 204 –0.20 4 Figure 7. Typical AD5601 INL 54 104 154 DAC CODE 204 Figure 10. AD5601 Total Unadjusted Error (TUE) Rev. G | Page 7 of 24 06853-009 –0.15 –0.075 06853-006 INL ERROR (LSB) 0.050 –0.100 216 Figure 9. AD5611 Total Unadjusted Error (TUE) Figure 6. Typical AD5611 INL 0.075 116 06853-008 –0.4 AD5601/AD5611/AD5621 0.20 Data Sheet 12 V DD = 5V T A = 25°C 0.15 10 VDD = 3V VIH = DVDD VIL = GND TA = 25°C VDD = 5V VIH = DVDD VIL = GND TA = 25°C NUMBER OF DEVICES DNL ERROR (LSB) 0.10 0.05 0 0 –0.05 8 6 4 –0.10 2 0 IDD (mA) Figure 11. Typical AD5621 DNL 0.05 0.04 Figure 14. IDD Histogram (3 V/5 V) TA = 25°C VDD = 5V VDD = 5V TA = 25°C CH1 = SCLK DNL ERROR (LSB) 0.03 0.02 0.01 0 –0.01 –0.02 –0.03 CH2 = VOUT 116 216 316 416 516 616 DAC CODE 716 816 916 CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV 06853-014 –0.05 16 06853-011 –0.04 Figure 15. Full-Scale Settling Time Figure 12. Typical AD5611 DNL 0.010 TA = 25°C VDD = 5V VDD = 5V TA = 25°C 0.008 CH1 = SCLK 0.006 0.002 0 CH2 = VOUT –0.002 –0.004 06853-015 –0.006 –0.008 –0.010 4 54 104 154 DAC CODE 204 06853-012 DNL ERROR (LSB) 0.004 Figure 13. Typical AD5601 DNL CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV Figure 16. Half-Scale Settling Time Rev. G | Page 8 of 24 06853-013 3564 0.05885 0.06648 0.06710 0.06773 0.06835 0.06897 0.06960 0.07022 0.07084 0.07147 0.07209 0.07271 0.07334 3064 0.05814 1564 2064 2564 DAC CODE 0.05742 1064 0.05671 564 0.05599 64 06853-010 –0.20 0.05456 0.05527 –0.15 Data Sheet AD5601/AD5611/AD5621 VDD = 5V TA = 25°C MIDSCALE LOADED VDD VDD = 5V TA = 25°C CH1 CH1 06853-016 06853-019 VOUT = 70mV CH2 CH1 1V, CH2 20mV, TIME BASE = 20µs/DIV CH1 5µV/DIV Figure 20. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth Figure 17. Power-On Reset to 0 V CH1 VDD VDD = 5V TA = 25°C VDD = 5V TA = 25°C CH1 VOUT CH2 CH2 CH1 1V, CH2 5V, TIME BASE = 50µs/DIV 06853-020 06853-017 VOUT CH1 5V, CH2 1V, TIME BASE = 2µs/DIV Figure 21. Exiting Power-Down Mode Figure 18. VDD vs. VOUT 140 2.458 3/4 SCALE 2.456 FULL SCALE 120 2.454 MIDSCALE 100 1/4 SCALE 2.450 80 IDD (µA) 2.448 2.446 2.444 2.438 2.436 0 100 200 300 SAMPLE NUMBER 400 500 ZERO SCALE 40 TA = 25°C VDD = 5V LOAD = 2kΩ AND 220pF CODE 0x2000 TO 0x1FFF 10ns/SAMPLE NUMBER 2.440 60 20 0 0 5 10 15 FREQUENCY (MHz) Figure 22. IDD vs. SCLK vs. Code Figure 19. Digital-to-Analog Glitch Energy Rev. G | Page 9 of 24 20 25 06853-021 2.442 06853-018 AMPLITUDE (V) 2.452 AD5601/AD5611/AD5621 Data Sheet 0.3 VDD = 5V TA = 25°C UNLOADED OUTPUT 600 VDD = 5V 0.1 AD5601 MAX INL ERROR AD5611 MAX INL ERROR 500 300 MIDSCALE 200 0 INL ERROR (LSB) 400 –0.1 AD5611 MIN INL ERROR AD5601 MIN INL ERROR –0.2 –0.3 FULL SCALE –0.4 AD5621 MIN INL ERROR 100 –0.5 10k FREQUENCY (Hz) 100k –0.6 –40 –20 TA = 25°C 60 DNL ERROR (LSB) 50 30 20 0 6000 8000 10000 12000 14000 16000 DIGITAL INPUT CODE 06853-023 10 4000 80 100 120 0.08 0.07 VDD = 5V 0.06 AD5621 MAX DNL ERROR 0.05 0.04 0.03 AD5611 MAX DNL ERROR 0.02 0.01 0 –0.01 –0.02 AD5601 MAX DNL ERROR AD5611 MIN DNL ERROR AD5601 MIN DNL ERROR –0.03 –0.04 –0.05 –0.06 AD5621 MIN DNL ERROR –0.07 –0.08 –40 10 60 110 160 TEMPERATURE (°C) Figure 27. DNL vs. Temperature (5 V) Figure 24. Supply Current vs. Digital Input Code 0.00149 0.8 0.6 60 VDD = 5V TA = 25°C VDD = 5V AD5621 ZERO-CODE ERROR DAC LOADED WITH ZERO-SCALE CODE 0.00099 ERROR (LSB) 0.4 0.2 0.0 –0.2 AD5611 ZERO-CODE ERROR AD5601 ZERO-CODE ERROR AD5601 FULL-SCALE ERROR 0.00049 –0.00001 –0.4 –0.6 –15 –10 –5 0 5 10 15 06853-024 DAC LOADED WITH FULL-SCALE CODE I (mA) AD5611 FULL-SCALE ERROR AD5621 FULL-SCALE ERROR –0.00051 –40 –20 0 –20 40 60 80 TEMPERATURE (°C) 100 120 140 Figure 28. Zero-Code Error and Full-Scale Error vs. Temperature Figure 25. Sink and Source Capability Rev. G | Page 10 of 24 06853-027 IDD (µA) VDD = 3V 40 2000 40 Figure 26. INL vs. Temperature (5 V) 70 0 20 TEMPERATURE (°C) Figure 23. Noise Spectral Density VDD = 5V 0 06853-026 1k 06853-025 ZERO SCALE 0 100 ΔVOUT (V) AD5621 MAX INL ERROR 0.2 06853-022 OUTPUT NOISE SPECTRAL DENSITY (nV/ Hz) 700 Data Sheet AD5601/AD5611/AD5621 0.10 1.5 0.09 AD5621 MAX TUE 1.1 0.08 0.9 0.07 VDD = 5V 0.06 IDD (mA) 0.7 0.5 AD5601 MAX TUE AD5611 MAX TUE 0.3 0.05 VDD = 3V 0.04 0.03 0.1 0.02 –0.1 AD5601 MIN TUE AD5611 MIN TUE AD5621 MIN TUE –0.5 –40 –20 20 40 60 80 TEMPERATURE (°C) 0 0.01 100 120 140 0 –40 –20 0 20 40 60 80 120 100 140 TEMPERATURE (°C) Figure 29. Total Unadjusted Error (TUE) vs. Temperature (5 V) 06853-031 –0.3 06853-028 TOTAL UNADJUSTED ERROR (LSB) 1.3 Figure 32. Supply Current vs. Temperature (3 V/5 V Supply) 1.5 1.4 0.4 TA = 25°C 1.3 1.2 0.2 VDD = 5V 1.0 INL ERROR (LSB) OFFSET ERROR (mV) 1.1 0.9 0.8 0.7 VDD = 3V 0.6 0.5 AD5621 MAX INL ERROR AD5601 MAX INL ERROR AD5611 MAX INL ERROR 0 AD5601 MIN INL ERROR –0.2 AD5611 MIN INL ERROR 0.4 0.3 –0.4 AD5621 MIN INL ERROR 0.2 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 –0.6 2.7 –0.002 VDD = 5V DNL ERROR (LSB) –0.006 –0.008 –0.010 VDD = 3V –0.012 –0.014 20 40 60 80 TEMPERATURE (°C) 100 120 140 06853-030 GAIN ERROR (%FSR) –0.004 0 4.2 4.7 5.2 Figure 33. INL vs. Supply Voltage at 25°C 0 –20 3.7 SUPPLY VOLTAGE (V) Figure 30. Offset Error vs. Temperature (3 V/5 V Supply) –0.016 –40 3.2 Figure 31. Gain Error vs. Temperature (3 V/5 V Supply) 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 –0.01 –0.02 –0.03 –0.04 –0.05 –0.06 –0.07 –0.08 –0.09 –0.10 2.7 TA = 25°C AD5621 MAX DNL ERROR AD5611 MAX DNL ERROR AD5611 MIN DNL ERROR AD5601 MAX DNL ERROR AD5601 MIN DNL ERROR AD5621 MIN DNL ERROR 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) 5.7 Figure 34. DNL vs. Supply Voltage at 25°C Rev. G | Page 11 of 24 6.2 6.7 06853-033 –20 06853-029 0 –40 06853-032 0.1 AD5601/AD5611/AD5621 1.5 0.10 TA = 25°C TA = 25°C 1.3 0.09 AD5621 MAX TUE 0.08 1.1 0.07 IDD (mA) 0.9 0.7 0.5 0.06 0.05 AD5611 MAX TUE 0.04 AD5621 MIN TUE 0.03 0.3 0.1 0.02 AD5601 MAX TUE AD5611 MIN TUE AD5601 MIN TUE –0.3 2.7 0.01 3.7 4.2 4.7 SUPPLY VOLTAGE (V) 3.2 5.2 0 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) Figure 37. Supply Current vs. Supply Voltage at 25°C Figure 35. Total Unadjusted Error (TUE) vs. Supply Voltage at 25°C 450 0.0010 TA = 25°C TA = 25°C AD5621 ZERO-CODE ERROR 400 0.0008 SCLK/SDIN INCREASING VDD = 5V SCLK/SDIN DECREASING VDD = 5V 350 0.0006 300 0.0004 IDD (µA) ERROR (LSB) 06853-036 –0.1 06853-034 TOTAL UNADJUSTED ERROR (LSB) Data Sheet AD5601 FULL-SCALE ERROR AD5611 ZERO-CODE ERROR 0.0002 SCLK/SDIN INCREASING VDD = 3V 250 200 AD5601 ZERO-CODE ERROR 150 AD5611 FULL-SCALE ERROR 100 AD5621 FULL-SCALE ERROR 50 –0.0004 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) 5.7 6.2 6.7 Figure 36. Zero-Code Error and Full-Scale Error vs. Supply Voltage at 25°C Rev. G | Page 12 of 24 0 SCLK/SDIN DECREASING VDD = 3V 0 1 2 3 4 VLOGIC (V) Figure 38. SCLK/SDIN vs. Logic Voltage 5 6 06853-037 –0.0002 06853-035 0 Data Sheet AD5601/AD5611/AD5621 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. See Figure 5 to Figure 7 for plots of typical INL vs. code. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. See Figure 11 to Figure 13 for plots of typical DNL vs. code. Zero-Code Error Zero-code error is a measure of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5601/AD5611/AD5621 because the output of the DAC cannot go below 0 V. Zero-code error is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV. See Figure 28 for a plot of zero-code error vs. temperature. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD − 1 LSB. Full-scale error is expressed in mV. See Figure 28 for a plot of full-scale error vs. temperature. Total Unadjusted Error Total unadjusted error (TUE) is a measure of the output error, taking all the various errors into account. See Figure 8 to Figure 10 for plots of typical TUE vs. code. Zero-Code Error Drift Zero-code error drift is a measure of the change in zero-code error with a change in temperature. It is expressed in µV/°C. Gain Temperature Coefficient Gain temperature coefficient is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x2000 to 0x1FFF). See Figure 19. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and is measured with a full-scale code change on the data bus—from all 0s to all 1s and vice versa. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percent of the full-scale range. Rev. G | Page 13 of 24 AD5601/AD5611/AD5621 Data Sheet THEORY OF OPERATION DAC SECTION OUTPUT AMPLIFIER The AD5601/AD5611/AD5621 DACs are fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 39 is a block diagram of the DAC architecture. The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier are shown in Figure 25. The slew rate is 0.5 V/µs, with a halfscale settling time of 8 µs with the output loaded. VDD REF (+) SERIAL INTERFACE RESISTOR NETWORK DAC REGISTER REF (–) VOUT 06853-038 OUTPUT AMPLIFIER GND Figure 39. DAC Architecture Because the input coding to the DAC is straight binary, the ideal output voltage is given by D VOUT = VDD × n 2 where: D is the decimal equivalent of the binary code that is loaded to the DAC register. n is the bit resolution of the DAC. RESISTOR STRING The resistor string structure is shown in Figure 40. It is simply a string of resistors, each of Value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. R R TO OUTPUT AMPLIFIER R The AD5601/AD5611/AD5621 have a 3-wire serial interface (SYNC, SCLK, and SDIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the SDIN line is clocked into the 16-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5601/AD5611/AD5621 compatible with high speed DSPs. On the 16th falling clock edge, the last data bit is clocked in and the programmed function is executed (a change in DAC register contents and/or a change in the mode of operation). At this stage, the SYNC line may be kept low or brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Because the SYNC buffer draws more current when VIN = 1.8 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation of the part, as mentioned previously. However, it must be brought high again just before the next write sequence. INPUT SHIFT REGISTER The input shift register is 16 bits wide (see Figure 41). The first two bits are control bits, which control the operating mode of the part (normal mode or any one of three power-down modes). For a complete description of the various modes, see the Power-Down Modes section. For the AD5621, the next 12 bits are the data bits, which are transferred to the DAC register on the 16th falling edge of SCLK. The information in the last two bits is ignored by the AD5621. See Figure 42 and Figure 43 for the AD5611 and AD5601 input shift register map. SYNC INTERRUPT R 06853-039 R In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 44). Figure 40. Resistor String Structure Rev. G | Page 14 of 24 Data Sheet AD5601/AD5611/AD5621 DB15 (MSB) PD1 DB0 (LSB) PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X DATA BITS 0 0 NORMAL OPERATION 0 1 1kΩ TO GND 1 0 100kΩ TO GND 1 1 THREE-STATE 06853-040 POWER-DOWN MODES Figure 41. AD5621 Input Register Contents DB15 (MSB) PD1 DB0 (LSB) PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X DATA BITS 0 0 NORMAL OPERATION 0 1 1kΩ TO GND 1 0 100kΩ TO GND 1 1 THREE-STATE 06853-041 POWER-DOWN MODES Figure 42. AD5611 Input Register Contents DB15 (MSB) PD1 DB0 (LSB) PD0 D8 D7 D6 D5 D4 D3 D2 D1 X DATA BITS 0 0 NORMAL OPERATION 0 1 1kΩ TO GND 1 0 100kΩ TO GND 1 1 THREE-STATE 06853-042 POWER-DOWN MODES Figure 43. AD5601 Input Register Contents SCLK SDIN DB15 DB0 DB15 INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 16TH FALLING EDGE DB0 VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 16TH FALLING EDGE Figure 44. SYNC Interrupt Facility Rev. G | Page 15 of 24 06853-043 SYNC AD5601/AD5611/AD5621 Data Sheet POWER-ON RESET MICROPROCESSOR INTERFACING The AD5601/AD5611/AD5621 contain a power-on reset circuit that controls the output voltage during power-up. The DAC register is filled with 0s and the output voltage is 0 V. It remains there until a valid write sequence is made to the DAC. This is useful in applications in which it is important to know the state of the DAC output while it is in the process of powering up. AD5601/AD5611/AD5621 to ADSP-2101 Interface The AD5601/AD5611/AD5621 have four separate modes of operation. These modes are software-programmable by setting two bits (DB15 and DB14) in the control register. Table 6 shows how the state of the bits corresponds to the operating mode of the device. ADSP-2101* Table 6. Operating Modes of the AD5601/AD5611/AD5621 0 1 1 DB14 0 1 0 1 Operating Mode Normal operation Power-down modes: 1 kΩ to GND 100 kΩ to GND Three-state SDIN SCLK AD5601/AD5611/AD5621 to 68HC11/68L11 Interface There are three different options: the output is connected internally to GND through a 1 kΩ resistor or a 100 kΩ resistor, or the output is left open-circuited (three-stated). Figure 45 shows the output stage. Figure 47 shows a serial interface between the AD5601/AD5611/ AD5621 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5601/AD5611/ AD5621, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that the CPOL bit is 0 and the CPHA bit is 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 are configured as indicated, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5601/AD5611/ AD5621, PC7 is left low after the first eight bits are transferred and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. VOUT 68HC11/ 68L11* PC7 RESISTOR NETWORK 06853-044 POWER-DOWN CIRCUITRY SCLK Figure 46. AD5601/AD5611/AD5621 to ADSP-2101 Interface Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. AMPLIFIER SYNC DT *ADDITIONAL PINS OMITTED FOR CLARITY When both bits are set to 0, the part has normal power consumption of 100 µA maximum at 5 V. However, for the three power-down modes, the supply current falls to typically 0.2 µA at 3 V. RESISTOR STRING DAC TFS Figure 45. Output Stage During Power-Down AD5601/AD5611/ AD5621* SYNC SCK SCLK MOSI SDIN *ADDITIONAL PINS OMITTED FOR CLARITY The bias generator, output amplifier, resistor string, and other associated linear circuitry are all shut down when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit powerdown is typically 13 µs for VDD = 5 V and 16 µs for VDD = 3 V. See Figure 21 for a plot. Rev. G | Page 16 of 24 Figure 47. AD5601/AD5611/AD5621 to 68HC11/68L11 Interface 06853-046 DB15 0 AD5601/AD5611/ AD5621* 06853-045 POWER-DOWN MODES Figure 46 shows a serial interface between the AD5601/ AD5611/AD5621 and the ADSP-2101. The ADSP-2101 should be set up to operate in SPORT transmit alternate framing mode. The ADSP-2101 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT is enabled. Data Sheet AD5601/AD5611/AD5621 Figure 48 shows a serial interface between the AD5601/AD5611/ AD5621 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5601/AD5611/AD5621, the setup for the interface is as follows: DT0PRI drives the SDIN pin of the AD5601/AD5611/ AD5621, while TSCLK0 drives the SCLK of the part. The SYNC is driven from TFS0. AD5601/AD5611/ AD5621* SDIN SCLK TFS0 SYNC P3.3 AD5601/AD5611/ AD5621* SYNC TxD SCLK RxD SDIN Figure 49. AD5601/AD5611/AD5621 to 80C51/80L51 Interface AD5601/AD5611/AD5621 to MICROWIRE Interface *ADDITIONAL PINS OMITTED FOR CLARITY Figure 48. AD5601/AD5611/AD5621 to Blackfin ADSP-BF53x Interface AD5601/AD5611/AD5621 to 80C51/80L51 Interface Figure 49 shows a serial interface between the AD5601/ AD5611/AD5621 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5601/AD5611/AD5621, while RxD drives the serial data line of the part. The SYNC signal is again derived from a bit programmable pin on the port. In this case, Port Line P3.3 is used. When data is to be transmitted to the AD5601/AD5611/AD5621, P3.3 is taken low. The 80C51/80L51 transmit data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, Figure 50 shows an interface between the AD5601/AD5611/ AD5621 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5601/AD5611/AD5621 on the rising edge of the SK. MICROWIRE* CS AD5601/AD5611/ AD5621* SYNC SK SCLK SO SDIN *ADDITIONAL PINS OMITTED FOR CLARITY Rev. G | Page 17 of 24 Figure 50. AD5601/AD5611/AD5621 to MICROWIRE Interface 06853-049 DT0PRI TSCLK0 80C51/80L51* *ADDITIONAL PINS OMITTED FOR CLARITY 06853-047 ADSP-BF53x* and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 output the serial data LSB first. The AD5601/AD5611/AD5621 require data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account. 06853-048 AD5601/AD5611/AD5621 to Blackfin® ADSP-BF53x Interface AD5601/AD5611/AD5621 Data Sheet APPLICATIONS CHOOSING A REFERENCE AS POWER SUPPLY FOR THE AD5601/AD5611/AD5621 BIPOLAR OPERATION USING THE AD5601/AD5611/AD5621 The AD5601/AD5611/AD5621 come in tiny LFCSP and SC70 packages with less than a 100 µA supply current. Because of this, the choice of reference depends on the application requirements. For applications with space-saving requirements, the ADR02 is recommended. It is available in an SC70 package and has excellent drift at 9 ppm/°C (3 ppm/°C in the R-8 package) and provides very good noise performance at 3.4 µV p-p in the 0.1 Hz to 10 Hz range. The AD5601/AD5611/AD5621 have been designed for singlesupply operation, but a bipolar output range is also possible using the circuit shown in Figure 52. The circuit in Figure 52 gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or OP295 as the output amplifier. +5V R1 = 10kΩ +5V AD820/ OP295 10µF 0.1µF +5V V VDD OUT AD5601/AD5611/ AD5621 –5V 3-WIRE SERIAL INTERFACE 7V Figure 52. Bipolar Operation with the AD5601/AD5611/AD5621 5V ADR395 The output voltage for any input code can be calculated as SYNC SCLK SDIN AD5601/AD5611/ AD5621 D R1 + R2 R2 VOUT = VDD × N × − VDD × 2 R1 R1 VOUT = 0V TO 5V 06853-050 3-WIRE SERIAL INTERFACE Figure 51. ADR395 as Power Supply to the AD5601/AD5611/AD5621 where D represents the input code in decimal (0 – 2N). With VDD = 5 V, R1 = R2 = 10 kΩ 10 × D VOUT = N − 5 V 2 Some recommended precision references for use as supplies to the AD5601/AD5611/AD5621 are listed in Table 7. Table 7. Precision References for the AD5601/AD5611/AD5621 Part No. ADR435 ADR425 ADR02 ADR02 ADR395 Initial Accuracy (mV max) ±2 ±2 ±3 ±3 ±5 Temp Drift (ppm/°C max) 3 (R-8) 3 (R-8) 3 (R-8) 3 (SC70) 9 (TSOT-23) 0.1 Hz to 10 Hz Noise (µV p-p typ) 8 3.4 10 10 8 This is an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output and 0x3FFF corresponding to a +5 V output. Rev. G | Page 18 of 24 06853-051 Because the supply current required by the AD5601/AD5611/ AD5621 is extremely low, the parts are ideal for low supply applications. The ADR395 voltage reference is recommended in this case. It requires less than 100 µA of quiescent current and can, therefore, drive multiple DACs in one system, if required. It also provides very good noise performance at 8 µV p-p in the 0.1 Hz to 10 Hz range. R2 = 10kΩ Data Sheet AD5601/AD5611/AD5621 USING THE AD5601/AD5611/AD5621 WITH A GALVANICALLY ISOLATED INTERFACE POWER SUPPLY BYPASSING AND GROUNDING In process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common-mode voltages that might occur in the area where the DAC is functioning. iCoupler® provides isolation in excess of 2.5 kV. Because the AD5601/AD5611/AD5621 use a 3-wire serial logic interface, the ADuM1300 3-channel digital isolator provides the required isolation (see Figure 53). The power supply to the part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5601/ AD5611/AD5621. 5V REGULATOR POWER 10µF 0.1µF VDD VOA VIA SCLK ADuM1300 SDI VIB VOB SYNC DATA VIC VOC SDIN AD5601/ AD5611/ AD5621 GND VOUT 06853-052 SCLK Figure 53. AD5601/AD5611/AD5621 with a Galvanically Isolated Interface When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The PCB containing the AD5601/AD5611/AD5621 should have separate analog and digital sections, each having its own area of the board. If the AD5601/AD5611/AD5621 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5601/AD5611/AD5621. The power supply to the AD5601/AD5611/AD5621 should be bypassed with 10 µF and 0.1 µF capacitors. The capacitors should be physically as close as possible to the device, with the 0.1 µF capacitor ideally right up against the device. The 10 µF capacitors are the tantalum bead type. It is important that the 0.1 µF capacitor have low effective series resistance (ESR) and effective series inductance (ESI), such as in common ceramic types of capacitors. This 0.1 µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a two-layer board. Rev. G | Page 19 of 24 AD5601/AD5611/AD5621 Data Sheet OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 1.25 1.15 6 5 4 1 2 3 2.40 2.10 1.80 0.65 BSC 1.00 0.90 0.70 1.10 0.80 0.10 MAX COPLANARITY 0.10 SEATING PLANE 0.30 0.15 0.40 0.10 0.46 0.36 0.26 0.22 0.08 072809-A 1.30 BSC COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 54. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters 1.50 1.40 1.30 2.10 2.00 1.90 0.65 REF 4 PIN 1 INDEX AREA EXPOSED PAD 0.45 0.40 0.35 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.203 REF 0.35 0.30 0.25 0.05 MAX 0.00 MIN 1 3 BOTTOM VIEW 0.20 MIN 1.70 1.60 1.50 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-229 Figure 55. 6-Lead Lead Frame Chip Scale Package [LFCSP_WD] 2.00 × 3.00 mm Body, Very Very Thin, Dual Lead (CP-6-5) Dimensions shown in millimeters Rev. G | Page 20 of 24 03-29-2012-B 3.10 3.00 2.90 6 Data Sheet AD5601/AD5611/AD5621 ORDERING GUIDE Model 1 AD5601BKSZ-500RL7 AD5601BKSZ-REEL7 AD5601BCPZ-RL7 AD5611AKSZ-500RL7 AD5611AKSZ-REEL7 AD5611ACPZ-RL7 AD5611BKSZ-500RL7 AD5611BKSZ-REEL7 AD5621AKSZ-500RL7 AD5621AKSZ-REEL7 AD5621ACPZ-RL7 AD5621BKSZ-500RL7 AD5621BKSZ-REEL7 EVAL-AD5621EBZ 1 Temperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C INL ±0.5 LSB ±0.5 LSB ±0.5 LSB ±4.0 LSB ±4.0 LSB ±4.0 LSB ±0.5 LSB ±0.5 LSB ±6.0 LSB ±6.0 LSB ±6.0 LSB ±1.0 LSB ±1.0 LSB Package Description 6-Lead Thin Shrink Small Outline Transistor Package [SC70] 6-Lead Thin Shrink Small Outline Transistor Package [SC70] 6-Lead Lead Frame Chip Scale Package [LFCSP_WD] 6-Lead Thin Shrink Small Outline Transistor Package [SC70] 6-Lead Thin Shrink Small Outline Transistor Package [SC70] 6-Lead Lead Frame Chip Scale Package[LFCSP_WD] 6-Lead Thin Shrink Small Outline Transistor Package [SC70] 6-Lead Thin Shrink Small Outline Transistor Package [SC70] 6-Lead Thin Shrink Small Outline Transistor Package [SC70] 6-Lead Thin Shrink Small Outline Transistor Package [SC70] 6-Lead Lead Frame Chip Scale Package[LFCSP_WD] 6-Lead Thin Shrink Small Outline Transistor Package [SC70] 6-Lead Thin Shrink Small Outline Transistor Package [SC70] Evaluation Board Z = RoHS Compliant Part. Rev. G | Page 21 of 24 Package Option KS-6 KS-6 CP-6-5 KS-6 KS-6 CP-6-5 KS-6 KS-6 KS-6 KS-6 CP-6-5 KS-6 KS-6 Branding D3V D3V 89 D3U D3U 8B D3T D3T D3S D3S D3S D3R D3R AD5601/AD5611/AD5621 Data Sheet NOTES Rev. G | Page 22 of 24 Data Sheet AD5601/AD5611/AD5621 NOTES Rev. G | Page 23 of 24 AD5601/AD5611/AD5621 Data Sheet NOTES ©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06853-0-6/13(G) Rev. G | Page 24 of 24