Zarlink MT90870 Flexible 12 k digital switch (f12kdx) Datasheet

MT90870
Flexible 12 k Digital Switch (F12kDX)
Data Sheet
Features
•
•
•
•
•
•
•
November 2005
12,288-channel x 12,288-channel non-blocking
unidirectional switching.The Backplane and
Local inputs and outputs can be combined to
form a non-blocking switching matrix with 48
stream inputs and 48 stream outputs
8,192-channel x 4,096-channel blocking
Backplane to Local stream switch
4,096-channel x 8,192-channel non-blocking
Local to Backplane stream switch
8,192-channel x 8,192-channel non-blocking
Backplane input to Backplane output switch
4,096-channel x 4,096-channel non-blocking
Local input to Local output stream switch
Rate conversion on all data paths, Backplane to
Local, Local to Backplane, Backplane to
Backplane and Local to Local streams
Backplane port accepts 32 ST-BUS streams with
data rates of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s
or 16.384 Mb/s in any combination, or a fixed
allocation of 16 streams at 32.768 Mb/s
VDD_IO
MT90870AG
272 Ball PBGA
Trays
MT90870AG2
272 Ball PBGA*
Trays
*Pb Free Tin/Silver/Copper
-40 to +85oC
*Note: the package thickness is different than the
MT90870AG (see drawing at the end of the data
sheet).
•
•
•
•
•
Local port accepts 16 ST-BUS streams with data
rates of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or
16.384 Mb/s, in any combination
Per-stream channel and bit delay for Local input
streams
Per-stream channel and bit delay for Backplane
input streams
Per-stream advancement for Local output streams
Per-stream advancement for Backplane output
streams
VSS (GND)
ODE
RESET
Backplane Data Memories
(8,192 channels)
BSTi0-31
Backplane
Interface
Local
Interface
Local
Connection Memory
(4,096 locations)
Backplane
Connection Memory
(8,192 locations)
BSTo0-31
LSTi0-15
Local
Interface
LSTo0-15
LCST0-1
BCST0-3
Local Data Memories
(4,096 channels)
BORS
FP8i
VDD_CORE
Ordering Information
Backplane
Timing Unit
PLL
Local
Timing
Unit
Microprocessor Interface
C8i
LORS
and Internal Registers
Test Port
VDD_PLL
DS CS R/W A14-A0 DTA D15-D0
TMS TDi TDo TCK TRST
Figure 1 - MT90870 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.
FP8o
FP16o
C8o
C16o
MT90870
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Data Sheet
Constant throughput delay for frame integrity
Per-channel high impedance output control for Local and Backplane streams
Per-channel driven-high output control for Local and Backplane streams
High impedance-control outputs for external drivers on Backplane and Local port
Per-channel message mode for Local and Backplane output streams
Connection memory block programming for fast device initialization
Automatic selection between ST-BUS and GCI-BUS operation
Non-multiplexed Motorola microprocessor interface
BER testing for Local and Backplane ports
Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard
Memory Built-In-Self-Test (BIST), controlled via microprocessor registers
1.8 V core supply voltage
3.3 V I/O supply voltage
5 V tolerant inputs, outputs and I/Os
Per streams subrate switching at 4 bit, 2 bit and 1 bit depending on stream data rate
Applications
•
Central Office Switches (Class 5)
•
Mediation Switches
•
Class-independent switches
•
Access Concentrators
•
Scalable TDM-Based Architectures
•
Digital Loop Carriers
Device Overview
The MT90870 has two data ports, the Backplane and the Local port. The Backplane port has two modes of
operation, either 32 input and 32 output streams operated at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s,
in any combination, or 16 input and 16 output streams operated at 32.768 Mb/s. The Local port has 16 input and 16
output streams operated at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s, in any combination.
The MT90870 contains two data memory blocks (Backplane and Local) to provide the following switching path
configurations:
•
•
•
•
Backplane-to-Local, supporting 8 K x 4 K data switching,
Local-to-Backplane, supporting 4 K x 8 K data switching,
Backplane-to-Backplane, supporting 8 K x 8 K data switching.
Local-to-Local, supporting 4 K x 4 K data switching.
The device contains two connection memory blocks, one for the Backplane output and one for the Local output.
Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly
from the connection memory contents (Message Mode).
2
Zarlink Semiconductor Inc.
MT90870
Data Sheet
In Connection Mode the contents of the connection memory defines, for each output stream and channel, the
source stream and channel (stored in data memory) to be switched.
In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output
streams on a per channel basis. This feature is useful for transferring control and status information to external
circuits or other ST-BUS devices.
The device uses a master frame pulse (FP8i) and master clock (C8i) to define the frame boundary and timing for
both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCI-BUS
style frame pulse is being used. There is a two frame delay from the time RESET is de-asserted to the
establishment of full switch functionality. During this period the frame format is determined before switching begins.
The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the Local port.
Subrate switching is accomplished by oversampling (i.e., 1 bit switching can be accomplished by sampling a 2 Mb/s
stream at 16 Mbps). Refer to MSAN-175.
A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and
switching configurations. The microprocessor port provides access for Register read/write, Connection Memory
read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and 4 control
signals. The microprocessor may monitor channel data in the Backplane and Local data memories.
The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port.
The MT90870 is manufactured in a 27 mm x 27 mm body, 1.27 mm ball-pitch, 272-PBGA to JEDEC standard
MS-034 BAL-2 Iss. A.
3
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Table of Contents
1.0 Bidirectional and Unidirectional Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1 Flexible Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1 Switching Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.1 Backplane-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1.2 Local-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1.3 Backplane-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1.4 Local-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1.5 Uni-directional Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2 Port Data Rate Modes and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.1 Local Port Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.1.1 Local Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.1.2 Local Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.2 Backplane Port Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.2.1 Backplane Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.2.2 Backplane Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3 Backplane Frame Pulse Input and Master Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4 Backplane Frame Pulse Input and Local Frame Pulse Output Alignment. . . . . . . . . . . . . . . . . . . . . . . . . 24
3.0 Input and Output Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 Input Channel Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 Input Bit Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Output Advancement Programming (Backplane and Local Output Streams) . . . . . . . . . . . . . . . . . . . . . . 27
3.3.1 Local Output Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.2 Backplane Output Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.0 Port High Impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1 Local Port High Impedance Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1.1 LORS Set LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2 Backplane High Impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.1 BORS Set LOW, Non-32 Mb/s Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.2 BORS Set LOW, 32 Mb/s Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.3 BORS Set HIGH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.0 Connection Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1 Local Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.2 Backplane Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.0 Device Power-up, Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.0 Bit Error Rate Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.2.2.1 The Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.2.2.2 The Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Table of Contents
11.2.2.3 The Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.3 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.1 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.2 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
12.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.5 Internal Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13.0 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.1 Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.2 Block Programming Register (BPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.3 Bit Error Rate Test Control Register (BERCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.4 Local Input Channel Delay Registers (LCDR0 to LCDR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13.4.1 Local Channel Delay Bits 7-0 (LCD7 - LCD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13.5 Local Input Bit Delay Registers (LIDR0 to LIDR15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
13.5.1 Local Input Delay Bits 4-0 (LID4 - LID0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
13.6 Backplane Input Channel Delay Registers (BCDR0 to BCDR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
13.6.1 Backplane Channel Delay Bits 8-0 (BCDn8 - BCDn0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
13.7 Backplane Input Bit Delay Registers (BIDR0 to BIDR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
13.7.1 Backplane Input Delay Bits 4-0 (BID4 - BID0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
13.8 Local Output Advancement Registers (LOAR0 to LOAR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.8.1 Local Output Advancement Bits 1-0 (LOA1-LOA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
13.9 Backplane Output Advancement Registers (BOAR0 - 31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
13.9.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
13.10 Local Bit Error Rate (BER) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.10.1 Local BER Start Send Register (LBSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.10.2 Local Transmit BER Length Register (LTXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.10.3 Local Receive BER Length Register (LRXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13.10.4 Local BER Start Receive Register (LBSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13.10.5 Local BER Count Register (LBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.11 Backplane Bit Error Rate (BER) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.11.1 Backplane BER Start Send Register (BBSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.11.2 Backplane Transmit BER Length Register (BTXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.11.3 Backplane Receive BER Length Register (BRXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.11.4 Backplane BER Start Receive Register (BBSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.11.5 Backplane BER Count Register (BBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.12 Local Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
13.12.1 Local Input Bit Rate Registers (LIBRR0-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
13.12.2 Local Output Bit Rate Resisters (LOBRR0-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
13.13 Backplane Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
13.13.1 Backplane Input Bit Rate Registers (BIBRR0-31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
13.13.2 Backplane Output Bit Rate Registers (BOBRR0-31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
13.14 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.15 Revision Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5
Zarlink Semiconductor Inc.
MT90870
Data Sheet
List of Figures
Figure 1 - MT90870 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - MT90870 PBGA Connections (272 PBGA) Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3 - 8,192 x 4,096 Channels (16 Mb/s), Bidirectional Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4 - 12,288 x 12,288 Channels (16 Mb/s), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5 - 6 K x 6 K Non-Blocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6 - Local Port Timing Diagram for 2,4,8 and 16 Mb/s stream rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7 - Backplane Port Timing Diagram for 2, 4, 8, 16 and 32 Mb/s stream rates . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8 - Backplane and Local Frame Pulse Alignment for Data Rates of 2 Mb/s, 4 Mb/s, 8 Mb/s and 16 Mb/s. 24
Figure 9 - Backplane and Local Input Channel Delay Timing Diagram (8 Mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mb/s. . . . . . . . . . . . . . . . . 26
Figure 11 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 8 Mb/s. . . . . . . . . . . . . . . . . . 27
Figure 12 - Backplane and Local Output Advancement Timing diagram for Data Rate of 16 Mb/s. . . . . . . . . . . . 28
Figure 13 - Local Port External High Impedance Control Bit Timing (ST-Bus Mode) . . . . . . . . . . . . . . . . . . . . . . 32
Figure 14 - Backplane Port External High Impedance Control Bit Timing (Non-32 Mb/s mode) . . . . . . . . . . . . . . 36
Figure 15 - Backplane Port External High Impedance Control Timing (32 Mb/s Mode) . . . . . . . . . . . . . . . . . . . . 40
Figure 16 - Constant Switch Delay: Examples of Different Stream Rates and Routing . . . . . . . . . . . . . . . . . . . . . 41
Figure 17 - Examples of BER transmission channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 18 - Frame Boundary Conditions, ST- BUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 19 - Frame Boundary Conditions, GCI - BUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 20 - Backplane and Local Clock Timing Diagram for ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 21 - Backplane and Local Clock Timing for GCI-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 22 - ST-BUS Backplane Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 23 - ST-BUS Backplane Data Timing Diagram (32 Mb/s, 16 Mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 24 - GCI BUS Backplane Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 25 - GCI BUS Backplane Data Timing Diagram (32 Mb/s, 16 Mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 26 - ST-BUS Local Timing Diagram (16 Mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 27 - ST-BUS Local Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 28 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 29 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 30 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6
Zarlink Semiconductor Inc.
MT90870
Data Sheet
List of Tables
Table 1 - Per-stream Data-Rate Selection: Backplane and Local, Non-32 Mb/s Mode and 32 Mb/s Mode. . . . . . 21
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams
(Non-32 Mb/s Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams
(32 Mb/s Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5 - Local and Backplane Connection Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 6 - Local Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 7 - Backplane Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 8 - Address Map for Data and Connection Memory Locations (A14=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 9 - Backplane Data Memory (BDM) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 10 - Local Data Memory (LDM) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 11 - LCM Bits for Local-to-Local and Backplane (Non-32 Mb/s Mode)-to-Local Switching . . . . . . . . . . . . . 49
Table 12 - LCM Bits for Backplane(32 Mb/s Mode)-to-Local Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 13 - BCM Bits for Local-to-Backplane and Backplane-to-Backplane Switching
(Non-32 Mb/s Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 14 - BCM Bits for Backplane-to-Backplane Switching (32 Mb/s mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 15 - Address Map for Register (A14 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 16 - Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 18 - Bit Error Rate Test Control Register (BERCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 17 - Block Programming Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 19 - Local Channel Delay Register (LCDRn) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 20 - Local Input Channel Delay Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 21 - Local Channel Delay Register (LIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 22 - Local Input Bit Delay Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 23 - Backplane Channel Delay Register (BCDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 24 - Backplane Input Channel Delay (BCD) Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 25 - Backplane Input Bit Delay Register (BIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 26 - Backplane Input Bit Delay Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 27 - Local Output Advancement Register (LOARn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 28 - Local Output Advancement (LOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 29 - Backplane Output Advancement Register (BOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 30 - Backplane Output Advancement (BOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 31 - Local BER Start Send Register (LBSSR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 32 - Local Transmit BER Length Register (LTXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 33 - Local Receive BER Length Register (LRXBLR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 34 - Local BER Start Receive Register (LBSRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 35 - Local BER Count Register (LBCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 36 - Backplane BER Start Send Register (BBSSR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 37 - Backplane Transmit BER Length (BTXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 38 - Backplane Receive BER Length (BRXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 39 - Backplane BER Start Receive Register (BBSRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 40 - Backplane BER Count Register (BBCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 41 - Local Input Bit Rate Register (LIBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 42 - Local Input Bit Rate (LIBR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 43 - Local Output Bit Rate Register (LOBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 44 - Output Bit Rate (LOBR) Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 45 - Backplane Input Bit Rate Register (BIBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 46 - Backplane Input Bit Rate (BIBR) Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7
Zarlink Semiconductor Inc.
MT90870
Data Sheet
List of Tables
Table 47 - Backplane Output Bit Rate Register (BOBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 49 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 50 - Revision Control Register (RCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Changes Summary
The following table captures the changes from the December 2002 issue.
Page
Item
Change
14
Pin Description, C8i
The internal frame boundary alignment description
is changed from the clock rising or falling edge to
rising edge only. Also added description to specify
setting the C8IPOL bit in the Control Register to
one for clock rising edge alignment operation.
21
Figure 6, Local Port Timing Diagram for
2,4,8 and 16 Mb/s stream rates
Changed C8i frame boundary active edge from
falling to rising edge.
23
Figure 7, Backplane Port Timing Diagram
for 2, 4, 8, 16 and 32 Mb/s stream rates
Changed C8i frame boundary active edge from
falling to rising edge.
23
Section 2.3. Backplane Frame Pulse Input
and Master Input Clock Timing
Removed the falling clock edge frame boundary
alignment option.
24
Figure 8, Backplane and Local Frame
Pulse Alignment for Data Rates of 2 Mb/s,
4 Mb/s, 8 Mb/s and 16 Mb/s
Changed C8i frame boundary active edge from
falling to rising edge.
25
Figure 9, Backplane and Local Input
Channel Delay Timing Diagram (8 Mb/s)
Changed FPo and C8o to FPi and C8i respectively
and showing rising C8i frame boundary active
edge.
26
Figure 10, Backplane and Local Input Bit
Delay Timing Diagram for Data Rate of
16 Mb/s
Changed FPo and C8o to FPi and C8i respectively
and showing rising C8i frame boundary active
edge.
27
Figure 11, Backplane and Local Input Bit
Delay Timing Diagram for Data Rate of
8 Mb/s
Changed FPo and C8o to FPi and C8i
respectively.
52
Section 13.1. Control Register (CR) Bit 6,
C8IPOL
Changed description to specify Bit 6, C8IPOL
must be set high for rising clock edge frame
boundary alignment operation.
53
Figure 18, Frame Boundary Conditions,
ST- BUS Operation
Removed waveforms showing C8i falling edge
frame boundary option.
54
Figure 19, Frame Boundary Conditions,
GCI - BUS Operation
Removed waveforms showing C8i falling edge
frame boundary option.
Backplane and Local Clock Timing:
Item 2, Backplane Frame Pulse Setup
Time before C8i clock falling edge
Item 3, Backplane Frame Pulse Hold Time
from C8i clock falling edge
Item 2, Backplane Frame Pulse Setup Time
before C8i clock falling edge changed to
Backplane Frame Pulse Setup Time before C8i
clock rising edge.
Item 3, Backplane Frame Pulse Hold Time from
C8i clock falling edge changed to Backplane
Frame Pulse Hold Time from C8i clock rising
edge.
73
9
Zarlink Semiconductor Inc.
MT90870
Page
Item
Data Sheet
Change
75
Figure 20, Backplane and Local Clock
Timing Diagram for ST-BUS
Changed C8i frame boundary active edge from
falling to rising edge.
78
Figure 22, ST-BUS Backplane Data
Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s)
Changed C8i frame boundary active edge from
falling to rising edge.
79
Figure 23, ST-BUS Backplane Data
Timing Diagram (32 Mb/s, 16 Mb/s)
Changed C8i frame boundary active edge from
falling to rising edge.
82
Figure 26, ST-BUS Local Timing Diagram
(16 Mb/s)
Changed C8i frame boundary active edge from
falling to rising edge.
82
Figure 27, ST-BUS Local Data Timing
Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s)
Changed FPo and C8o to FPi and C8i respectively
and shows rising C8i frame boundary active edge.
10
Zarlink Semiconductor Inc.
11
Zarlink Semiconductor Inc.
(as viewed through top of package)
A1 corner identified by metallized marking
Figure 2 - MT90870 PBGA Connections (272 PBGA) Pin Diagram
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
BSTi26
BSTi23
VDD_CORE
BSTi22
BSTi18
BSTi15
BSTi11
BSTi9
BSTi5
BSTi1
VDD_CORE
BSTo28
BSTo25
BSTo21
BSTo18
BSTo14
BSTo11
BSTo9
BSTo6
GND
1
BSTi27
BSTi24
IC
IC
BSTi19
BSTi16
BSTi12
BSTi10
BSTi6
BSTi2
BORS
BSTo29
BSTo26
BSTo22
BSTo19
BSTo15
BSTo12
BSTo10
BSTo7
IC
2
IC
BSTi25
IC
IC
BSTi20
BSTi17
BSTi13
VDD_CORE
BSTi7
BSTi3
BSTi0
BSTo30
BSTo27
BSTo23
BSTo20
BSTo16
BSTo13
IC
BSTo8
BSTo5
3
BSTi31
BSTi30
BSTi29
GND
BSTi21
VDD_IO
BSTi14
GND
BSTi8
BSTi4
VDD_IO
BSTo31
GND
BSTo24
VDD_IO
BSTo17
GND
BSTo3
VDD_CORE
BSTo4
4
D14
D15
VDD_CORE
BSTi28
A0
BSTo0
BSTo1
BSTo2
5
D11
D12
D13
VDD_IO
VDD_IO
A1
IC
A2
6
VDD_CORE
D8
D9
D10
A3
A4
A5
VDD_CORE
7
D5
D6
D7
GND
GND
A6
A7
A8
8
D1
D2
D3
D4
GND
GND
GND
GND
A9
IC
A10
A11
9
IC
IC
D0
VDD_IO
GND
GND
GND
GND
A12
A13
IC
A14
10
VDD_CORE
IC
IC
GND
GND
GND
GND
GND
VDD_IO
R/W
CS
DS
11
NC
C8i
IC
VDD_PLL
GND
GND
GND
GND
TMS
RESET
VDD_CORE
ODE
12
NC
C16o
C8o
GND
GND
TDo
TDi
DTA
13
VDD_CORE
FP16o
FP8o
FP8i
VDD_CORE
BCSTo0
TRST
TCK
14
IC
IC
IC
VDD_IO
VDD_IO
BCSTo3
BCSTo2
BCSTo1
15
IC
IC
IC
VDD_CORE
IC
LCSTo1
NC
NC
16
IC
IC
IC
GND
VDD_CORE
VDD_IO
LSTi10
GND
LSTi3
VDD_IO
IC
IC
GND
IC
VDD_IO
LSTo12
GND
LCSTo0
IC
LSTo0
17
IC
IC
IC
IC
IC
LSTi13
VDD_CORE
LSTi7
LSTi4
LSTi0
IC
IC
IC
IC
IC
LSTo13
LSTo9
LSTo6
LSTo3
LSTo1
18
IC
IC
IC
IC
IC
LSTi14
LSTi11
LSTi8
LSTi5
LSTi1
LORS
IC
IC
IC
IC
LSTo14
LSTo10
LSTo7
LSTo4
LSTo2
19
IC
IC
IC
IC
IC
LSTi15
LSTi12
LSTi9
LSTi6
LSTi2
VDD_CORE
IC
IC
IC
IC
LSTo15
LSTo11
LSTo8
LSTo5
IC
20
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
MT90870
Data Sheet
MT90870
Data Sheet
Pin Description
Name
Package
Coordinates
Description
VDD_IO
D6, D11, D15, F4,
F17, K4, L17, R4,
R17, U6, U10,
U15
Power Supply for Periphery Circuits: +3.3 V
VDD_CORE
A7, B4, B12, D14,
K1, K20, N3, P18,
T17, U16, V1, V5,
Y7, Y11, Y14
Power Supply for Core Logic Circuits: +1.8 V
VDD_PLL
U12
Power Supply for Analogue PLL: +1.8 V
VSS (GND)
A1, D4, D8, D13,
D17, H4, H17, J9,
J10, J11, J12, K9,
K10, K11, K12, L9,
L10, L11, L12, M9,
M10, M11, M12,
N4, N17, U4, U8,
U11, U13, U17
Ground
BSTi0 - 15
K3, L1, L2, L3, L4,
M1, M2, M3, M4,
N1, N2, P1, P2,
P3, P4, R1
Backplane Serial Input Streams 0 to 15 (5 V Tolerant, Internal pulldown). In Non-32 Mb/s Mode, these pins accept serial TDM data streams
at a data-rate of:
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048 Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each input stream.
In 32 Mb/s Mode, these pins accept serial TDM data streams at a fixed
data-rate of 32.768 Mb/s (with 512 channels per stream).
BSTi16 - 31
R2, R3, T1, T2,
T3, T4, U1,W1,
W2, W3, Y1, Y2,
U5, V4, W4, Y4
Backplane Serial Input Streams 16 to 31 (5 V Tolerant, Internal pulldown).
In Non-32 Mb/s Mode, these pins accept serial TDM data streams at a
data-rate of:
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048 Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each input stream.
In 32 Mb/s Mode, these pins are unused and should be externally
connected to a defined logic level.
12
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Pin Description (continued)
Name
BSTo0 - 15
Package
Coordinates
C5, B5, A5 C4, A4,
A3, B1, B2, B3,
C1, C2, D1, D2,
D3, E1, E2
Description
Backplane Serial Output Streams 0 to 15 (5 V Tolerant, Three-state
Outputs).
In Non-32 Mb/s Mode, these pins output serial TDM data streams at a
data-rate of:
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048 Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each output stream.
In 32 Mb/s Mode, these pins output serial TDM data streams at a fixed
data-rate of 32.768 Mb/s (with 512 channels per stream).
Refer to descriptions of the BORS and ODE pins for control of the output
High or High-Impedance state.
BSTo16 - 31
E3, E4, F1, F2, F3,
G1, G2, G3, G4,
H1, H2, H3, J1, J2,
J3, J4
Backplane Serial Output Streams 16 to 31 (5 V Tolerant Three-state
Outputs).
In Non-32 Mb/s Mode, these pins output serial TDM data streams at a
data-rate of:
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048 Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each output stream.
These pins are unused when the 32 Mb/s Mode is selected.
Refer to descriptions of the BORS and ODE pins for control of the output
High or High-Impedance state.
13
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Pin Description (continued)
Name
BCSTo0-3
Package
Coordinates
C14, A15, B15,
C15
Description
Backplane Output Channel High Impedance Control (5 V Tolerant
Three-state Outputs). Active high output enable which may be used to
control external buffering individually for a set of Backplane output
streams on a per channel basis.
In non-32 Mb/s mode (stream rates 2 Mb/s to 16 Mb/s):
BCSTo0 is the output enable for BSTo[0,4,8,12,16,20,24,28],
BCSTo1 is the output enable for BSTo[1,5,9,13,17,21,25,29],
BCSTo2 is the output enable for BSTo[2,6,10,14,18,22,26,30],
BCSTo3 is the output enable for BSTo[3,7,11,15,19,23,27,31].
In 32 Mb/s mode (stream rate 32 Mb/s):
BCSTo0 is the output enable for BSTo[0,4,8,12],
BCSTo1 is the output enable for BSTo[1,5,9,13],
BCSTo2 is the output enable for BSTo[2,6,10,14],
BCSTo3 is the output enable for BSTo[3,7,11,15].
Refer to descriptions of the BORS and ODE pins for control of the output
High or High-Impedance state.
FP8i
U14
Frame Pulse Input (5 V Tolerant). This pin accepts the Frame Pulse
signal. The pulse width may be active for 122 ns or 244 ns at the frame
boundary and the Frame Pulse Width bit (FPW) of the Control Register
must be set Low (default) for a 122 ns and set High for a the 244 ns pulse
condition.The device will automatically detect whether an ST-BUS or GCIBUS style frame pulse is applied.
C8i
W12
Master Clock Input (5 V Tolerant). This pin accepts a 8.192 MHz clock.
The internal Frame Boundary is aligned with the rising edge of this clock.
This rising edge frame boundary alignment is controlled by the C8IPOL bit
in the Control Register as shown in Table 16 on page 52. The C8IPOL bit
MUST be set to ONE for the rising edge frame boundary to be detected
correctly. Falling C8i edge frame boundary alignment is not supported
and should not be used.
CS
B11
Chip Select (5 V Tolerant). Active low input used by the microprocessor
to enable the microprocessor port access. This input is internally set low
during a device RESET.
DS
A11
Data Strobe (5 V Tolerant). This active low input works in conjunction
with CS to enable the microprocessor port read and write operations.
R/W
C11
Read/Write (5 V Tolerant). This input controls the direction of the data
bus lines (D0-D15) during a microprocessor access.
A0 - A14
D5, C6, A6, D7,
C7, B7, C8, B8,
A8, D9, B9, A9,
D10, C10, A10
Address 0 - 14 (5 V Tolerant). These pins form the 15-bit address bus to
the internal memories and registers. (Address A0 = LSB).
14
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Pin Description (continued)
Name
Package
Coordinates
Description
D0 - D15
V10, Y9, W9, V9,
U9, Y8, W8, V8,
W7, V7, U7, Y6,
W6, V6, Y5, W5
Data Bus 0 - 15 (5 V Tolerant). These pins form the 16-bit data bus of the
microprocessor port. (Data D0 = LSB).
DTA
A13
Data Transfer Acknowledgment (5 V Tolerant). This active low output
indicates that a data bus transfer is complete. A pull-up resistor is
required to hold a HIGH level. (Max. IOL = 10mA).
TMS
D12
Test Mode Select (5 V Tolerant with internal pull-up). JTAG signal that
controls the state transitions of the TAP controller.
TCK
A14
Test Clock (5 V Tolerant). Provides the clock to the JTAG test logic.
TDi
B13
Test Serial Data In (5 V Tolerant with internal pull-up). JTAG serial test
instructions and data are shifted in on this pin.
TDo
C13
Test Serial Data Out (5 V Tolerant Three-state Output). JTAG serial
data is output on this pin on the falling edge of TCK. This pin is held in
high impedance state when JTAG is not enabled.
TRST
B14
Test Reset (5 V Tolerant with internal pull-up) Asynchronously
initializes the JTAG TAP controller to the Test-Logic-Reset state. To be
pulsed low during power-up for JTAG testing. This pin must be held LOW
for normal functional operation of the device.
RESET
C12
Device Reset (5 V Tolerant with internal pull-up). This input (active
LOW) asynchronously applies reset and synchronously releases reset to
the device. In the reset state, the outputs LSTo0 - 15 and BSTo0 - 31 are
set to a high or high impedance depending on the state of the LORS and
BORS external control pins, respectively. It clears the device registers
and internal counters. This pin must stay low for more than 2 cycles of
input clock C8i for the reset to be invoked.
LSTi0-15
L18, L19, L20,
M17, M18,
M19, M20, N18,
N19, N20, P17,
P19, P20, R18,
R19, R20,
Local Serial Input Streams 0 to 15 (5 V Tolerant with internal pulldown). These pins accept serial TDM data streams at a data-rate of:
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048 Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each input stream.
C16o
W13
C16o Output Clock (Three-state Output). A 16.384 MHz clock output.
The clock falling edge or rising edge is aligned with the Local frame
boundary, this is controlled by the COPOL bit of the Control Register.
C8o
V13
C8o Output Clock (Three-state Output). A 8.192 MHz clock output. The
clock falling edge or rising edge is aligned with the Local frame boundary,
this is controlled by the COPOL bit of the Control Register.
15
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Pin Description (continued)
Name
Package
Coordinates
Description
FP16o
W14
Frame Pulse Output (Three-state Output). Frame pulse output is active
for 61 ns at the frame boundary. The frame pulse, running at a 8 KHz rate,
will be the same format (ST-BUS or GCI-BUS) as the input frame pulse
(FP8i).
FP8o
V14
Frame Pulse Output (Three-state Output). Frame pulse output is active
for 122 ns at the frame boundary. The frame pulse, running at 8 KHz rate,
will be the same style (ST-BUS or GCI-BUS) as the input frame pulse
(FP8i).
LSTo0 - 15
A17, A18, A19,
B18, B19, B20,
C18, C19, C20,
D18, D19, D20,
E17, E18, E19,
E20,
Local Serial Output Streams 0 to 15 (5 V Tolerant Three-state
Outputs). These pins output serial TDM data streams at a data-rate of:
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048 Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each output stream.
Refer to descriptions of the LORS and ODE pins for control of the output
High or High-Impedance state.
LCSTo0-1
C17, C16
Local Output Channel High Impedance Control (5 V Tolerant Threestate Outputs).
Active high output enable: used to control, on a per-channel basis, the
external buffering of Local output streams.
LCSTo0 is the output enable for streams: LSTo[0,2,4,6,8,10,12, and 14].
LCSTo1 is the output enable for streams: LSTo[1,3,5,7,9,11,13, and 15].
Refer to descriptions of the LORS and ODE pins for control of the output
High or High-Impedance state.
ODE
A12
Output Drive Enable (5 V Tolerant, Internal pull-up).
An asynchronous input providing Output Enable control to the BSTo0- 31,
LSTo0-15, BCSTo0-3 and LCSTo0-1 outputs.
When LOW, the BSTo0-31 and LSTo0- 31 outputs are driven high or high
impedance (dependent on the BORS and LORS pin settings respectively)
and the outputs BCSTo0-3 and LCSTo0-1 are driven low.
When HIGH, the outputs BSTo0- 31, LSTo0-15, BCSTo0-3 and LCSTo0-1
are enabled.
16
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Pin Description (continued)
Package
Coordinates
Name
BORS
K2
Description
Backplane Output Reset State (5 V Tolerant, Internal pull-down).
When this input is LOW the device will initialize with the BSTo0-31 outputs
driven high, and the BCSTo0-3 outputs driven low. Following initialization,
the Backplane stream outputs are always active and a high impedance
state, if required on a per-channel basis, may be implemented with
external buffers controlled by outputs BCSTo0-3.
When this input is HIGH, the device will initialize with the BSTo0-31
outputs at high impedance and the BCSTo0-3 outputs driven low.
Following initialization, the Backplane stream outputs may be set active or
high impedance using the ODE pin, or on a per-channel basis with the BE
bit of the Backplane Connection Memory.
LORS
K19
Local Output Reset State (5 V Tolerant, Internal pull-down).
When this input is LOW, the device will initialize with the LSTo0-15
outputs driven high and the LCSTo0-1 outputs driven low. Following
initialization, the Local stream outputs are always active and a high
impedance state, if required on a per-channel basis, may be implemented
with external buffers controlled by the LCSTo0-1 outputs.
When this input is HIGH, the device will initialize with the LSTo0-15
outputs at high impedance and the LCSTo0-1 outputs driven low.
Following initialization, the Local stream outputs may be set active or high
impedance using the ODE pin, or on a per-channel basis with the LE bit
of the Local Connection Memory.
NC
A16, B16,
Y12, Y13
No Connect.
No connection to be made.
IC
A2, A20, B6, B10,
B17, C3, C9, D16,
U2, U3, V2, V3,
V11, V12, V15,
V16, W10, W11,
W15, W16, W17,
W20, Y3, Y10,
Y15, Y16,
Internal Connects
These inputs MUST be held LOW.
T18, T19, T20,
U18, U19, U20,
V17, V18, V19,
V20, W18, W19,
Y20, Y17, Y18,
Y19,
F18, F19, F20,
G17, G18, G19,
G20, H18, H19,
H20, J17, J18,
J19, J20, K17,
K18
17
Zarlink Semiconductor Inc.
MT90870
1.0
Data Sheet
Bidirectional and Unidirectional Applications
The MT90870 has a maximum capacity of 12,288 input channels and 12,288 output channels. This is calculated
from the maximum number of streams and channels: 48 input streams (32 Backplane, 16 Local) at 16.384 Mb/s
and 48 output streams (32 Backplane, 16 Local) at 16.384 Mb/s.
One typical mode of operation is to separate the Backplane and Local sides, as shown in Figure 3 below.
BSTi0-31
LSTo0-15
32 streams
16 streams
BACKPLANE
LOCAL
BSTo0-31
32 streams
LSTi0-15
16 streams
MT90870
Figure 3 - 8,192 x 4,096 Channels (16 Mb/s), Bidirectional Switching
In this system setup, the chip has a capacity of 8,192 input channels and 8,192 output channels on the Backplane
side as well as 4,096 input channels and 4,096 output channels on the Local side. Note that some of the output
channels on one side can come from the other side, i.e., Backplane input to Local output switching.
Often a system design does not need to differentiate between Backplane and Local side, and merely needs
maximum switching capacity. In this case, the MT90870 can be used as shown in Figure 4 to give the full 12,288 x
12,288 channel capacity.
BSTi0-31
BSTo0-31
32 streams
32 streams
INPUT
OUTPUT
LSTi0-15
16 streams
LSTo0-15
16 streams
MT90870
Figure 4 - 12,288 x 12,288 Channels (16 Mb/s), Unidirectional Switching
In this system, the Backplane and Local inputs and outputs are combined and the switch appears as a 48 stream
input by 48 stream output switch. This style of operation is similar to older switch designs, such as the MT90826.
Note, in either configuration the Backplane may be operated in the 32 Mb/s Mode, providing 512 channels on each
of the 16 available input and output streams (BSTi0-15 and BSTo0-15) operating at a data-rate of 32.768 Mb/s, in
conjunction with the Local streams (LSTi0-15 and LSTo0-15) operated at 16.384 Mb/s. This allows data-rate
conversion between 32.768 Mb/s and 16.384 Mb/s without loss to the switching capacity.
18
Zarlink Semiconductor Inc.
MT90870
1.1
Data Sheet
Flexible Configuration
The F12KDX can be configured as an 8 K by 4 K blocking bi-directional digital switch, a 12 K by 12 K unidirectional
non-blocking digital switch, and as a non-blocking switch with various switching capacities.
A. Blocking Bi-directional Configuration (Typical System Configuration)
•
•
•
•
8,192-channel
4,096-channel
8,192-channel
4,096-channel
x
x
x
x
4,096-channel
8,192-channel
8,192-channel
4,096-channel
blocking switching from backplane to local streams
blocking switching from local to backplane streams
non-blocking switching from backplane input to backplane output streams
non-blocking switching from local input to local output streams
B. Unidirectional Configuration
Because the input and output drivers are synchronous, the user can combine input backplane streams and input
local streams or output backplane streams and output local streams to increase the total number of input and
output streams of the switch in a unidirectional configuration.
•
12,288-channel x 12,288-channel non-blocking switching from input to output streams
C. Non-Blocking Configuration
The F12KDX can be configured as a non-blocking switch if it is an application requirement. For example, it can be
configured as a 6 K by 6 K non-blocking switch:
•
•
•
6,144-channel
6,144-channel
6,144-channel
streams
6,144-channel
•
x 6,144-channel non-blocking switching from "backplane" to "local" streams
x 6,144-channel non-blocking switching from "local" to "backplane" streams
x 6,144-channel non-blocking switching from "backplane" input to "backplane" output
x 6,144-channel non-blocking switching from local input to local output streams
MT90870
LSTo0-15
6 K by 6 K
BSTi0-23
6 K by 6 K
BSTo0-23
BSTo24-31
6 K by 6 K
6 K by 6 K
Total 24 input streams and 24 output streams
LSTi0-15
BSTi24-31
Total 24 input streams and 24 output streams
Figure 5 - 6 K x 6 K Non-Blocking Configuration
2.0
Functional Description
2.1
Switching Configurations
The device supports five switching configurations. (1) Backplane-to-Local, (2) Local-to-Backplane, (3) Backplaneto-Backplane, (4) Local-to-Local, and (5) Uni-directional switch. The following sections describe the switching
paths. The switch paths of Configurations (1) to (4) may be operated simultaneously and in all 5 cases the
Backplane streams may be operated at a fixed data-rate of 32.768 Mb/s on 16 input and 16 output streams, or
optionally, at 16.384 Mb/s or lower data-rates on 32 input and 32 output streams. The Local streams (16 input and
16 output) may be operated at 16.384 Mb/s or lower data-rates. When the lower data-rates of 8.192, 4.096, and
19
Zarlink Semiconductor Inc.
MT90870
Data Sheet
2.048 Mb/s are included, there will be a corresponding reduction in switch capacity although conversion between
differing rates will be maintained.
2.1.1
Backplane-to-Local Path
The device can provide data switching between the Backplane input port (8192 channels) and the Local output port
(4096 channels). The Local Connection Memory determines the switching configurations.
2.1.2
Local-to-Backplane Path
The device can provide data switching between the Local input port (4096 channels) and the Backplane output port
(8192 channels). The Backplane Connection Memory determines the switching configurations.
2.1.3
Backplane-to-Backplane Path
The device can provide data switching between the Backplane input (8192 channels) and output (8192 channels)
ports. The Backplane Connection Memory determines the switching configurations.
2.1.4
Local-to-Local Path
The device can provide data switching between the Local input (4096 channels) and output (4096 channels) ports.
The Local Connection Memory determines the switching configurations.
2.1.5
Uni-directional Switch
The device may be optionally configured to provide a 12,288 x 12,288 uni-directional switch by grouping together
Backplane and Local input and output streams.
2.2
Port Data Rate Modes and Selection
The selection of individual stream data-rates is summarized in Table 1.
2.2.1
Local Port Rate Selection
The Local port has 16 input (LSTi0-15) and 16 output (LSTo0-15) data streams. All input and output streams may
be individually selected for operation at a data rate of either 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s.
The timing of the input and output clocks and frame pulses are shown in Figure 6, Local Port Timing Diagram for
2,4,8 and 16 Mb/s stream rates.
2.2.1.1
Local Input Port
The bit rate for each input stream is selected by writing to a dedicated Local Input Bit Rate Register (LIBRR0-15).
Refer to Table 41, Local Input Bit Rate Register (LIBRRn) Bits.
Rate Selection Capability
(for each individual stream)
Stream Number
Input stream - Backplane 0-15 (BSTi0-15)
2.048, 4.096, 8.192 or 16.384 Mb/s - Non-32 Mb/s Mode
32.768 Mb/s - 32 Mb/s Mode
Input stream - Backplane 16-31 (BSTi16-31)
2.048, 4.096, 8.192 or 16.384 Mb/s - Non-32 Mb/s Mode
Unused - 32 Mb/s Mode
Output stream - Backplane 0-15 (BSTo0-15)
2.048, 4.096, 8.192 or 16.384 Mb/s - Non-32 Mb/s Mode
32.768 Mb/s - 32 Mb/s Mode
20
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Rate Selection Capability
(for each individual stream)
Stream Number
Output stream - Backplane 16-31 (BSTo16-31)
2.048, 4.096, 8.192 or 16.384 Mb/s - Non-32 Mb/s Mode
Unused - 32 Mb/s Mode
Input stream - Local 0-15 (LSTi0-15)
2.048, 4.096, 8.192 or 16.384 Mb/s
Output stream - Local 0-15 (LSTo0-15)
2.048, 4.096, 8.192 or 16.384 Mb/s
Table 1 - Per-stream Data-Rate Selection: Backplane and Local, Non-32 Mb/s Mode and 32 Mb/s Mode
FP8i (ST-BUS)
(8 kHz)
C8i (ST-BUS)
(8.192 MHz)
FP8i (GCI)
(8 kHz)
C8i (GCI)
(8.192 MHz)
Channel 0
LSTi/LSTo0-15
(16 Mb/s) ST
1
0
7
6
5
Channel 255
3
4
2
1
0
6
5
Channel 0
LSTi/LSTo0-15
(16 Mb/s) GCI
6
7
0
1
2
5
6
7
1
2
Channel 0
LSTi/LSTo0-15
(8 Mb/s) ST
0
7
6
LSTi/LSTo0-15
(8 Mb/s) GCI
7
0
1
4
3
7
2
3
4
7
0
0
7
4
7
5
6
7
0
1
5
6
1
1
6
0
7
6
7
0
0
7
7
0
Channel 63
Channel 31
0
7
7
Channel 31
Channel 0
LSTi/LSTo0-15
(2 Mb/s) GCI
0
Channel 63
Channel 0
LSTi/LSTo0-15
(2 Mb/s) ST
1
Channel 127
Channel 0
LSTi/LSTo0-15
(4 Mb/s) GCI
3
2
Channel 0
0
2
Channel 127
5
Channel 0
LSTi/LSTo0-15
(4 Mb/s) ST
3
Channel 255
4
3
4
7
0
Figure 6 - Local Port Timing Diagram for 2,4,8 and 16 Mb/s stream rates
21
Zarlink Semiconductor Inc.
0
MT90870
2.2.1.2
Data Sheet
Local Output Port
The bit rate for each output stream is selected by writing to a dedicated Local Output Bit Rate Register (LOBRR015). Refer to Table 43, Local Output Bit Rate Register (LOBRRn) Bits.
Operation of stream data in the Connection Mode or the Message Mode is determined by the state of the LMM bit,
and the channel High-impedance state is controlled by the LE bit of the Local Connection Memory. The data source
(i.e. from the Local or Backplane Data Memory) is determined by the LSRC bit of the Local Connection Memory.
Refer to Section 6.1, Local Connection Memory, and Section 12.3, Local Connection Memory Bit Definition.
2.2.2
Backplane Port Rate Selection
The Backplane streams may be operated in one of two modes, namely Non-32 Mb/s Mode and 32 Mb/s Mode. The
Local stream data-rates are not affected by the operating mode of the Backplane. The operating mode of the
Backplane is determined by setting the Control Register bit, MODE32. Setting the bit HIGH will invoke the 32 Mb/s
Mode. Setting the bit LOW will invoke the Non-32 Mb/s mode. The default bit value on device Reset is LOW. The
timing of the input and output clocks and frame pulses are shown in Figure 7, Backplane Port Timing Diagram for 2,
4, 8, 16 and 32 Mb/s stream rates.
Non-32 Mb/s Mode: Each of the 32 Backplane streams (BSTi0-31 and BSTo0-31) and Local streams (LSTi0-15 and
LSTo0-15) can be independently programmed for a data-rate of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or
16.384 Mb/s.
32 Mb/s Mode: 16 of the Backplane input streams (BSTi0-15) and 16 Backplane output (BSTo0-15) streams
operate at a fixed rate of 32.768 Mb/s. In this mode, the upper 16 input (BSTi16-31) and 16 output (BSTi16-31)
streams are unused. All 32 Local streams can be independently programmed for a data-rate of 2.048 Mb/s,
4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s.
2.2.2.1
Backplane Input Port
The bit rate for each input stream is selected by writing to a dedicated Backplane Input Bit Rate Register (BOBRR031). Refer to Table 45, Backplane Input Bit Rate Register (BIBRRn) Bits. If the 32 Mb/s mode is selected by writing
to the Control Register bit (MODE32), the settings in BIBRRn are ignored.
2.2.2.2
Backplane Output Port
The bit rate for each output stream is selected by writing to a dedicated Backplane Output Bit Rate Register
(BOBRR0-31). Refer to Table 47, Backplane Output Bit Rate Register (BOBRRn) Bits. If the 32 Mb/s mode is
selected by writing to the Control Register bit (MODE32), the settings in BOBRRn are ignored.
Operation of stream data in the Connection Mode or the Message Mode is determined by the state of the BMM bit,
and the channel High-impedance state is controlled by the BE bit of the Backplane Connection Memory. The data
source (i.e., from the Local or Backplane Data Memory) is determined by the BSRC bit of the Backplane
Connection Memory. Refer to Section 6.2, Backplane Connection Memory and Section 12.4, Backplane
Connection Memory Bit Definition.
22
Zarlink Semiconductor Inc.
MT90870
Data Sheet
FP8i (ST-BUS)
(8 kHz)
C8i (ST-BUS)
(8.192 MHz)
FP8i (GCI)
(8 kHz)
C8i (GCI)
(8.192 MHz)
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Channel 510
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1
0
7
7
0
6
5
Channel 255
3
4
2
1
0
6
5
Channel 0
BSTi/BSTo0-31
(16 Mb/s) GCI
6
1
2
5
6
7
1
2
Channel 0
BSTi/BSTo0-31
(8 Mb/s) ST
0
7
6
BSTi/BSTo0-31
(8 Mb/s) GCI
7
0
1
4
3
7
2
3
4
7
0
0
7
1
0
7
5
6
7
0
1
0
7
6
7
0
Channel 63
6
1
1
6
0
7
7
0
Channel 63
Channel 31
0
7
7
Channel 31
Channel 0
BSTi/BSTo0-31
(2 Mb/s) GCI
4
5
Channel 0
BSTi/BSTo0-31
(2 Mb/s) ST
2
Channel 127
Channel 0
BSTi/BSTo0-31
(4 Mb/s) GCI
3
2
Channel 0
0
3
Channel 127
5
Channel 0
BSTi/BSTo0-31
(4 Mb/s) ST
4
Channel 255
4
3
Channel 511
1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1
Channel 0
BSTi/BSTo0-31
(16 Mb/s) ST
Channel 511
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
Channel 1
Channel 0
BSTi/BSTo0-15
(32 Mb/s) GCI
Channel 510
Channel 1
Channel 0
BSTi/BSTo0-15
(32 Mb/s) ST
7
0
0
Figure 7 - Backplane Port Timing Diagram for 2, 4, 8, 16 and 32 Mb/s stream rates
2.3
Backplane Frame Pulse Input and Master Input Clock Timing
The Backplane frame pulse (FP8i) is an 8 kHz input signal active for 122 ns or 244 ns at the frame boundary. The
FPW bit in the Control Register must be set according to the applied pulse width. See Pin Description and Table
16, Control Register Bits, for details.
The active state and timing of FP8i may conform either to the ST-BUS or to the GCI-BUS as shown in Figure 6,
Local Port Timing Diagram for 2,4,8 and 16 Mb/s stream rates, and Figure 7, Backplane Port Timing Diagram for 2,
4, 8, 16 and 32 Mb/s stream rates. The MT90869 will automatically detect whether an ST-BUS or a GCI-BUS style
frame pulse is being used for the master frame pulse (FP8i). The device will detect the frame boundary alignment
using the rising edge of the input clock (C8i), provided the C8IPOL bit in Table 16, “Control Register Bits,” on
page 52 is set to one. Before the C8IPOL bit is set to one, the frame boundary will not be detected correctly. For the
23
Zarlink Semiconductor Inc.
MT90870
Data Sheet
purposes of describing the device operation, the remaining part of this document assumes the ST-BUS style frame
pulse with a single width frame pulse of 122 ns and the C8IPOL bit is set to one unless explicitly stated otherwise.
In addition, the device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to
the Local port. The Local frame pulses (FP8o, FP16o) will be provided in the same style as the master frame pulse
(FP8i). The polarity of C8o and C16o, at the Frame Boundary, can be controlled by the Control Register bit,
COPOL. An analogue phase lock loop (APLL) is used to multiply the external clock frequency to generate an
internal clock signal operated at 131.072 MHz.
2.4
Backplane Frame Pulse Input and Local Frame Pulse Output Alignment
The MT90870 accepts a Backplane Frame Pulse (FP8i) and generates the Local Frame Pulse outputs, FP8o and
FP16o, which are aligned to the master frame pulse. There is a constant three frame delay for data being switched.
Figure 8, Backplane and Local Frame Pulse Alignment for Data Rates of 2 Mb/s, 4 Mb/s, 8 Mb/s and 16 Mb/s,
shows the backplane and local frame pulse alignment for different data rates.
For further details of Frame Pulse conditions and options see Section 13.1, Control Register (CR), Figure 18,
Frame Boundary Conditions, ST- BUS Operation, and Figure 19, Frame Boundary Conditions, GCI - BUS
Operation.
FP8i
C8i
BSTi/BSTo0-31
(2 Mb/s)
BSTi/BSTo0-31
(4 Mb/s)
BSTi/BSTo0-31
(8 Mb/s)
BSTi/BSTo0-31
(16 Mb/s)
CH0
CH0
CH0
CH
0
CH1
CH1
CH
1
CH1
CH
2
CH2
CH
3
CH
4
CH
5
CH
6
CH3
CH2
CH3
CH4
CH
7
CH
8
CH5
CH
9
CH
10
CH2
CH7
CH6
CH
11
CH
12
CH4
CH
13
CH
14
CH9
CH8
CH
15
CH
16
CH
17
CH5
CH
18
CH
19
CH10
CH
20
CH
21
CH11
CH
22
CH
23
FP8o
C8o
LSTi/LSTo0-15
(2 Mb/s)
LSTi/LSTo0-15
(4 Mb/s)
LSTi/LSTo0-15
(8 Mb/s)
LSTi/LSTo0-15
(16 Mb/s)
CH0
CH0
CH0
CH
0
CH1
CH1
CH
1
CH
2
CH1
CH2
CH
3
CH
4
CH
5
CH
6
CH4
CH
7
CH
8
CH5
CH
9
CH
10
CH4
CH3
CH2
CH3
CH2
CH7
CH6
CH
11
CH
12
CH
13
CH
14
CH8
CH
15
CH
16
CH5
CH9
CH CH
17 18
CH
19
CH10
CH
20
CH11
CH CH
21 22
CH
23
Figure 8 - Backplane and Local Frame Pulse Alignment for Data Rates of 2 Mb/s, 4 Mb/s, 8 Mb/s
and 16 Mb/s
3.0
Input and Output Offset Programming
3.1
Input Channel Delay Programming (Backplane and Local Input Streams)
Various registers are used to control the input sampling point (delay) and the output advancement for the Local and
Backplane streams. The following sections explain the details of these offset programming features.
The control of the Input Channel Delay and the Input Bit Delay allows each input stream to have a different frame
boundary with respect to the master frame pulse, FP8i. By default, all input streams have channel delay of zero
such that Ch0 is the first channel that appears after the frame boundary.
24
Zarlink Semiconductor Inc.
MT90870
Data Sheet
By programming the Backplane or Local input channel delay registers, BCDR0-31 and LCDR0-15, users can
assign the Ch0 position to be located at any one of the channel boundaries in a frame. See Figure 9.
FP8i
C8i
BSTi0-31LSTi0-15
Channel Delay = 2
Ch125
Ch 0
Channel Delay, 2
Ch127
Ch126
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Ch127
Ch127
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Channel Delay,1
Ch127
BSTi0-31/LSTi0-15
Channel Delay = 1
Ch126
Ch 1
Ch 0
BSTi0-31/LSTi0-15
Channel Delay = 0
(Default)
Ch0
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Ch125
7 6 5 4 3 2 1 0 7 6
Figure 9 - Backplane and Local Input Channel Delay Timing Diagram (8 Mb/s)
For delays within channel boundaries, the input bit delay programming can be used. The use of Input Channel
Delay in combination with Input Bit Delay enables the Ch0 position to be placed anywhere within a frame to a
resolution of 1/4 of the bit period.
3.2
Input Bit Delay Programming (Backplane and Local Input Streams)
In addition to the Input Channel Delay programming, the Input Bit Delay programming feature provides users with
greater flexibility when designing switch matrices for high speed operation. The input bit delay may be programmed
on a per-stream basis to accommodate delays created on PCM highways. For all streams the delay is up to 7 3/4
bits with a resolution of 1/4 bit, for the selected data-rate.
See Figure 10 and Figure 11 for Input Bit Delay Timing at 16 Mb/s and 8 Mb/s data rates, respectively.
The Local input delay is defined by the Local Input Delay registers, LIDR0 to LIDR15, corresponding to the Local
data streams, LSTi0 to LSTi15, and the Backplane input delay is defined by the Backplane Input Delay registers,
BIDR0 to BIDR31, which correspond to the Backplane data streams, BSTi0 to BSTi31.
25
Zarlink Semiconductor Inc.
MT90870
Data Sheet
FP8i
C8i
Ch255
BSTi0-31/LSTi0-15
Bit Delay = 0
(Default)
3
2
Ch0
1
7
0
6
5
Ch1
4
3
2
1
7
0
6
5
4
Bit Delay, 1/4
BSTi0-31/LSTi0-15
Bit Delay = 1/4
Ch255
3
Ch0
2
1
7
0
6
5
Ch1
4
3
2
1
7
0
6
5
4
Bit Delay, 1/2
BSTi0-31/LSTi0-15
Bit Delay = 1/2
Ch255
3
Ch0
2
1
7
0
6
5
Ch1
4
3
2
1
7
0
6
5
4
Bit Delay, 3/4
BSTi0-31/LSTi0-15
Bit Delay = 3/4
Ch255
3
Ch1
Ch0
2
1
7
0
6
5
4
3
2
1
7
0
6
5
4
Bit Delay, 1
Ch0
Ch255
BSTi0-31/LSTi0-15
Bit Delay = 1
BSTi0-31/LSTi0-15
Bit Delay = 7 1/2
BSTi0-31/LSTi0-15
Bit Delay = 7 3/4
3
2
1
7
0
6
Ch254
2
Ch1
4
3
2
1
7
0
6
5
4
Ch254
0
7
6
5
3
4
6
5
Bit Delay, 7 1/2
Ch0
2
1
0
7
6
5
4
Bit Delay, 7 3/4
Ch0
Ch255
1
7
0
Ch255
1
2
5
3
2
1
0
7
6
5
4
Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mb/s
26
Zarlink Semiconductor Inc.
MT90870
Data Sheet
FP8i
C8i
Ch127
BSTi0-31/LSTi0-15
Bit Delay = 0
(Default)
3
2
Ch0
1
7
0
6
5
Ch1
4
3
2
1
7
0
6
5
4
Bit Delay, 1/4
BSTi0-31/LSTi0-15
Bit Delay = 1/4
Ch127
3
Ch0
2
1
7
0
6
5
Ch1
4
3
2
1
0
7
6
5
4
Bit Delay, 1/2
BSTi0-31/LSTi0-15
Bit Delay = 1/2
Ch127
3
Ch0
2
1
7
0
6
5
Ch1
4
3
2
1
7
0
6
5
4
Bit Delay, 3/4
BSTi0-31/LSTi0-15
Bit Delay = 3/4
Ch127
3
Ch0
2
1
7
0
6
5
Ch1
4
3
2
1
7
0
6
5
4
Bit Delay, 1
Ch0
Ch127
BSTi0-31/LSTi0-15
Bit Delay = 1
BSTi0-31/LSTi0-15
Bit Delay = 7 1/2
BSTi0-31/LSTi0-15
Bit Delay = 7 3/4
3
2
1
7
0
6
Ch126
2
Ch1
4
3
2
1
7
0
6
5
4
Ch126
0
7
6
5
3
4
6
5
Bit Delay, 7 1/2
Ch0
2
1
7
0
6
5
4
Bit Delay, 7 3/4
Ch0
Ch127
1
7
0
Ch127
1
2
5
3
2
1
0
7
6
5
4
Figure 11 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 8 Mb/s
3.3
Output Advancement Programming (Backplane and Local Output Streams)
This feature is used to advance the output channel alignment of individual Local or Backplane output streams with
respect to the frame boundary. Each output stream has its own advancement value which can be programmed by
the output advancement registers. The output advancement selection is useful in compensating for various
parasitic loading on the serial data output pins.
3.3.1
Local Output Advancement Programming
The Local output advancement registers, LOAR0-15, are used to control the Local output advancement. The
advancement is determined with reference to the internal system clock rate (131.072 MHz). For 2 Mb/s, 4 Mb/s,
8 Mb/s or 16 Mb/s streams the advancement may be 0, -2 cycles, -4 cycles or -6 cycles, which converts to
approximately 0ns, -15 ns, -30 ns or -45 ns as shown in Figure 12.
3.3.2
Backplane Output Advancement Programming
The Backplane output advancement registers, BOAR0-31 are used to control the Backplane output advancement.
The advancement is determined with reference to the internal system clock rate (131.072 MHz). For 2 Mb/s,
4 Mb/s, 8 Mb/s or 16 Mb/s streams the advancement may be 0, -2 cycles, -4 cycles or -6 cycles, which converts to
27
Zarlink Semiconductor Inc.
MT90870
Data Sheet
approximately 0ns, -15 ns, -30 ns or -45 ns as shown in Figure 12. For 32 Mb/s streams, the advancement may be
0, -1 cycle, -2 cycles or -3 cycles, which converts to approximately 0ns, -7 ns, -15 ns or -22 ns.
FP8o
System Clock
131.072 Mhz
Ch255
BSTo0-31/LSTo0-15
Bit Advancement = 0
(Default)
Bit 1
Ch0
Bit 0
Bit 7
Bit Advancement, -2
Ch255
BSTo0-31/LSTo0-15
Bit Advancement = -2
Bit 1
Bit 0
Bit 7
Bit 1
Bit 0
Bit 7
Bit 5
Ch0
Bit 6
Bit Advancement, -6
Ch255
BSTo0-31/LSTo0-15
Bit Advancement = -6
Bit 6
Bit Advancement, -4
Bit 0
Bit 1
Bit 5
Ch0
Bit 7
Ch255
BSTo0-31/LSTo0-15
Bit Advancement = -4
Bit 6
Bit 6
Bit 4
Bit 5
Ch0
Bit 5
Bit 4
Figure 12 - Backplane and Local Output Advancement Timing diagram for Data Rate of 16 Mb/s
4.0
Port High Impedance Control
4.1
Local Port High Impedance Control
The input pin, LORS, selects whether the Local output streams, LSTo0-15 are set to high impedance at the output
of the MT90870 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if required on
a per-channel basis, is invoked through an external interface circuit controlled by the LCSTo0-1 signals. Setting
LORS to a LOW state will configure the output streams, LSTo0-15, to transmit bi-state channel data with perchannel high-impedance determined by external circuits under the control of the LCSTo0-1 outputs. Setting LORS
to a HIGH state will configure the output streams, LSTo0-15, of the MT90870 to invoke a high-impedance output on
a per-channel basis.
The LORS pin is an asynchronous input and is expected to be hard-wired for a particular system application,
although it may be driven under logic control if preferred.
4.1.1
LORS Set LOW
The data (channel control bit) transmitted by LCSTo0-1 replicates the Local Output Enable Bit (LE) of the Local
Connection Memory, with a LOW state indicating the channel to be set to High Impedance. See Section 12.3, Local
Connection Memory Bit Definition for setting the Local Output Enable Bit (LE).
The LCSTo0-1 outputs transmit serial data (channel control bits) at 16.384 Mb/s, with each bit representing the perchannel high impedance state for specific streams. Eight output streams are allocated to each control line as
follows:
(See also Pin Description)
•
•
LCSTo0 outputs the channel control bits for streams: LSTo0, 2, 4, 6, 8, 10, 12, and 14.
LCSTo1 outputs the channel control bits for streams: LSTo1, 3, 5, 7, 9, 11, 13, and 15.
The Channel Control Bit location, within a frame period, for each channel of the Local output streams is presented
in Table 2, LCSTo Allocation of Channel Control Bits to the Output Streams.
28
Zarlink Semiconductor Inc.
MT90870
Data Sheet
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 2:
(1) The Channel Control Bit corresponding to Stream 0, Channel 0, LSTo0_Ch0, is transmitted on LCSTo0 and is
advanced, relative to the Frame Boundary, by 10 periods of C16o.
(2) The Channel Control Bit corresponding to Stream 14, Channel 0, LSTo14_Ch0, is transmitted on LCSTo0 in
advance of the Frame Boundary by three periods of output clock, C16o. Similarly, the Channel Control Bit for
LSTo15_Ch0, is advanced relative to the Frame Boundary by three periods of C16o, on LCSTo1.
The LCSTo0-1 outputs data at a constant data-rate of 16.384 Mb/s, independent of the data-rate selected for the
individual output streams, LSTo0-15. Streams at data-rates lower than 16.384 Mb/s will have the value of the
respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for 8.192 Mb/s
streams, four times for 4.096 Mb/s streams and eight times for 2.048 Mb/s streams. The channel control bit is not
repeated for 16.384 Mb/s streams.
Examples are presented, with reference to Table 2:
(3) With stream LSTo4 selected to operate at a data-rate of 2.048 Mb/s, the value of the Channel Control
Bit for Channel 0 will be transmitted during the C16o clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and
48.
(4) With stream LSTo8 operated at a data-rate of 8.192 Mb/s, the value of the Channel Control Bit for
Channel 1 will be transmitted during the C16o clock period nos. 9 and 17.
Figure 13, Local Port External High Impedance Control Bit Timing (ST-Bus Mode) shows the channel control bits for
LCSTo0 and LCSTo1 in one possible scenario which includes stream LSTo0 at a data-rate of 16.384 Mb/s, LSTo1
at 8.192 Mb/s, LSTo6 at 4.096 Mb/s and LSTo7 at 2.048 Mb/s. All remaining streams are operated at a data-rate of
16.384 Mb/s.
4.1.2
LORS Set HIGH
The Local Output Enable Bit (LE) of the Local Connection Memory has direct per-channel control on the highimpedance state of the Local Output streams, LSTo0-15. Programming the LE bit to a LOW state will set the
stream output of the MT90870 to High Impedance for the duration of the channel period. See Section 12.3, Local
Connection Memory Bit Definition, for programming details.
The LCSTo0-1 outputs remain active.
Allocated Channel No. 2
Allocated Stream No.
C16o
Period1
LCSTo0
LCSTo1
16 Mb/s
8 Mb/s
4 Mb/s
2 Mb/s
2039
0 3-1
1
Ch 0
Ch 0
Ch 0
Ch 0
2040
2
3-3
3
Ch 0
Ch 0
Ch 0
Ch 0
2041
4
5
Ch 0
Ch 0
Ch 0
Ch 0
2042
6
7
Ch 0
Ch 0
Ch 0
Ch 0
2043
8
9
Ch 0
Ch 0
Ch 0
Ch 0
2044
10
11
Ch 0
Ch 0
Ch 0
Ch 0
2045
12
13
Ch 0
Ch 0
Ch 0
Ch 0
2046
143-2
153-2
Ch 0
Ch 0
Ch 0
Ch 0
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams
29
Zarlink Semiconductor Inc.
MT90870
Allocated Channel No. 2
Allocated Stream No.
C16o
Period1
LCSTo0
LCSTo1
Data Sheet
16 Mb/s
8 Mb/s
4 Mb/s
2 Mb/s
2047
0
1
Ch 1
Ch 0
Ch 0
Ch 0
2048
2 3-3
3
Ch 1
Ch 0
Ch 0
Ch 0
Frame
1
4
5
Ch 1
Ch 0
Ch 0
Ch 0
Boundary
2
6
7
Ch 1
Ch 0
Ch 0
Ch 0
3
8
9
Ch 1
Ch 0
Ch 0
Ch 0
4
10
11
Ch 1
Ch 0
Ch 0
Ch 0
5
12
13
Ch 1
Ch 0
Ch 0
Ch 0
6
14
15
Ch 1
Ch 0
Ch 0
Ch 0
7
0
1
Ch 2
Ch 1
Ch 0
Ch 0
8
2 3-3
3
Ch 2
Ch 1
Ch 0
Ch 0
9
4
3-4
5
Ch 2
Ch 1
Ch 0
Ch 0
10
6
7
Ch 2
Ch 1
Ch 0
Ch 0
11
8
9
Ch 2
Ch 1
Ch 0
Ch 0
12
10
11
Ch 2
Ch 1
Ch 0
Ch 0
13
12
13
Ch 2
Ch 1
Ch 0
Ch 0
14
14
15
Ch 2
Ch 1
Ch 0
Ch 0
15
0
1
Ch 3
Ch 1
Ch 0
Ch 0
16
2
3-3
3
Ch 3
Ch 1
Ch 0
Ch 0
17
4 3-4
5
Ch 3
Ch 1
Ch 0
Ch 0
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
2029
etc
etc
Ch 254
Ch 127
Ch 63
Ch 31
2030
14
15
Ch 254
Ch 127
Ch 63
Ch 31
2031
0
1
Ch 255
Ch 127
Ch 63
Ch 31
2032
2
3
Ch 255
Ch 127
Ch 63
Ch 31
2033
4
5
Ch 255
Ch 127
Ch 63
Ch 31
2034
6
7
Ch 255
Ch 127
Ch 63
Ch 31
2035
8
9
Ch 255
Ch 127
Ch 63
Ch 31
2036
10
11
Ch 255
Ch 127
Ch 63
Ch 31
2037
12
13
Ch 255
Ch 127
Ch 63
Ch 31
2038
14
15
Ch 255
Ch 127
Ch 63
Ch 31
2039
0
1
Ch 0
Ch 0
Ch 0
Ch 0
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams (continued)
30
Zarlink Semiconductor Inc.
MT90870
Allocated Channel No. 2
Allocated Stream No.
C16o
Period1
LCSTo0
LCSTo1
Data Sheet
16 Mb/s
8 Mb/s
4 Mb/s
2 Mb/s
2040
2
3
Ch 0
Ch 0
Ch 0
Ch 0
2041
4
5
Ch 0
Ch 0
Ch 0
Ch 0
2042
6
7
Ch 0
Ch 0
Ch 0
Ch 0
2043
8
9
Ch 0
Ch 0
Ch 0
Ch 0
2044
10
11
Ch 0
Ch 0
Ch 0
Ch 0
2045
12
13
Ch 0
Ch 0
Ch 0
Ch 0
2046
14
15
Ch 0
Ch 0
Ch 0
Ch 0
2047
0
1
Ch 1
Ch 0
Ch 0
Ch 0
2048
2
3
Ch 1
Ch 0
Ch 0
Ch 0
Frame
1
4
5
Ch 1
Ch 0
Ch 0
Ch 0
Boundary
2
6
7
Ch 1
Ch 0
Ch 0
Ch 0
3
8
9
Ch 1
Ch 0
Ch 0
Ch 0
etc
etc
etc
etc
etc
etc
etc
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams (continued)
Note 1: Clock Period count is referenced to Frame Boundary.
Note 2: The Channel Numbers presented relate to the data-rate selected for a specific stream.
Note 3-1 to 3-4: See Section 4.1.1 for examples of Channel Control Bit for streams of different data-rates.
31
Zarlink Semiconductor Inc.
MT90870
Data Sheet
FP8o
C8o
Channel 255 bits 7-0
Channel 0
LSTo0
(16 Mb/s)
1
0
Chan 0
Bit 5
Chan 0 Bit 7
1
0
7
Chan 0
Bit 4
6
5
4
3
2
1
0
Chan 127 Chan 127 Chan 127 Chan 127
Bit 3
Bit 2
Bit 1
Bit 0
Chan 0 Bit 6
Chan 63 Bit 1
6
Chan 0
Bit 7
Chan 0
Bit 7
Chan 0
Bit 7
LCSTo0
CH 1
LSTo6
CH 1
LSTo8
CH 1
LSTo10
CH 1
LSTo12
CH 1
LSTo14
CH 2
LSTo0
CH 2
LST02
CH 0
LSTo4
CH 0
LSTo6
CH 0
LSTo8
CH 0
LSTo10
CH 0
LSTo12
CH 0
LSTo14
CH 1
LSTo0
CH 1
LSTo2
CH 1
LSTo4
CH 1
LSTo6
LCSTo1
CH 1
LSTo9
CH 1
LSTo11
CH 1
LSTo13
CH 1
LSTo15
CH 1
LSTo1
CH 2
LSTo3
CH 0
LSTo5
CH 0
LSTo7
CH 0
LSTo9
CH 0
LSTo11
CH 0
LSTo13
CH 0
LSTo15
CH 0
LSTo1
CH 1
LSTo3
CH 1
LSTo5
CH 1
LSTo7
Channel 31 Bit 0
CH 1
LSTo7
Channel 0 Bit 7
Chan 63 Bit 0
7
CH 1
LSTo4
Chan 31
Bit 0
2
CH 1
LSTo5
LSTo7
(2 Mb/s)
Chan 0
Bit 6
3
CH 1
LSTo2
Chan 63
Bit 0
4
CH 1
LSTo3
LSTo6
(4 Mb/s)
Chan 0
Bit 7
5
CH 1
LSTo0
Chan 127
Bit 0
6
CH 1
LSTo1
LSTo1
(8 Mb/s)
7
One C16o period
Figure 13 - Local Port External High Impedance Control Bit Timing (ST-Bus Mode)
4.2
Backplane High Impedance Control
The input pin, BORS, selects whether the Backplane output streams, BSTo0-31 are set to high impedance at the
output of the MT90870 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if
required on a per-channel basis, is invoked through an external interface circuit controlled by the BCSTo0-3
signals. Setting BORS to a LOW state will configure the output streams, BSTo0-31, to transmit bi-state channel
data with per-channel high-impedance determined by external circuits under the control of the BCSTo0-3 outputs.
Setting BORS to a HIGH state will configure the output streams, BSTo0-31, of the MT90870 to invoke a highimpedance output on a per-channel basis.
The BORS pin is an asynchronous input and is expected to be hard-wired for a particular system application,
although it may be driven under logic control if preferred.
4.2.1
BORS Set LOW, Non-32 Mb/s Mode
The data (channel control bit) transmitted by BCSTo0-3 replicates the Backplane Output Enable Bit (BE) of the
Backplane Connection Memory, with a LOW state indicating the channel to be set to High Impedance. See Section
12.4, Backplane Connection Memory Bit Definition for setting the Backplane Output Enable Bit (BE).
32
Zarlink Semiconductor Inc.
MT90870
Data Sheet
The BCSTo0-3 outputs transmit serial data (channel control bits) at 16.384 Mb/s, with each bit representing the perchannel high impedance state for specific streams. Eight output streams are allocated to each control line as
follows:
(See also Pin Description)
•
•
•
•
BCSTo0 outputs the channel control bits for streams BSTo0, 4, 8, 12, 16, 20, 24 and 28.
BCSTo1 outputs the channel control bits for streams BSTo1, 5, 9, 13, 17, 21, 25 and 29.
BCSTo2 outputs the channel control bits for streams BSTo2, 6, 10, 14, 18, 22, 26 and 30.
BCSTo3 outputs the channel control bits for streams BSTo3, 7, 11, 15, 19, 23, 27 and 31.
The Channel Control Bit location, within a frame period, for each channel of the Backplane output streams is
presented in Table 3, BCSTo Allocation of Channel Control Bits to the Output Streams (non-32 Mb/s Mode).
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 3:
(1) The Channel Control Bit corresponding to Stream 0, Channel 0, BSTo0_Ch0, is transmitted on BCSTo0 and is
advanced, relative to the Frame Boundary, by 10 periods of C16o.
(2) The Channel Control Bit corresponding to Stream 28, Channel 0, BSTo28_Ch0, is transmitted on BCSTo0 in
advance of the Frame Boundary by three periods of output clock, C16o. Similarly, the Channel Control Bits for
BSTo29_Ch0, BSTo30_Ch0 and BSTo31_Ch0 are advanced relative to the Frame Boundary by three periods of
C16o, on BCSTo1, BCSTo2 and BCSTo3, respectively.
The BCSTo0-3 outputs data at a constant data-rate of 16.384 Mb/s, independent of the data-rate selected for the
individual output streams, BSTo0-31. Streams at data-rates lower than 16.384 Mb/s will have the value of the
respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for 8.192 Mb/s
streams, four times for 4.096 Mb/s streams and eight times for 2.048 Mb/s streams. The channel control bit is not
repeated for 16.384 Mb/s streams.
Examples are presented, with reference to Table 3:
(3) With stream BSTo4 selected to operate at a data-rate of 2.048 Mb/s, the value of the Channel
Control Bit for Channel 0 will be transmitted during the C16o clock period nos. 2040, 2048, 8, 16, 24, 32,
40 and 48.
(4) With stream BSTo8 operated at a data-rate of 8.192 Mb/s, the value of the Channel Control Bit for
Channel 1 will be transmitted during the C16o clock period nos. 9 and 17.
Channel No. 2
Allocated Stream No.
C16o
Period1
BCSTo0
BCSTo1
BCSTo2
BCSTo3 16 Mb/s
8 Mb/s
4 Mb/s
2 Mb/s
2039
0 3-1
1
2
3
Ch 0
Ch 0
Ch 0
Ch 0
2040
4 3-3
5
6
7
Ch 0
Ch 0
Ch 0
Ch 0
2041
8
9
10
11
Ch 0
Ch 0
Ch 0
Ch 0
2042
12
13
14
15
Ch 0
Ch 0
Ch 0
Ch 0
2043
16
17
18
19
Ch 0
Ch 0
Ch 0
Ch 0
2044
20
21
22
23
Ch 0
Ch 0
Ch 0
Ch 0
2045
24
25
26
27
Ch 0
Ch 0
Ch 0
Ch 0
2046
28 3-2
29 3-2
30 3-2
31 3-2
Ch 0
Ch 0
Ch 0
Ch 0
Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams
(Non-32 Mb/s Mode)
33
Zarlink Semiconductor Inc.
MT90870
Channel No. 2
Allocated Stream No.
C16o
Period1
2047
BCSTo0
0
BCSTo1
BCSTo2
Data Sheet
BCSTo3 16 Mb/s
8 Mb/s
4 Mb/s
2 Mb/s
1
2
3
Ch 1
Ch 0
Ch 0
Ch 0
5
6
7
Ch 1
Ch 0
Ch 0
Ch 0
Frame
Boundary
2048
4
1
8
9
10
11
Ch 1
Ch 0
Ch 0
Ch 0
2
12
13
14
15
Ch 1
Ch 0
Ch 0
Ch 0
3
16
17
18
19
Ch 1
Ch 0
Ch 0
Ch 0
4
20
21
22
23
Ch 1
Ch 0
Ch 0
Ch 0
5
24
25
26
27
Ch 1
Ch 0
Ch 0
Ch 0
6
28
29
30
31
Ch 1
Ch 0
Ch 0
Ch 0
7
0
1
2
3
Ch 2
Ch 1
Ch 0
Ch 0
8
4 3-3
5
6
7
Ch 2
Ch 1
Ch 0
Ch 0
9
8 3-4
9
10
11
Ch 2
Ch 1
Ch 0
Ch 0
10
12
13
14
15
Ch 2
Ch 1
Ch 0
Ch 0
11
16
17
18
19
Ch 2
Ch 1
Ch 0
Ch 0
12
20
21
22
23
Ch 2
Ch 1
Ch 0
Ch 0
13
24
25
26
27
Ch 2
Ch 1
Ch 0
Ch 0
14
28
29
30
31
Ch 2
Ch 1
Ch 0
Ch 0
15
0
1
2
3
Ch 3
Ch 1
Ch 0
Ch 0
16
4 3-3
5
6
7
Ch 3
Ch 1
Ch 0
Ch 0
17
8 3-4
9
10
11
Ch 3
Ch 1
Ch 0
Ch 0
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
2029
etc
etc
etc
etc
Ch 254
Ch 127
Ch 63
Ch 31
2030
28
29
30
31
Ch 254
Ch 127
Ch 63
Ch 31
2031
0
1
2
3
Ch 255
Ch 127
Ch 63
Ch 31
2032
4
5
6
7
Ch 255
Ch 127
Ch 63
Ch 31
2033
8
9
10
11
Ch 255
Ch 127
Ch 63
Ch 31
2034
12
13
14
15
Ch 255
Ch 127
Ch 63
Ch 31
2035
16
17
18
19
Ch 255
Ch 127
Ch 63
Ch 31
2036
20
21
22
23
Ch 255
Ch 127
Ch 63
Ch 31
2037
24
25
26
27
Ch 255
Ch 127
Ch 63
Ch 31
2038
28
29
30
31
Ch 255
Ch 127
Ch 63
Ch 31
2039
0
1
2
3
Ch 0
Ch 0
Ch 0
Ch 0
2040
4
5
6
7
Ch 0
Ch 0
Ch 0
Ch 0
2041
8
9
10
11
Ch 0
Ch 0
Ch 0
Ch 0
2042
12
13
14
15
Ch 0
Ch 0
Ch 0
Ch 0
3-3
Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams
(Non-32 Mb/s Mode) (continued)
34
Zarlink Semiconductor Inc.
MT90870
Channel No. 2
Allocated Stream No.
C16o
Period1
BCSTo0
BCSTo1
BCSTo2
Data Sheet
BCSTo3 16 Mb/s
8 Mb/s
4 Mb/s
2 Mb/s
2043
16
17
18
19
Ch 0
Ch 0
Ch 0
Ch 0
2044
20
21
22
23
Ch 0
Ch 0
Ch 0
Ch 0
2045
24
25
26
27
Ch 0
Ch 0
Ch 0
Ch 0
2046
28
29
30
31
Ch 0
Ch 0
Ch 0
Ch 0
2047
0
1
2
3
Ch 1
Ch 0
Ch 0
Ch 0
2048
4
5
6
7
Ch 1
Ch 0
Ch 0
Ch 0
Frame
1
8
9
10
11
Ch 1
Ch 0
Ch 0
Ch 0
Boundary
2
12
13
14
15
Ch 1
Ch 0
Ch 0
Ch 0
3
16
17
18
19
Ch 1
Ch 0
Ch 0
Ch 0
etc
etc
etc
etc
etc
etc
etc
etc
etc
Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams
(Non-32 Mb/s Mode) (continued)
Note 1: Clock Period count is referenced to Frame Boundary.
Note 2: The Channel Numbers presented relate to the data-rate selected for a specific stream.
Note 3-1 to 3-4: See Section 4.2.1 for examples of Channel Control Bit for streams of different data-rates.
35
Zarlink Semiconductor Inc.
MT90870
Data Sheet
FP8o
C8o
Channel 255 bits 7-0
Chan 63 Bit 1
1
0
Chan 63 Bit 0
Chan 0
Bit 7
CH 1
BSTo4
CH 0
BSTo6
CH 1
BSTo10
CH 1
BSTo14
CH 0
BSTo7
CH 1
BSTo11
CH 1
BSTo15
CH 1
BSTo5
CH 1
BSTo0
CH 1
BSTo2
CH 1
BSTo3
CH 0
BSTo1
CH 0
BSTo28
CH 0
BSTo30
CH 0
BSTo31
CH 0
BSTo29
CH 0
BSTo24
CH 0
BSTo26
CH 0
BSTo27
CH 0
BSTo25
CH 0
BSTo20
CH 0
BSTo22
CH 0
BSTo23
CH 0
BSTo21
CH 0
BSTo16
CH 0
BSTo18
CH 0
BSTo17
CH 0
BSTo12
CH 0
BSTo13
CH 0
BSTo8
CH 0
BSTo19
CH 0
BSTo6
CH 0
BSTo7
Chan 0
Bit 7
CH 0
BSTo14
CH 1
BSTo2
CH 1
BSTo3
Chan 0
Bit 7
CH 0
BSTo15
CH 1
BSTo30
CH 1
BSTo31
6
CH 0
BSTo10
CH 1
BSTo26
CH 1
BSTo27
CH 0
BSTo 7
CH 1
BSTo22
CH 1
BSTo23
7
CH 0
BSTo11
CH 0
BSTo9
CH 1
BST04
CH 1
BSTo18
CH 1
BSTo19
CH 1
BSTo5
CH 2
BSTo0
CH 1
BSTo14
CH 1
BSTo15
CH 1
BSTo1
CH 1
BSTo28
2
Channel 31 Bit 0
CH 1
BSTo10
CH 1
BSTo29
CH 1
BSTo24
3
CH 1
BSTo12
Chan 0 Bit 6
CH 1
BSTo25
CH 1
BSTo20
4
Chan 127 Chan 127 Chan 127 Chan 127
Bit 3
Bit 2
Bit 1
Bit 0
Channel 0 Bit 7
CH 1
BSTo21
5
CH 1
BSTo13
6
CH 1
BSTo8
7
Chan 0
Bit 4
CH 1
BSTo11
CH 1
BSTo5
CH 0
BSTo1
Chan 0 Bit 7
0
CH 1
BSTo0
BCSTo3
Chan 0
Bit 5
1
CH 0
BSTo7
BCSTo2
2
CH 1
BSTo2
BCSTo1
Chan 0
Bit 6
3
CH 1
BSTo3
BCSTo0
4
CH 1
BSTo16
Chan 31
Bit 0
5
CH 1
BSTo17
BSTo7
(2 Mb/s)
Chan 0
Bit 7
CH 1
BSTo12
Chan 63
Bit 0
6
CH 1
BSTo13
BSTo6
(4 Mb/s)
CH 1
BSTo4
Chan 127
Bit 0
CH 1
BSTo0
BSTo1
(8 Mb/s)
7
CH 1
BSTo8
0
CH 1
BSTo9
1
CH 1
BSTo9
Channel 0
BSTo0
(16 Mb/s)
One C16o period
Figure 14 - Backplane Port External High Impedance Control Bit Timing (Non-32 Mb/s mode)
Figure 14, Backplane Port External High Impedance Control Bit Timing (Non-32 Mb/s mode) shows the channel
control bits for BCSTo0, BCSTo1, BCSTo2 and BCSTo3 in one possible scenario which includes stream BSTo0 at
a data-rate of 16.384 Mb/s, BSTo1 at 8.192 Mb/s, BSTo6 at 4.096 Mb/s and BSTo7 at 2.048 Mb/s. All remaining
streams are operated at a data-rate of 16.384 Mb/s.
4.2.2
BORS Set LOW, 32 Mb/s Mode
The data (channel control bit) transmitted by BCSTo0-3 replicates the Backplane Output Enable Bit (BE) of the
Backplane Connection Memory, with a LOW state indicating the channel be set to High Impedance. See Section
12.4, Backplane Connection Memory Bit Definition for setting the Backplane Output Enable Bit (BE).
36
Zarlink Semiconductor Inc.
MT90870
Data Sheet
The BCSTo0-3 outputs transmit serial data (channel control bits) at 16.384 Mb/s, with each bit representing the perchannel high impedance state for specific streams. Four output streams are allocated to each control line as
follows:
•
•
•
•
•
(See also Pin Description)
BCSTo0 outputs the channel control bits for streams BSTo0, 4, 8, and 12.
BCSTo1 outputs the channel control bits for streams BSTo1, 5, 9, and 13.
BCSTo2 outputs the channel control bits for streams BSTo2, 6, 10, and 14.
BCSTo3 outputs the channel control bits for streams BSTo3, 7, 11, and 15.
The Channel Control Bit location, within a frame period, for each channel of the Backplane output streams is
presented in Table 4, BCSTo Allocation of Channel Control Bits to the Output Streams (32 Mb/s Mode)
The BCSTo0-3 outputs data at a constant data-rate of 16.384 Mb/s and all output streams, BSTo0-15, operate at a
data-rate of 32.768 Mb/s.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 4:
(1) The Channel Control Bit corresponding to Stream 0, Channel 0, BSTo0_Ch0, is transmitted on
BCSTo0 and is advanced, relative to the Frame Boundary, by six periods (clock period no. 2043) of
C16o.
(2) The Channel Control Bit corresponding to Stream 12, Channel 0, BSTo12_Ch0, is transmitted on
BCSTo0 in advance of the Frame Boundary by three periods (clock period no. 2046) of output clock,
C16o. Similarly, the Channel Control Bits for BSTo13_Ch0, BSTo14_Ch0 and BSTo15_Ch0 are
advanced relative to the Frame Boundary by three periods of C16o, on BCSTo1, BCSTo2 and BCSTo3,
respectively.
(3) For stream BSTo4 the value of the Channel Control Bit for Channel 510 will be transmitted during the
C16o clock period no. 2036 on BCSTo0.
(4) For stream BSTo5 the value of the Channel Control Bit for Channel 4 will be transmitted during the
C16o clock period no. 12 on BCSTo1.
Figure 15, Backplane Port External High Impedance Control Timing (32 Mb/s Mode) shows the channel control bits
for BCSTo0, BCSTo1, BCSTo2 and BCSTo3.
Channel No. 2
Allocated Stream No.
C16o
Period1
BCSTo0
BCSTo1
BCSTo2
BCSTo3
32 Mb/s
2039
0
1
2
3
Ch 511
2040
4
5
6
7
Ch 511
2041
8
9
10
11
Ch 511
2042
12
13
14
15
Ch 511
2043
0 3-1
1
2
3
Ch 0
2044
4
5
6
7
Ch 0
2045
8
9
10
11
Ch 0
2046
12 3-2
13 3-2
14 3-2
15 3-2
Ch 0
2047
0
1
2
3
Ch 1
Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams
(32 Mb/s Mode)
37
Zarlink Semiconductor Inc.
MT90870
Channel No. 2
Allocated Stream No.
C16o
Period1
BCSTo0
BCSTo1
BCSTo2
Data Sheet
BCSTo3
32 Mb/s
2048
4
5
6
7
Ch 1
Frame
1
8
9
10
11
Ch 1
Boundary
2
12
13
14
15
Ch 1
3
0
1
2
3
Ch 2
4
4
5
6
7
Ch 2
5
8
9
10
11
Ch 2
6
12
13
14
15
Ch 2
7
0
1
2
3
Ch 3
8
4
5
6
7
Ch 3
9
8
9
10
11
Ch 3
10
12
13
14
15
Ch 3
11
0
1
2
3
Ch 4
12
4
5 3-4
6
7
Ch 4
13
8
9
10
11
Ch 4
14
12
13
14
15
Ch 4
15
0
1
2
3
Ch 5
16
4
5
6
7
Ch 5
17
8
9
10
11
Ch 5
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
etc
2029
etc
etc
etc
etc
Ch 508
2030
12
13
14
15
Ch 508
2031
0
1
2
3
Ch 509
2032
4
5
6
7
Ch 509
2033
8
9
10
11
Ch 509
2034
12
13
14
15
Ch 509
2035
0
1
2
3
Ch 510
2036
43-3
5
6
7
Ch 510
2037
8
9
10
11
Ch 510
2038
12
13
14
15
Ch 510
2039
0
1
2
3
Ch 511
Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams
(32 Mb/s Mode) (continued)
38
Zarlink Semiconductor Inc.
MT90870
Channel No. 2
Allocated Stream No.
C16o
Period1
BCSTo0
BCSTo1
BCSTo2
Data Sheet
BCSTo3
32 Mb/s
2040
4
5
6
7
Ch 511
2041
8
9
10
11
Ch 511
2042
12
13
14
15
Ch 511
2043
0
1
2
3
Ch 0
2044
4
5
6
7
Ch 0
2045
8
9
10
11
Ch 0
2046
12
13
14
15
Ch 0
2047
0
1
2
3
Ch 1
2048
4
5
6
7
Ch 1
Frame
1
8
9
10
11
Ch 1
Boundary
2
12
13
14
15
Ch 1
3
0
1
2
3
Ch 2
etc
etc
etc
etc
etc
etc
Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams
(32 Mb/s Mode) (continued)
Note 1: Clock Period count is referenced to Frame Boundary.
Note 2: The Channel Numbers presented relate to the specific stream operating at a data-rate of 32.768 Mb/s.
Note 3-1 to 3-4: See Section 4.2.2 for examples of Channel Control Bits.
39
Zarlink Semiconductor Inc.
MT90870
Data Sheet
FP8o
CH 1
BSTo12
CH 0
BSTo14
CH 1
BSTo2
CH 1
BSTo6
CH 1
BSTo10
CH 1
BSTo14
CH 0
BSTo15
CH 1
BSTo3
CH 1
BSTo7
CH 1
BSTo11
CH 1
BSTo15
CH 1
BSTo5
CH 0
BSTo10
CH 0
BSTo11
CH 1
BSTo1
CH 0
BSTo6
CH 0
BSTo7
CH 0
BSTo13
CH 0
BSTo2
CH 0
BSTo3
CH 0
BSTo9
CH 511
BSTo14
CH 511
BSTo15
CH 0
BSTo5
CH 511
BSTo10
CH 511
BSTo11
CH 0
BSTo1
CH 3
BSTo6
CH 3
BSTo7
CH 511
BSTo13
CH 3
BSTo2
CH 3
BSTo3
CH 511
BSTo9
CH 2
BSTo14
CH 2
BSTo15
CH 3
BSTo5
CH 2
BSTo10
CH 2
BSTo11
CH 3
BSTo1
CH 2
BSTo6
CH 2
BSTo7
CH 2
BSTo13
CH 2
BSTo2
CH 2
BSTo3
CH 1
BSTo9
CH 1
BSTo14
CH 1
BSTo15
CH 2
BSTo5
CH 1
BSTo10
CH 1
BSTo11
CH 2
BSTo1
CH 1
BSTo6
CH 1
BSTo7
CH 1
BSTo13
CH 1
BSTo2
CH 1
BSTo3
BCSTo2
CH 1
BSTo9
CH 1
BSTo5
BCSTo1
CH 1
BSTo1
BCSTo0
CH 1
BSTo13
Channel 511
bits 7-0
CH 1
BSTo4
Channel 510
bits 7-0
CH 1
BSTo0
Channel 1
bits 7-0
CH 0
BSTo12
Channel 0
bits 7-0
CH 0
BSTo8
BSTo3
(32 Mb/s)
CH 0
BSTo4
Channel 511
bits 7-0
CH 0
BSTo0
Channel 510
bits 7-0
CH 511
BSTo12
Channel 1
bits 7-0
CH 511
BSTo8
Channel 0
bits 7-0
CH 3
BSTo4
BSTo2
(32 Mb/s)
CH 3
BSTo0
Channel 511
bits 7-0
CH 2
BSTo12
Channel 510
bits 7-0
CH 2
BSTo8
Channel 1
bits 7-0
CH 2
BSTo4
Channel 0
bits 7-0
CH 2
BSTo0
BSTo1
(32 Mb/s)
CH 1
BSTo12
Channel 511
bits 7-0
CH 1
BSTo8
Channel 510
bits 7-0
CH 1
BSTo4
Channel 1
bits 7-0
CH 1
BSTo0
Channel 0
bits 7-0
CH 1
BSTo9
BSTo0
(32 Mb/s)
CH 1
BSTo8
C8o
BCSTo3
One C16o cycle
Figure 15 - Backplane Port External High Impedance Control Timing (32 Mb/s Mode)
4.2.3
BORS Set HIGH
The Backplane Output Enable Bit (BE) of the Backplane Connection Memory has direct per-channel control on the
high-impedance state of the Backplane Output streams, BSTo0-31 (for Non-32 MB/s Mode) and BSTo0-15 (for
32 Mb/s Mode). Programming the BE bit to a LOW state will set the stream output of the MT90870 to High
Impedance for the duration of the channel period. See Section 12.4, Backplane Connection Memory Bit Definition,
for programming details.
The BCSTo0-3 outputs remain active.
40
Zarlink Semiconductor Inc.
MT90870
5.0
Data Sheet
Data Delay Through the Switching Paths
For all data rates, the received serial data is converted to parallel format and stored sequentially in the data
memory. Each data memory location corresponds to an input stream and channel number. To provide constant
delay and maintain frame integrity, the MT90870 utilizes four pages of data memory. Consecutive frames are
written in turn to each page of memory. Reading is controlled to allow a channel data written in frame N to be read
during frame N+3.
A constant delay of three frames is applied to all switching paths irrespective of data-rate or channel number. See
Figure 16.
FP8o
Frames N+1 and N+2
Frame N
Frame N+3
Frame N+4
Example showing Backplane to Backplane switching
BSTi0 CH CH CH CH
1
(16 Mb/s) 254 255 0
CH CH
254 255
CH
0
CH
1
CH CH
254 255
CH
0
CH
1
BSTo1 CH CH CH CH
1
(16 Mb/s) 254 255 0
CH CH
254 255
CH
0
CH
1
CH CH
254 255
CH
0
CH
1
Example showing Backplane to Local switching
BSTi0
(8 Mb/s)
CH
127
CH
0
CH
127
CH
0
CH
127
CH
0
LSTo1
(8 Mb/s)
CH
127
CH
0
CH
127
CH
0
CH
127
CH
0
LSTi0
(8 Mb/s)
CH
127
CH
0
CH
127
CH
0
CH
127
CH
0
BSTo1
(4 Mb/s)
CH
63
CH
0
CH
63
CH
0
CH
63
CH
0
LSTi0
(8 Mb/s)
CH
127
CH
0
CH
127
CH
0
CH
127
CH
0
LSTo1
(2 Mb/s)
CH
31
CH
0
CH
31
CH
0
CH
31
CH
0
Example showing Local to Backplane switching
Example showing Local to Local switching
Example showing 32 Mb/s mode, Backplane to Local switching
0
511
BSTi0 C C C C C C C C
(32 Mb/s) H H H H H H H H
C C C C
H H H H
C C C C
H H H H
C C C C C C C C
H H H H H H H H
LSTo1 CH CH CH CH
1
(16 Mb/s) 254 255 0
CH CH
254 255
CH
0
CH CH
254 255
CH
1
CH
0
CH
1
Figure 16 - Constant Switch Delay: Examples of Different Stream Rates and Routing
41
Zarlink Semiconductor Inc.
MT90870
6.0
Data Sheet
Connection Memory Description
The MT90870 incorporates two connection memories, Local Connection Memory and Backplane Connection
Memory.
6.1
Local Connection Memory
The Local Connection Memory (LCM) is 16-bit wide with 4,096 memory locations to support the Local output port.
The most significant bit of each word, bit [15], selects the source stream from either the Backplane or the Local port
and determines the Backplane-to-Local or Local-to-Local data routing. Bits [14:13] select the control modes of the
Local output streams, namely the per-channel message and the per-channel high impedance output control modes.
In Connection Mode (Bit14 = LOW), Bits [12:0] select the source stream and channel number as detailed in Table 5.
In Message Mode (Bit14 = HIGH), Bits [12:8] are unused and Bits [7:0] contain the message byte to be transmitted.
The Control Register bits MS2, MS1, and MS0 must be set to 000, respectively, to select the Local Connection
Memory for the Write and Read operations via the microprocessor port. See Section 7.0, Microprocessor Port, and
Section 13.1, Control Register (CR) for details on microprocessor port access.
Source Stream Bit Rate
Source Stream No.
Source Channel No.
2 Mb/s
[12:8]
legal values:
0 - 31 (Backplane)
0 - 15 (Local)
[7:0]
legal values 0 - 31
4 Mb/s
[12:8]
legal values:
0 - 31 (Backplane)
0 - 15 (Local)
[7:0]
legal values 0 - 63
8 Mb/s
[12:8]
legal values:
0 - 31 (Backplane)
0 - 15 (Local)
[7:0]
legal values 0 - 127
16 Mb/s
[12:8]
legal values:
0 - 31 (Backplane)
0 - 15 (Local)
[7:0]
legal values 0 - 255
32 Mb/s
(Backplane streams only)
[12:9]
legal values: 0 - 15
[8:0]
legal values 0 - 511
Table 5 - Local and Backplane Connection Memory Configuration
6.2
Backplane Connection Memory
The Backplane Connection Memory (BCM) is 16-bit wide with 8,192 memory locations to support the Backplane
output port. The most significant bit of each word, bit [15], selects the source stream from either the Backplane or
the Local port and determines the Local-to-Backplane or Backplane-to-Backplane data routing. Bits [14:13] select
the control modes of the Backplane output streams, namely the per-channel Message Mode and the per-channel
high impedance output control mode. In Connection Mode (Bit14 = LOW), Bits [12:0] select the source stream and
channel number as detailed in Table 5. In Message Mode (Bit14 = HIGH), Bits [12:8] are unused and Bits [7:0]
contain the message byte to be transmitted.
42
Zarlink Semiconductor Inc.
MT90870
Data Sheet
The Control Register bits MS2, MS1, and MS0 must be set to 001, respectively, to select the Backplane Connection
Memory for the Write and Read operations via the microprocessor port. See Section 7.0, Microprocessor Port, and
Section 13.1, Control Register (CR) for details on microprocessor port access.
6.3
Connection Memory Block Programming
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after power
up. When the Memory Block Programming mode is enabled, the contents of the Block Programming Register
(BPR) will be loaded into the connection memories. See Table 16 and Table 17 for details of the Control Register
and Block Programming Register values, respectively.
6.3.1
•
•
Memory Block Programming Procedure
Set the MBP bit in the Control Register from LOW to HIGH.
Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD2-0, of the Block Programming Register, will be loaded into Bit 15, Bit 14 and Bit 13, respectively. of
the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 6.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LBPD2
LBPD1
LBPD0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 6 - Local Connection Memory in Block Programming Mode
The Backplane Block Programming data bits, BBPD2-0, of the Block Programming Register, will be loaded into
Bit 15, Bit 14 and Bit 13, respectively, of the Backplane Connection Memory. The remaining bit positions are loaded
with zeros as shown in Table 7.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BBPD2
BBPD1
BBPD0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 7 - Backplane Connection Memory in Block Programming Mode
The Block Programming Register bit, BPE will be automatically reset LOW within 125 us, to indicate completion of
memory programming. The Block Programming Mode can be terminated at any time prior to completion by setting
the BPE bit of the Block Programming Register or the MBP bit of the Control Register to LOW.
Note the default values (LOW) of LBPD2-0 and BBPD2-0 of the Block Programming Register, following a device
reset, may be used. These settings shall set all output channels to High, or High-Impedance, in accordance with the
LORS and BORS pin conditions, see Pin Description for further details. The Local Connection Memory shall be
configured to select data from Channel 0 of Backplane input Stream 0 (BSTi0), and the Backplane Connection
Memory shall be configured to select data from Channel 0 of Local input Stream 0 (LSTi0). Alternative conditions
may be established by programming bits LBPD2-0 and BBPD2-0 of the Block Programming Register at the time of
setting Bit BPE to HIGH. See Section 12.3, Local Connection Memory Bit Definition, Section 12.4, Backplane
Connection Memory Bit Definition, and Section 13.2, Block Programming Register (BPR).
7.0
Microprocessor Port
The MT90870 supports non-multiplexed Motorola microprocessors. The microprocessor port consists of 16-bit
parallel data bus (D0-15), 15-bit address bus (A0-14) and four control signals (CS, DS, R/W and DTA). The data
bus provides access to the internal registers, the Backplane Connection and Data memories, and the Local
Connection and Data memories. Each Backplane memory has 8,192 locations and each Local memory has 4,096
43
Zarlink Semiconductor Inc.
MT90870
Data Sheet
locations. See Table 8, Address Map for Data and Connection Memory Locations (A14=1), for the address
mapping.
Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only
be read (but not written) from the microprocessor port.
To prevent the bus ’hanging’ in the event of the MT90870 not receiving a master clock, the microprocessor port
shall complete the DTA handshake when accessed but any data read from the bus will be invalid.
There must be a minimum of 30 ns between CPU accesses, to allow the MT90869 device to recognize the
accesses as separate (i.e. a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of
CS and/or DS to initiate the next access).
8.0
Device Power-up, Initialization and Reset
8.1
Power-Up Sequence
The recommended power-up sequence is for the VDD_IO supply (nominally +3.3 V) to be established before the
power-up of the VDD_PLL and VDD_CORE supplies (nominally +1.8 V). The VDD_PLL and VDD_CORE supplies
may be powered up simultaneously, but neither should 'lead' the VDD_IO supply by more than 0.3 V.
All supplies may be powered-down simultaneously.
8.2
Initialization
Upon power up, the MT90870 should be initialized by applying the following sequence:
8.3
1
Ensure the TRST pin is permanently LOW to disable the JTAG TAP controller.
2
Set ODE pin to LOW. This configures the LCSTo0-1 output signals to LOW (i.e., to set
optional external output buffers to high impedance), and sets the LSTo0-15 outputs to high
or high impedance, dependent on the LORS input value, and sets the BCSTo0-3 output
signals to LOW (i.e., to set optional external output buffers to high impedance), and sets the
BSTo0-31 outputs to high or high impedance, dependent on BORS input value. Refer to
Pin Description for details of the LORS and BORS pins.
3
Reset the device by pulsing the RESET pin to zero for at least two cycles of the input
clock, C8i.
4
Use the Block Programming Mode to initialize the Local and the Backplane Connection
Memories. Refer to Section 6.3, Connection Memory Block Programming.
5
Set ODE pin to HIGH after the connection memories are programmed to ensure that bus
contention will not occur at the serial stream outputs.
Reset
The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the MT90870. It
is synchronized to the internal clock and remains active for 50 us following release (set HIGH) of the external
RESET to allow time for the PLL to fully settle. During the reset period, depending on the state of input pins LORS
and BORS, the output streams LSTo0-15 and BSTo0-31 are set to high or high impedance, and all internal
registers and counters are reset to the default state.
The RESET pin must remain low for two input clock cycles (C8i) to guarantee a synchronized reset release.
44
Zarlink Semiconductor Inc.
MT90870
Data Sheet
When a RESET is applied to the MT90870, the CS line is inhibited and the DTA line may become active through
simultaneous microport activity. External gating of the DTA line with CS is recommended to avoid bus conflict in
applications incorporating multiple devices with individual reset conditions.
9.0
Bit Error Rate Test
Independent Bit Error Rate (BER) test mechanisms are provided for the Local and Backplane ports. In both ports
there is a BER transmitter and a BER receiver. The transmitter and receiver are each independently controlled to
allow either looped back, or uni-directional testing. The transmitter generates a 215-1 or 223-1 Pseudo Random
Binary Sequence (PRBS), which may be allocated to a specific stream and a number of channels. This is defined
by a stream number, a start channel number, and the number of consecutive channels following the start channel.
The stream, channel number and the number of consecutive channels following the start channel are similarly
allocated for the receiver and detection of the PRBS. Examples of a channel sequence are presented in Figure 17.
When enabled, the receiver attempts to lock to the PRBS on the incoming bit stream. Once lock is achieved, by
detection of a seed value, a bit by bit comparison takes place and each error shall increment a 16-bit counter. A
counter ’roll-over’ shall occur in the event of an error count in excess of 65535.
The BER operations are controlled by registers as follows (refer to Section 13.3, Bit Error Rate Test Control
Register (BERCR) for overall control, Section 13.10, Local Bit Error Rate (BER) Registers and Section 13.11,
Backplane Bit Error Rate (BER) Registers for register programming details):
•
•
•
•
•
•
BER Control Register (BERCR) - Independently enables BER transmission and receive testing for
Backplane and Local ports.
Local and Backplane BER Start Send Registers (LBSSR and BBSSR) - Defines the output stream and start
channel for BER transmission.
Local and Backplane Transmit BER Length Registers (LTXBLR and BTXBLR) - Defines, for transmit
stream, how many consecutive channels to follow the start channel.
Local and Backplane BER Start Receive Registers (LBSR and BBSR) - Define the input stream and channel
from where the BER sequence will start to be compared.
Local and Backplane Receive BER Length Registers (LRXBLR and BRXBLR) - Defines, for the receive
stream, how many consecutive channels follow the start channel.
Local and Backplane BER Count Registers (LBCR and BBCR) - Contain the number of counted errors.
The registers listed completely define the transmit stream and channels. When BER transmission is enabled for
these channels, the source bits and the message mode bits, LSRC and LMM in the Local Connection Memory, and
BSRC and BMM in the Backplane Connection Memory, are ignored. The enable bits (LE and BE) of the respective
connection memories should be set to HIGH to enable the outputs for the selected channels.
45
Zarlink Semiconductor Inc.
MT90870
Data Sheet
frame boundary
FP8i
Start Ch=0
Length=256
0
1
2
3
......
.....
.....
.....
254
255
0
1
2
Start Ch=0
Length=3
0
1
2
3
......
.....
.....
.....
254
255
0
1
2
Start Ch=254
Length=4
0
1
2
3
......
.....
.....
.....
254
255
0
1
2
Channels containing PRBS sequence
Channels containing data (traffic)
Note: Length = Start Chan. + No. of Consecutive channels
Once Started BER transmission continues until stopped by the BER control register:
FP
stream
Figure 17 - Examples of BER transmission channels
10.0
Memory Built-In-Self-Test (BIST) Mode
As operation of the memory BIST will corrupt existing data, this test must only be performed when the device is
placed “out-of-service” or isolated from live traffic.
The memory BIST mode is enabled through the microprocessor port (Section 13.14, Memory BIST Register).
Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The
memory test result is monitored through the Memory BIST Register when controlled via the microprocessor
interface.
11.0
JTAG Port
The MT90870 JTAG interface conforms to the Boundary-Scan IEEE 1149.1 standard. The operation of the
boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. JTAG is intended to be
used during the development cycle. The JTAG interface is operational when the MT90870 Core (VDD_core) is
powered at typical voltage levels.
11.1
Test Access Port (TAP)
The Test Access Port (TAP) consists of four input pins and one output pin described as follows:
•
•
Test Clock Input (TCK)
TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the
shifting of test data into or out of the Boundary-Scan Registers cells, under the control of the TAP
Controller in Boundary-Scan Mode.
Test Mode Select Input (TMS)
The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS
signals are sampled at the rising edge of the TCK pulse. This pin in internally pulled to V DD_IO when not
driven from an external source.
46
Zarlink Semiconductor Inc.
MT90870
•
•
•
Data Sheet
Test Data Input (TDi)
Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port
is connected either to the Instruction Register or to a Test Data Register. Both registers are described in
a Section 11.2, TAP Registers. The applied input data is sampled at the rising edge of TCK pulses. This
pin is internally pulled to V DD_IO when not driven from an external source.
Test Data Output (TDo)
Depending on the previously applied sequence to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on
the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo
output is set to a high impedance state.
Test Reset (TRST)
TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled to VDD_IO
when not driven from an external source.
11.2
TAP Registers
The MT90870 uses the public instructions defined in the IEEE 1149.1 standard with the provision of an Instruction
Register and three Test Data Registers.
11.2.1
Test Instruction Register
The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the Instruction
Register from the TDi pin when the TAP Controller is in the shift-IR state. Instructions are subsequently decoded to
achieve two basic functions: to select the Test Data Register to operate while the instruction is current, and to
define the serial Test Data Register path to shift data between TDi and TDo during data register scanning.
11.2.2
Test Data Registers
11.2.2.1
The Boundary-Scan Register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the
boundary of the MT90870 core logic.
11.2.2.2
The Bypass Register
The Bypass register is a single stage shift register to provide a one-bit path from TDi to TDo.
11.2.2.3
The Device Identification Register
The JTAG device ID for the MT90870 is 0087014BH.
Version, Bits <31:28>:
0000
Part No., Bits <27:12>:
0000 1000 0111 0000
Manufacturer ID, Bits <11:1>: 0001 0100 101
Header, Bit <0> (LSB):
11.3
1
Boundary Scan Description Language (BSDL) File
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.
47
Zarlink Semiconductor Inc.
MT90870
12.0
Data Sheet
Memory Address Mappings
Address Bit
A14
Description
Selects memory or register access
A13-A9
Stream address (0-31)
A8-A0
Channel address (0-511)
Notes:
1. Bit A14 must be high for accessing to data and connection memory positions. Bit A14 must
be low for accessing registers.
2. Streams 0 to 15 are used when the Backplane serial streams are at 32.768 Mb/s.
3. Channels 0 to 31 are used when serial stream is at 2.048 Mb/s.
4. Channels 0 to 63 are used when serial stream is at 4.096 Mb/s.
5. Channels 0 to 127 are used when serial stream is at 8.192 Mb/s.
6. Channels 0 to 255 are used when serial stream is at 16.384 Mb/s.
7. Channels 0 to 511 are used when serial stream is at 32.768 Mb/s.
Table 8 - Address Map for Data and Connection Memory Locations (A14=1)
The device contains two data memory blocks, one for received Backplane data and one for received Local data. For
all data rates the received data is converted to parallel format by internal serial to parallel converters and stored
sequentially in the relevant data memory.
12.1
Backplane Data Memory Bit Definition
The 8-bit Backplane Data Memory (BDM) has 8,192 positions. The locations are associated with the Backplane
input streams and channels. The address bits (A13:0) of the microprocessor define the addresses of the streams
and the channels. The BDM is configured as follows:
Bit
Name
15-8
Reserved
7-0
BDM
Description
Set to a default value of 0
Backplane Data Memory
Backplane Input Channel Data
Table 9 - Backplane Data Memory (BDM) Bits
12.2
Local Data Memory Bit Definition
The 8-bit Local Data Memory (LDM) has 4,096 positions. The locations are associated with the Local input streams
and channels. The address bits of the microprocessor define the addresses of the streams and the channels. The
LDM is configured as follows:
Bit
Name
Description
15-8
Reserved
Set to a default value of 0
7-0
LDM
Local Data Memory
Local Input Channel Data
Table 10 - Local Data Memory (LDM) Bits
48
Zarlink Semiconductor Inc.
MT90870
12.3
Data Sheet
Local Connection Memory Bit Definition
The Local Connection Memory (LCM) has 4,096 addresses of 16-bit words. Each address, accessed through bits
A13-A0 of the microprocessor port, is allocated to an individual Local output stream and channel. The bit definition
for each 16-bit word is presented in Table 11 for Local-to-Local and Backplane (Non-32 MB/s Mode)-to-Local
connections, and in Table 12, for Local-to-Local and Backplane(32 Mb/s Mode)-to-Local connections. Bit LSRC
selects the switch configuration for Backplane-to-Local or Local-to-Local. When the per-channel Message Mode is
selected (LMM = HIGH), the lower byte of the LCM word (LCAB7-0) will be transmitted as data on the output
stream (LSTo0-15) in place of data defined by the Source Control, Stream and Channel Address bits.
.
Bit
Name
Description
15
LSRC
Source Control Bit
When LOW, the source is from the Backplane input port (Backplane Data Memory).
When HIGH, the source is from the Local input port (Local Data Memory).
Ignored when LMM is set HIGH.
14
LMM
Local Message Mode Bit
When LOW, the channel is in Connection Mode.
When HIGH, the channel is in Message Mode.
13
LE
12-8
LSAB4-0
Source Stream Address Bits
The binary value of these 5 bits represents the input stream number.
Ignored when LMM is set HIGH.
7-0
LCAB7-0
Source Channel Address Bits
The binary value of these 8 bits represents the input channel number when LMM is set
LOW. Transmitted as data when LMM is set HIGH.
Local Output Enable Bit
When LOW the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the LORS pin. When HIGH the channel is active.
Table 11 - LCM Bits for Local-to-Local and Backplane (Non-32 Mb/s Mode)-to-Local Switching
Bit
Name
Description
15
LSRC
Source Control Bit.
When LOW, the source is from the Backplane input port (Backplane Data Memory).
When HIGH, the source is from the Local input port (Local Data Memory).
Ignored when LMM is set HIGH.
14
LMM
Local Message Mode Bit
When LOW, the channel is in Connection Mode.
When HIGH, the channel is in Message Mode.
13
LE
Local Output Enable Bit
When LOW, the channel may be high impedance, either at the device output or set by an
external buffer, dependent upon the LORS pin. When HIGH, the channel is active.
12-9
LSAB3-0
Source Stream Address Bits.
The binary value of these 4 bits represents the input stream number.
Ignored when LMM is set HIGH.
8-0
LCAB8-0
Channel Address Bits.
The binary value of these 9 bits represents the input channel number, when LMM is LOW.
Bits LCAB7-0 transmitted as data when LMM is set HIGH.
Table 12 - LCM Bits for Backplane(32 Mb/s Mode)-to-Local Switching
49
Zarlink Semiconductor Inc.
MT90870
12.4
Data Sheet
Backplane Connection Memory Bit Definition
The Backplane Connection Memory (BCM) has 8,192 addresses of 16-bit words. Each address, accessed through
bits A13-A0 of the microprocessor port, is allocated to an individual Backplane output stream and channel. The bit
definition for each 16-bit word is presented in Table 13 for Local-to- Backplane (Non-32 Mb/s Mode) and
Backplane-to-Backplane (Non-32 Mb/s Mode) connections, and in Table 14, for Local-to-Backplane (32 Mb/s
Mode) and Backplane-to-Backplane (32 Mb/s Mode) connections.
Bit BSRC selects the switch configuration for Local-to-Backplane or Backplane-to-Backplane. When the perchannel Message Mode is selected (BMM = HIGH), the lower byte of the BCM word (BCAB7-0) will be transmitted
as data on the output stream (BSTo0-31) in place of data defined by the Source Control, Stream Address and
Channel Address bits.
Bit
Name
Description
15
BSRC
Backplane Source Control Bit.
When LOW, the source is from the Local input port (Local Data Memory). When HIGH, the
source is from the Backplane input port (Backplane Data Memory).
Ignored when BMM is set HIGH.
14
BMM
Backplane Message Mode Bit.
When LOW, the channel is in Connection Mode. When HIGH, the channel is in Message
Mode.
13
BE
Backplane Output Enable Bit.
When LOW the channel may be high impedance, either at the device output or set by an
external buffer, dependent upon the BORS pin. When HIGH the channel is active.
12-8
BSAB4-0
Backplane Source Stream Address Bits.
The binary value of these 5 bits represents the input stream number. BSAB4-0 are ignored
when BMM is set HIGH in Message Mode.
7-0
BCAB7-0
Source Channel Address Bits.
The binary value of these 8 bits represents the input channel number when BMM is set
LOW. BCAB7-0 are transmitted as data when BMM is set HIGH in Message Mode.
Table 13 - BCM Bits for Local-to-Backplane and Backplane-to-Backplane Switching
(Non-32 Mb/s Mode)
Bit
Name
Description
15
BSRC
Backplane Source Control Bit.
When LOW, the source is from the Local input port (Local Data Memory).
When HIGH, the source is from the Backplane input port (Backplane Data Memory).
BSRC is ignored when BMM is set HIGH in Message Mode.
14
BMM
Backplane Message Mode Bit.
When LOW, the channel is in Connection Mode.
When HIGH, the channel is in Message Mode.
13
BE
12-9
BSAB3-0
Backplane Output Enable Bit.
When this bit is low the channel may be high impedance, either at the device output or set
by an external buffer, dependent upon the BORS pin. When the bit is high the channel is
active.
Backplane Source Stream Address Bits.
The binary value of these 4 bits represents the input stream number.
BSAB3-0 are ignored when BMM is set HIGH in Message Mode.
50
Zarlink Semiconductor Inc.
MT90870
Bit
Name
8-0
BCAB8-0
Description
Source Channel Address Bits.
The binary value of these 9 bits represents the input channel number, when BMM is LOW.
Bits BCAB7-0 transmitted as data when BMM is set HIGH in Message Mode.
Table 14 - BCM Bits for Backplane-to-Backplane Switching (32 Mb/s mode)
12.5
Data Sheet
Internal Register Mappings
A14 - A0
Register
0000H
Control Register, CR
0001H
Block Programming Register, BPR
0002H
BER Control Register, BERCR
0003H - 0012H
Local Input Channel Delay Register 0, LCDR0 - Register 15, LCDR15
0023H - 0032H
Local Input Bit Delay Register 0, LIDR0 - Register 15, LIDR15
0043H - 0062H
Backplane Input Channel Delay Register 0, BCDR0 - Register 31, BCDR31
0063H - 0082H
Backplane Input Bit Delay Register 0, BIDR0 - Register 31, BIDR31
0083H - 0092H
Local Output Advancement Register 0, LOAR0 - Register 15, LOAR15
00A3H - 00C2H
Backplane Output Advancement Register 0, BOAR0 - Register 31, BOAR31
00C3H
Local BER Start Send Register, LBSSR
00C4H
Local Transmit BER Length Register, LTXBLR
00C5H
Local Receive BER Length Register, LRXBLR
00C6H
Local BER Start Receive Register, LBSRR
00C7H
Local BER Count Register, LBCR
00C8H
Backplane BER Start Send Register, BBSSR
00C9H
Backplane Transmit BER Length Register, BTXBLR
00CAH
Backplane Receive BER Length Register, BRXBLR
00CBH
Backplane BER Start Receive Register, BBSRR
00CCH
Backplane BER Count Register, BBCR
00CDH - 00DCH
Local Input Bit rate Register 0, LIBRR0 - Register 15, LIBRR15
00EDH - 00FCH
Local Output Bit rate Register 0, LOBRR0 - Register 15, LOBRR15
010DH - 012CH
Backplane Input Bit rate Register 0, BIBRR0 - Register 31, BIBRR31
012DH - 014CH
Backplane Output Bit rate Register 0, BOBRR0 - Register 31, BOBRR31
014DH
Memory BIST Register, MBISTR
3FFFH
Revision control register, RCR
Table 15 - Address Map for Register (A14 = 0)
51
Zarlink Semiconductor Inc.
MT90870
13.0
Data Sheet
Detailed Register Description
This section describes the registers that are used in the device.
13.1
Control Register (CR)
Address 0000h.
The control register defines which memory is to be accessed. It initiates the memory block programming mode and
selects the Backplane data rate mode. The Control Register (CR) is configured as follows:
Bit
Name
Reset
Description
15-9
Reserved
0
Reserved.
8
FPW
0
Frame Pulse Width
When LOW, an input frame pulse width of 122 ns shall be applied to FP8i. When
HIGH, an input frame pulse width of 244 ns shall be applied to FP8i.
7
MODE32
0
32 MHz Mode
When LOW, Backplane streams (BSTi0-31 and BSTo0-31) may be individually
programmed for data-rates of 2, 4, 8, or 16 Mb/s. When HIGH, the Backplane
streams (BSTi0-15 and BSTo0-15) operate in 32Mb/s mode.
6
C8IPOL
0
8 MHz Input Clock Polarity
The input frame boundary MUST be aligned to the C8i clock rising edge. This bit,
C8IPOL, MUST be set HIGH to achieve correct frame boundary alignment. If this
bit is LOW, the input frame boundary alignment will not work correctly.
5
COPOL
0
Output Clock Polarity
When set LOW, the output clock is the same polarity as the input clock. When set
HIGH, the output clock is inverted. This applies to both 8 MHz (C8o)and 16 MHz
(C16o) output clocks.
4
MBP
0
Memory Block Programming
When LOW, the memory block programming mode is disabled. When HIGH, the
connection memory block programming mode is ready to program the Local
Connection Memory (LCM), and the Backplane Connection Memory (BCM).
3
OSB
0
Output Stand By
This bit enables the BSTo0 - 31 and the LSTo0 - 15 serial outputs.
ODE Pin
OSB bit
BSTo0 - 31, LSTo0 - 15
0
1
1
X
0
1
Disable
Disable
Enable
Output Control with ODE pin and OSB bit
When set LOW, the BSTo0-31 and LSTo0-15 are driven high or high impedance,
dependent on the BORS and LORS pin settings respectively, and BCSTo0-3 and
LCSTo0-1 are driven low.
When set HIGH, the BSTo0-31, LSTo0-15, BCSTo0-3 and LCSTo0-1 are enabled.
Table 16 - Control Register Bits
52
Zarlink Semiconductor Inc.
MT90870
Bit
Name
Reset
2-0
MS(2:0)
0
Data Sheet
Description
Memory Select Bits.
These three bits select the connection or data memory for subsequent micro-port
memory access operations:
000, Local Connection Memory (LCM) is selected for Read or Write operations.
001, Backplane Connection Memory (BCM) is selected for Read or Write
operations. 010, Local Data Memory is selected for Read-only operation. 011,
Backplane Data Memory is selected for Read-only operation.
Table 16 - Control Register Bits (continued)
Frame Boundary
(a) Frame Pulse Width = 122 ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 1
C8i
FP8i
(b) Frame Pulse Width = 244 ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 1
C8i
FP8i
Figure 18 - Frame Boundary Conditions, ST- BUS Operation
53
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Frame Boundary
(a) Pulse Width = 122 ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 1
C8i
FP8i
(b) Pulse Width = 244 ns,
Control Register B it8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 1
C8i
FP8i
Figure 19 - Frame Boundary Conditions, GCI - BUS Operation
13.2
Block Programming Register (BPR)
Address 0001h.
The block programming register stores the bit patterns to be loaded into the connection memories when the
Memory Block Programming feature is enabled. The BPE, LBPD2-0 and BBPD2-0 bits in the BPR register must
be defined in the same write operation.
The BPE bit is set HIGH, to commence the block programming operation. Programming is completed in one frame
period and may be instigated at any time within a frame.The BPE bit returns to LOW to indicate the block
programming function has completed.
When BPE is HIGH, no other bits of the BPR register must be changed for at least a single frame period, except to
abort the programming operation. The programming operation may be aborted by setting either BPE to LOW, or the
Control Register bit, MBP, to LOW.
The BPR register is configured as follows.
.
54
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Bit
Name
Reset
Description
15-7
Unused
0
Set LOW.
6-4
BBPD(2:0)
0
Backplane Block Programming Data.
These bits refer to the value loaded into the Backplane Connection Memory
(BCM) when the Memory Block Programming feature is activated. When the
MBP bit in the Control Register (CR) is set HIGH and the BPE is set HIGH, the
contents of Bits BBPD2-0 are loaded into Bits 15-13, respectively, of the BCM.
Bits 12-0 of the BCM are set LOW.
3-1
LBPD(2:0)
0
Local block Programming Data.
These bits refer to the value loaded into the Local Connection Memory (LCM),
when the Memory Block Programming feature is activated. When the MBP bit in
the Control Register is set HIGH and the BPE is set HIGH, the contents of Bits
LBPD2-0 are loaded into Bits 15-13, respectively, of the LCM.
Bits 12-0 of the LCM are set LOW.
0
BPE
0
Block Programming Enable.
A LOW to HIGH transition of this bit enables the Memory Block Programming
function. A LOW will be returned after 125 us, upon completion of programming.
Set LOW to abort the programming operation.
Table 17 - Block Programming Register Bits
13.3
Bit Error Rate Test Control Register (BERCR)
Address 0002h.
The BER control register controls Backplane and Local port BER testing. It independently enables and disables
transmission and reception. It is configured as follows:
Description
Bit
Name
RESET
15-12
Reserved
0
Reserved.
11
LOCKB
0
Backplane Lock (READ ONLY).
This bit is automatically set HIGH when the receiver has locked to the
incoming data sequence. The bit is reset by a LOW to HIGH transition on
SBERRXB.
10
PRSTB
0
PBER Reset for Backplane.
A LOW to HIGH transition initializes the Backplane BER generator to the
seed value.
9
CBERB
0
Clear Bit Error Rate Register for Backplane.
A LOW to HIGH transition in this bit resets the Backplane internal bit error
counter and the Backplane bit error (BBERR) register to zero.
Table 18 - Bit Error Rate Test Control Register (BERCR) Bits
55
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Bit
Name
RESET
Description
8
SBERRXB
0
Start Bit Error Rate Receiver for Backplane.
A LOW to HIGH transition enables the Backplane BER receiver. The receiver
monitors incoming data for reception of the seed value. When detected, the
LOCK state is indicated (LOCKB) and the receiver compares the incoming
bits with the reference generator for bit equality and increments the
Backplane Bit error Register (BBCR) on each failure. When set LOW, bit
comparison is disabled and the error count is frozen. The error count is stored
in the Backplane Bit Error Register (BBCR).
7
SBERTXB
0
Start Bit Error Rate Transmitter for Backplane.
A LOW to HIGH transition starts the BER transmission. When set LOW,
transmission is disabled.
6
PRBSB
0
BER Mode Select for Backplane.
When set HIGH, a PRBS sequence of length 223-1 is selected for the
Backplane port. When set LOW, a PRBS sequence of length 215-1 is
selected for the Backplane port.
5
LOCKL
0
Local Lock (READ ONLY).
This bit is automatically set HIGH when the receiver has locked to the
incoming data sequence. The bit is reset by a LOW to HIGH transition on
SBERRXL
4
PRSTL
0
PBER Reset for Local.
A LOW to HIGH transition initializes the Local BER generator to the seed
value.
3
CBERL
0
Clear Bit Error Rate Register for Local.
A LOW to HIGH transition resets the Local internal bit error counter and the
Local bit error (LBERR) register to zero.
2
SBERRXL
0
Start Bit Error Rate Receiver for Local.
A LOW to HIGH transition enables the Local BER receiver. The receiver
monitors incoming data for reception of the seed value. When detected, the
LOCK state is indicated (LOCKL) and the receiver compares the incoming
bits with the reference generator for bit equality and increments the Local Bit
error Register (LBCR) on each failure. When set LOW, bit comparison is
disabled and the error count is frozen. The error count is stored in the Local
Bit Error Register (LBCR).
1
SBERTXL
0
Start Bit Error Rate Transmitter for Local.
A LOW to HIGH transition enables the Local BER transmission. When set
LOW, transmission is disabled.
0
PRBSL
0
BER Mode Select for Local.
When set HIGH, a PRBS sequence of length 223-1 is selected for the Local
port. When set LOW, a PRBS sequence of length 215-1 is selected for the
Local port.
Table 18 - Bit Error Rate Test Control Register (BERCR) Bits (continued)
56
Zarlink Semiconductor Inc.
MT90870
13.4
Data Sheet
Local Input Channel Delay Registers (LCDR0 to LCDR15)
Address 0003h to 0012h.
Sixteen Local input channel delay registers (LCDR0 to LCDR15) allow users to program the input channel delay for
the Local input data streams LSTi0-15. The possible adjustment is 255 channels and the LCDR0 to LCDR15
registers are configured as follows:
:
LCDRn Bit
(where n = 0 to
15)
Name
Reset
Description
15-8
Reserved
0
Reserved
7-0
LCD(7:0)
0
Local Channel Delay Register
The binary value of these bits refers to the channel delay value
for the Local input stream.
Table 19 - Local Channel Delay Register (LCDRn) Bits
13.4.1
Local Channel Delay Bits 7-0 (LCD7 - LCD0)
These eight bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data
from the Local stream input pins. The input channel delay can be set to 255 (16 Mb/s streams), 127 (8 Mb/s
streams), 63 (4 Mb/s streams) or 31 (2 Mb/s streams) from the frame boundary.
Corresponding
Delay Bits
Input Stream
Channel Delay
LCD7-LCD0
0 Channel (Default)
0000 0000
1 Channel
0000 0001
2 Channels
0000 0010
3 Channels
0000 0011
4 Channels
0000 0100
5 Channels
0000 0101
...
...
...
...
253 Channels
1111 1101
254 Channels
1111 1110
255 Channels
1111 1111
Table 20 - Local Input Channel Delay Programming Table
57
Zarlink Semiconductor Inc.
MT90870
13.5
Data Sheet
Local Input Bit Delay Registers (LIDR0 to LIDR15)
Address 0023h to 0032h.
Sixteen Local input delay registers (LIDR0 to LIDR15) allow users to program the input bit delay for the Local input
data streams LSTi0-15. The possible adjustment is up to 7 3/4 of the data rate, advancing forward with a resolution
of 1/4 of the data rate. The data rate can be either 2 Mb/s, 4 Mb/s, 8 Mb/s or 16 Mb/s.
The LIDR0 to LIDR15 registers are configured as follows:
LIDRn Bit
(where n = 0
to 15)
Name
Reset
Description
15-5
Reserved
0
Reserved
4-0
LIDn(4:0)
0
Local Input Bit Delay Register
The binary value of these bits refers to the input bit delay value
for the Local input stream
Table 21 - Local Channel Delay Register (LIDRn) Bits
13.5.1
Local Input Delay Bits 4-0 (LID4 - LID0)
These five bits define the delay from the bit boundary that the receiver uses to sample each input. Input bit delay
adjustment can range up to 73/4 bit periods forward, with resolution of 1/4 bit period.
This can be described as: LIDn(4:0) = (no. of bits delay) / 4
For example, if LIDn(4:0) is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4.
Table 22, Local Input Bit Delay Programming Table, illustrates the bit delay selection.
Corresponding Delay Bits
Data Rate
LID4
LID3
LID2
LID1
LID0
0 (Default)
1/4
1/2
3/4
1
1 1/4
1 1/2
1 3/4
2
2 1/4
2 1/2
2 3/4
3
3 1/4
3 1/2
3 3/4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 22 - Local Input Bit Delay Programming Table
58
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Corresponding Delay Bits
Data Rate
LID4
LID3
LID2
LID1
LID0
4
4 1/4
4 1/2
4 3/4
5
5 1/4
5 1/2
5 3/4
6
6 1/4
6 1/2
6 3/4
7
7 1/4
7 1/2
7 3/4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 22 - Local Input Bit Delay Programming Table (continued)
13.6
Backplane Input Channel Delay Registers (BCDR0 to BCDR31)
Address 0043h to 0062h
Thirty-two Backplane input channel delay registers (BCDR0 to BCDR31) allow users to program the input channel
delay for the Backplane input data streams BSTi0-31. The possible adjustment is 511 channels and the BCDR0 to
BCDR31 registers are configured as follows:
BCDRn Bit
(where n = 0 to 31 for non-32Mb/s
mode, n = 0 to 15 for 32Mb/s
mode)
Name
Reset
15-9
Reserved
0
Reserved
8-0
BCD(8:0)
0
Backplane Channel Delay Register
The binary value of these bits refers to the channel
delay value for the Backplane input stream
Description
Table 23 - Backplane Channel Delay Register (BCDRn) Bits
13.6.1
Backplane Channel Delay Bits 8-0 (BCDn8 - BCDn0)
These nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data
from the Backplane stream input pins. The input channel delay can be set to 511 (32 Mb/s streams), 255 (16 Mb/s
streams), 127 (8 Mb/s streams), 63 (4 Mb/s streams) or 31 (2 Mb/s streams) from the frame boundary.
59
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Input Stream
Channel Delay
Corresponding Delay Bits
0 Channel (Default)
0 0000 0000
1 Channel
0 0000 0001
2 Channels
0 0000 0010
3 Channels
0 0000 0011
4 Channels
0 0000 0100
5 Channels
0 0000 0101
...
...
...
...
509 Channels
1 1111 1101
510 Channels
1 1111 1110
511 Channels
1 1111 1111
BCD8-BCD0
Table 24 - Backplane Input Channel Delay (BCD) Programming Table
13.7
Backplane Input Bit Delay Registers (BIDR0 to BIDR31)
Address 0063h to 0082h
Thirty-two Backplane input delay registers (BIDR0 to BIDR31) allow users to program the input bit delay for the
Backplane input data streams BSTi0-31. The possible adjustment is 7 3/4 of the data rate, in steps of 1/4 of the
data rate. The data rate can be either 2 Mb/s, 4 Mb/s, 8 Mb/s, 16 Mb/s, or 32 Mb/s.
The BIDR0 to BIDR31 registers are configured as follows:
BIDRn Bit
(where n = 0 to 31 for Non-32Mb/s
Mode, n = 0 to15 for 32Mb/s Mode)
Name
Reset
Description
15-5
Reserved
0
Reserved
4-0
BID(4:0)
0
Backplane Input Bit Delay Register
The binary value of these bits refers to the input bit
delay value for the Backplane input stream
Table 25 - Backplane Input Bit Delay Register (BIDRn) Bits
13.7.1
Backplane Input Delay Bits 4-0 (BID4 - BID0)
These five bits define how long in the cycle the serial interface receiver takes to recognize and stores the bit 0 from
the BSTi input pins: i.e., start assuming a new frame. Input bit delay adjustment can range up to 73/4 bit periods
forward with resolution of 1/4 bit period.
This can be described as BIDn(4:0) = (no. of bits delay) / 4
For example, if BID(4:0) is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4.
60
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Table 26 illustrates the bit delay selection.
Corresponding Delay Bits
Data Rate
BID4
BID3
BID2
BID1
BID0
0 (Default)
1/4
1/2
3/4
1
1 1/4
1 1/2
1 3/4
2
2 1/4
2 1/2
2 3/4
3
3 1/4
3 1/2
3 3/4
4
4 1/4
4 1/2
4 3/4
5
5 1/4
5 1/2
5 3/4
6
6 1/4
6 1/2
6 3/4
7
7 1/4
7 1/2
7 3/4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 26 - Backplane Input Bit Delay Programming Table
13.8
Local Output Advancement Registers (LOAR0 to LOAR15)
Address 0083h to 0092h.
Sixteen Local output advancement registers (LOAR0 to LOAR15) allow users to program the output advancement
for output data streams LSTo0 to LSTo15. The possible adjustment is -2, -4 or -6 cycles of the internal system clock
(131.072 MHz).
61
Zarlink Semiconductor Inc.
MT90870
Data Sheet
The LOAR0 to LOAR15 registers are configured as follows:
LOARn Bit
Name
Reset
15-2
Reserved
0
Reserved
1-0
LOA(1:0)
0
Local Output Advancement Register
(where n = 0 to 15)
Description
Table 27 - Local Output Advancement Register (LOARn) Bits
13.8.1
Local Output Advancement Bits 1-0 (LOA1-LOA0)
The binary value of these two bits is the amount of offset that a particular stream output can be advanced. When
the advancement is 0, the serial output stream has the normal alignment with the Local frame pulse.
Local Output Advancement
Corresponding Advancement Bits
Clock Rate 131.072 MHz
LOA1
LOA0
0 (Default)
0
0
-2 cycle
0
1
-4 cycles
1
0
-6 cycles
1
1
Table 28 - Local Output Advancement (LOAR) Programming Table
13.9
Backplane Output Advancement Registers (BOAR0 - 31)
Address 00A3h to 00C2h
Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR3) allow users to program the output
advancement for output data streams BSTo0 to BSTo31. For 2 Mb/s, 4 Mb/s, 8 Mb/s and 16 Mb/s stream operation
the possible adjustment is -2, -4 or -6 cycles of the internal system clock (131.072MHz). For 32 Mb/ s stream
operation the possible adjustment is -1, -2 or -3 cycles of the internal system clock (131.072 MHz). The BOAR0 to
BOAR3 registers are configured as follows:
BOARn Bit
(where n = 0 to 31 for non-32 Mb/s
mode, n = 0 to 15 for 32 Mb/s mode)
Name
Reset
Description
15-2
Reserved
0
Reserved
1:0
BOA(1:0)
0
Backplane Output Advancement Register
Table 29 - Backplane Output Advancement Register (BOAR) Bits
13.9.1
Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
The binary value of these two bits is the amount of offset that a particular stream output can be advanced. When
the advancement is 0, the serial output stream has the normal alignment with the Backplane frame pulse.
62
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Backplane Output Advancement For
2 Mb/s, 4 Mb/s, 8 Mb/s & 16 Mb/s
Backplane Output
Advancement For 32 Mb/s
Corresponding
Advancement Bits
clock Rate 131.072 MHz
clock Rate 131.072 MHz
BOA1
BOA0
0 (Default)
0 (Default)
0
0
-2 cycle
-1 cycle
0
1
-4 cycles
-2 cycle
1
0
-6 cycles
-3 cycle
1
1
Table 30 - Backplane Output Advancement (BOAR) Programming Table
13.10
Local Bit Error Rate (BER) Registers
13.10.1
Local BER Start Send Register (LBSSR)
Address 00C3h.
Local BER Start Send Register defines the output channel and the stream in which the BER sequence starts to
be transmitted. The LBSSR register is configured as follows:
Bit
Name
Reset
Description
15-12
Reserved
0
Reserved.
11-8
LBSSA(3:0)
0
Local BER Send Stream Address Bits.
The binary value of these bits refers to the Local output stream
which carries the BER data.
7-0
LBSCA(7:0)
0
Local BER Send Channel Address Bits.
The binary value of these bits refers to the Local output channel in
which the BER data starts to be sent.
Table 31 - Local BER Start Send Register (LBSSR) Bits
13.10.2
Local Transmit BER Length Register (LTXBLR)
Address 00C4h
Local BER Transmit Length Register (LTXBLR) defines how many channels the BER sequence will be transmitted
during each frame. The LTXBLR register is configured as follows:
Bit
Name
Reset
15-8
Reserved
0
Description
Reserved.
Table 32 - Local Transmit BER Length Register (LTXBLR) Bits
63
Zarlink Semiconductor Inc.
MT90870
Bit
Name
Reset
7-0
LTXBL(7:0)
0
Data Sheet
Description
Local Transmit BER Length Bits
The binary value of these bits define the number of channels in addition to the
Start Channel that the BER data will be transmitted on. (i.e. Total Channels =
Start Channel + LTXBL value)
Table 32 - Local Transmit BER Length Register (LTXBLR) Bits
13.10.3
Local Receive BER Length Register (LRXBLR)
Address 00C5h
Local BER Receive Length Register (LRXBLR) defines how many channels the BER sequence will be received
during each frame. The LRXBLR register is configured as follows:
Bit
Name
Reset
Description
15-8
Reserved
0
Reserved.
7-0
LRXBL(7:0)
0
Local Receive BER Length Bits
The binary value of these bits define the number of channels in addition to
the Start Channel allocated for the BER receiver. (i.e. Total Channels =
Start Channel + LRXBL value)
Table 33 - Local Receive BER Length Register (LRXBLR) Bits
13.10.4
Local BER Start Receive Register (LBSRR)
Address 00C6h
Local BER Start Receive Register defines the Input Stream and Start Channel and the stream in which the BER
sequence shall be received. The LBSRR register is configured as follows:
Bit
Name
Reset
Description
15-12
Reserved
0
Reserved.
11-8
LBRSA(3:0)
0
Local BER Receive Stream Address Bits
The binary value of these bits refers to the Local input stream to receive
the BER data.
7-0
LBRCA(7:0)
0
Local BER Receive Channel Address Bits
The binary value of these bits refers to the Local input channel in which
the BER data starts to be compared.
Table 34 - Local BER Start Receive Register (LBSRR) Bits
64
Zarlink Semiconductor Inc.
MT90870
13.10.5
Data Sheet
Local BER Count Register (LBCR)
Address 00C7h
Local BER Count Register contains the number of counted errors. This register is read only. The LBCR register is
configured as follows:
Bit
Name
Reset
15-0
LBC(15:0)
0
Description
Local Bit Error Rate Count
The binary value of the bits define the Local Bit Error count.
Table 35 - Local BER Count Register (LBCR) Bits
13.11
13.11.1
Backplane Bit Error Rate (BER) Registers
Backplane BER Start Send Register (BBSSR)
Address 00C8h
Backplane BER Start Send Register defines the output channel and the stream in which the BER sequence is
transmitted. The BBSSR register is configured as follows:
Bit
Name
Reset
Description
15-14
Reserved
0
Reserved.
13-9
BBSSA(4:0)
0
Backplane BER Send Stream Address Bits
The binary value of these bits define the Backplane output stream to
transmit the BER data.
8-0
BBSCA(8:0)
0
Backplane BER Send Channel Address Bits
The binary value of these bits define the Backplane output Start
Channel in which the BER data is transmitted.
Table 36 - Backplane BER Start Send Register (BBSSR) Bits
13.11.2
Backplane Transmit BER Length Register (BTXBLR)
Address 00C9h
Backplane Transmit BER Length Register (BTXBLR) defines how many channels in each frame the BER sequence
will be transmitted. The BTXBLR register is configured as follows:
Bit
Name
Reset
Description
15-9
Reserved
0
Reserved.
8-0
BTXBL(8:0)
0
Backplane Transmit BER Length Bits
The binary value of these bits define the number of channels in addition to the
Start Channel allocated for the BER Transmitter. (i.e. Total Channels = Start
Channel + BTXBL value)
Table 37 - Backplane Transmit BER Length (BTXBLR) Bits
65
Zarlink Semiconductor Inc.
MT90870
13.11.3
Data Sheet
Backplane Receive BER Length Register (BRXBLR)
Address 00CAh
Backplane Receive BER Length Register (BRXBLR) defines how many channels in each frame the BER sequence
will be transmitted. The BRXBLR register is configured as follows:
Bit
Name
Reset
Description
15-9
Reserved
0
Reserved.
8-0
BRXBL(8:0)
0
Backplane Receive BER Length Bits
The binary value of these bits define the number of channels in addition to the
Start Channel allocated for the BER receiver. (i.e. Total Channels = Start
Channel + BRXBL value)
Table 38 - Backplane Receive BER Length (BRXBLR) Bits
13.11.4
Backplane BER Start Receive Register (BBSRR)
Address 00CBh
Backplane BER Start Receive Register defines the Input Stream and the Start Channel in which the BER sequence
shall be received. The BBSRR register is configured as follows:
Bit
Name
Reset
Description
15-14
Reserved
0
Reserved.
13-9
BBRSA(4:0)
0
Backplane BER Receive Stream Address Bits
The binary value of these bits defines the Backplane input stream that
receives the BER data.
8-0
BBRCA(8:0)
0
Backplane BER Receive Channel Address Bits
The binary value of these bits define the Backplane input start channel in
which the BER data will be received.
Table 39 - Backplane BER Start Receive Register (BBSRR) Bits
13.11.5
Backplane BER Count Register (BBCR)
Address 00CCh
Backplane BER Count Register contains the number of counted errors. This register is read only. The BBCR
register is configured as follows:
Bit
Name
Reset
15-0
BBC(15:0)
0
Description
Backplane Bit Error Rate Count
The binary value of these bits define the Backplane Bit Error count.
Table 40 - Backplane BER Count Register (BBCR) Bits
66
Zarlink Semiconductor Inc.
MT90870
13.12
Data Sheet
Local Bit Rate Registers
13.12.1
Local Input Bit Rate Registers (LIBRR0-15)
Address 00CDh to 00DCh.
Sixteen Local Input Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or
16 Mb/s. The LIBRR registers are configured as follows:
LIBRn
Name
Reset
15-2
Reserved
0
Reserved
1-0
LIBR(1:0)
0
Local Input Bit Rate
(for n=0 to 15)
Description
Table 41 - Local Input Bit Rate Register (LIBRRn) Bits
LIBR1
LIBR0
Bit rate for stream n
0
0
2 Mb/s
0
1
4 Mb/s
1
0
8 Mb/s
1
1
16 Mb/s
Table 42 - Local Input Bit Rate (LIBR) Programming Table
13.12.2
Local Output Bit Rate Resisters (LOBRR0-15)
Address 00EDh to 00FCh.
Sixteen Local Output Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16 Mb/s.
The LOBRR registers are configured as follows:
LOBRn Bit
Name
Reset
15-2
Reserved
0
Reserved
1-0
LOBR(1:0)
0
Local Output Bit Rate
(where n = 0 to 15)
Description
Table 43 - Local Output Bit Rate Register (LOBRRn) Bits
LOBR1
LOBR0
Bit rate for stream n
0
0
2 Mb/s
0
1
4 Mb/s
1
0
8 Mb/s
1
1
16 Mb/s
Table 44 - Output Bit Rate (LOBR) Programming Register
67
Zarlink Semiconductor Inc.
MT90870
13.13
Data Sheet
Backplane Bit Rate Registers
13.13.1
Backplane Input Bit Rate Registers (BIBRR0-31)
Address 010Dh to 012Ch
Thirty-two Backplane Input Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16
Mb/s. These registers may be overridden by setting 32 Mb/s mode in the control register, in which case, Backplane
streams 0-15 will operate at 32 Mb/s and Backplane streams 16-31 will be unused. The BIBRR registers are
configured as follows:
BIBRn Bit
(for n=0 to 31)
Name
Reset
15-2
Reserved
0
Reserved
1-0
BIBR(1:0)
0
Backplane Input Bit Rate
Description
Table 45 - Backplane Input Bit Rate Register (BIBRRn) Bits
BIBR1
BIBR0
Bit rate for stream n
0
0
2 Mb/s
0
1
4 Mb/s
1
0
8 Mb/s
1
1
16 Mb/s
Table 46 - Backplane Input Bit Rate (BIBR) Programming Table
13.13.2
Backplane Output Bit Rate Registers (BOBRR0-31)
Address 012Dh to 014Ch
Thirty-two Backplane Output Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16
Mb/s.These registers may be overridden by setting 32 Mb/s mode in the control register, in which case, Backplane
streams 0-15 will operate at 32 Mb/s and Backplane streams 16-31 will be unused. The BOBRR registers are
configured as follows:
BOBRn Bit
Name
Reset
15-2
Reserved
0
Reserved
1-0
BOBR(1:0)
0
Backplane Output Bit Rate
(for n=0 to 31)
Description
Table 47 - Backplane Output Bit Rate Register (BOBRRn) Bits
68
Zarlink Semiconductor Inc.
MT90870
Data Sheet
BOBR1
BOBR0
Bit rate for stream n
0
0
2Mb/s
0
1
4Mb/s
1
0
8Mb/s
1
1
16Mb/s
Table 48 - Backplane Output Bit Rate (BOBRR) Programming Table
13.14
Memory BIST Register
Address 014Dh
The Memory BIST register enables the built-in-self-test function for the on-chip memory testing. Two consecutive
write operations are required to start MBIST. The first with only Bit 12 (LV_TM) set High (i.e. 1000h), the second
with Bit 12 maintained High but with the required start bit(s) set High.
The MBISTR register is configured as follows:
Bit
Name
Reset
Description
15-13
Reserved
0
Reserved.
12
LV_TM
0
MBIST Test enable.
High for MBIST mode, Low for scan mode.
11
BISTSDB
0
Backplane Data Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
10
BISTCDB
0
Backplane Data Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
9
BISTPDB
0
Backplane Data Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
8
BISTSDL
0
Local Data Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
7
BISTCDL
0
Local Data Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
6
BISTPDL
0
Local Data Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
5
BISTSCB
0
Backplane Connection Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
4
BISTCCB
0
Backplane Connection Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
Table 49 - Memory BIST Register (MBISTR) Bits
69
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Bit
Name
Reset
Description
3
BISTPCB
0
Backplane Connection Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
2
BISTSCL
0
Local Connection Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
1
BISTCCL
0
Local Connection Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
0
BISTPCL
0
Local Connection Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
Table 49 - Memory BIST Register (MBISTR) Bits (continued)
13.15
Revision Control Register
Address 3FFFh
The revision control register stores the binary value of the silicon revision number. This register is read only. The
RCR register is configured as follows:
Bit
Name
Reset Value
Description
15-4
Reserved
0
3-0
RC(3:0)
defined by silicon
Reserved.
Revision Control Bits.
Table 50 - Revision Control Register (RCR) Bits
70
Zarlink Semiconductor Inc.
MT90870
Data Sheet
DC Electrical Characteristics
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
VDD_CORE
-0.5
2.5
V
1
Core Supply Voltage
2
I/O Supply Voltage
VDD_IO
-0.5
5.0
V
3
PLL Supply Voltage
VDD_PLL
-0.5
2.5
V
4
Input Voltage (non-5V tolerant inputs)
VI
-0.5
VDD_IO +0.5
V
5
Input Voltage (5V tolerant inputs)
VI_5V
-0.5
7.0
V
6
Continuous Current at digital outputs
IO
15
mA
7
Package power dissipation
PD
2
W
8
Storage temperature
TS
+125
°C
- 55
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions
Characteristics
Sym.
Min.
Typ.
Max.
Units
TOP
-40
25
+85
°C
1
Operating Temperature
2
Positive Supply
VDD_IO
3.0
3.3
3.6
V
3
Positive Supply
VDD_CORE
1.62
1.8
1.98
V
4
Positive Supply
VDD_PLL
1.62
1.8
1.98
V
5
Input Voltage
VI
0
3.3
VDD_IO
V
6
Input Voltage on 5 V Tolerant Inputs
VI_5V
0
5
5.5
V
Voltages are with respect to ground (V SS) unless otherwise stated.
71
Zarlink Semiconductor Inc.
MT90870
Data Sheet
DC Electrical Parameters
Characteristics
1a
N
1c
1d
P
U
Min.
Typ.
Max.
Units
4
mA
Static IDD_Core and
PLL current
200
mA
Applied clock
C8i = 8.192 MHz
IDD_Core
Supply Current
IDD_Core
Supply Current
IDD_IO
100
µA
Static IDD_IO
Supply Current
IDD_IO
85
mA
IAV with all output
streams at max.
data-rate
160
T
2
Test Conditions
Supply Current
I
1b
Sym.
2.0
V
Input High Voltage
VIH
Input Low Voltage
VIL
0.8
V
Input Leakage (input pins)
Input Leakage (bi-directional pins)
IIL
IBL
5
5
µA
µA
0 < VI < VDD_IO
Weak Pullup Current
IPU
-200
µA
Input at 0V
5
Weak Pulldown Current
IPD
200
µA
Input at VDD_IO
6
Input Pin Capacitance
CI
5
pF
3
S
4
7
8
9
10
O
U
T
P
U
T
S
V
IOH = 10mA
0.4
V
IOL = 10mA
IOZ
5
µA
0 < VO < VDD_IO
CO
5
pF
Output High Voltage
VOH
Output Low Voltage
VOL
High Impedance Leakage
Output Pin Capacitance
2.4
Voltages are with respect to ground (V ss) unless otherwise stated.
AC Electrical Characteristics
Timing Parameter Measurement: Voltage Levels
Characteristics
Sym.
Level
Units
Conditions
1
CMOS Threshold
VCT
0.5VDD_IO
V
3.0V < VDD_IO < 3.6V
2
Rise/Fall Threshold Voltage High
VHM
0.7VDD_IO
V
3.0V < VDD_IO < 3.6V
3
Rise/Fall Threshold Voltage Low
VLM
0.3VDD_IO
V
3.0V < VDD_IO < 3.6V
72
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Backplane and Local Clock Timing
Characteristic
Sym.
Min. Typ. Max. Units
1
Backplane Frame Pulse Width
tBFPW244
tBFPW122
tBGFPW
210
10
10
2
Backplane Frame Pulse Setup Time
before C8i clock rising edge
tBFPS244
tBFPS122
tBGFPS
3
Backplane Frame Pulse Hold Time
from C8i clock rising edge
4
244
122
122
350
220
220
ns
5
5
5
110
110
110
ns
tBFPH244
tBFPH122
tBGFPH
5
5
5
110
110
110
ns
C8i Clock Period
tBCP8
120
122
124
ns
5
C8i Clock Pulse Width High
tBCH8
50
61
70
ns
6
C8i Clock Pulse Width Low
tBCL8
50
61
70
ns
7
C8i Clock Rise/Fall Time
trBC8i, tfBC8i
0
2
3
ns
8
C8i Cycle to Cycle Variation
tCVC8i
3
ns
9
Local Frame Boundary Offset
tLFBOS
7.5
ns
10
FP8o Width
tLFPW8
tGFPW8
117
117
127
127
ns
11
FP8o Output Delay
from edge to Local Frame Boundary
tFODF8
tGFPS8o
56
56
68
56
ns
12
FP8o Output Delay
from Local Frame Boundary to Edge
tFODR8
tGFPH8o
59
59
61
61
ns
13
C8o Clock Period
tLCP8
117
127
ns
14
C8o Clock Pulse Width High
tLCH8
56
68
ns
15
C8o Clock Pulse Width Low
tLCL8
59
61
ns
16
C8o Clock Rise/Fall Time
trLC8o, tfLC8o
3
7
ns
17
FP16o Width
tFPW16
62
66
ns
18
FP16o Output Delay
from Falling edge to Local Frame
Boundary
tFODF16
-29
-36
ns
19
FP16o Output Delay
from Local Frame Boundary to Rising
edge
tFODR16
30
33
ns
73
Zarlink Semiconductor Inc.
122
122
Notes
CL=60pF
CL=60pF
CL=60pF
MT90870
Data Sheet
Backplane and Local Clock Timing (continued)
Characteristic
Sym.
Min. Typ. Max. Units
20
C16o Clock Period
tLCP16
62
66
ns
21
C16o Clock Pulse Width High
tLCH16
29
36
ns
22
C16o Clock Pulse Width Low
tLCL16
30
33
ns
23
C16o Clock Rise/Fall Time
trLC16o, tfLC16o
0
5
ns
74
Zarlink Semiconductor Inc.
Notes
CL=60pF
MT90870
tBFPW244
FP8i
(244 ns)
tBFPS244
tBFPH244
tBFPW122
FP8i
(122 ns)
tBFPS122
C8i
Data Sheet
tBCH8
tBFPH122
tBCP8
tBCL8
tfBC8i
trBC8i
CK_int *
tLFBOS
tLFPW8_244
FP8o
(244ns)
tFODF8_244
tFODR8_244
tLFPW8
FP8o
(122 ns)
C8o
tLFODF8
tLCL8
tLFODR8
tLCP8
tLCH8
trLC8o
tfLC8o
tFPW16
FP16o
tLCL16 tLCH16
tFODR16
tFODF16
tLCP16
C16o
trLC16o
tfLC16o
* CK_int is the internal clock signal of 131.072 MHz
Figure 20 - Backplane and Local Clock Timing Diagram for ST-BUS
75
Zarlink Semiconductor Inc.
MT90870
Data Sheet
tBGFPW
FP8i
tBGFPS
tBGFPH
tBCP8
tBCH8
tBCL8
C8i
tfBC8i
trBC8i
CK_int*
tLFBOS
tGFPW8
FP8o
tGFPS8o
tLCL8
tGFPH8o
tLCP8
tLCH8
C8o
trLC8o
tfLC8o
tFPW16
FP16o
tLCH16
tFRS16o
tLCL16
tFRH16o
tLCP16
C16o
* CK_int is the internal clock signal of 131.072 MHz
trLC16o
tfLC16o
Figure 21 - Backplane and Local Clock Timing for GCI-BUS
76
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Backplane Data Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
23
46
92
183
366
28
51
97
188
371
ns
With zero
offset.
1
Backplane Input data sampling point
tBIDS32
tBIDS16
tBIDS8
tBIDS4
tBIDS2
18
41
87
178
361
2
Backplane Serial Input Set-up Time
tBSIS32
tBSIS16
tBSIS8
tBSIS4
tBSIS2
2.1
ns
Backplane Serial Input Hold Time
tBSIH32
tBSIH16
tBSIH8
tBSIH4
tBSIH2
3
ns
Backplane Serial Output Delay
tBSOD32
tBSOD16
tBSOD8
tBSOD4
tBSOD2
3
4
77
Zarlink Semiconductor Inc.
2.1
2.1
2.1
2.1
3
3
3
3
10.5
10.5
10.5
10.5
10.5
ns
CL=50pF
MT90870
Data Sheet
FP8i
C8i
CK_int *
tBIDS8
tBSIS8
tBSIH8
BSTi0 - 31
8.192 Mb/s
0
1
6
7
4
5
2
3
1
tBSOD8
BSTo0 - 31
8.192 Mb/s
Bit1
Ch127
Bit0
Ch127
Bit7
Ch0
tBIDS4
BSTi0 - 31
4.096 Mb/s
Bit4
Ch0
Bit2
Ch0
Bit3
Ch0
Bit1
Ch0
tBSIS4
tBSIH4
Bit7
Ch0
Bit0
Ch63
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
tBSOD4
BSTo0 - 31
4.096 Mb/s
Bit0
Ch63
Bit0
Ch31
Bit5
Ch0
Bit6
Ch0
Bit7
Ch0
tBIDS2
BSTi0 - 31
2.048 Mb/s
BSTo0 - 31
2.048 Mb/s
Bit5
Ch0
Bit6
Ch0
tBSIS2
tBSIH2
Bit6
Ch0
Bit7
Ch0
tBSOD2
Bit0
Ch31
Bit4
Ch0
Bit7
Ch0
Bit6
Ch0
* CK_int is the internal clock signal of 131.072 MHz
Figure 22 - ST-BUS Backplane Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s)
78
Zarlink Semiconductor Inc.
MT90870
Data Sheet
FP8i
C8i
CK_int *
tBIDS32
tBSIS32
tBSIH32
BSTi0 - 15
32.768 Mb/s
2
6
7
0
1
4
5
2
3
tBSOD32
BSTo0 - 15
32.768 Mb/s
Bit2
Ch511
Bit1
Ch511
Bit7
Ch0
Bit0
Ch511
tBIDS16
BSTi0 - 31
16.384 Mb/s
BSTo0 - 31
16.384 Mb/s
Bit1
Bit0
Ch 255
Ch 255
Bit5
Ch0
Bit6
Ch0
Bit4
Ch0
Bit2
Ch0
Bit3
Ch0
tBSIS16
tBSIH16
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
tBSOD16
Bit0
Ch255
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
* CK_int is the internal clock signal of 131.072 MHz
Figure 23 - ST-BUS Backplane Data Timing Diagram (32 Mb/s, 16 Mb/s)
79
Zarlink Semiconductor Inc.
MT90870
Data Sheet
FP8i
C8i
CK_int *
tBIDS8
tBSIS8
tBSIH8
BSTi0 - 31
8.192 Mb/s
0
7
6
1
2
3
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
5
4
6
tBSOD8
BSTo0 - 31
8.192 Mb/s
Bit6
Ch127
Bit7
Ch127
Bit0
Ch0
tBIDS4
Bit5
Ch0
Bit4
Ch0
Bit6
Ch0
tBSIS4
tBSIH4
BSTi0 - 31
4.096 Mb/s
Bit7
Ch63
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
Bit4
Ch0
tBSOD4
BSTo0 - 31
4.096 Mb/s
Bit7
Ch63
Bit2
Ch0
Bit1
Ch0
Bit0
Ch0
Bit3
Ch0
tBIDS2
tBSIS2
tBSIH2
BSTi0 - 31
2.048 Mb/s
Bit7
Ch31
Bit1
Ch0
Bit0
Ch0
tBSOD2
BSTo0 - 31
2.048 Mb/s
Bit7
Ch31
Bit0
Ch0
Bit1
Ch0
* CK_int is the internal clock signal of 131.072 MHz
Figure 24 - GCI BUS Backplane Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s)
80
Zarlink Semiconductor Inc.
MT90870
Data Sheet
FP8i
C8i
CK_int *
tBIDS32
tBSIS32
tBSIH32
BSTi0 - 15
32.768 Mb/s
5
7
6
1
9
3
2
5
4
tBSOD32
BSTo0 - 15
32.768 Mb/s
Bit5
Ch 511
Bit6
Ch 511
Bit7
Ch 511
Bit0
Ch0
tBIDS16
BSTi0 - 31
16.384 Mb/s
Bit6
Bit7
Ch255
Ch255
BSTo0 - 31
16.384 Mb/s
Bit2
Ch0
Bit1
Ch0
Bit3
Ch0
Bit5
Ch0
Bit4
Ch0
tBSIS16
tBSIH16
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
tBSOD16
Bit7
Ch255
Bit2
Ch0
Bit1
Ch0
Bit0
Ch0
* CK_int is the internal clock signal of 131.072 MHz
Figure 25 - GCI BUS Backplane Data Timing Diagram (32 Mb/s, 16 Mb/s)
Local Clock Data Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
7.5
ns
51
97
188
371
ns
1
Local Frame Boundary Offset
tLFBOS
2
Input data sampling point
tLIDS16
tLIDS8
tLIDS4
tLIDS2
41
87
178
361
3
Local Serial Input Set-up Time
tLSIS16
tLSIS8
tLSIS4
tLSIS2
2.1
2.1
2.1
2.1
ns
4
Local Serial Input Hold Time
tLSIH16
tLSIH8
tLSIH4
tLSIH2
3
3
3
3
ns
5
Local Serial Output Delay
tLSOD16
tLSOD8
tLSOD4
tLSOD2
81
Zarlink Semiconductor Inc.
46
92
183
366
10.5
10.5
10.5
10.5
ns
Notes
With zero
offset.
CL=50pF
MT90870
Data Sheet
FP8i
C8i
tLFBOS
CK_int *
tLIDS16
LSTi0 - 15
16.384 Mb/s
Bit1
Bit0
Ch 255
Bit7
tLSOD16Ch 0
Ch 255
LSTo0 - 15
16.384 Mb/s
tLSIS16
tLSIH16
Bit0
Ch255
Bit6
Bit5
Ch 0
Ch 0
Bit5
Ch0
Bit6
Ch0
Bit7
Ch0
* CK_int is the internal clock signal of 131.072MHz
Figure 26 - ST-BUS Local Timing Diagram (16 Mb/s)
FP8i
C8i
tLFBOS
CK_int *
tLIDS8
tLSIS8
tLSIH8
LSTi0 - 15
8.192 Mb/s
0
1
6
5
4
3
2
1
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
Bit1
Ch0
7
tLSOD8
LSTo0 - 15
8.192 Mb/s
Bit1
Ch127
Bit0
Ch127
Bit7
Ch0
tLIDS4
tLSIS4
tLSIH4
LSTi0 - 15
4.096 Mb/s
Bit7
Ch0
Bit0
Ch63
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
tLSOD4
LSTo0 - 15
4.096 Mb/s
Bit0
Ch63
Bit5
Ch0
Bit6
Ch0
Bit7
Ch0
Bit4
Ch0
tLIDS2
tLSIS2
tLSIH2
LSTi0 - 15
2.048 Mb/s
LSTo0 - 15
2.048 Mb/s
Bit0
Ch31
tLSOD2
Bit0
Ch31
Bit6
Ch0
Bit7
Ch0
Bit7
Ch0
Bit6
Ch0
* CK_int is the internal clock signal of 131.072 MHz
Figure 27 - ST-BUS Local Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s)
82
Zarlink Semiconductor Inc.
MT90870
Data Sheet
Backplane and Local Output High-Impedance Timing
1
Characteristic
Sym.
STo delay - Active to High-Z
- High-Z to Active
2
Output Driver Enable (ODE)
Delay to Active Data
Output Driver Enable (ODE)
Delay to High-Impedance
Min.
Typ.
Max.
Units
Test Conditions
tDZ
tZD
4
4
ns
ns
RL=1K, CL=50pF, See Note 1
tODE
15
ns
RL=1K, CL=50pF, See Note 1
tODZ
14
ns
RL=1K, CL=50pF, See Note 1
Note 1:
High Impedance is measured by pulling to the appropriate rail with RL =1k//1k potential divider, with timing corrected for C L .
VTT
CLK
tDZ
Valid Data
STo
HiZ
VTT
Valid Data
VTT
tZD
HiZ
STo
Figure 28 - Serial Output and External Control
VTT
ODE
tODE
STo
tODZ
Valid Data
Hi-Z
VTT
Hi-Z
Figure 29 - Output Driver Enable (ODE)
Non-Multiplexed Microprocessor Port Timing
Characteristics
Sym.
Min.
Typ.
1
CS setup from DS falling
tCSS
0
0
2
R/W setup from DS falling
tRWS
8
ns
3
Address setup from DS falling
tADS
8
ns
4
CS hold after DS rising
tCSH
0
ns
5
R/W hold after DS rising
tRWH
8
ns
83
Zarlink Semiconductor Inc.
Max.
Units
ns
Test Conditions
MT90870
Data Sheet
Non-Multiplexed Microprocessor Port Timing
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
6
Address hold after DS rising
tADH
8
ns
7
Data setup from DTA Low on Read
tDDR
14
ns
CL=60pF
8
Data hold on read
tDHR
ns
CL=60pF, RL=1K
9
Data setup on write
tWDS
8
ns
10
Data hold on write
tDHW
8
ns
11
Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory
tAKD
Acknowledgment Hold Time
tAKH
12
30
Note 1
85
70
ns
ns
CL=60pF
CL=60pF
12
ns
CL=60pF, RL=1K,
Note 1
Note:
1. High impedance is measured by pulling to the appropriate rail with R L = 1K/1K potential divider, with timing corrected to cancel time
taken to charge C L.
DS
VTT
tCSH
tCSS
VTT
CS
tRWH
tRWS
VTT
R/W
tADS
tADH
VTT
VALID ADDRESS
A0-A14
tDHR
D0-D15
READ
VTT
VALID READ DATA
tDHW
tWDS
VTT
VALID WRITE DATA
D0-D15
WRITE
tDDR
tAKD
DTA
VTT
tAKH
Figure 30 - Motorola Non-Multiplexed Bus Timing
Note: There must be a minimum of 30 ns between CPU accesses, to allow the MT90869 device to recognize the
accesses as separate (i.e., a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion
of CS and/or DS (to initiate the next access).
84
Zarlink Semiconductor Inc.
Package Code
c Zarlink Semiconductor 2003 All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes:
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE