ON NCP5331 Two-phase pwm controller with integrated gate driver Datasheet

NCP5331
Two−Phase PWM
Controller with Integrated
Gate Drivers
The NCP5331 is a second−generation, two−phase, buck controller
that incorporates advanced control functions to power 64−bit AMD
Athlon processors and low voltage, high current power supplies.
Proprietary multiphase architecture guarantees balanced load−current
sharing, reduces output voltage and input current ripple, decreases
filter requirements and inductor values, and increases output current
slew rate. Traditional Enhanced V2 has been combined with an
internal PWM ramp and voltage feedback directly from VCORE to the
internal PWM comparator. These features and enhancements deliver
the fastest transient response, reduce output voltage jitter, provide
greater design flexibility and portability, and minimize overall
solution cost.
Advanced features include adjustable power−good delay,
programmable overcurrent shutdown timer, superior overvoltage
protection (OVP), and differential remote sensing. An innovative
overvoltage protection (OVP) scheme safeguards the CPU during
extreme situations including power up with a shorted upper MOSFET,
shorting of an upper MOSFET during normal operation, and loss of
the voltage feedback signal, COREFB+.
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LQFP−32
FT SUFFIX
CASE 873A
MARKING DIAGRAMS
NCP5331
AWLYYWWx
32
Features
•
•
•
•
•
•
•
•
•
•
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1
Reduced SMT Package Size (7 mm × 7 mm)
Enhanced V2 Control Method
Four On−Board Gate Drivers
Internal PWM Ramps
Differential Remote Voltage Sense
Fast Feedback Pin (VFFB)
5−Bit DAC with 0.8% System Tolerance
Timed Hiccup Mode Current Limit
Power Good Output with Programmable Delay
Advanced Overvoltage Protection (OVP)
Adjustable Output Voltage Positioning
150 kHz to 600 kHz Operation Set by Resistor
“Lossless” Current Sensing through Output Inductors
Independent Current Sense Amplifiers
5.0 V, 2 mA Reference Output
Pb−Free Package is Available*
A
WL
YY
WW
x
= Assembly Location
= Wafer Lot
= Year
= Work Week
= G or *Pb−Free indicator, “G” or microdot “ ”,
may or may not be present.
ORDERING INFORMATION
Device
Package
Shipping†
NCP5331FTR2
LQFP−32
2000 Tape & Reel
NCP5331FTR2G
LQFP−32
(Pb−Free)
2000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2005
March, 2005 − Rev. 12
1
Publication Order Number:
NCP5331/D
NCP5331
PIN CONNECTIONS
COMP
ILIM
5 VSB
PGD
CPGD
COVC
VCCL
VCCL1
LQFP−32
1
32 31 30 29 28 27 26 25
24
VDRP
LGND
CS1
CSREF
CS2
VFFB
5 VREF
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
ROSC
−SEN
VID0
VID1
VID2
VID3
VID4
VCCL2
VFB
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2
GL1
GND1
GH1
CBOUT
VCCH
GH2
GND2
GL2
RLIM2
910
RLIM1
2.37 k
RS
1.87 k
CSB
470 pF
RF1
3.6 k
CF1
1.0 nF
Figure 1. Application Diagram, 12 V to 1.2 V at 52 A, 200 kHz for 64−Bit AMD Athlon Processor
VCORE
R4
56
VFB
VDRP
LGND
CS1
CSREF
CS2
VFFB
5 VREF
ROSC
51 k
CS1
0.11 F
8
7
6
5
4
3
2
1
PGD
COVC
0.22 F
CPGD
0.022 F
CVCC
1.0 F
NCP5331
26
CS2
0.1 F
VID4
RS1
10 k
VID3
VID2
VID1
VID0
RS2
10 k
12 V
5 VSB
17
18
19
20
21
22
23
CL
1.0 F
GL1
GND1
GH1
CBOUT
VCCH
GH2
GND2
GL2
24
D2
D3
CCB
1.0 F
Q4
C3
4700 pF
SWNODE1
R6
2
CP1
1.0 F
L3
300 nH
Q8
SWNODE2
Q7
Q6
C2
0.33 F
Q1
RCB
6.2 k
Q5
CH
1.0 F
D4
BAT54CLT1
+12 V
+12 VPWR
C4
4700 pF
R7
2
CP2
1.0 F
+
CO1
L2
825 nH
Q9
L1
825 nH
VCORE
CIN
CO4
CO3
CO2
+
LGND Ties to PGND
at 1 Point
CFFB
0.01 F
CREF
0.1 F
1.0 M
RDRP
14.7 k
CA1
0.01 F
ILIM
C5VSB
0.1 F
R5
3
7.0 V
+
COREFB#
ILIM
CSA
0.1 F
COREFB+
R3
56
VCORE
RC1
7.5 k
32
9
CC2
0.1 F
31
10
CC1
2.2 nF
5 VSB
30
11
D1
7.5 V, 5%
BZX84C7V5LT3
Q7
MMBT2132LT3
29
12
R2
910
27
C1
10 F
28
13
+12 V
25
COMP
ILIM
5 VSB
PGD
CPGD
COVC
VCCL
VCCL1
14
3
15
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ROSC
−SEN
VID0
VID1
VID2
VID3
VID4
VCCL2
Recommended Components:
Q1, Q4: ON Semiconductor NTD60N03 (60 A, 28 V, 6.1 m)
Q5−Q9: ON Semiconductor NTD80N02 (80 A, 24 V, 5.0 m)
L1, L2: Coiltronics CTX22−15274 or T50−8B/90 w/ 6 T of #16
AWG Bifilar (1 m)
L3: Coiltronics CTX15−14771 or T30−26 w/ 3 T of #16 AWG
16
R1
15
NCP5331
CIN: 5 × Rubycon 16MBZ1500M10X20 (1500 F, 16 V, 2.55 ARMS)
CO1: 10 × Rubycon 16MBZ1000M10X16 (1000 F, 16 V, 19 m)
CO2: 24 × TDK C2012X5R0J106M (10 F, 6.3 V, 0805)
CO3: 16 × TDK C1608X5R1A224KT (0.22 F, 10 V, 0603)
CO4: 2 × Sanyo PosCAP 6TPD330M (330 F, 6.3 V, 10 m, 4.4 ARMS)
NCP5331
MAXIMUM RATINGS*
Rating
Value
Unit
Operating Junction Temperature
150
°C
Lead Temperature Soldering
SMD Reflow Profile (60 seconds maximum)
230
183
°C peak
°C
−65 to 150
°C
52
°C/W
2.0
kV
TBD
−
Storage Temperature Range
Package Thermal Resistance:
Junction−to−Ambient, RJA
ESD Susceptibility (Human Body Model)
JEDEC Moisture Sensitivity
*The maximum package power dissipation must be observed.
MAXIMUM RATINGS
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
COMP
6.0 V
−0.3 V
1.0 mA
1.0 mA
VFB
6.0 V
−0.3 V
1.0 mA
1.0 mA
VDRP
6.0 V
−0.3 V
1.0 mA
1.0 mA
CS1, CS2
6.0 V
−0.3 V
1.0 mA
1.0 mA
CSREF
6.0 V
−0.3 V
1.0 mA
1.0 mA
ROSC
6.0 V
−0.3 V
1.0 mA
1.0 mA
PGD
6.0 V
−0.3 V
1.0 mA
8.0 mA
VID Pins
6.0 V
−0.3 V
1.0 mA
1.0 mA
ILIM
6.0 V
−0.3 V
1.0 mA
1.0 mA
5 VREF
6.0 V
−0.3 V
1.0 mA
20 mA
CBOUT
13.2 V
−0.3 V
1.0 mA
4.0 mA
CPGD
6.0 V
−0.3 V
1.0 mA
1.0 mA
COVC
6.0 V
−0.3 V
1.0 mA
1.0 mA
VCCL
16 V
−0.3 V
N/A
50 mA
VCCH
20 V
−0.3 V
N/A
1.5 A for 1.0 s,
200 mA dc
VCCLx
16 V
−0.3 V
N/A
1.5 A for 1.0 s,
200 mA dc
5 VSB
6.0 V
−0.3 V
N/A
1.0 mA
GHx
20 V
−2.0 V for 100 ns,
−0.3 V dc
1.5 A for 1.0 s,
200 mA dc
1.5 A for 1.0 s,
200 mA dc
GLx
16 V
−2.0 V for 100 ns,
−0.3 V dc
1.5 A for 1.0 s,
200 mA dc
1.5 A for 1.0 s,
200 mA dc
GND1, GND2
0.3 V
−0.3 V
2.0 A for 1.0 s,
200 mA dc
N/A
LGND
0V
0V
50 mA
N/A
−SEN
0.3 V
−0.3 V
1.0 mA
1.0 mA
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4
NCP5331
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCCL < 16 V; 9.0 V < VCCH < 20 V;
9.0 V < VCCL1 = VCCL2 < 14 V; CGATE = 3.3 nF, RROSC = 32.4 k, CCOMP = 1.0 nF, C5V(REF) = 0.1 F, DAC Code 01110 (1.2 V),
CVCC = 1.0 F, 0.25 V ≤ ILIM ≤ 1.0 V; unless otherwise noted)
Test Conditions
Characteristic
Min
Typ
Max
Unit
Voltage Identification DAC
Voltage Identification (VID) Codes
Measure VFB = COMP,
COMP −SEN
SEN = LGND
VID4
VID3
VID2
VID1
VID0
0
0
0
0
0
−
−
1.550
−
V
0
0
0
0
1
−
−
1.525
−
V
0
0
0
1
0
−
−
1.500
−
V
0
0
0
1
1
−
−
1.475
−
V
0
0
1
0
0
−
−
1.450
−
V
0
0
1
0
1
−
−
1.425
−
V
0
0
1
1
0
−
−
1.400
−
V
0
0
1
1
1
−
−
1.375
−
V
0
1
0
0
0
−
−
1.350
−
V
0
1
0
0
1
−
−
1.325
−
V
0
1
0
1
0
−
−
1.300
−
V
0
1
0
1
1
−
−
1.275
−
V
0
1
1
0
0
−
−
1.250
−
V
0
1
1
0
1
−
−
1.225
−
V
0
1
1
1
0
−
−
1.200
−
V
0
1
1
1
1
−
−
1.175
−
V
1
0
0
0
0
−
−
1.150
−
V
1
0
0
0
1
−
−
1.125
−
V
1
0
0
1
0
−
−
1.100
−
V
1
0
0
1
1
−
−
1.075
−
V
1
0
1
0
0
−
−
1.050
−
V
1
0
1
0
1
−
−
1.025
−
V
1
0
1
1
0
−
−
1.000
−
V
1
0
1
1
1
−
−
0.975
−
V
1
1
0
0
0
−
−
0.950
−
V
1
1
0
0
1
−
−
0.925
−
V
1
1
0
1
0
−
−
0.900
−
V
1
1
0
1
1
−
−
0.875
−
V
1
1
1
0
0
−
−
0.850
−
V
1
1
1
0
1
−
−
0.825
−
V
1
1
1
1
0
−
−
0.800
−
V
1
1
1
1
1
−
Shutdown
V
System Accuracy
Percent deviation from programmed VID codes
−0.8
−
0.8
%
Shutdown Time Delay
VID = 11111
5.0
10
15
s
Input Threshold
VID0−VID4
1.00
1.25
1.50
V
VID Pin Bias Current
VID0−VID4
12
25
40
A
−
2.3
2.6
V
VID Pin Clamp Voltage
−
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5
NCP5331
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCCL < 16 V; 9.0 V < VCCH < 20 V;
9.0 V < VCCL1 = VCCL2 < 14 V; CGATE = 3.3 nF, RROSC = 32.4 k, CCOMP = 1.0 nF, C5V(REF) = 0.1 F, DAC Code 01110 (1.2 V),
CVCC = 1.0 F, 0.25 V ≤ ILIM ≤ 1.0 V; unless otherwise noted)
Characteristic
Test Conditions
Min
Typ
Max
Unit
40
80
120
A
−
−150
−
200
mV
−
175
290
425
s
Voltage Identification DAC (continued)
−SEN Bias Current
LGND < 55 mV, All DAC Codes
−SEN Offset from GND
Power Good Output
Internal Delay Time
PWRGD Low Output Voltage
IPGD = 4.0 mA
−
250
400
mV
Output Leakage Current
VPGD = 5.5 V
−
0.1
2.0
A
VCORE/CSREF Comparator
Threshold Voltage
Tolerance from DAC Setting
−15%
−12.5%
−10%
%
CPGD Charge Current
ROSC = 32.4 k
14.5
16
17.5
A
2.8
3.0
3.2
V
4.8
6.0
7.8
ms
CPGD Comparator Threshold
Voltage
CPGD External Delay Time
−
CPGD = 0.033 F. Note 1.
Voltage Feedback Error Amplifier
VFB Bias Current
0.7 V < VFB < 1.6 V. Note 2.
9.4
10.3
11.1
A
COMP Source Current
COMP = 0.5 V to 2.0 V; VFB = 0.8 V
15
30
60
A
COMP Sink Current
COMP = 0.5 V to 2.0 V; VFB = 1.5 V
15
30
60
A
0.20
0.33
0.40
V
−
32
−
mmho
−
2.5
−
M
COMP Discharge Threshold
Voltage
Transconductance
−
−10 A < ICOMP < +10 A
Output Impedance
−
Open Loop Dc Gain
Note 1.
60
90
−
dB
Unity Gain Bandwidth
CCOMP = 0.01 F
−
400
−
kHz
−
70
−
dB
−
PSRR @ 1.0 kHz
COMP Max Voltage
VFB = 0.8 V, COMP Open
4.1
4.4
−
V
COMP Min Voltage
VFB = 1.5 V, COMP Open
−
0.1
0.2
V
Hiccup Latch Discharge Current
−
4.0
7.5
13
A
Hiccup Latch Charge/Discharge
Ratio
−
−
4.0
−
−
−
235
280
ns
0.45
0.60
0.80
V
PWM Comparators
Minimum Pulse Width
CS1 = CS2 = CSREF
Channel Start−Up Offset
CS1 = CS2 = VFB = CSREF = 0 V;
Measure COMP when GHx switch High
Overcurrent Shutdown Timer
Overcurrent Shutdown Voltage
Threshold
−
2.8
3.0
3.2
V
COVC Low Output Voltage
−
−
250
400
mV
COVC Source Current
−
3.0
5.0
8.0
A
1. Guaranteed by design. Not tested in production.
2. The VFB Bias Current changes with the value of ROSC per Figure 5.
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6
NCP5331
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCCL < 16 V; 9.0 V < VCCH < 20 V;
9.0 V < VCCL1 = VCCL2 < 14 V; CGATE = 3.3 nF, RROSC = 32.4 k, CCOMP = 1.0 nF, C5V(REF) = 0.1 F, DAC Code 01110 (1.2 V),
CVCC = 1.0 F, 0.25 V ≤ ILIM ≤ 1.0 V; unless otherwise noted)
Characteristic
Test Conditions
Min
Typ
Max
Unit
65
120
230
ms
2.0
2.1
2.2
V
Overcurrent Shutdown Timer (continued)
Overcurrent Shutdown Time
COVC = 0.22 F. Note 3.
Internal Overvoltage Protection (OVP)
Overvoltage Threshold
LGND = 0 V, VFB = 0 V, CSREF = 0 V,
Increase CSREF until GL1 and GL2 switch High.
External Overvoltage Protection (CBOUT)
Overvoltage Positive Threshold
5 VSB = 5.0 V, LGND = 0 V, CSREF = 0 V,
Increase CSREF until CBOUT = High.
2.0
2.1
2.2
V
Overvoltage Negative Threshold
5 VSB = 5.0 V, LGND = 0 V, CSREF = 3.0 V,
Decrease CSREF until CBOUT = Low.
0.8
0.9
1.0
V
−
−
2.0
mA
6.6 k Pull−Up to 13.2 V
−
−
0.4
V
High Voltage (AC)
Measure VCCLx − GLx or VCCHx − GHx. Note 3.
−
0
1.0
V
Low Voltage (AC)
Measure GLx or GHx. Note 3.
−
0
0.5
V
Rise Time GHx
1.0 V < GHx < 8.0 V; VCCH = 10 V
−
35
80
ns
Rise Time GLx
1.0 V < GLx < 8.0 V; VCCLx = 10 V
−
35
80
ns
Fall Time GHx
8.0 V > GHx > 1.0 V; VCCH = 10 V
−
35
80
ns
Fall Time GLx
8.0 V > GLx > 1.0 V; VCCLx = 10 V
−
35
80
ns
GHx to GLx Delay
GHx < 2.0 V, GLx > 2.0 V
30
65
110
ns
GLx to GHx Delay
GLx < 2.0 V, GHx > 2.0 V
30
65
110
ns
GATE Pull−Down
Force 100 A into GATE with no power applied to
VCCH and VCCLx = 2.0 V.
−
1.2
1.6
V
CBOUT Maximum Allowable
Sink Current
CBOUT Low Voltage
−
GATE DRIVERS
Oscillator
Switching Frequency
ROSC = 32.4 k
255
300
345
kHz
Switching Frequency
ROSC = 63.4 k; Note 3.
110
150
190
kHz
Switching Frequency
ROSC = 16.2 k; Note 3.
450
600
750
kHz
ROSC Voltage
−
−
1.0
−
V
Phase Delay
−
165
180
195
deg
Adaptive Voltage Positioning
VDRP Output Voltage to
DACOUT Offset
CS1 = CS2 = CSREF, VFB = COMP,
Measure VDRP − COMP
Maximum VDRP Voltage
10 mV ≤ (CS1 = CS2) − CSREF ≤ 50 mV,
VFB = COMP, Measure VDRP − COMP
300
400
500
mV
Current Sense Amp to VDRP
Gain
10 mV ≤ (CS1 = CS2) − CSREF ≤ 50 mV
VFB = COMP, Measure VDRP − COMP
3.9
4.2
4.75
V/V
3. Guaranteed by design. Not tested in production.
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7
6
mV
NCP5331
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCCL < 16 V; 9.0 V < VCCH < 20 V;
9.0 V < VCCL1 = VCCL2 < 14 V; CGATE = 3.3 nF, RROSC = 32.4 k, CCOMP = 1.0 nF, C5V(REF) = 0.1 F, DAC Code 01110 (1.2 V),
CVCC = 1.0 F, 0.25 V ≤ ILIM ≤ 1.0 V; unless otherwise noted)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Current Sensing
CS1−CS2 Input Bias Current
CSx = CSREF = 0 V
−
0.1
0.5
A
CSREF Input Bias Current
CSx − CSREF = 50 mV
−
0.35
1.5
A
80
110
145
k
VFFB Pull−Up Resistor
−
Current Sense Amplifier Gain
CSx − CSREF = 40 mV
1.85
2.1
2.35
V/V
Current Sense Input to ILIM
Gain
ILIM = 1.00 V
9.5
12
14
V/V
4.0
7.0
13
mV/s
Current Limit Filter Slew Rate
−
ILIM Operating Voltage Range
Note 4.
−
−
3.0
V
ILIM Bias Current
0 < ILIM < 1.0 V
−
0.1
1.0
A
Current Sense Amplifier
Bandwidth
Note 4.
1.0
−
−
MHz
General Electrical Specifications
VCCL Operating Current
VFB = COMP (no switching)
−
22
26
mA
VCCL1 or VCCL2 Operating
Current
VFB = COMP (no switching)
−
5.0
10
mA
VCCH Operating Current
VFB = COMP (no switching)
−
6.4
9.0
mA
5 VSB Quiescent Current
CBOUT = Low
−
−
400
A
VCCL Start Threshold
GATEs switching, COMP charging
8.1
8.5
8.9
V
VCCL Stop Threshold
GATEs stop switching, COMP discharging
5.75
6.15
6.55
V
VCCL Hysteresis
GATEs not switching, COMP not charging
2.05
2.35
2.65
V
VCCH Start Threshold
GATEs switching, COMP charging
8.1
8.5
8.9
V
VCCH Stop Threshold
GATEs stop switching, COMP discharging
6.35
6.75
7.15
V
VCCH Hysteresis
GATEs not switching, COMP not charging
1.45
1.75
2.05
V
0 mA < I(5 VREF) < 1.0 mA
4.85
5.0
5.15
V
−
125
−
mV
Reference Output
5 VREF Output Voltage
Internal Ramp
Ramp Height @ 50% PWM
Duty Cycle
CS1 = CS2 = CSREF
4. Guaranteed by design. Not tested in production.
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8
NCP5331
PACKAGE PIN DESCRIPTION
Pin No.
Symbol
Description
1
VFB
Voltage Feedback Pin. To use Adaptive Voltage Positioning (AVP), set the light load offset voltage
by connecting a resistor between VFB and VCORE. The resistor and the VFB bias current determine
the offset. For no adaptive positioning connect VFB directly to VCORE.
2
VDRP
Current sense output for Adaptive Voltage Positioning (AVP). The offset of this pin above the DAC
voltage is proportional to the output current. Connect a resistor from this pin to VFB to set the
amount AVP or leave this pin open for no AVP. This pin’s maximum working voltage is 4.1 Vdc.
3
LGND
Return for the internal control circuits and the IC substrate connection.
4, 6
CS1, CS2
5
CSREF
7
VFFB
8
5 VREF
9
ROSC
A resistor from this pin to ground sets the operating frequency and VFB bias current.
10
−SEN
Ground connection for the DAC. Provides remote sensing of ground at the load.
11−15
VID pins
16
VCCL2
17
GL2
Low side driver #2.
18
GND2
Return for driver #2.
19
GH2
High side driver #2.
20
VCCH
Power for GH1 and GH2.
21
CBOUT
22
GH1
High side driver #1.
23
GND1
Return for driver #1.
24
GL1
Low side driver #1.
25
VCCL1
Power for GL1.
26
VCCL
Power for the internal control circuits. UVLO sense for Logic connects to this pin.
27
COVC
A capacitor from this pin to ground sets the time the controller will be in hiccup mode current limit.
This timer is started by the first overcurrent condition (set by the ILIM voltage). Once timed out, voltage at the VCCL pin must be cycled to reset this fault. Connecting this pin to LGND ±200 mV will
disable this function and hiccup mode current limit will operate indefinitely.
28
CPGD
A capacitor from this pin to ground sets the programmable time between when VCORE crosses the
PWRGD threshold and when the open−collector PWRGD pin transitions from a logic Low to a logic
High. The minimum delay is internally set to 200 s. Connecting this pin to 5 VREF will disable the
programmable timer and the delay will be set to the internal delay.
29
PGD
Power Good output. Open collector output that will transition Low when CSREF (VCORE) is out of
regulation.
30
5 VSB
Input power for the CBOUT circuitry. To provide maximum overvoltage protection to the CPU, this pin
should be connected to 5 VSB from the ATX supply (ATX, pin 9). If the CBOUT function is not used,
this pin must be connected to the NCP5331 controller’s internal voltage reference (5 VREF, pin 8).
31
ILIM
Sets the threshold for current limit. Connect to reference through a resistive divider. This pin’s maximum working voltage is 3.0 Vdc.
32
COMP
Current sense inputs. Connect the current sense network for the corresponding phase to each input. The input voltages to these pins must be kept within 125 mV of CSREF.
Reference for both differential current sense amplifiers. To balance input offset voltages between
the inverting and non−inverting inputs of the Current Sense Amplifiers, connect this pin to the output
voltage through a resistor equal to one third of the value of the current sense resistors.
Fast Feedback connection to the PWM comparators and input to the Power Good comparator.
Reference output. Decouple to LGND with 0.1 F.
Voltage ID DAC inputs. These pins are internally pulled up and clamped at 2.3 V if left unconnected.
Power for GL2.
Open−collector crowbar output pin. This pin is high impedance when an overvoltage condition is
detected at CSREF. Connect this pin to the gate of a MOSFET or SCR to crowbar either VCORE or
VIN to GND. To prevent failure of the crowbar device, this pin should be used in conjunction with
logic on the motherboard to disable the ATX supply via PSON and/or a relatively fast fuse should be
placed upstream to disconnect the input voltage.
Output of the error amplifier and input for the PWM comparators.
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Figure 2. Block Diagram, Control Functions
LGND
ROSC
VFFB
CS2
CSREF
CS1
−SEN
VID2
VID3
VID4
VID0
VID1
100 k
5.0 VREF
+
11111
OUT
ITOTAL
10 s
Delay
OSC
OSCIBIAS Current
Gen
VFB_BIAS
−
+
GCSA2
2.0
+
−
GCSA1
2.0
5−Bit DAC
5.0 VREF
PH2
PH1
GVDRP
2.0
+
VDRP
11111
Shutdown
VFB
DAC Out
Over
Fault
−+
CSREF
+−
12.5% of
DAC
SU Offset
0.6 V
PH2 Current
RAMP2
RAMP1
PH1 Current
DAC Out
−
+
Error Amp
+
+
−
+
PGD
Comparator
1 = ON
COMP
PH2
Fault
PH1
PGD No Delay
7.5 A
COMP
Discharge
PWMC2
+
−
PWMC1
−
+
R
S
R
S
Q
Int. Delay
200 s
D
F/F
Q
Q
RESET
Dominant
D
F/F
Q
RESET
Dominant
Gate Driver
+−
3.0 V/0.5 V
UVLO
1 = ON
7.5 A
15 A
5.0 VREF
PGD
EXT Delay
Over
Gate Driver
COMP_LO
Non−Overlap
Non−Overlap
5.0 VREF
+
−
VCCL
VCCH
CPGD
PGD
GND2
GL2
VCCL2
GH2
GND1
GL1
VCCL1
GH1
NCP5331
ILIM
CSREF
ITOTAL
GILIM
6.0
+
−
Figure 3. Block Diagram, Protection
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VCCL
Slew
Rate
Limit
CBOUT
+
−
2.0V
+
−
VCCH
PGD
Start 8.50 V
Stop 6.15 V
−
+
−
+
Current Limit
External Crowbar
2.05 V/0.75 V
5 VSB
Overvoltage
+
−
UVLO
Q
Q
VCCH Fault
VCCL Fault
Overcurrent
SET
Dominant
D
F/F
Start 8.50 V
Stop 6.75 V
−
+
R
S
OVC Timer
Internal Crowbar
+
−
COVC
+
−
0.27 V
COMP
UVLO
+ 3.0V
−
5.0 A
5.0 VREF
+ COMP Discharge
− Threshold
−
+
R
S
R
S
D
F/F
Q
Q
RESET
Dominant
Q
COMP_LO
SET
Dominant
D
F/F
Q
Fault Latch
11111 Shutdown
UVLO
COMP Reset
Overcurrent
Overcurrent
and
Overvoltage
Latch
Over
Fault
NCP5331
NCP5331
NCP5331
Controller
5.0 V
25 A
VID0−VID4
Hi or Lo
0.65 V
+ 1.65 V
−
Figure 4. Simplified VID Pin Input Circuitry
TYPICAL PERFORMANCE CHARACTERISTICS
600
25
550
VFB Bias Current, A
20
450
400
350
300
250
15
10
5
200
150
100
10
20
30
40
50
0
10
70
60
20
30
ROSC (k)
Figure 5. Oscillator Frequency vs. ROSC Value
VSOURCE = 5 V
600
Minimum NCP5331
Pulse Width = 280 ns
550
500
450
400
350
VSOURCE = 12 V
300
VCORE (V)
Figure 7. Maximum Frequency vs. VCORE
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1.550
1.500
1.450
1.400
1.350
1.300
1.250
1.200
1.150
1.100
1.050
1.000
0.950
0.900
0.800
0.850
250
200
40
50
ROSC Value, k
60
Figure 6. VFB Current vs. ROSC Value
650
Maximum Frequency (kHz)
Frequency (kHz)
500
70
80
NCP5331
TYPICAL PERFORMANCE CHARACTERISTICS
5.15
4.8
4.7
5.10
4.6
5.0 VREF (V)
Gain (V/V)
4.5
4.4
4.3
4.2
5.05
5.00
4.95
4.1
4.90
4.0
3.9
0
10
20
30
40
50
60
4.85
70
0
10
20
30
40
50
60
70
Temperature (°C)
Temperature (°C)
Figure 8. CSA to VDRP Gain vs. Temperature
Figure 9. 5.0 VREF Output Voltage vs.
Temperature
25
14.0
13.5
20
13.0
15
Vdp (mV)
Gain (V/V)
12.5
12.0
11.5
10
5
11.0
10.5
0
10.0
9.5
0
10
20
30
40
50
60
−5
0
70
10
20
30
40
50
60
Temperature (°C)
Temperature (°C)
Figure 10. CSA to ILIM Gain vs. Temperature
Figure 11. VDRP Output to DACOUT Offset vs.
Temperature
11.0
70
15
VCORE Percent of DAC (%)
10.8
IFB ;(A)
10.6
10.4
10.2
10.0
9.8
14
13
12
11
9.6
9.4
0
10
20
30
40
50
60
10
70
0
Temperature (°C)
10
20
30
40
50
60
Temperature (°C)
Figure 12. VFB Bias Current vs. Temperature
Figure 13. PGD Threshold vs. Temperature
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70
NCP5331
APPLICATIONS INFORMATION
Overview
converters are connected in parallel, output current can ramp
up or down faster than a single converter (with the same
value output inductor) and heat is spread among multiple
components.
The NCP5331 controller uses a two−phase, fixed
frequency, Enhanced V2 architecture to measure and control
currents in individual phases. Each phase is delayed 180°
from the previous phase. Normally, GHx (x = 1 or 2)
transitions to a high voltage at the beginning of each
oscillator cycle. Inductor current ramps up until the
combination of the current sense signal, the internal ramp
and the output voltage ripple trip the PWM comparator and
bring GHx low. Once GHx goes low, it will remain low until
the beginning of the next oscillator cycle. While GHx is
high, the Enhanced V2 loop will respond to line and load
variations (i.e. the upper gate on−time will be increased or
reduced as required). On the other hand, once GHx is low,
the loop can not respond until the beginning of the next
PWM cycle. Therefore, constant frequency Enhanced V2
will typically respond to disturbances within the off−time of
the converter.
The Enhanced V2 architecture measures and adjusts the
output current in each phase. An additional input, CSx (x =
1 or 2), for inductor current information has been added to the
V2 loop for each phase as shown in Figure 14. The triangular
inductor current is measured differentially across RS,
amplified by CSA and summed with the Channel Startup
Offset, the Internal Ramp, and the Output Voltage at the
noninverting input of the PWM comparator. The purpose of
the Internal Ramp is to compensate for propagation delays in
the NCP5331. This provides greater design flexibility by
allowing smaller external ramps, lower minimum pulse
widths, higher frequency operation, and PWM duty cycles
above 50% without external slope compensation. As the sum
of the inductor current and the internal ramp increase, the
voltage on the positive pin of the PWM comparator rises and
terminates the PWM cycle. If the inductor starts a cycle
The NCP5331 dc/dc controller utilizes an Enhanced V2
topology to meet requirements of low voltage, high current
loads with fast transient requirements. Transient response
has been improved and voltage jitter virtually eliminated by
including an internal PWM ramp, connecting fast−feedback
from VCORE directly to the internal PWM comparator, and
precise routing and grounding inside the controller.
Advanced features such as adjustable power−good delay,
programmable overcurrent shutdown time, superior
overvoltage protection (OVP), and differential remote
voltage sensing make it easy to obtain AMD certification.
An innovative overvoltage protection (OVP) scheme
safeguards the CPU during extreme situations including
power up with a shorted upper MOSFET, shorting of an
upper MOSFET during normal operation, and loss of the
voltage feedback signal, COREFB+. The NCP5331
provides a “fully integrated solution” to simplify design,
minimize circuit board area, and reduce overall system cost.
Two advantages of a multiphase converter over a
single−phase converter are current sharing and increased
apparent output frequency. Current sharing allows the
designer to use less inductance in each phase than would be
required in a single−phase converter. The smaller inductor
produces larger ripple currents but the total per phase power
dissipation is reduced because the rms current is lower.
Transient response is improved because the control loop will
measure and adjust the current faster in a smaller output
inductor. Increased apparent output frequency is desirable
because the off−time and the ripple voltage of the two−phase
converter will be less than that of a single−phase converter.
Fixed Frequency Multiphase Control
In a multiphase converter, multiple converters are
connected in parallel and are switched on at different times.
This reduces output current from the individual converters
and increases the apparent ripple frequency. Because several
SWNODE
CSx
Lx
RLx
+
CSA
−
x = 1 or 2
RSx
COn
Internal Ramp
CSREF
−+
VOUT
(VCORE)
VFFB
“Fast−Feedback”
Connection
VFB
+
Channel
Start−Up
Offset
−
DAC
Out
+
COMP
To F/F
Reset
+
−
PWM
COMP
Error
Amp
Figure 14. Enhanced V2 Control Employing Resistive Current Sensing and Additional Internal Ramp
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NCP5331
RSx
SWNODE
CSx
+
CSA
−
x = 1 or 2
Lx
CSx
COn
Internal Ramp
RLx
CSREF
−+
VOUT
(VCORE)
“Fast−Feedback”
Connection
VFFB
VFB
+
−
DAC
Out
+
COMP
Channel
Start−Up
Offset
To F/F
Reset
+
−
PWM
COMP
Error
Amp
Figure 15. Enhanced V2 Control Employing Lossless Inductive Current Sensing and Internal Ramp
VCOMP VCORE @ 0 A Channel_Startup_Offset
with higher current, the PWM cycle will terminate earlier
providing negative feedback. The NCP5331 provides a CSx
input for each phase, but the CSREF and COMP inputs are
common to all phases. Current sharing is accomplished by
referencing all phases to the same CSREF and COMP pins,
so that a phase with a larger current signal will turn off earlier
than a phase with a smaller current signal.
Enhanced V2 responds to disturbances in VCORE by
employing both “slow” and “fast” voltage regulation. The
internal error amplifier performs the slow regulation.
Depending on the gain and frequency compensation set by
the amplifier’s external components, the error amplifier will
typically begin to ramp its output to react to changes in the
output voltage in 1−2 PWM cycles. Fast voltage feedback is
implemented by a direct connection from VCORE to the
noninverting pin of the PWM comparator via the summation
with the inductor current, internal ramp, and the Startup
OFFSET. A rapid increase in load current will produce a
negative offset at VCORE and at the output of the summer.
This will cause the PWM duty cycle to increase almost
instantly. Fast feedback will typically adjust the PWM duty
cycle within 1 PWM cycle.
As shown in Figure 14, an internal ramp (nominally 125 mV
at a 50% duty cycle) is added to the inductor current ramp at
the positive terminal of the PWM comparator. This additional
ramp compensates for propagation time delays from the
current sense amplifier (CSA), the PWM comparator, and the
MOSFET gate drivers. As a result, the minimum ON time of
the controller is reduced and lower duty cycles may be
achieved at higher frequencies. Also, the additional ramp
reduces the reliance on the inductor current ramp and allows
greater flexibility when choosing the output inductor and the
RSxCSx (x = 1 or 2) time constant (see Figure 15) of the
feedback components from VCORE to the CSx pin.
Including both current and voltage information in the
feedback signal allows the open loop output impedance of
the power stage to be controlled. When the average output
current is zero, the COMP pin will be
Int_Ramp GCSA Ext_Ramp2
Int_Ramp is the internal ramp value at the corresponding
duty cycle, Ext_Ramp is the peak−to−peak external
steady−state ramp at 0 A, GCSA is the Current Sense
Amplifier Gain (nominally 2.0 V/V), and the Startup Offset
is typically 0.60 V. The magnitude of the Ext_Ramp can be
calculated from
Ext_Ramp D (VIN VCORE)(RSx CSx fSW)
For example, if VCORE at 0 A is set to 1.225 V with AVP
and the input voltage is 12.0 V, the duty cycle (D) will be
1.225/12.0 or 10.2%. Int_Ramp will be 125 mV ⋅ 10.2/50 =
25.5 mV. Realistic values for RSx, CSx and fSW are 5.6 k,
0.1 F, and 200 kHz − using these and the previously
mentioned formula, Ext_Ramp will be 9.8 mV.
VCOMP 1.225 V 0.60 V 25.5 mV
2.0 VV 9.8 mV2
1.855 Vdc.
If the COMP pin is held steady and the inductor current
changes, there must also be a change in the output voltage.
Or, in a closed loop configuration when the output current
changes, the COMP pin must move to keep the same output
voltage. The required change in the output voltage or COMP
pin depends on the scaling of the current feedback signal and
is calculated as
V RSx GCSA IOUT.
The single−phase power stage output impedance is
Single Stage Impedance VOUTIOUT RS GCSA
The multiphase power stage output impedance is the
single−phase output impedance divided by the number of
phases. The output impedance of the power stage determines
how the converter will respond during the first few
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NCP5331
be considered. Cores with a low permeability material or a
large gap will usually have minimal inductance change with
temperature and load. Copper magnet wire has a
temperature coefficient of 0.39% per °C. The increase in
winding resistance at higher temperatures should be
considered when setting the overcurrent (ILIM)threshold. If
a more accurate current sense is required than inductive
sensing can provide, current can be sensed through a resistor
as shown in Figure 14.
SWNODE
VFB (VOUT)
Internal Ramp
Current Sharing Accuracy
CSA Out w/
Exaggerated
Delays
Printed circuit board (PCB) traces that carry inductor
current can be used as part of the current sense resistance
depending on where the current sense signal is connected.
For accurate current sharing, the current sense inputs should
sense the current at relatively the same point for each phase
and the connection to the CSREF pin should be made so that
no phase is favored. In some cases, especially with inductive
sensing, resistance of the PCB can be useful for increasing
the current sense resistance. The total current sense
resistance used for calculations must include any PCB trace
resistance between the CSx input and the CSREF input that
carries inductor current.
Current Sense Amplifier (CSA) input mismatch and the
value of the current sense component will determine the
accuracy of the current sharing between phases. The worst
case Current Sense Amplifier input mismatch is ±5.0 mV
and will typically be within ±3.0 mV. The difference in peak
currents between phases will be the CSA input mismatch
divided by the current sense resistance. If all current sense
components are of equal resistance a 3.0 mV mismatch with
a 2.0 m total sense resistance will produce a 1.5 A
difference in current between phases.
COMP−Offset
CSA Out + Ramp + CSREF
T1
T2
Figure 16. Open Loop Operation
microseconds of a transient before the feedback loop has
repositioned the COMP pin.
The peak output current can be calculated from
IOUT,PEAK (VCOMP VCORE Offset)
(RSx GCSA)
Figure 16 shows the step response of the COMP pin at a
fixed level. Before time T1 the converter is in normal steady
state operation. The inductor current provides a portion of
the PWM ramp through the Current Sense Amplifier. The
PWM cycle ends when the sum of the current ramp, the
internal ramp voltage and Startup OFFSET exceed the
voltage level of the COMP pin. At T1 the output current
increases and the output voltage sags. The next PWM cycle
begins and this PWM cycle continues longer than
previously. As a result, the current signal increases enough
to make up for the lower voltage at the VFB pin and the cycle
ends at T2. After T2 the output voltage remains lower than
at light load and the average current signal level (CSx
output) is raised so that the sum of the current and voltage
signal is the same as with the original load. In a closed loop
system the COMP pin would move higher to restore the
output voltage to the original level.
External Ramp Size and Current Sensing
The internal ramp allows flexibility of current sense time
constant. Typically, the current sense RSxCSx time constant
should be equal to or slower than the inductor’s time
constant. If the RC time constant is chosen to be smaller
(faster) than L/RL, the ac or transient portion of the current
sensing signal will be scaled larger than the dc portion. This
will provide a larger steady state ramp, but circuit
performance (i.e. transient response) will be affected and
must be evaluated carefully. The current signal will
overshoot during transients and settle at the rate determined
by RSx ⋅ CSx. It will eventually settle to the correct dc level,
but the error will decay with the time constant of RSx ⋅ CSx.
If this error is excessive it will effect transient response,
adaptive positioning and current limit. During a positive
current transient, the COMP pin will be required to
undershoot in response to the current signal in order to
maintain the output voltage. Similarly, the VDRP signal will
overshoot and will produce too much transient droop in the
output voltage. Also, the hiccup mode current limit will have
a lower threshold for fast rise step loads than for slowly
rising output currents.
Inductive Current Sensing
For lossless sensing, current can be sensed across the
output inductor as shown in Figure 15. In the diagram, Lx is
the output inductance and RLx is the inherent inductor
resistance. To compensate the current sense signal, the
values of RSx and CSx are chosen so that Lx/RLx = RSx ⋅
CSx. If this criteria is met, the current sense signal will be the
same shape as the inductor current and the voltage signal at
CSx will represent the instantaneous value of inductor
current. Also, the circuit can be analyzed as if a sense resistor
of value RLx was used as a sense resistor (RSx).
When choosing or designing inductors for use with
inductive sensing, tolerances and temperature effects should
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NCP5331
The waveforms in Figure 17 show a simulation of the
current sense signal and the actual inductor current during
a positive step in load current with values of L = 500 nH,
RL = 1.6 m, RSx = 20 k and CSx = 0.01 F. For ideal current
signal compensation the value of RSx should be 31 k. Due
to the faster than ideal RC time constant there is an overshoot
of 50% and the overshoot decays with a 200 s time
constant. With this compensation the ILIM pin threshold
must be set more than 50% above the full load current to
avoid triggering hiccup mode during a large output load
step.
Current Limit, Hiccup Mode and Overcurrent Timer
The individual phase currents are summed and low−pass
filtered to create an average current signal. The average
current is then compared to a user adjustable voltage at the
ILIM pin. If the ILIM voltage is exceeded, the fault latch is set,
switching stops, and the COMP pin is discharged until it
decreases to 0.27 V. At this point, the fault latch is reset, the
COMP voltage will begin to rise and a new startup cycle
begins. During startup, the output voltage and load current
will increase until either regulation is achieved or the ILIM
voltage is again exceeded. The converter will continue to
operate in “hiccup mode” until the fault condition is
corrected or the overcurrent timer expires.
When an overcurrent fault occurs the converter will enter
a low duty cycle hiccup mode. During hiccup mode the
converter will not switch from the time a fault is detected
until the soft start capacitor (CC2) has discharged below the
COMP Discharge Threshold and then charged back up
above the Channel Start Up Offset. Figure 18 shows the
NCP5331 operating in hiccup mode with the converter
output shorted to GND. Hiccup mode will continue until the
overcurrent timer terminates operation.
The overcurrent timer sets a limit to how long the
converter will operate in hiccup mode. Placing a capacitor
from the COVC pin to GND sets the length of time − a larger
capacitor sets a longer time. The first hiccup pulse starts the
timer by turning on a current source that charges the
capacitor at the COVC pin. If the voltage at the COVC pin rises
to 3 V before the output voltage exceeds the PGD threshold,
then the overcurrent latch is set, COMP is discharged, and
PGD is latched Low. Once set, the overcurrent latch will
hold the converter in this state until the input voltage, either
VCCL or VCCH, is cycled. Conversely, if the timer starts and
either the output short circuit is removed or the load is
decreased before the overcurrent timer expires, PGD will
transition High after its programmed delay time and the
timer will be reset. The nominal overcurrent time can be
calculated using the following equation.
Figure 17. Inductive Sensing Waveform During a
Load Step with Fast RC Time Constant (50 s/div)
Figure 18. Hiccup Mode Operation
tOVC COVC (OVCTHRESH OVCMIN)IOVC
COVC (3.0 V 0.25 V)5.0 A
COVC 5.5 105
Figure 19 shows the overcurrent timer terminating hiccup
mode when COVC charges up to 3.0 V.
Figure 19. Overcurrent Timer Operation
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NCP5331
NOTE:
Using the lower MOSFETs to prevent overvoltage
is not adequate if the MOSFETs are turned OFF at
the UVLO threshold − VCORE reaches 4.0 V within
100 s.
NOTE:
Figure 20. Overvoltage Occurs with UVLO Enabled
Even if the lower MOSFETs remain ON after
UVLO, there is not enough gate drive voltage to
prevent VCORE from reaching 4.0 V.
Figure 21. Overvoltage Occurs with UVLO Disabled
Overvoltage Protection
the CBOUT pin. This additional MOSFET will clamp VCORE
and dissipate the remainder of the energy in the system. The
CBOUT circuitry is powered by 5 VSB and is not disabled
during UVLO. Also, the CBOUT pin will always have
adequate gate drive to enhance the lower MOSFET. The
OVP circuits in the NCP5331 are not effected when the ATX
supply current limits and VIN is removed. Figure 22 and
Figure 23 document successful operation of the CBOUT
circuitry when an upper MOSFET is shorted during normal
operation with 0 A and 45 A loading.
The second most difficult overvoltage scenario is when an
upper MOSFET is shorted and the ATX power is applied. In
this case, VCORE is equal to VIN due to the shorted upper
MOSFET. When VIN reaches the maximum rating for the
CPU (2.2 V) adequate gate drive voltage is not available to
enhance the lower MOSFETs or crowbar device enough to
protect the CPU. A typical “Logic Level” MOSFET will
conduct only 100−300 A for a gate drive of 2.0−2.5 V
(RDS(on) = 6 k to 25 k). The RDS(on) of the crowbar
device must be lower than 15 m during startup to prevent
damage to the CPU. The NCP5331 avoids this problem by
taking advantage of the 5 VSB voltage from the ATX supply.
If VIN is less than 5 VSB, then 5 V will be used to enhance
the crowbar device. Most modern MOSFETs will be less
than 10 m for a VGS greater than 4.5 V. Figure 24 shows
the NCP5331 preventing VCORE from exceeding 2.0 V with
a shorted upper MOSFET during startup.
If the voltage feedback signal (COREFB+) is broken, a
high value internal pull−up resistor will cause VFFB (and
VFB) to float higher in voltage. As VFFB (and VFB) are
pulled higher, the error amplifier will “think” VCORE is too
high and command a lower and lower duty cycle until
VCORE is driven to 0 V. Without the internal pull−up resistor
the error amplifier would command 100% duty cycle and
VCORE would be driven very high, damaging the CPU.
The NCP5331 provides a comprehensive level of
overvoltage protection. Overvoltage protection (OVP)
addresses the following five cases (in decreasing level of
difficulty):
1. Normal operation, upper MOSFET shorts
2. Upper MOSFET shorted, turn on the ATX power
3. Normal operation, open the voltage feedback signal
4. Normal operation, ground the voltage feedback
signal
5. Open the voltage feedback signal, apply ATX power
By far the most difficult overvoltage scenario is when the
upper MOSFET shorts during normal operation. The energy
stored in the output filters of both the ATX supply and the
dc/dc converter must be dissipated very quickly or an
overvoltage condition will occur. When the upper MOSFET
shorts, VCORE rises and the error amplifier, due to the closed
loop control, will within approximately 400 ns, command
the upper MOSFETs (those that aren’t shorted) to turn OFF
and all the lower MOSFETs to turn ON. This will cause two
things to occur: VCORE will stop increasing, and a very high
current will be drawn from the ATX supply. The current
limit in the ATX supply should become active and the input
voltage to the converter will be removed. Now, when the
input voltage drops below the NCP5331’s UVLO threshold
the lower MOSFETs will be turned OFF. At this point, a fair
amount of the energy in the system will have been
dissipated, however, the converter’s output voltage will
begin to rise again as shown in Figure 20. Even if the lower
MOSFETs are not turned OFF at the UVLO threshold, as
VIN decays, adequate gate drive voltage will not exist to
fully enhance the devices and the CPU may be damaged.
This case is shown in Figure 21.
The NCP5331 avoids the problems with UVLO and the
gate drive voltage. When VCORE exceeds 2.05 V, the
NCP5331 will activate an external crowbar MOSFET via
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NCP5331
NOTE:
NOTE:
The NCP5331 maintains VCORE < 2.2 V when an
upper MOSFET shorts during no−load operation.
The NCP5331 maintains VCORE < 2.2 V when an
upper MOSFET shorts with 45 A loading.
Figure 23. NCP5331 Prevents Overvoltage at 45 A
Figure 22. NCP5331 Prevents Overvoltage at 0 A
If the voltage feedback signal (COREFB+) is accidentally
grounded (but VCORE is not), the error amplifier will respond
by increasing the duty cycle. Of course, this will cause VCORE
to rise. When VCORE reaches 2.0 V, the internal crowbar
circuit will be activated and the overcurrent/overvoltage latch
will be set. This latch will discharge COMP, turn OFF the
upper MOSFETs, and turn ON the lower MOSFETs. The
overcurrent/overvoltage latch will hold the controller in this
state until the input power is cycled.
Transient Response and Adaptive Positioning
For applications with fast transient currents the output
filter is frequently sized larger than ripple currents require in
order to reduce voltage excursions during load transients.
Adaptive voltage positioning can reduce peak−to−peak
output voltage deviations during load transients and allow
for a smaller output filter. The output voltage can be set
higher than nominal at light loads to reduce output voltage
sag when the load current is applied. Similarly, the output
voltage can be set lower than nominal during heavy loads to
reduce overshoot when the load current is removed. For low
current applications a droop resistor can provide fast
accurate adaptive positioning. However, at high currents the
loss in a droop resistor becomes excessive. For example; in
a 50 A converter a 1 m resistor to provide a 50 mV change
in output voltage between no load and full load would
dissipate 2.5 W.
Lossless adaptive positioning is an alternative to using a
droop resistor, but must respond to changes in load current.
Figure 25 shows how adaptive positioning works. The
waveform labeled “Normal” shows a converter without
adaptive positioning. On the left, the output voltage sags
when the output current is stepped up and later overshoots
when current is stepped back down. With fast (ideal)
adaptive positioning the peak to peak excursions are cut in
half. In the slow adaptive positioning waveform the output
voltage is not repositioned quickly enough after current is
stepped up and the upper limit is exceeded.
NOTE:
The NCP5331 maintains VCORE < 2.2 V when an
upper MOSFET is shorted and ATX power is applied.
Figure 24. NCP5331 Prevents Overvoltage at Startup
Normal
Fast Adaptive Positioning
Slow Adaptive Positioning
Limits
Figure 25. Adaptive Positioning
The controller can be configured to adjust the output
voltage based on the output current of the converter. (Refer
to the application schematic in Figure 1). To set the no−load
positioning, a resistor is placed between the output voltage
and VFB pin. The VFB bias current will develop a voltage
across the resistor to adjust the no−load output voltage. The
VFB bias current is dependent on the value of ROSC as shown
in the data sheets.
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NCP5331
During no load conditions the VDRP pin is at the same
voltage as the VFB pin, so none of the VFB bias current flows
through the VDRP resistor. When output current increases
the VDRP pin increases proportionally and the VDRP pin
current offsets the VFB bias current and causes the output
voltage to decrease.
The response during the first few microseconds of a load
transient are controlled primarily by power stage output
impedance and the ESR and ESL of the output filter. The
transition between fast and slow positioning is controlled by
the total ramp size and the error amp compensation. If the
current signal (external ramp) size is too large or the error
amp too slow there will be a long transition to the final
voltage after a transient. This will be most apparent with
lower capacitance output filters.
NOTE:
Error Amp Compensation, Tuning, and Soft Start
The PGD timer insures that PGD will transition high
when VCORE is in regulation.
Figure 26. Power Good Delay Operation
The transconductance error amplifier requires a
capacitance (CC1 + CC2 in the Applications Diagram)
between the COMP pin and GND for two reasons. First, this
capacitance stabilizes the transconductance error amplifier.
Values less than a few nF may cause oscillations of the
COMP voltage and increase the output voltage jitter.
Second, this capacitance sets the soft start and hiccup mode
slopes. The internal error amplifier will source
approximately 30 A during soft start and hiccup mode. No
switching will occur until the COMP voltage exceeds the
Channel Startup Offset (nominally 0.6 V). If CC2 is set to
0.1 F the 30 A from the error amplifier will allow the
output to ramp up or down at approximately 30 A/0.1 F
or 0.3 V/ms or 1.2 V in 4 ms.
The COMP voltage will ramp up to the following value.
Setting up and tuning the error amplifier is a three step
process. First, the no−load and full−load adaptive voltage
positioning (AVP) are set using RF1 and RDRP, respectively.
Second, the current sense time constant and error amplifier
gain are adjusted with RSx and CA1 while monitoring
VCORE during transient loading. Lastly, the peak−to−peak
voltage ripple on the COMP pin is examined when the
converter is fully loaded to insure low output voltage jitter.
The exact details of this process are covered in the Design
Procedure section.
Undervoltage Lockout (UVLO)
The controller has undervoltage lockout comparators
monitoring two pins. One, intended for the logic and
low−side drivers, is connected to the VCCL pin with an 8.5 V
turn−on and 6.15 V turn−off threshold. A second, for the
high side drivers, is connected to the VCCH pin with an 8.5 V
turn−on and 6.75 V turn−off threshold. A UVLO fault sets
the fault latch which forces switching to stop and the upper
and lower gate drivers produce a logic low (i.e., all the
MOSFETs are turned OFF). Power good (PGD) is pulled
low when UVLO occurs. The overcurrent/overvoltage latch
is reset by the UVLO signal.
VCOMP VCORE @ 0 A Channel_Startup_Offset
Int_Ramp GCSA Ext_Ramp2
The COMP pin will disable the converter when pulled
below the COMP Discharge Threshold (nominally 0.27 V).
The RC network between the COMP pin and the soft start
capacitor (RC1, CC1) allows the COMP voltage to slew
quickly during transient loading of the converter. Without
this network the error amplifier would have to drive the large
soft start capacitor (CC2) directly, which would drastically
limit the slew rate of the COMP voltage. The RC1/CC1
network allows the COMP voltage to undergo a step change
of approximately RC1 ⋅ ICOMP.
The capacitor (CA1) between the COMP pin and the error
amplifier’s inverting input (the VFB pin) and the parallel
combination of the resistors RF1 and RDRP determine the
bandwidth of the error amplifier. The gain of the error
amplifier crosses 0 dB at a high enough frequency to give a
quick transient response, but well below the switching
frequency to minimize ripple and noise on the COMP pin.
A capacitor in parallel with the RF1 resistor (CF1) adds a zero
to boost phase near the crossover frequency to improve loop
stability.
Power Good (PGD) Delay Time
When VCORE is less than the power good threshold,
87.5% ⋅ DAC, or greater than 2.0 V the open−collector
power good pin (PGD) will be pulled low by the NCP5331.
When VCORE is in regulation PGD will become high
impedance. An external pull−up resistor is required on PGD.
During soft start, when VCORE reaches the power good
threshold, 87.5% ⋅ DAC, then the “longer” of two timers will
dictate when PGD becomes high impedance. One timer is
internally set to 200 s and can not be changed. Placing a
capacitor from the CPGD pin to GND sets the second
programmable timer. When VCORE crosses the PGD
threshold, a current source will charge CPGD starting at
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NCP5331
kept low at turn−off, preventing VCORE from being pulled
below ground.
However, if using the “Timed Hiccup Mode Current
Limit” feature with Method A, the Covc pin will time out
when the Ilim pin is pulled low, and the NCP5331 will not
turn back on (after time out) unless the power is recycled.
This can be avoided by adding another transistor to the Covc
pin, thereby keeping it low while the part is disabled.
The second method (Method B in Figure 28) is to pull low
on the NCP5331’s comp pin. With this method, GHx will be
low and GLx will be high while the part is disabled.
However, under Method B, if the part is disabled at
turn−on, and if using the “Timed Hiccup Mode Current
Limit” feature, the Covc pin will again time out and the
NCP5331 will not be able to be turned on after the time out
has occurred. This too can be avoided by the use of a
transistor at the Covc pin keeping it low while the part is
disabled.
If using Method B but not with a transistor at the Covc pin,
a 1.0 K resistor must be added between the drain of the
transistor and the Comp pin to prevent the current limit from
being tripped when the Comp pin is quickly pulled low.
0.25 V and “timing out” at 3 V. The current delivered to the
CPGD capacitor (IPGD) is a function of the ROSC resistor
according to the following equation.
IPGD 0.52 VROSC
The programmed delay time can be calculated from
tPGD CPGD (PGDTHRESH PGDMIN)IPGD
CPGD (3.0 V 0.25 V)IPGD
The programmable timer may be disabled (set to 0) by
connecting the CPGD pin to 5 VREF. This will set the PGD
delay time to the internal delay of 200 s. Figure 26
demonstrates the use of the programmable PGD timer (set
to 6.0 ms) to allow PGD to transition high when VCORE is
safely within the regulation limits for the processor (DAC
±50 mV).
Implementing an Enable Function
An Enable function may be implemented on the NCP5331
in one of two ways. The first method (Method A in
Figure 27) is to pull low on the Ilim pin. This method is the
preferred method, as both the GHx and the GLx pins will be
COMP
ILIM
*R
1.0 k
3
3
Hi to Disable
Lo to Enable
QILIM
BSS123
1
Hi to Disable
Lo to Enable
2
QCOMP
BSS123
1
2
COVC
COVC
3
3
*QCOVC
BSS123
1
**QCOVC
BSS123
1
2
2
*Needed if not using QCovc
*Needed if using ‘Timed
Hiccup Mode Current Limit’
**Allows Disabling at Turn−On
(when using ‘Timed Hiccup Mode Current Limit’)
Figure 27. Enable Method A
Figure 28. Enable Method B
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NCP5331
Power Dissipation
ICCL, ICCLx, ICCH are typical device quiescent currents and
can be found under the General Electrical Specifications.
NCP5331 power dissipation may be approximated by the
following equation:
QTHighFETs is the sum of the High−Side MOSFets total gate
charge
QTLowFETs is the sum of the Low−Side MOSFets total gate
charge
Figure 29 shows device temperature rise versus switching
frequency at various gate drive voltage combinations using
ON Semiconductor’s NTD60N03 (Qt = 31nC at 5.0 V) as
the high−side MOSFet and NTD80N02 (Qt = 39nC at 7.0 V)
as the low−side MOSFet. Using other MOSFets will of
course result in different losses, but the general conclusion
will be the same.
If trying to drive 2 lower MOSFets at frequencies higher
than 200 KHz, it may be necessary to reduce the low−side
gate drive voltage.
Ploss FSW · (VCCH · QTHighFETs
VCCLx · QTLowFETs) PQuiescent
where:
PQuiescent VCCL · ICCL 2 · VCCLx ·ICCLx
(VCCH Vin) · ICCH
FSW is the switching frequency
VCCL is 12 V
VCCLx is the low−side gate drive voltage and may be varied
between 5.0 and 12 V
VCCH is the high−side gate drive voltage and is between 4.5
and 7.0 V
Vin is the input voltage to the converter and is either 5.0 or
12 V
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
VCCH = 7.0 V;
VCCLx = 12 V;
2 Low−Side FETS
VCCH = 4.5 V;
VCCLx = 12 V;
2 Low−Side FETS
VCCH = 7.0 V;
VCCLx = 12 V;
1 Low−Side FETS
VCCH = 4.5 V;
VCCLx = 12 V;
1 Low−Side FETS
VCCH = 7.0 V;
VCCLx = 12 V;
2 Low−Side FETS
VCCH 4.5 V;
VCCLx = 12 V;
2 Low−Side FETS
100
150
200
250
300
350
FREQUENCY (kHz)
Figure 29. Calculated NCP5331 temperature rise (LQFP−32 package)
versus frequency at various typical gate drive voltage combinations
with typical ON Semiconductor MOSFets.
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NCP5331
Layout Guidelines
With the fast rise, high output currents of microprocessor
applications, parasitic inductance and resistance should be
considered when laying out the power, filter and feedback
signal sections of the board. Typically, a multilayer board
with at least one ground plane is recommended. If the layout
is such that high currents can exist in the ground plane
underneath the controller or control circuitry, the ground
plane can be slotted to route the currents away from the
controller. The slots should typically not be placed between
the controller and the output voltage or in the return path of
the gate drive. Additional power and ground planes or
islands can be added as required for a particular layout.
Gate drives experience high di/dt during switching and the
inductance of gate drive traces should be minimized. Gate
drive traces should be kept as short and wide as practical and
should have a return path directly below the gate trace.
Output filter components should be placed on wide planes
connected directly to the load to minimize resistive drops
during heavy loads and inductive drops and ringing during
transients. If required, the planes for the output voltage and
return can be interleaved to minimize inductance between
the filter and load.
The current sense signals are typically tens of millivolts.
Noise pick−up should be avoided wherever possible.
Current feedback traces should be routed away from noisy
areas such as the switch node and gate drive signals. If the
current signals are taken from a location other than directly
at the inductor any additional resistance between the
pick−off point and the inductor appears as part of the
inherent inductor resistances and should be considered in
design calculations. The capacitors for the current feedback
networks should be placed as close to the current sense pins
as practical. After placing the NCP5331 control IC, follow
these guidelines to optimize the layout and routing:
1. Place the 1 F ceramic power−supply bypass
capacitors close to their associated pins: VCCL,
VCCH, VCCL1 and VCCL2.
2. Place the MOSFETs to minimize the length of the
Gate traces. Orient the MOSFETs such that the
Drain connections are away from the controller and
the Gate connections are closest to the controller.
3. Place the components associated with the internal
error amplifier (RF1, CF1, CC1, CC2, RC1, CA1,
RDRP) to minimize the trace lengths to the pins
VFB, VDRP and COMP.
4. Place the current sense components (RS1, RS2,
CS1, CS2, RS, CSA, CSB) near the CS1, CS2, and
CSREF pins.
5. Place the frequency setting resistor (ROSC) close to
the ROSC pin. The ROSC pin is very sensitive to
noise. Route noisy traces, such as the SWNODEs
and GATE traces, away from the ROSC pin and
resistor.
6. Place the MOSFETs and output inductors to
reduce the size of the noisy SWNODEs. However,
there is a trade−off between reducing the size of
the SWNODEs for noise reduction and providing
adequate heat−sinking for the synchronous
MOSFETs.
7. Place the input inductor and input capacitor(s) near
the Drain of the control (upper) MOSFETs. There
is a trade−off between reducing the size of this
node to save board area and providing adequate
heat−sinking for the control (upper) MOSFETs.
8. Place the output capacitors (electrolytic and
ceramic) close to the processor socket or output
connector.
9. The trace from the SWNODEs to the current sense
components (RS1, RS2) will be very noisy. Route
this away from more sensitive, low−level traces.
The Ground layer can be used to help isolate this
trace.
10. The Gate traces are very noisy. Route these away
from more sensitive, low−level traces. Try to keep
each Gate signal on one layer and insure that there
is an uninterrupted return path directly below the
Gate trace. The Ground layer can be used to help
isolate these traces.
11. Gate driver returns, GND1 and GND2, should not
be connected to LGND, but instead directly to the
ground plane.
12. Try not to “daisy chain” connections to Ground
from one via. Ideally, each connection to Ground
will have its own via located as close to the
component as possible.
13. Use a slot in the ground plane to prevent high
currents from flowing beneath the control IC. This
slot should form an “island” for signal ground
under the control IC. “Signal ground” and “power
ground” must be separated. Examples of signal
ground include the capacitors at COMP, CSREF,
and 5VREF, the resistors at ROSC and ILIM, and the
LGND pin to the controller. Examples of power
ground include the capacitors to VCCH and VCCL1
and VCCL2, the Source of the synchronous
MOSFETs, and the GND1 and GND2 pins of the
controller.
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NCP5331
2. Output Inductor Selection
14. The CSREF sense point should be equidistant
between the output inductors to equalize the PCB
resistance added to the current sense paths. This
will insure acceptable current sharing. Also, route
the CSREF connection away from noisy traces such
as the SWNODEs and GATE traces. If noise from
the SWNODEs or GATE signals capacitively
couples to the CSREF trace the external ramps
will be very noisy and voltage jitter will result.
15. Ideally, the SWNODEs are exactly the same shape
and the current sense points (connections to RS1
and RS2) are made at identical locations to equalize
the PCB resistance added to the current sense paths.
This will help to insure acceptable current sharing.
16. Place the 1 F ceramic capacitors, CP1 and CP2,
close to the drains of the MOSFETs Q1 and Q2,
respectively.
17. If snubbers are used, they must be placed very
close to their associated MOSFETs and
SWNODE. The connections to the snubber
components should be as short as possible.
The output inductor may be the most critical component
in the converter because it will directly effect the choice of
other components and dictate both the steady−state and
transient performance of the converter. When selecting an
inductor the designer must consider factors such as dc
current, peak current, output voltage ripple, core material,
magnetic saturation, temperature, physical size, and cost
(usually the primary concern).
In general, the output inductance value should be as low
and physically small as possible to provide the best transient
response and minimum cost. If a large inductance value is
used, the converter will not respond quickly to rapid changes
in the load current. On the other hand, too low an inductance
value will result in very large ripple currents in the power
components (MOSFETs, capacitors, etc) resulting in
increased dissipation and lower converter efficiency. Also,
increased ripple currents will force the designer to use
higher rated MOSFETs, oversize the thermal solution, and
use more, higher rated input and output capacitors − the
converter cost will be adversely effected.
One method of calculating an output inductor value is to
size the inductor to produce a specified maximum ripple
current in the inductor. Lower ripple currents will result in
less core and MOSFET losses and higher converter
efficiency. Equation 3 may be used to calculate the
minimum inductor value to produce a given maximum
ripple current (α) per phase. The inductor value calculated
by this equation is a minimum because values less than this
will produce more ripple current than desired. Conversely,
higher inductor values will result in less than the maximum
ripple current.
Design Procedure
1. Output Capacitor Selection
The output capacitors filter the current from the output
inductor and provide a low impedance for transient load
current changes. Typically, microprocessor applications
will require both bulk (electrolytic, tantalum) and low
impedance, high frequency (ceramic) types of capacitors.
The bulk capacitors provide “hold up” during transient
loading. The low impedance capacitors reduce steady−state
ripple and bypass the bulk capacitance when the output
current changes very quickly. The microprocessor
manufacturers usually specify a minimum number of
ceramic capacitors. The designer must determine the
number of bulk capacitors.
Choose the number of bulk output capacitors to meet the
peak transient requirements. The following formula can be
used to provide a starting point for the minimum number of
bulk capacitors (NOUT,MIN).
NOUT,MIN ESR per capacitor IO,MAX
VO,MAX
(VIN VCORE) VCORE
LoMIN ( IO,MAX VIN fSW)
(3)
α is the ripple current as a percentage of the maximum
output current per phase (α = 0.15 for ±15%, α = 0.25 for
±25%, etc). If the minimum inductor value is used, the
inductor current will swing ± α% about its value at the center
(half the dc output current for a two−phase converter).
Therefore, for a two−phase converter, the inductor must be
designed or selected such that it will not saturate with a peak
current of (1 + α) ⋅ IO,MAX/2.
The maximum inductor value is limited by the transient
response of the converter. If the converter is to have a fast
transient response then the inductor should be made as small
as possible. If the inductor is too large its current will change
too slowly, the output voltage will droop excessively, more
bulk capacitors will be required, and the converter cost will
be increased. For a given inductor value, its interesting to
determine the time required to increase or decrease the
current.
(1)
In reality, both the ESR and ESL of the bulk capacitors
determine the voltage change during a load transient
according to
VO,MAX (IO,MAXt) ESL IO,MAX ESR (2)
Unfortunately, capacitor manufacturers do not specify the
ESL of their components and the inductance added by the
PCB traces is highly dependent on the layout and routing.
Therefore, it is necessary to start a design with slightly more
than the minimum number of bulk capacitors and perform
transient testing or careful modeling/simulation to
determine the final number of bulk capacitors.
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NCP5331
ILo,MAX IO,MAX2 ILo2
For increasing current
tINC Lo IO(VIN VCORE)
(3.1)
For decreasing current
tDEC Lo IO(VCORE)
IC,MAX
(3.2)
0A
FET On,
Caps Discharging
Figure 30. Input Capacitor Current for a
Two−Phase Converter
ILo,MIN is the minimum output inductor current.
ILo,MIN IO,MAX2 ILo2
ILo (VIN VCORE) D(Lo fSW)
(10)
For the two−phase converter, the input capacitor(s) rms
current is then
ICIN,RMS [2D (IC,MIN2 IC,MIN IC,IN
(11)
IC,IN23) IIN,AVG2 (1 2D)]12
Select the number of input capacitors (NIN) to provide the
rms input current (ICIN,RMS) based on the rms ripple current
rating per capacitor (IRMS,RATED).
The choice and number of input capacitors is primarily
determined by their voltage and ripple current ratings. The
designer must choose capacitors that will support the worst
case input voltage with adequate margin. To calculate the
number of input capacitors one must first determine the total
rms input ripple current. To this end, begin by calculating the
average input current to the converter.
NIN ICIN,RMSIRMS,RATED
(12)
For a two−phase converter with perfect efficiency (η = 1),
the worst case input ripple current will occur when the
converter is operating at a 25% duty cycle. At this operating
point, the parallel combination of input capacitors must
support an rms ripple current equal to 25% of the converter’s
dc output current. At other duty cycles, the ripple current
will be less. For example, at a duty cycle of either 10% or
40%, the two−phase input ripple current will be
approximately 20% of the converter’s dc output current.
In general, capacitor manufacturers require derating to the
specified ripple current based on the ambient temperature.
More capacitors will be required because of the current
derating. The designer should be cognizant of the ESR of the
input capacitors. The input capacitor power loss can be
calculated from
(5)
where
D
is the duty cycle of the converter,
D = VCORE/VIN,
η
is the specified minimum efficiency,
IO,MAX is the maximum converter output current.
The input capacitors will discharge when the control FET
is ON and charge when the control FET is OFF as shown in
Figure 30.
The following equations will determine the maximum and
minimum currents delivered by the input capacitors.
(7)
(9)
ILo is the peak−to−peak ripple current in the output
inductor of value Lo.
3. Input Capacitor Selection
IC,MIN ILo,MIN IIN,AVG
T/2
−IIN,AVG
This formula assumes steady−state conditions with no
more than one phase on at any time. The second term in
Equation 4 is the total ripple current seen by the output
capacitors. The total output ripple current is the “time
summation” of the two individual phase currents that are
180 degrees out−of−phase. As the inductor current in one
phase ramps upward, current in the other phase ramps
downward and provides a canceling of currents during part
of the switching cycle. Therefore, the total output ripple
current and voltage are reduced in a multiphase converter.
(6)
tON
FET Off,
Caps Charging
VOUT,P−P (ESR per cap NOUT,MIN) (4)
(VIN #Phases VCORE) D (LoMIN fSW)
IC,MAX ILo,MAX IIN,AVG
IC,IN = IC,MAX − IC,MIN
IC,MIN
For typical processor applications with output voltages
less than half the input voltage, the current will be increased
much more quickly than it can be decreased. It may be more
difficult for the converter to stay within the regulation limits
when the load is removed than when it is applied − excessive
overshoot may result.
The output voltage ripple can be calculated using the
output inductor value derived in this Section (LoMIN), the
number of output capacitors (NOUT,MIN) and the per
capacitor ESR determined in the previous Section.
IIN,AVG IO,MAX D
(8)
PCIN ICIN,RMS2 ESR_per_capacitorNIN (13)
Low ESR capacitors are recommended to minimize losses
and reduce capacitor heating. The life of an electrolytic
capacitor is reduced 50% for every 10°C rise in the
capacitor’s temperature.
ILo,MAX is the maximum output inductor current.
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NCP5331
VOUT
MAX dI/dt occurs in
first few PWM cycles.
ILi
Vi(t = 0) = 12 V
Q1
SWNODE
Li
TBD
ILo
Vo(t = 0) = 1.225 V
Lo
729 nH
Ci
5 × 16MBZ1500M10X20
+ VCi
+ Co
6 × 16MBZ1000M10X16
Q2
+ Vi
− 12 V
ESRCi
13 m/5 = 2.6 m
26 u(t)
ESRCo
19 m/6 = 3.2 m
Figure 31. Calculating the Input Inductance
4. Input Inductor Selection
Current changes slowly in the input inductor so the input
capacitors must initially deliver the vast majority of the
input current. The amount of voltage drop across the input
capacitors (VCi) is determined by the number of input
capacitors (NIN), their per capacitor ESR (ESRIN), and the
current in the output inductor according to
The use of an inductor between the input capacitors and
the power source will accomplish two objectives. First, it
will isolate the voltage source and the system from the noise
generated in the switching supply. Second, it will limit the
inrush current into the input capacitors at power up. Large
inrush currents will reduce the expected life of the input
capacitors. The inductor’s limiting effect on the input
current slew rate becomes increasingly beneficial during
load transients.
The worst case input current slew rate will occur during
the first few PWM cycles immediately after a step−load
change is applied as shown in Figure 31. When the load is
applied, the output voltage is pulled down very quickly.
Current through the output inductors will not change
instantaneously so the initial transient load current must be
conducted by the output capacitors. The output voltage will
step downward depending on the magnitude of the output
current (IO,MAX), the per capacitor ESR of the output
capacitors (ESROUT), and the number of the output
capacitors (NOUT) as shown in Figure 31. Assuming the load
current is shared equally between the two phases, the output
voltage at full, transient load will be
VCORE,FULL−LOAD VCi ESRINNIN dILodt tON
ESRINNIN dILodt DfSW
Before the load is applied, the voltage across the input
inductor (VLi) is very small − the input capacitors charge to
the input voltage, VIN. After the load is applied the voltage
drop across the input capacitors, VCi, appears across the
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from
LiMIN VLi dIINdtMAX
where dIIN/dt MAX is the maximum allowable input current
slew rate.
The input inductance value calculated from Equation 18
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality input voltage
“sag,” lower capacitor ESRs, and stray inductance will help
reduce the slew rate of the input current.
As with the output inductor, the input inductor must
support the maximum current without saturating the
magnetic. Also, for an inexpensive iron powder core, such
as the −26 or −52 from Micrometals, the inductance “swing”
with dc bias must be taken into account − inductance will
decrease as the dc input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
(14)
When the control MOSFET (Q1 in Figure 31) turns ON,
the input voltage will be applied to the opposite terminal of
the output inductor (the SWNODE). At that instant, the
voltage across the output inductor can be calculated as
(15)
VIN VCORE,NO−LOAD
(IO,MAX2) ESROUTNOUT
The differential voltage across the output inductor will
cause its current to increase linearly with time. The slew rate
of this current can be calculated from
dILodt VLoLo
(18)
VCi dIINdtMAX
VCORE,NO−LOAD (IO,MAX2) ESROUTNOUT
VLo VIN VCORE,FULL−LOAD
(17)
(16)
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NCP5331
5. MOSFET and Heatsink Selection
Power dissipation, package size, and thermal solution drive
MOSFET selection. To adequately size the heat sink, the
design must first predict the MOSFET power dissipation.
Once the dissipation is known, the heat sink thermal
impedance can be calculated to prevent the specified
maximum case or junction temperatures from being exceeded
at the highest ambient temperature. Power dissipation has two
primary contributors: conduction losses and switching losses.
The control or upper MOSFET will display both switching
and conduction losses. The synchronous or lower MOSFET
will exhibit only conduction losses because it switches into
nearly zero voltage. However, the body diode in the
synchronous MOSFET will suffer diode losses during the
nonoverlap time of the gate drivers.
For the upper or control MOSFET, the power dissipation
can be approximated from
PD,CONTROL (IRMS,CNTL2 RDS(on))
ID
VGATE
VGS_TH
QGS1
PD,SYNCH (IRMS,SYNCH2 RDS(on))
(Vfdiode IO,MAX2 t_nonoverlap fSW)
(26)
The first term represents the conduction or IR losses when
the MOSFET is ON, and the second term represents the
diode losses that occur during the gate nonoverlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of
(27)
IRMS,SYNCH [(1 D)
(ILo,MAX2 ILo,MAX ILo,MIN ILo,MIN2)3]12
IRMS,CNTL [D (ILo,MAX2 ILo,MAX ILo,MIN (20)
ILo,MIN2)3]12
Vfdiode is the forward voltage of the MOSFET’s intrinsic
diode at the converter output current.
t_nonoverlap is the nonoverlap time between the upper
and lower gate drivers to prevent cross conduction. This
time is usually specified in the data sheet for the control IC.
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature.
ILo,MAX is the maximum output inductor current.
(21)
ILo,MIN is the minimum output inductor current.
(22)
IO,MAX is the maximum converter output current.
D is the duty cycle of the converter.
T (TJ TA)PD
(23)
ILo is the peak−to−peak ripple current in the output
inductor of value Lo.
ILo (VIN VCORE) D(Lo fSW)
(25)
Ig is the output current from the gate driver IC.
VIN is the input voltage to the converter.
fsw is the switching frequency of the converter.
QRR is the reverse recovery charge of the lower MOSFET.
Qoss is the sum of all the MOSFET output charges.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from
(19)
The first term represents the conduction or IR losses when
the MOSFET is ON, while the second term represents the
switching losses. The third term is the losses associated with
the control and synchronous MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
IRMS,CNTL is the rms value of the trapezoidal current in the
control MOSFET.
D VCOREVIN
VDRAIN
Qswitch Qgs2 Qgd
(Qoss2 VIN fSW) (VIN QRR fSW)
ILo,MIN IO,MAX2 ILo2
QGD
Figure 32. MOSFET Switching Characteristics
(ILo,MAX QswitchIg VIN fSW)
ILo,MAX IO,MAX2 ILo2
QGS2
where
T
JC
(24)
SA
RDS(on) is the ON resistance of the MOSFET at the
applied gate drive voltage.
Qswitch is the post gate threshold portion of the
gate−to−source charge plus the gate−to−drain charge. This
may be specified in the data sheet or approximated from the
gate−charge curve as shown in the Figure 32.
TJ
TA
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27
(28)
is the total thermal impedance (JC + SA),
is the junction−to−case thermal impedance of
the MOSFET,
is the sink−to−ambient thermal impedance of
the heatsink assuming direct mounting of the
MOSFET (no thermal “pad” is used),
is the specified maximum allowed junction
temperature,
is the worst case ambient operating temperature.
NCP5331
For TO−220 and TO−263 packages, standard FR−4
copper clad circuit boards will have approximate thermal
resistances (SA) as shown in the following table.
Single−Sided
1 oz. Copper
0.5/323
60−65°C/W
0.75/484
55−60°C/W
1.0/645
50−55°C/W
1.5/968
45−50°C/W
2.0/1290
38−42°C/W
2.5/1612
33−37°C/W
RF1 VNO−LOADIBIASVFB
As with any power design, proper laboratory testing
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow, maximum
input voltage, maximum loading, and component variations
(i.e., worst case MOSFET RDS(on)). Also, the inductors and
capacitors share the MOSFET’s heatsinks and will add heat
and raise the temperature of the circuit board and MOSFET.
For any new design, its advisable to have as much heatsink
area as possible − all too often new designs are found to be
too hot and require redesign to add heatsinking.
6. Adaptive Voltage Positioning
There are two resistors that determine the Adaptive
Voltage Positioning, RF1 and RDRP. RF1 establishes the
no−load “high” voltage position and RDRP determines the
full−load “droop” voltage.
Resistor RF1 is connected between VCORE and the VFB
pin of the controller. At no load, this resistor will conduct the
internal bias current of the VFB pin and develop a voltage
drop from VCORE to the VFB pin. Because the error amplifier
regulates VFB to the DAC setting, the output voltage,
VCORE, will be higher by the amount IBIASVFB ⋅ RF1. This
condition is shown in Figure 33.
To calculate RF1 the designer must specify the no−load
voltage increase above the VID setting (VNO−LOAD) and
RS1
L1
0A
CS1
CS1
RS2
L2
0A
CS2
CS2
VDRP IO,MAX (RL RPCB) GVDRP
RDRP VDRP
(31)
(IBIASVFB VCORE,FULL−LOADRF1)
VCORE,FULL−LOAD is the full−load voltage reduction
from the VID (DAC) setting. VCORE,FULL−LOAD is not the
voltage change from the no−load AVP setting.
COMP
Σ
Error
Amp
IBIASVFB
VDRP = VID
RF1
VFB = VID
IDRP = 0
CSREF
VID Setting
RDRP
+
−
GVDRP
(30)
The value of RDRP can then be calculated.
+−
+
−
GVDRP
(29)
Resistor RDRP is connected between the VDRP and the
VFB pins. At no−load, the VDRP and the VFB pins will both
be at the DAC voltage so this resistor will conduct zero
current. However, at full−load, the voltage at the VDRP pin
will increase proportional to the output inductor’s current
while VFB will still be regulated to the DAC voltage. Current
will be conducted from VDRP to VFB by RDRP. This current
will be large enough to supply the VFB bias current and cause
a voltage drop from VFB to VCORE across RF1 − the
converter’s output voltage will be reduced. This condition is
shown in Figure 34.
To determine the value of RDRP the designer must specify
the full−load voltage reduction from the VID (DAC) setting
(VCORE,FULL−LOAD) and predict the voltage increase at
the VDRP pin at full−load. Usually, the full−load voltage
reduction is specified in the design guide for the processor
that is available from the manufacturer. To predict the
voltage increase at the VDRP pin at full−load (VDRP), the
designer must consider the output inductor’s resistance
(RL), the PCB trace resistance between the current sense
points (RPCB), and the controller IC’s gain from the current
sense to the VDRP pin (GVDRP).
−
+
Pad Size
(in2/mm2)
determine the VFB bias current. Usually, the no−load voltage
increase is specified in the design guide for the processor
that is available from the manufacturer. The VFB bias current
is determined by the value of the resistor from ROSC to
ground (see Figure TBD for a graph of IBIASVFB versus
ROSC). The value of RF1 can then be calculated.
IFBK = IBIASVFB
VCORE = VID + IBIASVFB RF1
Figure 33. AVP Circuitry at No−Load
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VCORE
NCP5331
L1
IMAX/2
CS1
COMP
Σ
CS2
VID Setting
Error
Amp
CS1
RS2
L2
IMAX/2
+−
+
−
GVDRP
−
+
RS1
IBIASVFB
RDRP
+
−
GVDRP
RF1
VDRP = VID +
VFB = VID
IMAX • RL • GVDRP
VCORE
CS2
IDRP
IFBK
IDRP = IMAX • RL • GVDRP/RDRP
IFBK = IDRP − IBIASVFB
CSREF
VCORE = VID − (IDRP − IBIASVFB) RF1
Figure 34. AVP Circuitry at Full−Load
7. Current Sensing
For inductive current sensing, choose the current sense
network (RSx, CSx) to satisfy
RSx CSx Lo(RL RPCB)
(32)
For resistive current sensing, choose the current sense
network (RSx, CSx) to satisfy
RSx CSx Lo(Rsense)
NOTE:
(33)
This will provide an adequate starting point for RSx and
CSx. After the converter is constructed, the value of RSx
(and/or LSx) should be fine−tuned in the lab by observing
the VDRP signal during a step change in load current. Tune
the RSx ⋅ CSx network to provide a “square−wave” at the
VDRP output pin with maximum rise time and minimal
overshoot as shown in Figures 34 − 36.
The RC time constant of the current sense network is
too long (slow); VDRP and VCORE respond too slowly.
Figure 35. VDRP Tuning, RC Time Too Long
NOTE:
NOTE:
The RC time constant of the current sense network is
too short (fast); VDRP and VCORE both overshoot.
The RC time constant of the current sense network is
optimal; VDRP and VCORE respond to the load current
quickly without overshooting.
Figure 37. VDRP Tuning, RC Time Optimal
Figure 36. VDRP tuning, RC Time Too Short
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NCP5331
8. Error Amplifier Tuning
NOTE:
After the steady−state (static) AVP has been set and the
current sense network has been optimized the Error
Amplifier must be tuned. Basically, the gain of the Error
Amplifier should be adjusted to provide an acceptable
transient response by increasing or decreasing the Error
Amplifier’s feedback capacitor (CA1 in the Applications
Diagram). The bandwidth of the control loop will vary
directly with the gain of the error amplifier.
If CA1 is too large the loop gain/bandwidth will be low, the
COMP pin will slew too slowly, and the output voltage will
overshoot as shown in Figure 38. On the other hand, if CA1
is too small the loop gain/bandwidth will be high, the COMP
pin will slew very quickly and overshoot. Integrator “wind
up” is the cause of the overshoot. In this case the output
voltage will transition more slowly because COMP spikes
upward as shown in Figure 39. Too much loop
gain/bandwidth increase the risk of instability. In general,
one should use the lowest loop gain/bandwidth as possible
to achieve acceptable transient response − this will insure
good stability. If CA1 is optimal the COMP pin will slew
quickly but not overshoot and the output voltage will
monotonically settle as shown in Figure 40.
After the control loop is tuned to provide an acceptable
transient response the steady−state voltage ripple on the COMP
pin should be examined. When the converter is operating at
full, steady−state load, the peak−to−peak voltage ripple on
the COMP pin should be less than 20 mVpp as shown in
Figure 41. Less than 10 mVpp is ideal. Excessive ripple on
the COMP pin will contribute to output voltage jitter.
The value of CA1 is too high and the loop gain/
bandwidth too low. COMP slews too slowly which
results in overshoot in VCORE.
Figure 38. COMP Tuning, Bandwidth Too Low
9. Current Limit Setting
NOTE:
When the output of the current sense amplifier (CO1 or
CO2 in the block diagram) exceeds the voltage on the ILIM
pin the part will enter hiccup mode. For inductive sensing,
the ILIM pin voltage should be set based on the inductor’s
maximum resistance (RLMAX). The design must consider
The value of CA1 is too low and the loop gain/
bandwidth too high. COMP moves too quickly, which is
evident from the small spike in its voltage when the
load is applied or removed. The output voltage
transitions more slowly because of the COMP spike.
Figure 39. COMP Tuning, Bandwidth Too High
NOTE:
NOTE:
The value of CA1 is optimal. COMP slews quickly
without spiking or ringing. VCORE does not overshoot
and monotonically settles to its final value.
At full load the peak−to−peak voltage ripple on the
COMP pin should be less than 20 mV for a
well−tuned/stable controller. Higher COMP voltage
ripple will contribute to output voltage jitter.
Figure 41. COMP Ripple for a Stable System
Figure 40. COMP Tuning, Bandwidth Optimal
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NCP5331
GCSA
the inductor’s resistance increase due to current heating and
ambient temperature rise. Also, depending on the current
sense points, the circuit board may add additional resistance.
In general, the temperature coefficient of copper is +0.393%
per °C. If using a current sense resistor (RSENSE), the ILIM
pin voltage should be set based on the maximum value of the
sense resistor. To set the level of the ILIM pin,
VILIM (IOUT,LIM ILo2) R GILIM
is the Current Sense Amplifier Gain
(nominally 2.0 V/V),
Startup Offset is typically 0.60V.
12. Power Good Delay Time
The power good timer sets the delay time between when
VCORE exceeds the CPGD comparator’s threshold voltage
and when PGD will actually transition high. The PGD delay
time can be calculated from
(34)
where
IOUT,LIM is the current limit threshold of the converter,
ILo/2 is half the inductor ripple current,
R
is either (RLMAX + RPCB) or RSENSE,
is the current sense to ILIM gain.
GILIM
For the overcurrent protection to work properly, the
current sense time constant (RC) should be slightly larger
than the RL time constant. If the RC time constant is too fast,
during step load changes the sensed current waveform will
appear larger than the actual inductor current and will
probably trip the current limit at a lower level than expected.
tPGD CPGD (PGDTHRESH PGDMIN)IPGD
CPGD (3.0 V 0.25V)IPGD
where
PGDTHRESH is the PGD comparator’s threshold
voltage, nominally 3 V,
PGDMIN
is the PGD timer’s starting voltage,
nominally 0.25 V,
is the charge current supplied to the
IPGD
capacitor at the CPGD pin. This current
is a function of the ROSC resistor
according to IPGD = 0.52 V/ROSC.
10. Overcurrent Timer
The overcurrent timer sets the time the converter will
allow hiccup mode operation. Given the capacitance from
the COVC pin to GND, the nominal overcurrent time (tOVC)
can be calculated from the following equation.
tOVC COVC (OVCTHRESH OVCMIN)IOVC
Design Example
Typical Design Requirements:
VIN = 12.0 Vdc
VCORE = 1.20 Vdc (nominal)
VOUT,RIPPLE < 20 mVPP max
VID Range: 0.800 Vdc − 1.550 Vdc
IO,MAX = 52 A at full−load
IOUT,LIM = 72 Adc
dIIN/dt = 0.50 A/s max
fSW = 200 kHz
η = 80% min at full−load
TA,MAX = 55°C
TJ,MAX = 120°C
tSS = 6.0 ms (Soft Start time)
tOVC = 120 ms (Overcurrent time)
tPGD = 6.0 ms (PGD Delay time)
VCORE at no−load (static) =
−25 mV from VID setting = 1.225 Vdc
VCORE at full−load (static) =
–37 mV from VID setting = 1.163 Vdc
VCORE transient loading from 3.0 A to 25 A =
−50 mV from VID setting = 1.150 Vdc
(35)
COVC (3.0 V 0.25 V)5.0 A
COVC 5.5 105
where
OVCTHRESH is the overcurrent timer’s shutdown
voltage, nominally 3 V,
OVCMIN
is the overcurrent timer’s starting
voltage, nominally 0.25 V,
IOVC
is the charge current supplied to the
capacitor at the COVC pin, nominally
5 A.
11. Soft Start Time
The Soft Start time (tSS) can be calculated from
tSS (VCOMP RC1 ICOMP) CC2ICOMP (36)
where
VCOMP VCORE @ 0 A Channel_Startup_Offset
Int_Ramp GCSA Ext_Ramp2
1. Output Capacitor Selection
First, choose a low−cost, low−ESR output capacitor such
as the Rubycon 16MBZ1000M10X16: 16 V, 1000 F,
2.55 ARMS, 19 m, 10 × 16 mm. Calculate the minimum
number of output capacitors.
Ext_Ramp D (VIN VCORE)(RCSx CCSx fSW)
Int_Ramp 125 mV D0.50
ICOMP
Int_Ramp
Ext_Ramp
(37)
is the COMP source current from the
data sheet,
is the internal ramp value at the
corresponding duty cycle,
is the peak−to−peak external
steady−state ramp at 0 A,
NOUT,MIN ESR per capacitor IO,MAX
VO,MAX
19 m 22 A(1.225 V 1.150 V)
5.6 or 6 capacitors minimum (6000 F)
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(1)
NCP5331
2. Output Inductor Selection
Next, use Equation 6 to Equation 10 with the full−load
inductance value of 729 nH.
Calculate the minimum output inductance at IO,MAX
according to Equation 3 with ±20% inductor ripple current
(α = 0.15).
(VIN VOUT) VOUT
LoMIN ( IO,MAX VIN fSW)
ILo (VIN VOUT) D(Lo fSW)
(3)
(12 V 1.163 V) (1.163 V12 V)
(729 nH 200 kHz)
(10)
7.20 App
(12 V 1.163 V) 1.163 V
(0.15 52 A 12 V 200 kHz)
ILo,MAX IO,MAX2 ILo2
673 nH
52 A2 7.20 App2 29.6 A
To minimize core losses, we choose the T50−8B/90 core
from Micrometals: 23.0 nH/N2, 2.50 cm/turn. According to
the Micrometals catalog, at 26 A (per phase) the
permeability of this core will be approximately 88% of the
permeability at 0 A. Therefore, at 0 A we must achieve at
least 673 nH/0.88 or 765 nH. Using 6 turns of #16 AWG
bifilar (2 m/ft) will produce 828 nH.
We will need the nominal and worst case inductor
resistances for subsequent calculations.
ILo,MIN IO,MAX2 ILo2
(9)
52 A2 7.20 App2 22.4 A
IC,MAX ILo,MAX IIN,AVG
(6)
29.6 A0.80 6.30 A 30.7 A
IC,MIN ILo,MIN IIN,AVG
RL 6 turns 2.5 cmturn 0.03218 ftcm 2 mft
(7)
22.4 A0.80 6.30 A 21.7 A
0.965 m
For the two−phase converter, the input capacitor(s) rms
current at full−load is as follows. (Note: D = 1.163 V/12 V
= 0.097.)
The inductor resistance will be maximized when the
inductor is “hot” due to the load current and the ambient
temperature is high. Assuming a 50°C temperature rise of
the inductor at full−load and a 35°C ambient temperature
rise we can calculate
ICIN,RMS [2D (IC,MIN2 IC,MIN IC,IN
(11)
IC,IN23) IIN,AVG2 (1 2D)]12
RL,MAX 0.965 m [1 0.39%°C (50°C 35°C)]
[0.19 (21.72 21.7 9.0 9.023)
1.28 m
6.302 (1 0.19)]12
The output inductance at full−load will be reduced due to
the saturation characteristic of the core material.
12.9 ARMS
At this point, the designer must decide between saving
board space by using higher−rated/more costly capacitors
or saving cost by using more lower−rated/less costly
capacitors. To save cost, we choose the MBZ series
capacitors by Rubycon. Part number 16MBZ1500M10X20:
1500 F, 16 V, 2.55 ARMS, 13 m, 10 × 20 mm. This design
will require NIN = 12.8 A/2.55 A = 5 capacitors on the input
for a cost sensitive design or 6 capacitors for a conservative
design.
Lo52 A 0.88 828 nH 729 nH at full load
Next, use Equation 4 to insure the output voltage ripple
will satisfy the design goal with the minimum number of
output capacitors and the full load output inductance.
VOUT,P−P (ESR per cap NOUT,MIN)
(8)
(4)
{(VIN #Phases VCORE) D (Lo52 A fSW)}
(19 m6) {(12 V 2 1.163 V)
(1.163 V12 V)(729 nH 200 kHz)}
4. Input Inductor Selection
For the Claw Hammper CPU, the input inductor must
limit the input current slew rate to less than 0.5 A/s during
a load transient from 0 to 52 A. A conservative value will be
calculated assuming the minimum number of output
capacitors (NOUT = 6), five input capacitors (NIN = 5), worst
case ESR values for both the input and output capacitors,
and a maximum duty cycle at the maximum DAC setting
with 25 mV of no−load AVP.
20 mV
So, the ripple requirement will be satisfied if the minimum
number of output capacitors is used. More output capacitors
will probably be required to satisfy the transient
requirement, which will result in a lower ripple voltage.
3. Input Capacitor Selection
Use Equation 5 to determine the average input current to
the converter at full−load.
IIN,AVG IO,MAX D
DMAX (1.550 V 25 mVAVP)10.8 VIN 0.146
(5)
52 A (1.163 V12 V)0.80 6.30 A
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NCP5331
First, use Equation 15 to calculate the voltage across the
output inductor due to the 52 A load current being shared
equally between the two phases.
The rms value of the current in the control MOSFET is
calculated from Equation 20 and the previously derived
values for D, ILMAX, and ILMIN at the converter’s maximum
output current.
(15)
VLo VIN VCORE,NO−LOAD
(IO,MAX2) ESROUTNOUT
IRMS,CNTL [D (ILo,MAX2 ILo,MAX ILo,MIN (20)
12 V 1.575 V 52 A2 19 m6
ILo,MIN2)3]12
10.51 V
0.097 [(29.62 29.6 22.4 22.42)3]12
2.53 ARMS
Second, use Equation 16 to determine the rate of current
increase in the output inductor when the load is applied (i.e.,
Lo has decreased to 88% due to the dc current).
dILodt VLoLo
Equation 19 is used to calculate the power dissipation of
the control MOSFET but has been modified for one upper
and two lower MOSFETs.
(16)
10.51 V729 nH 14.4 Vs
PD,CONTROL {(IRMS,CNTL2) RDS(on)}
(ILo,MAX QswitchIg VIN fSW)
Finally, use Equation 17 and Equation 18 to calculate the
minimum input inductance value.
VCi ESRINNIN dILodt DfSW
(19)
(3 Qoss2 VIN fSW) (VIN QRR fSW)
(17)
{2.532 ARMS 8.0 m}
13 m5 14.4 Vs 0.146200 kHz
(29.6 A 27 nC1.5 A 12 V 200 kHz)
28 mV
(3 12 nC2 12 V 200 kHz)
LiMIN VCi dIINdtMAX
(12 V 43 nC 200 kHz)
(18)
28 mV0.50 As 55 nH
0.051 W 1.28 W 0.043 W 0.10 W
1.48 W per FET
Next, choose the small, cost effective T30−26 core from
Micrometals (33.5 nH/N2) with #16 AWG. The design
requires only 1.28 turns to achieve the minimum inductance
value. We allow for inductance “swing” at full−load by
using three turns. The input inductor’s value will be
The rms value of the current in the synchronous MOSFET
is calculated from Equation 27 and the previously derived
values for D, ILo,MAX, and ILo,MIN at the converter’s
maximum output current.
Li 32 33.5 nHN2 301 nH
(27)
IRMS,SYNCH [(1 D) (ILo,MAX2 ILo,MAX ILo,MIN ILo,MIN2)3]12
This inductor is available as part number CTX15−14771
from Coiltronics.
(1 0.097) [(29.62 29.6 22.4 22.42)3]12
5. MOSFET & Heatsink Selection
23.5 ARMS (shared by two synchronous MOSFETs)
For the upper MOSFET we choose two (1) NTD60N03
and for the lower MOSFETs we choose two (2) NTD80N02,
both are from ON Semiconductor. The following parameters
are derived from the data sheets.
NCP5331 Parameter
Equation 26 is used to calculate the power dissipation of
each synchronous MOSFET. Note: The rms current is
shared by the two lower MOSFETs so the total rms current
is divided by two in the following equation. Also, during the
nonoverlap time, the per−phase current is shared by two
body diodes so the full load current is divided between two
phases and two forward body diodes per phase.
Value
Gate Drive Current
1.5 A for 1.0 s
Upper Gate Voltage
6.5 V
Lower Gate Voltage
11.5 V
Gate Nonoverlap Time
65 ns
PD,SYNCH (IRMS,SYNCH2 RDS(on))
(26)
(Vfdiode IO,MAX2 t_nonoverlap fSW)
Parameter
NTD60N03
NTD80N02
RDS(on)
8.0 m @ 6.5 V
5.0 m @ 10 V
QSWITCH
27 nC
26 nC
QRR
43 nC
36 nC
(23.52)2 ARMS 5.0 m
0.92 V (52 A22) 65 ns 200 kHz
0.69 W 0.16 W 0.85 W per FET
QOSS
12 nC
12 nC
VF,diode
0.75 V @ 2.3 A
0.92 V @ 20 A
JC
1.65°C/W
1.65°C/W
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NCP5331
7. Current Sensing
Equation 28 is used to calculate the heat sink thermal
impedances necessary to maintain less than the specified
maximum junction temperatures at 55°C ambient.
Choose the current sense network (RSx, CSx, x = 1 or 2) to
satisfy
CNTRLSA (120 55°C)1.48 W 1.65°CW
RSx CSx Lo(RL RPCB)
42.3°CW
Equation 32 will be most accurate for better iron powder
core material (such as the −8 from Micrometals). This
material is very consistent with dc current and frequency.
Less expensive core materials (such as the −52 from
Micrometals) change their characteristics with dc current,
ac flux density, and frequency. This material will yield
acceptable converter performance if the current sense time
constant is set lower (longer) than anticipated. As a rule of
thumb, start with approximately twice the resistance (RSx)
or twice the capacitance (CSx) when using the less expensive
core material.
The component values determined thus far are Lo = 828 nH,
RL = 0.965 m, and RPCB = 0.2 m. We choose a convenient
value for CS1 (0.1 F) and solve for RSx.
SYNCHSA (120 55°C)0.85 W 1.65°CW
74.8°CW per MOSFET
or 37.4°CW per phase for two MOSFETsphase
If board area permits, a cost effective heatsink could be
formed by using a TO−263 mounting pad of at least 2.0 in2
(1282 mm2) for the upper and lower MOSFETs on a
single−sided, 1 oz copper PCB. The total required pad area
would be slightly less if the area were divided evenly
between top and bottom layers with multiple thermal vias
joining the two areas. To conserve board space, AAVID
offers clip−on heatsinks for TO−220 thru−hole packages.
Examples of these heatsinks include #577002 (1″ × 0.75″ ×
0.25″, 33°C/W at 2 W) and #591302 (0.75″ × 0.5″ × 0.5″,
29°C/W at 2 W).
RSn 828 nH(0.965 m 0.2 m) 0.1 F
7.10 k
After the circuit is constructed, the values of RSx and/or
CSx should be tuned to provide a “square−wave” at the VDRP
pin with minimal overshoot and fast rise time due to a step
change in load current as shown in Figure 35, Figure 36 and
Figure 37. This testing has shown that for a 3 to 25 A
transient, a value of 10.0 k will produce the desired square
wave at VDRP.
6. Adaptive Voltage Positioning
First, to achieve the 200 kHz switching frequency, use
Figure 5 to determine that a 51 k resistor is needed for
ROSC. Then, use Figure 6 to find the VFB bias current at the
corresponding value of ROSC. In this example, the 51 k
ROSC resistor results in a VFB bias current of approximately
7.0 A. Knowing the VFB bias current, one can calculate the
required values for RF1 and RDRP using Equation 29 through
Equation 31.
The no−load position is easily set using Equation 29.
RVFBK VNO−LOADIBIASVFB
8. Error Amplifier Tuning
The error amplifier is tuned by adjusting CA1 to provide
an acceptable full−load transient response as shown in
Figure 38, Figure 39 and Figure 40. After a value for CA1 is
chosen, the peak−to−peak voltage ripple on the COMP pin
is examined under full−load to insure less than 20 mVpp as
shown in Figure 41.
(29)
+25 mV7.0 A
3.6 k
For inductive current sensing, the designer must calculate
the inductor’s resistance (RL) and approximate any
resistance added by the circuit board (RPCB). We found the
inductor’s nominal resistance in Section 2 (0.965 m). In
this example, we assume 0.2 m for the circuit board
resistance (RPCB). With this information, Equation 30 can
be used to calculate the increase at the VDRP pin at full load.
VDRP IO,MAX (RL RPCB) GVDRP
9. Current Limit Setting
The maximum inductor resistance, the maximum PCB
resistance, and the maximum current−sense gain determine
the current limit as shown in Equation 34. The maximum
current, IOUT,LIMIT, was specified in the design
requirements. The maximum inductor resistance occurs at
full load and the highest ambient temperature. This value
was found in the “Output Inductor Section” (1.28 m). This
analysis assumes the PCB resistance only increases due to
the change in ambient temperature. Component heating will
also increase the PCB temperature but quantifying this
effect is difficult. Lab testing should be used to “fine tune”
the overcurrent threshold.
(30)
52 A (0.965 m 0.2 m) 4.2 VV
0.254 mV
RDRP can then be calculated from Equation 31.
RDRP (32)
VDRP
(31)
(IBIASVFB VCORE,FULL−LOADRF1)
RPCB,MAX 0.2 m {1 0.39%°C
(100°C 25°C)}
254 mV(7.0 A 37 mV3.6 k)
0.26 m
14.7 k
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34
NCP5331
VILIM (IOUT,LIM ILo2) (RLMAX RPCB,MAX)
5 VREF
GILIM
RLIM1
VLIM
(72 A 7.20 A2) (1.28 m 0.26 m)
To ILIM Pin
RLIM2
910
12 VV
1.4 Vdc
Figure 42. Setting the Current Limit
Set the voltage at the ILIM pin using a resistor divider from
the 5.0 V reference output as shown in Figure 42. If the
resistor from ILIM to GND is chosen to be 910 (RLIM2),
then the resistor from ILIM to 5.0 VREF can be calculated
from
Then calculate the steady−state COMP voltage.
VCOMP VOUT @ 0 A Channel_Startup_Offset
Int_Ramp GCSA Ext_Ramp2
RLIM1 (VREF VILIM)(VILIMRLIM2)
1.225 V 0.60 V 0.102 250 mV
(5.0 V 1.4 V)(1.4 V910 )
4.0 VV 5.3 mV2
2340 or 2.37 k
1.86 V
Finally, solve Equation 35 for the soft−start capacitor,
CC2, and substitute as required.
10. Overcurrent Timer
To set the overcurrent timer, solve Equation 35 for COVC
and substitute tOVC = 120 ms.
COVC tOVC(5.5 105)
CC2 (tSS ICOMP)(VCOMP RC1 ICOMP) (36)
(6 ms 30 A)(1.86 V 7.5 k 30 A)
(35)
0.11 F or 0.1 F
120 ms(5.5 105)
0.218 F or 0.22 F
12. Power Good Delay Time
First, use the previously derived value for ROSC to
calculate the current that will be supplied to the CPGD
capacitor.
11. Soft Start Time
To set the Soft Start time, first calculate the external ramp
size at a duty−cycle of D = 1.225 V/12 V = 0.102.
IPGD 0.52 VROSC
0.52 V51 k
10.2 A
(VIN VOUT)
Ext_Ramp D (RSx CSx fSW)
0.102 (12 V 1.225 V)
(10.0 k 0.1 F 200 kHz)
Next, solve equation 37 for CPGD and substitute as
required.
5.5 mV
CPGD tPGD IPGD(PGDTHRESH PGDMIN)
6 ms 10.2 A(3.0 V 0.25 V)
0.022 F
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(37)
NCP5331
PACKAGE DIMENSIONS
LQFP−32
FT SUFFIX
CASE 873A−02
ISSUE B
A
32
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
4X
A1
0.20 (0.008) AB T−U Z
25
1
−U−
−T−
B
V
B1
DETAIL Y
V1
17
8
9
4X
−Z−
9
0.20 (0.008) AC T−U Z
S1
AC T−U Z
S
BASE
METAL
F
−AC−
0.10 (0.004) AC
M
−AB−
SEATING
PLANE
D
J
0.20 (0.008)
ÉÉ
ÉÉ
ÉÉ
N
DETAIL AD
G
−T−, −U−, −Z−
SECTION AE−AE
8X
M
R
C E
DETAIL AD
0.250 (0.010)
K
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12 REF
0.090
0.160
0.400 BSC
1
5
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12 REF
0.004
0.006
0.016 BSC
1
5
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
P
Q
GAUGE PLANE
H
AE
W
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
AE
DETAIL Y
V2 is a trademark of Switch Power, Inc.
AMD Athlon is a trademark of Advanced Micro Devices, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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Phone: 81−3−5773−3850
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36
For additional information, please contact your
local Sales Representative.
NCP5331/D