Infineon BTS7040-2EPA Smart high-side power switch Datasheet

BTS7040-2EPA
PROFETTM+2
2x 40 mΩ
Smart High-Side Power Switch
1
Package
PG-TSDSO-14-22
Marking
7040-2A
Overview
Potential Applications
•
Suitable for resistive, inductive and capacitive loads
•
Replaces electromechanical relays, fuses and discrete circuits
•
Driving capability suitable for 3.5 A loads and high inrush current loads
such as P27W + R5W lamps or LED equivalent
VBAT
R/L cable
T1
CVS
DZ2
VDD
VS
VDD
GPIO
RIN
IN0
GPIO
RIN
IN1
GPIO
GPIO
RDEN
DEN
RDSEL
DSEL
T
ROL
R/L cable
OUT0
Protection
Micro controller
RPD
Control
COUT0
T
Diagnosis
RAD
A/D IN
IS
RIS_PROT
GND
R/L cable
OUT1
DZ1
RSENSE
CSENSE
RGND
VSS
COUT1
RPD
App_2CH_LI_INTDIO_Cover.emf
Figure 1
Data Sheet
BTS7040-2EPA Application Diagram. Further information in Chapter 10
www.infineon.com
1
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Overview
Basic Features
•
High-Side Switch with Diagnosis and Embedded Protection
•
Part of PROFETTM+2 Family
•
ReverSave™ for low power dissipation in Reverse Polarity
•
Switch ON capability while Inverse Current condition (InverseON)
•
Green Product (RoHS compliant)
•
Qualified in accordance with AEC Q100 grade 1
Protection Features
•
Absolute and dynamic temperature limitation with controlled restart
•
Overcurrent protection (tripping) with Intelligent Restart Control
•
Undervoltage shutdown
•
Overvoltage Protection with external components
Diagnostic Features
•
Proportional load current sense
•
Open Load in ON and OFF state
•
Short circuit to ground and battery
Description
The BTS7040-2EPA is a Smart High-Side Power Switch, providing protection functions and diagnosis. The
device is integrated in SMART7 technology.
Table 1
Product Summary
Parameter
Symbol
Values
Minimum Operating voltage (at switch ON)
VS(OP)
4.1 V
Minimum Operating voltage (cranking)
VS(UV)
3.1 V
Maximum Operating voltage
VS
28 V
Minimum Overvoltage protection (TJ = 25 °C)
VDS(CLAMP)
35 V
Maximum current in Sleep mode (TJ ≤ 85 °C)
IVS(SLEEP)
1 µA
Maximum operative current
IGND(ACTIVE)
4 mA
Maximum ON-state resistance (TJ = 150 °C)
RDS(ON)
36 mΩ
Nominal load current (TA = 85 °C)
IL(NOM)
3.5 A
Typical current sense ratio at IL = IL(NOM)
kILIS
1800
Data Sheet
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BTS7040-2EPA
PROFETTM+2
Block Diagram and Terms
2
Block Diagram and Terms
2.1
Block Diagram
VS
Supply Voltage
Monitoring
Overvolt age
Protec tion
In ternal Power Sup ply
In telligent Restart
Cont rol
IS
Channel 1
Channel 0
SENSE output
Voltage
Sensor
Overtemp
erat
ure
DEN
ESD
Protec tion
+
In put logic
DSEL
In ternal Reverse
Polarity P rotection
OUT1
OUT0
Outp ut Voltage Limitation
GND
Data Sheet
T
Load Current Sense
Outp ut Voltage Limitation
GND c ircu itry
Figure 2
T
Overvolt age
Clamping
Overvolt age
Clamping
Overcurrent
Protec tion
Overcurrent
Protec tion
Overtemp erature
Gat e Co ntrol
+
driver Gat eChargepump
Co ntrol
logic
+
driver
Chargepump
ReverSave TM
logic
In verseO N
ReverSave TM
In verseO N
Load Current Sense
IN0
IN1
Voltage Sensor
Block_PROFET2ch_REVON.emf
Block Diagram of BTS7040-2EPA
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PROFETTM+2
Block Diagram and Terms
2.2
Terms
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.
IVS
VSIS
IINn
VS
VDSn
INn
IDEN
VS
DEN
OUTn
IDSEL
ILn
DSEL
VINn
IIS
VDEN
IS
VDSEL
VOUTn
GND
VIS
IGND
Terms_PROFET.emf
Figure 3
Data Sheet
Voltage and Current Convention
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PROFETTM+2
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
GND
IN0
DEN
IS
DSEL
IN1
n.c.
1
2
3
4
5
6
7
14
13
12
VS
11
10
9
exposed pad (bottom)
8
OUT0
OUT0
OUT0
n.c.
OUT1
OUT1
OUT1
PinOut_PROFET2ch.emf
Figure 4
Data Sheet
Pin Configuration
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BTS7040-2EPA
PROFETTM+2
Pin Configuration
3.2
Pin Definitions and Functions
Table 2
Pin Definition
Pin
Symbol
Function
EP
VS
(exposed pad)
Supply Voltage
Battery voltage
1
GND
Ground
Signal ground
2, 6
INn
Input Channel n
Digital signal to switch ON channel n (“high” active)
If not used: connect with a 10 kΩ resistor either to GND pin or to module
ground
3
DEN
Diagnostic Enable
Digital signal to enable device diagnosis (“high” active) and to clear the
protection counter of channel selected with DSEL pin
If not used: connect with a 10 kΩ resistor either to GND pin or to module
ground
4
IS
SENSE current output
Analog/digital signal for diagnosis
If not used: left open
5
DSEL
Diagnosis Selection
Digital signal to select one channel to perform ON and OFF state diagnosis
(“high” active)
If not used: connect with a 10 kΩ resistor either to GND pin or to module
ground
7, 11
n.c.
Not connected, internally not bonded
8-10, 1214
OUTn
Output n
Protected high-side power output channel n1)
1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally connected
together. PCB traces have to be designed to withstand the maximum current which can flow
Data Sheet
6
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BTS7040-2EPA
PROFETTM+2
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings - General
Table 3
Absolute Maximum Ratings1)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Number
Test Condition
Supply pins
Power Supply Voltage
VS
-0.3
–
28
V
–
P_4.1.0.1
Load Dump Voltage
VBAT(LD)
–
–
35
V
suppressed
Load Dump
acc. to
ISO16750-2
(2010).
Ri = 2 Ω
P_4.1.0.3
Supply Voltage for Short Circuit VBAT(SC)
Protection
0
–
24
V
Setup acc. to
AEC-Q100-012
P_4.1.0.25
Reverse Polarity Voltage
-VBAT(REV)
–
–
16
V
t ≤ 2 min
TA = +25 °C
Setup as
described in
Chapter 10
P_4.1.0.5
Current through GND Pin
IGND
-50
–
50
mA
RGND according P_4.1.0.9
to Chapter 10
Logic & control pins (Digital Input = DI)
DI = INn, DEN, DSEL
Current through DI Pin
IDI
-1
–
2
mA
2)
P_4.1.0.14
Current through DI Pin
Reverse Battery condition
IDI
-1
–
10
mA
2)
P_4.1.0.36
Voltage at IS Pin
VIS
-1.5
–
VS
Current through IS Pin
IIS
-25
–
IIS(SAT),M mA
t ≤ 2 min
IS pin
V
IIS = 10 μA
P_4.1.0.16
–
P_4.1.0.18
AX
Temperatures
Junction Temperature
TJ
-40
–
150
°C
–
P_4.1.0.19
Storage Temperature
TSTG
-55
–
150
°C
–
P_4.1.0.20
ESD Susceptibility
Data Sheet
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PROFETTM+2
General Product Characteristics
Table 3
Absolute Maximum Ratings1) (continued)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit
Note or
Number
Test Condition
Min.
Typ.
Max.
-2
–
2
kV
HBM3)
P_4.1.0.21
ESD Susceptibility OUTn vs GND VESD(HBM)_OU -4
and VS connected (HBM)
T
–
4
kV
HBM3)
P_4.1.0.22
ESD Susceptibility all Pins
(HBM)
VESD(HBM)
ESD Susceptibility all Pins
(CDM)
VESD(CDM)
-500
–
500
V
CDM4)
P_4.1.0.23
ESD Susceptibility Corner Pins
(CDM)
(pins 1, 7, 8, 14)
VESD(CDM)_CR -750
–
750
V
CDM4)
P_4.1.0.24
1)
2)
3)
4)
N
Not subject to production test - specified by design.
Maximum VDI to be considered for Latch-Up tests: 5.5 V
ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)
ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2
Absolute Maximum Ratings - Power Stages
4.2.1
Power Stage - 40 mΩ
Table 4
Absolute Maximum Ratings1)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Maximum Energy Dissipation
Single Pulse
Data Sheet
Symbol
EAS
Values
Min.
Typ.
Max.
–
–
36
8
Unit
Note or
Test Condition
Number
mJ
IL = 2*IL(NOM)
TJ(0) = 150 °C
VS = 28 V
P_4.2.6.1
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2017-08-24
BTS7040-2EPA
PROFETTM+2
General Product Characteristics
Table 4
Absolute Maximum Ratings1) (continued)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
mJ
IL = IL(NOM)
TJ(0) = 85 °C
VS = 13.5 V
1M cycles
P_4.2.6.2
–
P_4.2.6.3
Maximum Energy Dissipation
Repetitive Pulse
EAR
–
–
13
Load Current
|IL|
–
–
IL(OVL),M A
AX
1) Not subject to production test - specified by design.
4.3
Functional Range
Table 5
Functional Range - Supply Voltage and Temperature1)
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
6
13.5
18
V
–
P_4.3.0.1
Lower Extended Supply
VS(EXT,LOW)
Voltage Range for Operation
3.1
–
6
V
2)3)
P_4.3.0.2
Upper Extended Supply
VS(EXT,UP)
Voltage Range for Operation
18
Junction Temperature
-40
Supply Voltage Range for
Normal Operation
VS(NOR)
TJ
(parameter
deviations possible)
–
28
V
3)
P_4.3.0.3
(parameter
deviations possible)
–
150
°C
–
P_4.3.0.5
1) Not subject to production test - specified by design.
2) In case of VS voltage decreasing: VS(EXT,LOW),MIN = 3.1 V. In case of VS voltage increasing: VS(EXT,LOW),MIN = 4.1 V
3) Protection functions still operative
Note:
Data Sheet
Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics
tables.
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PROFETTM+2
General Product Characteristics
4.4
Thermal Resistance
Note:
This thermal data was generated in accordance with JEDEC JESD51 standards. For more
information, go to www.jedec.org.
Table 6
Thermal Resistance1)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Thermal Characterization
Parameter Junction-Top
ΨJTOP
–
2.4
4.1
K/W
2)
P_4.4.0.1
Thermal Resistance
Junction-to-Case
RthJC
–
1.6
2.7
K/W
2)
P_4.4.0.2
Thermal Resistance
Junction-to-Ambient
RthJA
–
simulated at
exposed pad
31.8
–
K/W
2)
P_4.4.0.3
1) Not subject to production test - specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip
+ Package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. Simulation done
at TA = 105°C, PDISSIPATION = 1 W.
4.4.1
PCB Setup
1,5 mm
70 µm Modeled (traces, cooling area)
70 µm, 5% metalization*
*: means percentual Cu metalization on each layer
Figure 5
PCB_Zth_1s0p.emf
1s0p PCB Cross Section
70 µm modelled (traces)
1,5 mm
35 µm, 90% metalization*
35 µm, 90% metalization*
70 µm, 5% metalization*
*: means percentual Cu metalization on each layer
PCB_Zth_2s2p.emf
Figure 6
Data Sheet
2s2p PCB Cross Section
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PROFETTM+2
General Product Characteristics
PCB 1s0p + 600 mm2 cooling
PCB 2s2p / 1s0p footprint
PCB_sim _setup_TSDSO14.emf
Figure 7
PCB setup for thermal simulations
PCB_2s2p_vias_TSDSO14.emf
Figure 8
Thermal vias on PCB for 2s2p PCB setup
4.4.2
Thermal Impedance
Data Sheet
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BTS7040-2EPA
PROFETTM+2
General Product Characteristics
BTS7040-2EPx
100
ZthJA (K/W)
TA = 105°C
10
1
2s2p
1s0p - 600 mm
1s0p - 300 mm
1s0p - footprint
0.1
0.0001
Figure 9
0.001
0.01
0.1
1
Time (s)
10
100
1000
Typical Thermal Impedance. PCB setup according Chapter 4.4.1
BTS7040-EPx
130
1s0p - Ta = 105°C
120
110
100
RthJA (K/W)
90
80
70
60
50
40
30
0
Figure 10
Data Sheet
100
200
300
Cooling area (mm2)
400
500
600
Thermal Resistance on 1s0p PCB with various cooling surfaces
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PROFETTM+2
Logic Pins
5
Logic Pins
The device has 4 digital pins for direct control.
5.1
Input Pins (INn)
The input pins IN0, IN1 activate the corresponding output channel. The input circuitry is compatible with 3.3V
and 5V micro controller. The electrical equivalent of the input circuitry is shown in Figure 11. In case the pin
is not used, it must be connected with a 10 kΩ resistor either to GND pin or to module ground.
VS
IN
VS(CLAMP )
IDI
ESD
IDI
VDI (CLAMP)
V DI
IGND
RGND
GND
Input_IN_INTDIO.emf
Figure 11
Input circuitry
The logic thresholds for “low” and “high” states are defined by parameters VDI(TH) and VDI(HYS). The relationship
between these two values is shown in Figure 12. The voltage VIN needed to ensure a “high” state is always
higher than the voltage needed to ensure a “low” state.
V DI
V DI(TH ),M AX
V DI(TH)
V DI(HYS)
V DI(TH ),M IN
t
Internal channel
activation signal
0
x
1
x
0
t
Input_VDITH_2.emf
Figure 12
Data Sheet
Input Threshold voltages and hysteresis
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PROFETTM+2
Logic Pins
5.2
Diagnosis Pin
The Diagnosis Enable (DEN) pin controls the diagnosis circuitry and the protection circuitry. When DEN pin is
set to “high”, the diagnosis is enabled (see Chapter 9.2 for more details). When it is set to “low”, the diagnosis
is disabled (IS pin is set to high impedance).
The Diagnosis Selection (DSEL) pin selects the channel where diagnosis is performed (see Chapter 9.1.1).
The transition from “high” to “low” of DEN pin clears the protection latch of the channel selected with DSEL
pin depending on the logic state of IN pin and DEN pulse length (see Chapter 8.3 for more details). The internal
structure of diagnosis pins is the same as the one of input pins. See Figure 11 for more details.
Data Sheet
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BTS7040-2EPA
PROFETTM+2
Logic Pins
5.3
Electrical Characteristics Logic Pins
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Digital Input (DI) pins = IN, DEN, DSEL
Table 7
Electrical Characteristics: Logic Pins - General
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Digital Input Voltage
Threshold
VDI(TH)
0.8
1.3
2
V
See Figure 11 and P_5.4.0.1
Figure 12
Digital Input Clamping
Voltage
VDI(CLAMP1)
–
7
–
V
1)
Digital Input Clamping
Voltage
VDI(CLAMP2)
6.5
7.5
8.5
V
IDI = 2 mA
P_5.4.0.3
See Figure 11 and
Figure 12
Digital Input Hysteresis
VDI(HYS)
–
0.25
–
V
1)
IDI
2
10
25
µA
VDI = 2 V
P_5.4.0.5
See Figure 11 and
Figure 12
Digital Input Current (“low”) IDI
2
10
25
µA
VDI = 0.8 V
P_5.4.0.6
See Figure 11 and
Figure 12
Digital Input Current
(“high”)
P_5.4.0.2
IDI = 1 mA
See Figure 11 and
Figure 12
P_5.4.0.4
See Figure 11 and
Figure 12
1) Not subject to production test - specified by design
Data Sheet
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Rev. 1.00
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BTS7040-2EPA
PROFETTM+2
Power Supply
6
Power Supply
The BTS7040-2EPA is supplied by VS, which is used for the internal logic as well as supply for the power output
stages. VS has an undervoltage detection circuit, which prevents the activation of the power output stages and
diagnosis in case the applied voltage is below the undervoltage threshold.
6.1
Operation Modes
BTS7040-2EPA has the following operation modes:
•
Sleep mode
•
Active mode
•
Stand-by mode
The transition between operation modes is determined according to these variables:
•
logic level at INn pins
•
logic level at DEN pin
The state diagram including the possible transitions is shown in Figure 13. The behavior of BTS7040-2EPA as
well as some parameters may change in dependence from the operation mode of the device. Furthermore,
due to the undervoltage detection circuitry which monitors VS supply voltage, some changes within the same
operation mode can be seen accordingly.
There are three parameters describing each operation mode of BTS7040-2EPA:
•
status of the output channel
•
status of the diagnosis
•
current consumption at VS pin (measured by IVS in Sleep mode, IGND in all other operative modes)
Table 8 shows the correlation between operation modes, VS supply voltage, and the state of the most
important functions (channel status, diagnosis).
Unsupplied
Power-up
VS > VS(OP)
IN = „low“
& DEN = „low“
IN = „high“
Sleep
IN = „low“ &
DEN = „high“
IN = „low“
& DEN = „low“
Active
DEN = „high“
IN = „high“
DEN = „low“
Figure 13
Data Sheet
Stand-by
IN = „low“
& DEN = „high“
PowerSupply_OpMode_PROFE T.emf
Operation Mode State Diagram
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PROFETTM+2
Power Supply
Table 8
Device function in relation to operation modes and VS voltage
Operative Mode Function
VS in undervoltage
VS not in undervoltage
Sleep
Channels
OFF
OFF
Diagnosis
OFF
OFF
Channels
OFF
available
Diagnosis
OFF
available in OFF and ON states
Channels
OFF
OFF
Diagnosis
OFF
available in OFF state
Active
Stand-by
6.1.1
Unsupplied
In this state, the device is either unsupplied (no voltage applied to VS pin) or the supply voltage is below the
undervoltage threshold.
6.1.2
Power-up
The Power-up condition is entered when the supply voltage (VS) is applied to the device. The supply is rising
until it is above the undervoltage threshold VS(OP) therefore the internal power-on signals are set.
6.1.3
Sleep mode
The device is in Sleep mode when all Digital Input pins (INn, DEN, DSEL) are set to “low”. When BTS7040-2EPA
is in Sleep mode, all outputs are OFF. The current consumption is minimum (see parameter IVS(SLEEP)). No
Overtemperature or Overload protection mechanism is active when the device is in Sleep mode. The device
can go in Sleep mode only if the protection is not active (counter = 0, see Chapter 8.3.1 for further details).
6.1.4
Stand-by mode
The device is in Stand-by mode as long as DEN pin is set to “high” while input pins are set to “low”. All channels
are OFF therefore only Open Load in OFF diagnosis is possible. Depending on the load condition, either a fault
current IIS(FAULT) or an Open Load in OFF current IIS(OLOFF) may be present at IS pin. In such situation, the current
consumption of the device is increased.
6.1.5
Active mode
Active mode is the normal operation mode of BTS7040-2EPA. The device enters Active mode as soon as one IN
pin is set to “high”. Device current consumption is specified with IGND(ACTIVE) (measured at GND pin because the
current at VS pin includes the load current). Overload, Overtemperature and Overvoltage protections are
active. Diagnosis is available.
6.2
Undervoltage on VS
Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative (in Active mode)
and the supply voltage drops below the undervoltage threshold VS(UV), the internal logic switches OFF the
output channels.
As soon as the supply voltage VS is above the operative threshold VS(OP), the channels having the corresponding
input pin set to “high” are switched ON again. The restart is delayed with a time tDELAY(UV) which protects the
device in case the undervoltage condition is caused by a short circuit event (according to AEC-Q100-012), as
shown in Figure 14.
Data Sheet
17
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BTS7040-2EPA
PROFETTM+2
Power Supply
If the device is in Sleep mode and one input is set to “high”, the corresponding channel is switched ON if
VS > VS(OP) without waiting for tDELAY(UV).
VS
VS(OP)
VS(UV)
VS(HYS)
t
Channel
activat ion signal
t
VOUT
tDELA Y(UV)
t
PowerSupply_UVRVS.emf
Figure 14
Data Sheet
VS undervoltage behavior
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PROFETTM+2
Power Supply
6.3
Electrical Characteristics Power Supply
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
RL = 3.3 Ω
Table 9
Electrical Characteristics: Power Supply - General
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
Power Supply Undervoltage VS(UV)
Shutdown
1.8
2.3
3.1
V
VS decreasing
IN = “high”
From VDS ≤ 0.5 V to
VDS = VS
See Figure 14
P_6.4.0.1
Power Supply Minimum
Operating Voltage
2.0
3.0
4.1
V
VS increasing
IN = “high”
From VDS = VS to
VDS ≤ 0.5 V
See Figure 14
P_6.4.0.3
Power Supply Undervoltage VS(HYS)
Shutdown Hysteresis
–
0.7
–
V
1)
P_6.4.0.6
Power Supply Undervoltage tDELAY(UV)
Recovery Time
2.5
5
7.5
ms
dVS/dt ≤ 0.5 V/µs
VS ≥ -1 V
See Figure 14
P_6.4.0.7
Breakdown Voltage
-VS(REV)
between GND and VS Pins in
Reverse Battery
16
–
30
V
1)
P_6.4.0.9
VS pin
VS(OP)
VS(OP) - VS(UV)
See Figure 14
IGND(REV) = 7 mA
TJ = 150 °C
1) Not subject to production test - specified by design
6.4
Electrical Characteristics Power Supply - product specific
6.4.1
BTS7040-2EPA
Data Sheet
19
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Power Supply
Table 10
Electrical Characteristics: Power Supply BTS7040-2EPA
Parameter
Symbol
Power Supply Current
IVS(SLEEP)_85
Consumption in Sleep Mode
with Loads at TJ ≤ 85 °C
Values
Min.
Typ.
Max.
–
0.03
0.5
IGND(ACTIVE)
Operating Current in Stand- IGND(STBY)
by Mode
Note or
Test Condition
Number
µA
1)
P_6.5.6.1
VS = 18 V
VOUT = 0 V
IN = DEN = “low”
TJ ≤ 85 °C
Power Supply Current
IVS(SLEEP)_150 –
Consumption in Sleep Mode
with Loads at TJ = 150 °C
Operating Current in Active
Mode (all Channels ON)
Unit
3.5
14
µA
VS = 18 V
VOUT = 0 V
IN = DEN = “low”
TJ = 150 °C
P_6.5.6.2
–
3
4
mA
VS = 18 V
IN = DEN = “high”
P_6.5.6.3
–
1.2
1.8
mA
VS = 18 V
IN = “low”
DEN = “high”
P_6.5.6.5
1) Not subject to production test - specified by design
Data Sheet
20
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Power Stages
7
Power Stages
The high-side power stages are built using a N-channel vertical Power MOSFET with charge pump.
7.1
Output ON-State Resistance
The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 15 shows the variation of
RDS(ON) across the whole TJ range. The value “2” on the y-axis corresponds to the maximum RDS(ON) measured
at TJ = 150 °C.
RDS(ON) variation over TJ
2.20
Reference value:
"2" = RDS(ON),MAX @ 150 °C
2.00
1.80
RDS(ON) variation factor
1.60
1.40
1.20
1.00
0.80
0.60
0.40
Typical
0.20
0.00
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
Junction Temperature (°C)
Figure 15
RDS(ON) variation factor
The behavior in Reverse Polarity is described in Chapter 8.4.1.
7.2
Switching loads
7.2.1
Switching Resistive Loads
When switching resistive loads, the switching times and slew rates shown in Figure 16 can be considered. The
switch energy values EON and EOFF are proportional to load resistance and times tON and tOFF.
Data Sheet
21
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Power Stages
IN
VIN(TH)
VIN(HYS)
t
VOUT
tON
90% of VS
tOFF(DELAY)
70% of VS
70% of VS
-(dV/dt)OFF
(dV/dt)ON
30% of VS
tON(DELAY)
10% of VS
30% of VS
tOFF
t
PDMOS
EON
EOFF
t
PowerStage_SwitchRes.emf
Figure 16
Switching a Resistive Load
7.2.2
Switching Inductive Loads
When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential,
because the inductance intends to continue driving the current. To prevent the destruction of the device due
to overvoltage, a voltage clamp mechanism is implemented. The clamping structure limits the negative
output voltage so that VDS = VDS(CLAMP). Figure 17 shows a concept drawing of the implementation. The
clamping structure protects the device in all operation modes listed in Chapter 6.1.
VS
High-side
Channel
VS
VIS (CLAMP)
VDS
VDS(CLAMP)
IS
IL
RSENSE
VS(CLAMP)
OUTn
GND
VO UTn
L,
RL
RGN D
IL
PowerStage_Clamp_INTDIO.emf
Figure 17
Data Sheet
Output Clamp concept
22
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Power Stages
During demagnetization of inductive loads, energy has to be dissipated in BTS7040-2EPA. The energy can be
calculated with Equation (7.1):
RL  IL
V S – V DS  CLAMP 
L
- + I L  -----E = V DS  CLAMP   --------------------------------------------  ln  1 – ------------------------------------------
RL
RL
V S – V DS  CLAMP 
(7.1)
The maximum energy, therefore the maximum inductance for a given current, is limited by the thermal design
of the component.
7.2.3
Output Voltage Limitation
To increase the current sense accuracy, VDS voltage is monitored. When the output current IL decreases while
the channel is diagnosed (DEN pin set to “high”, channel selected with DSEL pins - see Figure 18) bringing VDS
equal or lower than VDS(SLC), the output DMOS gate is partially discharged. This increases the output resistance
so that VDS = VDS(SLC) even for very small output currents. The VDS increase allows the current sensing circuitry
to work more efficiently, providing better kILIS accuracy for output current in the low range.
IN
t
DEN
IL
tsIS(ON)
tsIS(OFF)
t
t
VDS
VS
VDS(SLC)
t
PowerStage_GBR_diag.emf
Figure 18
Output Voltage Limitation activation during diagnosis
7.3
Advanced Switching Characteristics
7.3.1
Inverse Current behavior
When VOUT > VS, a current IINV flows into the power output transistor (see Figure 19). This condition is known
as “Inverse Current”.
If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses
therefore an increase of overall device temperature. This may lead to a switch OFF of unaffected channels due
to Overtemperature. If the channel is in ON state, RDS(INV) can be expected and power dissipation in the output
stage is comparable to normal operation in RDS(ON).
During Inverse Current condition, the channel remains in ON or OFF state as long as IINV < IL(INV). If one channel
has inverse current applied, the neighbor channel is not influenced, meaning that switching ON and OFF
timings, protection (Overcurrent, Overtemperature) and current sensing (kILIS) are still within specified limits.
Data Sheet
23
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Power Stages
With InverseON, it is possible to switch ON the channel during Inverse Current condition as long as IINV < IL(INV)
(see Figure 20).
VBAT
VS
Gate
driver
Device
logic
IINV
INV
Comp.
VINV = VOUT > VS
OUT
RGND
GND
PowerStage_Inv Curr_INTDIO.emf
Figure 19
Inverse Current Circuitry
IN
IN
CASE 1 : Switch is ON
CASE 2 : Switch is OFF
OFF
ON
t
IL
NORMAL
t
IL
NORMAL
NORMAL
t
INVERSE
NORMAL
t
INVERSE
DMOS state
DMOS state
OFF
ON
t
t
CASE 3 : Switch ON into Inverse Current
CASE 4 : Switch OFF into Inverse Current
IN
IN
OFF
ON
IL
NORMAL
t
IL
NORMAL
NORMAL
t
INVERSE
OFF
ON
t
NORMAL
t
INVERSE
DMOS state
DMOS state
OFF
ON
ON
OFF
t
t
PowerStage_InvCurr_INVON.emf
Figure 20
Data Sheet
InverseON - Channel behavior in case of applied Inverse Current
24
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Power Stages
Note:
No protection mechanism like Overtemperature or Overload protection is active during applied
Inverse Currents.
7.3.2
Switching Channels in Parallel
In case of appearance of a short circuit with connected in parallel to drive a single load, it may happen that the
two channels switch OFF asynchronously, therefore bringing an additional thermal stress to the channel that
switches OFF last. For this reason it is not recommended to use the device with channels in parallel.
7.3.3
Cross Current robustness with H-Bridge configuration
When BTS7040-2EPA is used as high-side switch e.g. in a bridge configuration (therefore paired with a low-side
switch as shown in Figure 21), the maximum slew rate applied to the output by the low-side switch must be
lower than | dVOUT / dt |. Otherwise the output stage may turn ON in linear mode (not in RDS(ON)) while the lowside switch is commutating. This creates an unprotected over heating situation for the DMOS due to the crossconduction current.
VBAT
R/L cable
VS
T
T
ON (DC)
IN1
IN0
OUT1
OUT0
Current through Motor
OFF
| dVOUT / dt |
Cross
Current
M
ON (PWM)
OFF
PowerSt age_PassiveSlew_PROFET.emf
Figure 21
Data Sheet
High-Side switch used in Bridge configuration
25
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Power Stages
7.4
Electrical Characteristics Power Stages
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
RL = 3.3 Ω
Table 11
Electrical Characteristics: Power Stages - General
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Voltages
Drain to Source Clamping
Voltage at TJ = -40 °C
VDS(CLAMP)_-40 33
36.5
42
V
IL = 5 mA
TJ = -40°C
See Figure 17
P_7.4.0.1
Drain to Source Clamping
Voltage at TJ ≥ 25 °C
VDS(CLAMP)_25 35
38
44
V
1)
P_7.4.0.2
IL = 5 mA
TJ ≥ 25°C
See Figure 17
1) Tested at TJ = 150°C
7.4.1
Electrical Characteristics Power Stages - PROFET
Table 12
Electrical Characteristics: Power Stages - PROFET
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Timings
Switch-ON Delay
tON(DELAY)
10
35
60
μs
VS = 13.5 V
VOUT = 10% VS
See Figure 16
P_7.4.1.1
Switch-OFF Delay
tOFF(DELAY)
10
25
50
μs
VS = 13.5 V
VOUT = 90% VS
See Figure 16
P_7.4.1.2
Switch-ON Time
tON
30
60
110
μs
VS = 13.5 V
VOUT = 90% VS
See Figure 16
P_7.4.1.3
Switch-OFF Time
tOFF
15
50
100
μs
VS = 13.5 V
VOUT = 10% VS
See Figure 16
P_7.4.1.4
Switch-ON/OFF Matching
tON - tOFF
ΔtSW
-20
20
60
μs
VS = 13.5 V
P_7.4.1.5
Voltage Slope
Data Sheet
26
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Power Stages
Table 12
Electrical Characteristics: Power Stages - PROFET (continued)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
Switch-ON Slew Rate
(dV/dt)ON
0.3
0.6
0.9
V/μs
VS = 13.5 V
P_7.4.1.6
VOUT = 30% to 70%
of VS
See Figure 16
Switch-OFF Slew Rate
-(dV/dt)OFF
0.3
0.6
0.9
V/μs
VS = 13.5 V
P_7.4.1.7
VOUT = 70% to 30%
of VS
See Figure 16
Slew Rate Matching
(dV/dt)ON - (dV/dt)OFF
Δ(dV/dt)SW
-0.15
0
0.15
V/μs
VS = 13.5 V
P_7.4.1.8
VDS(SLC)
2
7
18
mV
1)
P_7.4.1.9
Voltages
Output Voltage Drop
Limitation at Small Load
Currents
DEN = “high”
channel selected
with DSEL pin
IL = IL(OL) = 20 mA
See Figure 18
1) Not subject to production test - specified by design
7.5
Electrical Characteristics - Power Output Stages
7.5.1
Power Output Stage - 40 mΩ
Table 13
Electrical Characteristics: Power Stages - 40 mΩ
Parameter
Symbol
Values
Min.
Typ.
Max.
19
–
Unit
Note or
Test Condition
Number
mΩ
1)
P_7.5.6.1
Output characteristics
ON-State Resistance at
TJ = 25 °C
RDS(ON)_25
–
ON-State Resistance at
TJ = 150 °C
RDS(ON)_150
–
–
36
mΩ
TJ = 150 °C
IL = 2 A
P_7.5.6.2
ON-State Resistance in
Cranking
RDS(ON)_CRAN –
–
45
mΩ
TJ = 150 °C
VS = 3.1 V
IL = 0.75 A
P_7.5.6.3
21
–
mΩ
1)
P_7.5.6.4
K
RDS(INV)_25
ON-State Resistance in
Inverse Current at TJ = 25 °C
Data Sheet
TJ = 25 °C
–
TJ = 25 °C
VS = 13.5 V
IL = -2 A
27
Rev. 1.00
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BTS7040-2EPA
PROFETTM+2
Power Stages
Table 13
Electrical Characteristics: Power Stages - 40 mΩ (continued)
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
ON-State Resistance in
RDS(INV)_150
Inverse Current at TJ = 150 °C
–
–
45
mΩ
TJ = 150 °C
VS = 13.5 V
IL = -2 A
P_7.5.6.5
RDS(REV)_25
ON-State Resistance in
Reverse Polarity at TJ = 25 °C
–
21
–
mΩ
1)
P_7.5.6.6
TJ = 25 °C
VS = -13.5 V
IL = -2 A
RSENSE = 1.2 kΩ
ON-State Resistance in
Reverse Polarity at
TJ = 150 °C
RDS(REV)_150
–
–
74
mΩ
TJ = 150 °C
VS = -13.5 V
IL = -2 A
RSENSE = 1.2 kΩ
P_7.5.6.7
Nominal Load Current per
Channel (all Channels
Active)
IL(NOM)
–
3.5
–
A
1)
P_7.5.6.8
Output Leakage Current at
TJ ≤ 85 °C
IL(OFF)_85
–
Output Leakage Current at
TJ = 150 °C
IL(OFF)_150
–
1.2
4
μA
VOUT = 0 V
VIN = “low”
TA = 150 °C
P_7.5.6.10
Inverse Current Capability
IL(INV)
–
3.5
–
A
1)
P_7.5.6.11
TA = 85 °C
TJ ≤ 150 °C
0.01
0.5
μA
1)
P_7.5.6.9
VOUT = 0 V
VIN = “low”
TA ≤ 85 °C
VS < VOUT
IN = “high”
Voltage Slope
Passive Slew Rate (e.g. for
Half Bridge Configuration)
|dVOUT / dt | –
–
10
V/μs
1)
P_7.5.6.12
VS = 13.5 V
Voltages
Drain Source Diode Voltage |VDS(DIODE)|
–
650
700
mV
IL = -190 mA
TJ = 150 °C
P_7.5.6.13
Switch-ON Energy
EON
–
0.44
–
mJ
1)
P_7.5.6.14
EOFF
–
Switch-OFF Energy
VS = 18 V
0.55
–
mJ
1)
P_7.5.6.15
VS = 18 V
1) Not subject to production test - specified by design
Data Sheet
28
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Protection
8
Protection
The BTS7040-2EPA is protected against Overtemperature, Overload, Reverse Battery (with ReverSave™) and
Overvoltage. Overtemperature and Overload protections are working when the device is not in Sleep mode.
Overvoltage protection works in all operation modes. Reverse Battery protection works when the GND and VS
pins are reverse supplied.
8.1
Overtemperature Protection
The device incorporates both an absolute (TJ(ABS)) and a dynamic (TJ(DYN)) temperature protection circuitry for
each channel. An increase of junction temperature TJ above either one of the two thresholds (TJ(ABS) or TJ(DYN))
switches OFF the overheated channel to prevent destruction. The channel remains switched OFF until
junction temperature has reached the “Restart” condition described in Table 14. The behavior is shown in
Figure 22 (absolute Overtemperature Protection) and Figure 23 (dynamic Overtemperature Protection).
TJ(REF) is the reference temperature used for dynamic temperature protection.
IN
t
DEN
t
IL
IL(OVL)
t
THYS(ABS)
TJ
TJ(ABS)
IIS
t
tIS(FAUL T)_D
IIS(SA T)
IIS(FAUL T)
IL / kILIS
t
In ternal
count er
1
0
t
Protection_PROFET_OT_IRC.emf
Figure 22
Data Sheet
Overtemperature Protection (Absolute)
29
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Protection
IN
t
DEN
t
IL
IL(OVL)
t
TJ(DYN)
TJ
TJ(ABS)
TJ(REF)
t
tIS(FAUL T)_D
IIS
IIS(FAUL T)
IL / kILIS
t
In ter nal
count er
0
1
2
t
Protection_PROFET_dT_IRC.emf
Figure 23
Overtemperature Protection (Dynamic)
When the Overtemperature protection circuitry allows the channel to be switched ON again, the retry strategy
described in Chapter 8.3 is followed.
8.2
Overload Protection
The BTS7040-2EPA is protected in case of Overload or short circuit to ground. Two Overload thresholds are
defined (see Figure 24) and selected automatically depending on the voltage VDS across the power DMOS:
•
IL(OVL0) when VDS < 13 V
•
IL(OVL1) when VDS > 22 V
Data Sheet
30
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Protection
Overload threshold variation ("1" = IL(OVL) typ @ VDS = 5 V)
1.1
IL(OVL0)
1
0.9
0.8
0.7
0.6
IL(OVL1)
0.5
0.4
0.3
0.2
0.1
0
4
6
8
10
12
14
16
18
20
22
24
26
28
Drain Source Voltage (V)
Figure 24
Overload Current Thresholds variation with VDS
In order to allow a higher load inrush at low ambient temperature, Overload threshold is maximum at low
temperature and decreases when TJ increases (see Figure 25). IL(OVL0) typical value remains constant up to a
junction temperature of +75 °C.
IL(OVL0) variation over TJ
1.3
1.2
1.1
IL(OVL0) variation factor
1.0
0.9
0.8
0.7
reference value
"1" = IL(OVL0) typ @ -40 °C
0.6
0.5
0.4
0.3
0.2
0.1
Typ
0.0
-40
-20
0
20
40
60
80
100
120
140
160
Junction Temperature (°C)
Figure 25
Data Sheet
Overload Current Thresholds variation with TJ
31
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Protection
Power supply voltage VS can increase above 18 V for short time, for instance in Load Dump or in Jump Start
condition. Whenever VS ≥ VS(JS), the overload detection current is set to IL(OVL_JS) as shown in Figure 26.
I L(OVL )
IL(OVL_ JS)
VS
V S(JS)
Protection_JS.emf
Figure 26
Overload Detection Current variation with VS voltage
When IL ≥ IL(OVL) (either IL(OVL0) or IL(OVL1)), the channel is switched OFF. The channel is allowed to restart
according to the retry strategy described in Chapter 8.3.
8.3
Protection and Diagnosis in case of Fault
Any event that triggers a protection mechanism (either Overtemperature or Overload) has 2 consequences:
•
the affected channel switches OFF and the internal counter is incremented
•
if the diagnosis is active for the affected channel, a current IIS(FAULT) is provided by IS pin (see Chapter 9.2.2
for further details)
The channel can be switched ON again if all the protection mechanisms fulfill the “restart” conditions
described in Table 14. Furthermore, the device has an internal retry counter (one for each channel) to
maximize the robustness in case of fault.
Table 14
Protection “Restart” Condition
Fault condition
Switch OFF event
“Restart” Condition
Overtemperature
TJ ≥ TJ(ABS) or (TJ - TJ(REF)) ≥ TJ(DYN)
TJ < TJ(ABS) and (TJ - TJ(REF)) < TJ(DYN)
(including hysteresis)
Overload
IL ≥ IL(OVL)
IL < 50 mA
TJ within TJ(ABS) and TJ(DYN) ranges
(including hysteresis)
8.3.1
Retry Strategy
When IN is set to “high”, the channel is switched ON. In case of fault condition the output stage is switched
OFF. The channel can be allowed to restart only if the “restart” conditions for the protection mechanisms are
fulfilled (see Table 14).
Data Sheet
32
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Protection
The channel is allowed to switch ON for nRETRY(CR) times before switching OFF. After a time tRETRY, if the input pin
is set to “high”, the channel switches ON again for nRETRY(NT) times before switching OFF again (“retry” cycle).
After nRETRY(CYC) consecutive “retry” cycles, the channel latches OFF. It is necessary to set the input pin to “low”
for a time longer than tDELAY(CR) to de-latch the channel (“counter reset delay” time) and to reset the internal
counter to the default value.
During the “counter reset delay” time, if the input is set to “high” the channel remains switched OFF and the
timer counting tDELAY(CR) is reset, starting to count again as soon as the input pin is set to “low” again. If the
input pin remains “low” for a time longer than tDELAY(CR) the internal retry counter is reset to the default value,
allowing nRETRY(CR) retries at the next channel activation.
The retry strategy is shown in Figure 29 (flowchart), Figure 27 (timing diagram - input pin always “high”) and
Figure 28 (timing diagram - channel controlled in PWM).
IN
t
Short c ircu it
to ground
t
nRETR Y(CYC)
"retry" cycle
nRETRY(CR)
IL
In ternal
counter
0
nR ETR Y(NT)
1
nRETR Y(NT)
tR ETR Y
tRETRY
nR ETR Y(C R)
nRETR Y(CR) + nR ETRY(NT)
t
tDELA Y(CR)
nR ETRY(C R) + (nRETRY(CYC) * nRETR Y(NT))
0
t
DEN
t
IIS(FAUL T)
IL / kILIS
IIS
IL / kILIS
t
Protection_PROFET_time_noPWM.emf
Figure 27
Retry Strategy Timing Diagram
IN
t
Short c ircu it
to ground
t
nRETR Y(CYC)
"retry" cy cle
nR ETR Y(C R)
IL
In ter nal
count er
0
1
nR ETR Y(NT)
nRETRY(NT)
tRETRY
tR ETRY
nRETR Y(CR)
nRETRY(CR) + nR ETR Y(NT)
t
tDELA Y(CR)
nRETR Y(CR) + (nR ETR Y(C YC) * nR ETR Y(NT))
0
t
Protect ion_PROFET_Timings.emf
Figure 28
Data Sheet
Retry Strategy Timing Diagram - Channel operated in PWM
33
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Protection
START
Channel remains OFF
IN is "high"
no
yes
yes
"Retry" cycles =
nRETRY(CYC)
no
no
ALL "Restart"
conditions fulfilled
Switch channel OFF
yes
no
Switch channel ON
IN is "high"
yes
Channel remains ON
Fault
(Overtemperature or
Overload)
no
yes
Switch channel OFF
Counter++
"Retry" cycles++
yes
Counter < nRETRY(CR)
Wait for tRETRY
no
"Retry" cycles =
nRETRY(CYC)
no
yes
Wait until IN is "low" then
start counting for tDELAY(CR)
IN is "low"
no
yes
Continue counting for
tDELAY(CR)
tDELAY(CR) elapsed
no
yes
Counter = 0
"Retry" cycles = 0
Protection_PROFET_Flow.emf
Figure 29
Data Sheet
Retry Strategy Flowchart
34
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Protection
It is possible to “force” a reset of the internal counter without waiting for tDELAY(CR) by applying a pulse (rising
edge followed by a falling edge) to the DEN pin while IN pin is “low”. The pulse applied to DEN pin must have
a duration longer than tDEN(CR) to ensure a reset of the internal counter. The DSEL pin must select the channel
that has to be de-latched and keep the same logic value while DEN pin toggles twice (rising edge followed by
a falling edge).
The timings are shown in Figure 30.
IN
t
Short c ircu it
to ground
t
nRETRY(CR)
IL
nRETRY(CR)
t
In ternal
count er
0
1
nRETRY(CR)
0 1
nRETRY(CR)
0
t
DEN
tDEN(CR)
tDEN(CR)
tDEN(CR)
t
Protection_PROFET_DENforce_time2.emf
Figure 30
Retry Strategy Timing Diagram with Forced Reset
8.4
Additional protections
8.4.1
Reverse Polarity Protection
In Reverse Polarity condition (also known as Reverse Battery), the output stages are switched ON (see
parameter RDS(REV)) because of ReverSave™ feature which limits the power dissipation in the output stages.
Each ESD diode of the logic contributes to total power dissipation. The reverse current through the output
stages must be limited by the connected loads. The current through digital input pins has to be limited as well
by an external resistor (please refer to the Absolute Maximum Ratings listed in Chapter 4.1 and to Application
Information in Chapter 10).
Figure 31 shows a typical application including a device with ReverSave™. A current flowing into GND pin (IGND) during Reverse Polarity condition is necessary to activate ReverSave™, therefore a resistive path between
module ground and device GND pin must be present.
Data Sheet
35
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Protection
-V BAT(REV)
High-side
Channel
Micro controller
DO
VS
IDI
RDI
DI
ReverSave TM
OUTn
-IL
IS
GND
R GND
-IIS
RSE NSE
GND
L, C, R
-I GND
Protection_RevBatt.emf
Figure 31
Reverse Battery Protection (application example)
8.4.2
Overvoltage Protection
In the case of supply voltages between VS(EXT,UP) and VBAT(LD), the output transistors are still operational and
follow the input pin. In addition to the output clamp for inductive loads as described in Chapter 7.2.2, there
is a clamp mechanism available for Overvoltage protection for the logic and the output channels, monitoring
the voltage between VS and GND pins (VS(CLAMP)).
8.5
Protection against loss of connection
8.5.1
Loss of Battery and Loss of Load
The loss of connection to battery or to the load has no influence on device robustness when load and wire
harness are purely resistive. In case of driving an inductive load, the energy stored in the inductance must be
handled. PROFETTM+2 devices can handle the inductivity of the wire harness up to 10 µH with IL(NOM). In case of
applications where currents and/or the aforementioned inductivity are exceeded, an external suppressor
diode (like diode DZ2 shown in Chapter 10) is recommended to handle the energy and to provide a welldefined path to the load current.
8.5.2
Loss of Ground
In case of loss of module ground with the load remaining connected to ground, the device protects itself by
automatically switching OFF (when it was previously ON) or remains OFF, regardless of the voltage applied on
IN pins.
In case of loss of device ground, it is recommended to have a resistor connected between any Digital Input pin
and the micro controller to ensure a channel switch OFF (as described in Chapter 10).
Data Sheet
36
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Protection
8.6
Electrical Characteristics Protection
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
RL = 3.3 Ω
Table 15
Electrical Characteristics: Protection - General
Parameter
Symbol
Values
Min.
Typ.
Max.
175
200
Thermal Shutdown
Temperature (Absolute)
TJ(ABS)
150
Thermal Shutdown
Hysteresis (Absolute)
THYS(ABS)
–
Thermal Shutdown
Temperature (Dynamic)
TJ(DYN)
–
Power Supply Clamping
Voltage at TJ = -40 °C
VS(CLAMP)_-40 33
Power Supply Clamping
Voltage at TJ ≥ 25 °C
VS(CLAMP)_25
Power Supply Voltage
VS(JS)
Threshold for Overcurrent
Threshold Reduction in case
of Short Circuit
Unit
Note or
Test Condition
Number
°C
1)2)
P_8.6.0.1
See Figure 22
30
–
K
3)
P_8.6.0.2
See Figure 22
80
–
K
3)
P_8.6.0.3
See Figure 23
35
36.5
42
V
IVS = 5 mA
TJ = -40 °C
See Figure 17
P_8.6.0.6
38
44
V
2)
P_8.6.0.7
IVS = 5 mA
TJ ≥ 25 °C
See Figure 17
20.5
22.5
24.5
V
3)
P_8.6.0.8
Setup acc. to AECQ100-012
1) Functional test only
2) Tested at TJ = 150°C only
3) Not subject to production test - specified by design
8.6.1
Electrical Characteristics Protection
Table 16
Electrical Characteristics: Protection
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Automatic Retries in Case of nRETRY(CR)
Fault after a Counter Reset
–
5
–
Automatic Retries in Case of nRETRY(NT)
Fault after the First tRETRY
Activation
–
nRETRY(CYC)
–
Maximum “Retry” Cycles
allowed before Channel
Latch OFF
Data Sheet
Note or
Test Condition
Number
1)
P_8.6.1.1
See Figure 27 and
Figure 28
1
–
1)
P_8.6.1.3
See Figure 27 and
Figure 28
2
–
1)
P_8.6.1.4
See Figure 27 and
Figure 28
37
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BTS7040-2EPA
PROFETTM+2
Protection
Table 16
Electrical Characteristics: Protection (continued)
Parameter
Symbol
Values
Min.
Typ.
Max.
70
100
Auto Retry Time after Fault
Condition
tRETRY
40
Counter Reset Delay Time
after Fault Condition
tDELAY(CR)
40
Minimum DEN Pulse
Duration for Counter Reset
tDEN(CR)
50
Unit
Note or
Test Condition
Number
ms
1)
P_8.6.1.5
See Figure 27 and
Figure 28
70
100
ms
1)
P_8.6.1.6
See Figure 27 and
Figure 28
100
150
µs
2)
P_8.6.1.7
See Figure 30
1) Functional test only
2) Not subject to production test - specified by design
8.7
Electrical Characteristics Protection - Power Output Stages
8.7.1
Protection Power Output Stage - 40 mΩ
Table 17
Electrical Characteristics: Protection - 40 mΩ
Parameter
Symbol
Values
Min.
Typ.
Max.
Overload Detection Current IL(OVL0)_-40
at TJ = -40 °C
42
47
52
Overload Detection Current IL(OVL0)_25
at TJ = 25 °C
40
Overload Detection Current IL(OVL0)_150
at TJ = 150 °C
34
Overload Detection Current IL(OVL1)
at High VDS
–
Overload Detection Current IL(OVL_JS)
Jump Start Condition
–
Unit
Note or
Test Condition
Number
A
1)
P_8.7.6.1
TJ = -40 °C
dI/dt = 0.2 A/µs
see Figure 24
46
52
A
2)
P_8.7.6.7
TJ = 25 °C
dI/dt = 0.2 A/µs
see Figure 24
39
45
A
2)
P_8.7.6.8
TJ = 150 °C
dI/dt = 0.2 A/µs
see Figure 24
26
–
A
2)
P_8.7.6.5
dI/dt = 0.2 A/µs
see Figure 24
26
–
A
2)
P_8.7.6.6
VS > VS(JS)
dI/dt = 0.2 A/µs
1) Functional test only
2) Not subject to production test - specified by design
Data Sheet
38
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Diagnosis
9
Diagnosis
For diagnosis purpose, the BTS7040-2EPA provides a combination of digital and analog signals at pin IS. These
signals are generically named SENSE and written IIS. In case of disabled diagnostic (DEN pin set to “low”), IS
pin becomes high impedance.
A sense resistor RSENSE must be connected between IS pin and module ground if the current sense diagnosis is
used. RSENSE value has to be higher than 820 Ω (or 400 Ω when a central Reverse Battery protection is present
on the battery feed) to limit the power losses in the sense circuitry. A typical value is RSENSE = 1.2 kΩ.
Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS
pin to the sense current output of other devices, if they are supplied by a different battery feed.
See Figure 32 for details as an overview.
VS
Channel 1
Channel 0
T
Overtemperature
Internal Counters
INn
OUT1
IS pin control
logic
OUT0
DEN
IL / kILIS
DSEL
MUX
+V
IIS(FAULT)
DS(OLOFF)
MUX
IIS(OLOFF)
MUX
IS
RSENSE
Diagnosis_PROFET_2CH.emf
Figure 32
Diagnosis Block Diagram
9.1
Overview
Table 18 gives a quick reference for the state of the IS pin during BTS7040-2EPA operation.
Data Sheet
39
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Diagnosis
Table 18
SENSE Signal, Function of Application Condition
Application Condition
Input level DEN level VOUT
Diagnostic Output
Normal operation
“low”
~ GND
Z
IIS(FAULT) if counter > 0
Short circuit to GND
~ GND
Z
IIS(FAULT) if counter > 0
Overtemperature
Z
IIS(FAULT)
Short circuit to VS
VS
IIS(OLOFF)
(IIS(FAULT) if counter > 0)
Open Load
< VS - VDS(OLOFF)
> VS - VDS(OLOFF)1)
Z
IIS(OLOFF)
(in both cases IIS(FAULT) if
counter > 0)
Inverse current
~ VINV = VOUT > VS
IIS(OLOFF)
(IIS(FAULT) if counter > 0)
~ VS
IIS = IL / kILIS
Overcurrent
< VS
IIS(FAULT)
Short circuit to GND
~ GND
IIS(FAULT)
Overtemperature
Z
IIS(FAULT)
Short circuit to VS
VS
Normal operation
“high”
“high”
IIS < IL / kILIS
~ VS
2)
IIS = IIS(EN)
Under load (e.g. Output Voltage
Limitation condition)
~ VS
3)
IIS(EN) < IIS < IL(NOM) / kILIS
Inverse current
~ VINV = VOUT > VS
IIS = IIS(EN)
n.a.
Z
Open Load
All conditions
n.a.
“low”
1) With additional pull-up resistor
2) The output current has to be smaller than IL(OL)
3) The output current has to be higher than IL(OL)
9.1.1
SENSE signal truth table
In case DEN is set to “high”, the SENSE for the selected channel is enabled or disabled using DSEL pin. Table 19
gives the truth table.
Table 19
Diagnostic Truth Table
DEN
DSEL
IS
“low”
not relevant
Z
“high”
“low”
SENSE output 0
“high”
“high”
SENSE output 1
9.2
Diagnosis in ON state
A current proportional to the load current (ratio kILIS = IL / IIS) is provided at pin IS when the following conditions
are fulfilled:
Data Sheet
40
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Diagnosis
•
the power output stage is switched ON with VDS < 2 V
•
the diagnosis is enabled for that channel
•
no fault (as described in Chapter 8.3) is present or was present and not cleared yet (see Chapter 9.2.2 for
further details)
If a “hard” failure mode is present or was present and not cleared yet a current IIS(FAULT) is provided at IS pin.
9.2.1
Current Sense (kILIS)
The accuracy of the sense current depends on temperature and load current. IIS increases linearly with IL
output current until it reaches the saturation current IIS(SAT). In case of Open Load at the output stage (IL close
to 0 A), the maximum sense current IIS(EN) (no load, diagnosis enabled) is specified. This condition is shown in
Figure 34. The blue line represents the ideal kILIS line, while the red lines show the behavior of a typical
product.
An external RC filter between IS pin and micro controller ADC input pin is recommended to reduce signal ripple
and oscillations (a minimum time constant of 1 µs for the RC filter is recommended).
The kILIS factor is specified with limits that take into account effects due to temperature, supply voltage and
manufacturing process. Tighter limits are possible (within a defined current window) with calibration:
•
a well-defined and precise current (IL(CAL)) is applied at the output during End of Line test at customer side
•
the corresponding current at IS pin is measured and the kILIS is calculated (kILIS @ IL(CAL))
•
within the current range going from IL(CAL)_L to IL(CAL)_H the kILIS is equal to kILIS @ IL(CAL) with limits defined by
ΔkILIS
The derating of kILIS after calibration is calculated using the formulas in Figure 33 and it is specified by ΔkILIS
Diagnosis_dKILIS.emf
Figure 33
ΔkILIS calculation formulas
The calibration is intended to be performed at TA(CAL) = 25°C. The parameter ΔkILIS includes the drift over
temperature as well as the drift over the current range from IL(CAL)_L to IL(CAL)_H.
IIS
I IS(OL)
IIS(EN)
I L(OL)
IL
Diagnosis_OLON_adv .emf
Figure 34
Data Sheet
Current Sense Ratio in Open Load at ON condition
41
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Diagnosis
9.2.2
Fault Current (IIS(FAULT))
As soon a protection event occurs, changing the value of the internal retry counter (see Chapter 8.3 for more
details) from its reset state, a current IIS(FAULT) is provided by pin IS when DEN is set to “high” and the affected
channel is selected. The following 3 situations may occur:
•
if the channel is ON and the number of retries is lower than “nRETRY(CR) + nRETRY(CYC) * nRETRY(NT)”, the current
IIS(FAULT) is provided for a time tIS(FAULT)_D after the channel is allowed to restart, after which IIS = IL / kILIS (as
shown in Figure 35). During a retry cycle (while timer tRETRY is running) the current IIS(FAULT) is provided each
time the channel diagnosis is checked
•
if the channel is ON and the number of retries is equal than “nRETRY(CR) + nRETRY(CYC) * nRETRY(NT)”, the current
IIS(FAULT) is provided until the internal counter is reset (either by expiring of tDELAY(CR) time or by DEN pin
pulse, as described in Chapter 8.3.1)
•
if the channel is OFF and the internal counter is not in the reset state, the current IIS(FAULT) is provided each
time the channel diagnosis is checked
IN
t
IL
IL(OVL)
t
In ternal
count er
0
1
2
0
t
DEN
tIS(FAUL T)_D
IIS
t
IIS(FAUL T)
IL / kILIS
IIS(FAUL T)
t
Diagnosis_PROFET_IISFAULT_load.emf
Figure 35
IIS(FAULT) at Load Switching
Figure 36 adds the behavior of SENSE signal to the timing diagram seen in Figure 28, while Figure 37 shows
the relation between IIS = IL / kILIS, IIS(SAT) and IIS(FAULT).
Data Sheet
42
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Diagnosis
IN
t
Short circu it
to ground
t
nRETRY(CYC)
"retry" cycle
nRETRY(CR)
IL
In ternal
count er
0
nRETRY(NT)
1
nRETRY(NT)
tRETRY
tRETRY
nRETRY(CR)
nRETRY(CR) + nRETRY(NT)
t
tDELA Y(CR)
nRETRY(CR) + (nRETRY(CYC) * nRETRY(NT))
0
t
DEN
IIS(FAUL T)
IIS(FAUL T)
t
IIS(FAUL T)
IL / kILIS
IIS
t
Diagnosis_PROFET_IISFAULT.emf
Figure 36
SENSE behavior in Fault condition
IIS
IIS(SA T),max
IIS(SA T)
IIS(FAUL T),max
IIS(FAUL T)
IIS(SA T),mi n =
IIS(FAUL T),min
IL / kILIS
IL(OVL)
IL
Diagnosis_PROFET_IISFAULT_IISSAT.emf
Figure 37
SENSE behavior - overview
9.3
Diagnosis in OFF state
When a power output stage is in OFF state, the BTS7040-2EPA can measure the output voltage and compare
it with a threshold voltage. In this way, using some additional external components (a pull-down resistor and
a switchable pull-up current source), it is possible to detect if the load is missing or if there is a short circuit to
battery. If a Fault condition was detected by the device (the internal counter has a value different from the
reset value, as described in Chapter 9.2.2) a current IIS(FAULT) is provided by IS pin each time the channel
diagnosis is checked also in OFF state.
Data Sheet
43
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Diagnosis
9.3.1
Open Load current (IIS(OLOFF))
In OFF state, when DEN pin is set to “high” and a channel is selected using DSEL pin, the VDS voltage is
compared with a threshold voltage VDS(OLOFF). If the load is properly connected and there is no short circuit to
battery, VDS ~ VS therefore VDS > VDS(OLOFF). When the diagnosis is active and VDS ≤ VDS(OLOFF), a current IIS(OLOFF) is
provided by IS pin. Figure 38 shows the relationship between IIS(OLOFF) and IIS(FAULT) as functions of VDS. The two
currents do not overlap making always possible to differentiate between Open Load in OFF and Fault
condition.
IIS
IIS(FAUL T)
IIS(OLOFF)
VDS
VDS(OLOFF)
Diagnosis_PROFET_IISOLOFF.emf
Figure 38
IIS in OFF State
It is necessary to wait a time tIS(OLOFF)_D between the falling edge of the input pin and the sensing at pin IS for
Open Load in OFF diagnosis to allow the internal comparator to settle. In Figure 39 the timings for an Open
Load detection are shown - the load is always disconnected.
IN
t
DEN
VOUT
tIS(OLOFF)_D
t
~ VS
VDS(OLOFF)
Load
conn ect ed
t
IIS
IIS(OLOFF)
IIS(OL)
t
Diagnosis_PROFET_OLOFF_time.emf
Figure 39
Data Sheet
Open Load in OFF Timings - load disconnected
44
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Diagnosis
9.4
SENSE Timings
Figure 40 and Figure 42 show the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including
the case of load change). As a proper signal cannot be established before the load current is stable (therefore
before tON), tsIS(DIAG) = tsIS(ON) + tON.
IN
OFF
OFF
ON
t
DEN
t
tO FF
IL
tsIS (L C)
tsIS (O FF)
tsIS (ON)
t
tsIS (O FF)
tsIS (DI AG)
IIS
t
Diagnose_PROFET_SENSE_timings.emf
Figure 40
SENSE Settling / Disabling Timing
IN
OFF
OFF
ON
t
DEN
t
IL
tsIS(ON)_SLC
tsIS(ON)
t
tsIS(LC)_SLC
IIS
t
Diagnose_PROFET_SENSE_timings_SLC.emf
Figure 41
Data Sheet
SENSE Timing with Small Load Current
45
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Diagnosis
DEN
t
DSEL
t
IL0
IL(CAL)
t
IL1
IL(CAL)_L
IL(CAL)_O L
tsI S(CC)
tsIS (O FF)
tsIS (ON)
tsI S(CC)_SLC
t
IIS
t
Diagnose_PROFET_SENSE_timings_CC.emf
Figure 42
Data Sheet
SENSE Settling Timing - Channel Change
46
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Diagnosis
9.5
Electrical Characteristics Diagnosis
VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
RL = 3.3 Ω
Table 20
Electrical Characteristics: Diagnosis - General
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
mA
1)
P_9.6.0.13
Min.
Typ.
Max.
IIS(SAT)
4.4
–
15
IIS(SAT)
4.1
SENSE Leakage Current
when Disabled
IIS(OFF)
–
0.01
0.5
µA
DEN = “low”
IL ≥ IL(NOM)
VIS = 0 V
P_9.6.0.2
SENSE Leakage Current
when Enabled at TJ ≤ 85 °C
IIS(EN)_85
–
0.2
1
µA
1)
P_9.6.0.3
SENSE Saturation Current
SENSE Saturation Current
IIS(EN)_150
SENSE Leakage Current
when Enabled at TJ = 150 °C
SENSE Operative Range for
kILIS Operation
(VS - VIS)
VSIS_k
SENSE Operative Range for VSIS_OL
Open Load at OFF Diagnosis
(VS - VIS)
SENSE Operative Range for
Fault Diagnosis
(VS - VIS)
Data Sheet
VSIS_F
VS = 8 V to 18 V
RSENSE = 1.2 kΩ
See Figure 37
–
15
mA
1)
P_9.6.0.14
VS = 6 V to 18 V
RSENSE = 1.2 kΩ
See Figure 37
TJ ≤ 85 °C
DEN = “high”
IL = 0 A
See Figure 34
–
0.2
1
µA
TJ = 150 °C
DEN = “high”
IL = 0 A
See Figure 34
P_9.6.0.4
–
0.5
1
V
1)
P_9.6.0.6
VS = 6 V
IN = DEN = “high”
IL ≤ 1.2 * IL(NOM)
–
0.5
1
V
1)
P_9.6.0.7
VS = 6 V
IN = “low”
DEN = “high”
–
0.5
1
V
1)
P_9.6.0.8
VS = 6 V
IN = “low”
DEN = “high”
counter > 0
47
Rev. 1.00
2017-08-24
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PROFETTM+2
Diagnosis
Table 20
Electrical Characteristics: Diagnosis - General (continued)
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min.
Typ.
Max.
33
36.5
42
V
IIS = 1 mA
TJ = -40 °C
See Figure 17
P_9.6.0.9
38
44
V
2)
P_9.6.0.10
Power Supply to IS Pin
Clamping Voltage at
TJ = -40 °C
VSIS(CLAMP)_-
Power Supply to IS Pin
Clamping Voltage at
TJ ≥ 25 °C
VSIS(CLAMP)_25 35
40
IIS = 1 mA
TJ ≥ 25 °C
See Figure 17
1) Not subject to production test - specified by design
2) Tested at TJ = 150°C
9.5.1
Electrical Characteristics Diagnosis
Table 21
Electrical Characteristics: Diagnosis
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
SENSE Fault Current
IIS(FAULT)
4.4
5.5
10
mA
See Figure 37 and P_9.6.1.1
Figure 38
SENSE Open Load in OFF
Current
IIS(OLOFF)
1.9
2.5
3.5
mA
See Figure 37 and P_9.6.1.2
Figure 38
SENSE Delay Time at
Channel Switch ON after
Last Fault Condition
tIS(FAULT)_D
–
500
–
µs
1)
SENSE Open Load in OFF
Delay Time
tIS(OLOFF)_D
30
70
120
µs
VDS < VOL(OFF)
from IN falling
edge to IIS =
IS(OLOFF),MIN * 0.9
DEN = “high”
counter = 0
See Figure 39
P_9.6.1.4
Open Load VDS Detection
Threshold in OFF State
VDS(OLOFF)
1.3
1.8
2.3
V
See Figure 38
P_9.6.1.5
SENSE Settling Time with
Nominal Load Current
Stable
tsIS(ON)
–
5
20
µs
IL = IL(CAL)
from DEN rising
edge to IIS = IL /
(kILIS,MAX @ IL) * 0.9
See Figure 40
P_9.6.1.6
SENSE Settling Time with
Small Load Current Stable
tsIS(ON)_SLC
–
–
60
µs
1)
P_9.6.1.13
Data Sheet
P_9.6.1.3
See Figure 35
IL = IL(CAL)_OL
from DEN rising
edge to IIS = IL /
(kILIS,MAX @ IL) * 0.9
48
Rev. 1.00
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BTS7040-2EPA
PROFETTM+2
Diagnosis
Table 21
Electrical Characteristics: Diagnosis (continued)
Parameter
Symbol
Values
Min.
Typ.
Max.
tsIS(OFF)
–
5
20
SENSE Settling Time after
Load Change
tsIS(LC)
–
SENSE Settling Time after
Load Change with Small
Load Current
tsIS(LC)_SLC
–
SENSE Settling Time after
Channel Change
tsIS(CC)
–
SENSE Disable Time
SENSE Settling Time after
tsIS(CC)_SLC
Channel Change with Small
Load Current
Unit
Note or
Test Condition
Number
µs
1)
P_9.6.1.8
From DEN falling
edge to IIS = IIS(OFF)
See Figure 40
5
20
µs
1)
P_9.6.1.9
from IL = IL(CAL)_L to
IL = IL(CAL) (see
ΔkILIS(NOM))
See Figure 40
250
400
µs
1)
P_9.6.1.14
DEN = “high”
from Load Change
to IIS = IL / (kILIS @ IL)
from IL(CAL) to
IL(CAL)_OL
5
20
µs
1)
P_9.6.1.10
Start channel:
IL = IL(CAL)
End channel:
IL = IL(CAL)_L
(see ΔkILIS(NOM))
See Figure 42
–
–
60
µs
1)
P_9.6.1.15
DEN = “high”
from DSEL toggling
to IIS = IL /
(kILIS,MIN @ IL) * 1.1
Start channel:
IL = IL(CAL)
End Channel:
IL = IL(CAL)_OL
(see ΔkILIS(NOM) and
ΔkILIS(OL))
1) Not subject to production test - specified by design
9.6
Electrical Characteristics Diagnosis - Power Output Stages
9.6.1
Diagnosis Power Output Stage - 40 mΩ
Data Sheet
49
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Diagnosis
Table 22
Electrical Characteristics: Diagnosis - 40 mΩ
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
mA
IIS = IIS(OL) = 4 µA
P_9.7.6.1
Open Load Output Current
at IIS = 4 µA
IL(OL)_4u
1
6
11
Current Sense Ratio at
IL = IL02
kILIS02
-40%
1800
+40%
IL02 = 20 mA
P_9.7.6.6
Current Sense Ratio at
IL = IL04
kILIS04
-35%
1800
+35%
IL04 = 50 mA
P_9.7.6.8
Current Sense Ratio at
IL = IL05
kILIS05
-30%
1800
+30%
IL05 = 100 mA
P_9.7.6.9
Current Sense Ratio at
IL = IL08
kILIS08
-26%
1800
+26%
IL08 = 250 mA
P_9.7.6.12
Current Sense Ratio at
IL = IL11
kILIS11
-11%
1800
+11%
IL11 = 1 A
P_9.7.6.15
Current Sense Ratio at
IL = IL13
kILIS13
-6%
1800
+6%
IL13 = 2 A
P_9.7.6.17
Current Sense Ratio at
IL = IL15
kILIS15
-5%
1800
+5%
IL15 = 4 A
P_9.7.6.19
SENSE Current Derating
with Low Current
Calibration
ΔkILIS(OL)
-30
0
+30
1)
P_9.7.6.27
SENSE Current Derating
with Nominal Current
Calibration
ΔkILIS(NOM)
-4
%
IL(CAL)_OL = IL04
IL(CAL)_OL_H = IL05
IL(CAL)_OL_L = IL02
TA(CAL) = 25 °C
0
+4
%
1)
P_9.7.6.29
IL(CAL) = IL13
IL(CAL)_H = IL15
IL(CAL)_L = IL11
TA(CAL) = 25 °C
1) Not subject to production test - specified by design
Data Sheet
50
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Application Information
10
Application Information
Note:
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
10.1
Application Setup
VBAT
R/L cable
T1
CVS
DZ2
VDD
ROL
VS
VDD
GPIO
RIN
IN0
GPIO
RIN
IN1
GPIO
RDEN
DEN
GPIO
RDSEL
DSEL
R/L cable
OUT0
RPD
COUT0
Micro controller
R/L cable
OUT1
RAD
A/D IN
IS
RIS_PROT
GND
DZ1
RSENSE
CSENSE
RGND
VSS
COUT1
RPD
App_2CH_LI_INTDIO.emf
Figure 43
BTS7040-2EPA Application Diagram
Note:
This is a very simplified example of an application circuit. The function must be verified in the real
application.
Table 23
Loads considered for Reverse Polarity setup (see P_4.1.0.5)
Output
RDS(ON),max @ TJ = 150 °C
Load connected
40 mΩ
36 mΩ
P27W + R5W
Data Sheet
51
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Application Information
10.2
External Components
Table 24
Suggested Component values
Reference
Value
Purpose
RIN
4.7 kΩ
Protection of the micro controller during Overvoltage and Reverse Polarity.
Necessary to switch OFF BTS7040-2EPA output during Loss of Ground
RDEN
4.7 kΩ
Protection of the micro controller during Overvoltage and Reverse Polarity.
Necessary to switch OFF BTS7040-2EPA output during Loss of Ground
RPD
47 kΩ
Output polarization (pull-down).
Improves BTS7040-2EPA immunity to electromagnetic noise
ROL
1.5 kΩ
Output polarization (pull-up).
Ensure polarization of BTS7040-2EPA output during Open Load in OFF
diagnosis
COUT
10 nF
Protection of BTS7040-2EPA output during ESD events and BCI
T1
BC 807
Switch the battery voltage for Open Load in OFF diagnosis
CVS
68 nF
Filtering of voltage spikes on the battery line
DZ2
33 V Z-Diode
Suppressor diode
Protection during Overvoltage and in case of Loss of Battery while driving
an inductive load
RSENSE
1.2 kΩ
SENSE resistor
RIS_PROT
4.7 kΩ
Protection during Overvoltage, Reverse Polarity, Loss of Ground.
Value to be tuned according to micro controller specifications.
DZ1
7 V Z-Diode
Protection of micro controller during Overvoltage
RA/D
4.7 kΩ
Protection of micro controller ADC input during Overvoltage, Reverse
Polarity, Loss of Ground.
Value to be tuned according to micro controller specifications.
CSENSE
220 pF
Sense signal filtering
A time constant (RA/D * CSENSE) longer than 1 µs is recommended.
RGND
47 Ω
(1/16 W)
Protection in case of Overvoltage and Loss of Battery while driving
inductive loads
10.3
Further Application Information
•
Please contact us for information regarding the Pin FMEA
•
For further information you may contact http://www.infineon.com/
Data Sheet
52
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Package Outlines
[
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6($7,1* &23/$1$5,7<
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Package Outlines
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Figure 44
PG-TSDSO-14-22 (Thin (Slim) Dual Small Outline 14 pins) Package Outline
FRSSHU
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$// ',0(16,216 $5( ,1 81,76 00
Figure 45
PG-TSDSO-14-22 (Thin (Slim) Dual Small Outline 14 pins) Package pads and stencil
Data Sheet
53
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Package Outlines
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Data Sheet
54
Dimensions in mm
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Revision History
12
Revision History
Table 25
BTS7040-2EPA - List of changes
Revision
Changes
1.00, 2017-08-24 Data Sheet available
Data Sheet
55
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Table of Contents
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
2.1
2.2
Block Diagram and Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
4.1
4.2
4.2.1
4.3
4.4
4.4.1
4.4.2
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings - General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings - Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Stage - 40 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PCB Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
5.1
5.2
5.3
Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Pins (INn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
15
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
6.4.1
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unsupplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Supply - product specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BTS7040-2EPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
17
17
17
17
17
19
19
19
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.5
7.5.1
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Inductive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inverse Current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Channels in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cross Current robustness with H-Bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Power Stages - PROFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Output Stage - 40 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
21
22
23
23
23
25
25
26
26
27
27
Data Sheet
56
Rev. 1.00
2017-08-24
BTS7040-2EPA
PROFETTM+2
Table of Contents
8
8.1
8.2
8.3
8.3.1
8.4
8.4.1
8.4.2
8.5
8.5.1
8.5.2
8.6
8.6.1
8.7
8.7.1
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection and Diagnosis in case of Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Retry Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection against loss of connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss of Battery and Loss of Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Protection - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Power Output Stage - 40 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
29
30
32
32
35
35
36
36
36
36
37
37
38
38
9
9.1
9.1.1
9.2
9.2.1
9.2.2
9.3
9.3.1
9.4
9.5
9.5.1
9.6
9.6.1
Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SENSE signal truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis in ON state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense (kILIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Current (IIS(FAULT)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis in OFF state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Load current (IIS(OLOFF)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SENSE Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Diagnosis - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnosis Power Output Stage - 40 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
40
40
41
42
43
44
45
47
48
49
49
10
10.1
10.2
10.3
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
51
52
52
11
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Data Sheet
57
Rev. 1.00
2017-08-24
Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2017-08-24
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2017 Infineon Technologies AG.
All Rights Reserved.
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aspect of this document?
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Document reference
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics ("Beschaffenheitsgarantie").
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer's compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer's products and any use of the product of
Infineon Technologies in customer's applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer's technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to
such application.
For further information on technology, delivery terms
and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
any applications where a failure of the product or any
consequences of the use thereof can reasonably be
expected to result in personal injury.