Intersil HI1-674AKD-5 Complete, 12-bit a/d converters with microprocessor interface Datasheet

HI-574A, HI-674A,
HI-774
Complete, 12-Bit A/D Converters
with Microprocessor Interface
August 1997
Features
Description
• Complete 12-Bit A/D Converter with Reference and Clock
The HI-X74(A) is a complete 12-bit, Analog-to-Digital
Converter, including a +10V reference clock, three-state outputs and a digital interface for microprocessor control. Successive approximation conversion is performed by two monolithic
dice housed in a 28 lead package. The bipolar analog die features the Intersil Dielectric Isolation process, which provides
enhanced AC performance and freedom from latch-up.
• Full 8-Bit, 12-Bit or 16-Bit Microprocessor Bus Interface
• Bus Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns
• No Missing Codes Over Temperature
• Minimal Setup Time for Control Signals
• Fast Conversion Times
- HI-574A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25µs
- HI-674A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15µs
- HI-774 (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9µs
• Digital Error Correction (HI-774)
• Low Noise, via Current-Mode Signal
Transmission Between Chips
• Byte Enable/Short Cycle (AO Input)
- Guaranteed Break-Before-Make Action, Eliminating
Bus Contention During Read Operation. Latched by
Start Convert Input (To Set the Conversion Length)
• Supply Voltage . . . . . . . . . . . . . . . . . . . . . ±12V to ±15V
Applications
• Military and Industrial Data Acquisition Systems
• Electronic Test and Scientific Instrumentation
• Process Control Systems
Custom design of each IC (bipolar analog and CMOS digital)
has yielded improved performance over existing versions of
this converter. The voltage comparator features high PSRR
plus a high speed current-mode latch, and provides precise
decisions down to 0.1 LSB of input overdrive. More than 2X
reduction in noise has been achieved by using current
instead of voltage for transmission of all signals between the
analog and digital ICs. Also, the clock oscillator is current
controlled for excellent stability over temperature.
The HI-X74(A) offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity, gain and offset
accuracy. The low noise buried zener reference circuit is
trimmed for minimum temperature coefficient.
Power requirements are +5V and ±12V to ±15V, with typical
dissipation of 385mW (HI-574A/674A) and 390mW (HI-774) at
12V. All models are available in sidebrazed DIP, PDIP, and
CLCC. For additional HI-Rel screening including 160 hour burnin, specify “-8” suffix. For MIL-STD-883 compliant parts, request
HI-574A/883, HI-674A/883, and HI-774/883 data sheets.
Pinouts
22 DB6
8
21 DB5
REFERENCE INPUT 10
19 DB3
-12V/-15V SUPPLY, VEE 11
18 DB2
BIPOLAR OFFSET 12
BIP OFF
17 DB1
10V INPUT 13
16 DB0
20V INPUT 14
15 DIG COMMON,
DC
NC
DB10
39 NC
NC 8
38 NC
READ CONVERT, R/C 9
37 DB9
CHIP ENABLE, CE 10
36 DB8
+15V SUPPLY, VCC
+10V REFERENCE,
REF OUT
ANALOG COMMON, AC
REFERENCE INPUT,
REF IN
-15V SUPPLY, VEE
20 DB4
1 44 43 42 41 40
11
35 DB7
12
34 DB6
13
33 DB5
14
32 DB4
15
31 DB3
NC 16
LSB
30 NC
29 DB2
18 19 20 21 22 23 24 25 26 27 28
10V
BIPOLAR OFFSET, 17
BIP OFF
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
6-952
DB1
+12V/+15V SUPPLY, VCC 7
DIGITAL
DATA
OUTPUTS
2
NC
23 DB7
3
NC
6
4
NC 7
(LSB) DB0
CHIP ENABLE, CE
9
5
STATUS, STS
24 DB8
DB11, MSB
25 DB9
5
NC
4
READ/CONVERT, R/C
NC
DIG
COMMON, DC
BYTE ADDR/SHORT
CYCLE, AO
MSB
NC
26 DB10
NC
27 DB11
3
ANALOG
COMMON, AC
NC
BYTE ADDRESS/
SHORT CYCLE, AO
CHIP SELECT, CS
DATA MODE
SELECT, 12/8
+5V SUPPLY, VLOGIC
2
CHIP SEL, CS
NC
DATA MODE SEL, 12/8
+10V REF, REF OUT
6
28 STATUS, STS
20V
+5V SUPPLY, VLOGIC 1
(CLCC)
TOP VIEW
NC
(PDIP, SBDIP)
TOP VIEW
File Number
3096.4
HI-574A, HI-674A, HI-774
Ordering Information
INL
TEMPERATURE RANGE
(oC)
HI3-574AJN-5
±1.0 LSB
0 to 75
28 Ld PDIP
E28.6
HI3-574AKN-5
±0.5 LSB
0 to 75
28 Ld PDIP
E28.6
HI3-574ALN-5
±0.5 LSB
0 to 70
28 Ld PDIP
E28.6
HI1-574AJD-5
±1.0 LSB
0 to 75
28 Ld SBDIP
D28.6
PART NUMBER
PACKAGE
PKG. NO.
HI1-574AKD-5
±0.5 LSB
0 to 75
28 Ld SBDIP
D28.6
HI1-574ALD-5
±0.5 LSB
0 to 75
28 Ld SBDIP
D28.6
HI1-574ASD-2
±1.0 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI1-574ATD-2
±0.5 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI1-574AUD-2
±0.5 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI1-574ASD/883
±1.0 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI1-574ATD/883
±0.5 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI1-574AUD/883
±0.5 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI4-574ASE/883
±1.0 LSB
-55 to 125
44 Ld CLCC
J44.A
HI4-574ATE/883
±0.5 LSB
-55 to 125
44 Ld CLCC
J44.A
HI4-574AUE/883
±0.5 LSB
-55 to 125
44 Ld CLCC
J44.A
HI3-674AJN-5
±1.0 LSB
0 to 75
28 Ld PDIP
E28.6
HI3-674AKN-5
±0.5 LSB
0 to 75
28 Ld PDIP
E28.6
HI3-674ALN-5
±0.5 LSB
0 to 75
28 Ld PDIP
E28.6
HI1-674AJD-5
±1.0 LSB
0 to 75
28 Ld SBDIP
D28.6
HI1-674AKD-5
±0.5 LSB
0 to 75
28 Ld SBDIP
D28.6
HI1-674ALD-5
±0.5 LSB
0 to 75
28 Ld SBDIP
D28.6
HI1-674ASD-2
±1.0 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI1-674ATD-2
±0.5 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI1-674AUD-2
±0.5 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI1-674ASD/883
±1.0 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI1-674ATD/883
±0.5 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI1-674AUD/883
±0.5 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI4-674ASE/883
±1.0 LSB
-55 to 125
44 Ld CLCC
J44.A
HI4-674ATE/883
±0.5 LSB
-55 to 125
44 Ld CLCC
J44.A
HI4-674AUE/883
±0.5 LSB
-55 to 125
44 Ld CLCC
J44.A
HI3-774J-5
±1.0 LSB
0 to 75
28 Ld PDIP
E28.6
HI3-774K-5
±0.5 LSB
0 to 75
28 Ld PDIP
E28.6
HI1-774J-5
±1.0 LSB
0 to 75
28 Ld SBDIP
D28.6
HI1-774K-5
±0.5 LSB
0 to 75
28 Ld SBDIP
D28.6
HI1-774U-2
±0.5 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI1-774T/883
±0.5 LSB
-55 to 125
28 Ld SBDIP
D28.6
HI4-774S/883
±1.0 LSB
-55 to 125
44 Ld CLCC
J44.A
HI4-774T/883
±0.5 LSB
-55 to 125
44 Ld CLCC
J44.A
HI4-774U/883
±0.5 LSB
-55 to 125
44 Ld CLCC
J44.A
6-953
HI-574A, HI-674A, HI-774
Functional Block Diagram
BIT OUTPUTS
MSB
12/8
CS
AO
LSB
NIBBLE A (NOTE)
CONTROL
LOGIC
NIBBLE B (NOTE)
NIBBLE C (NOTE)
THREE-STATE BUFFERS AND CONTROL
R/C
CE
VLOGIC
POWER-UP RESET
DIGITAL
COMMON
12 BITS
CLK
STS
SAR
OSCILLATOR
STROBE
DIGITAL CHIP
ANALOG CHIP
12 BITS
VCC
VEE
COMP
DAC
-
+
VREF IN
10K
VREF OUT
5K
+
+10V
REF
-
5K
2.5K
10K
5K
ANALOG
COMMON
BIP
OFF
NOTE: “Nibble” is a 4-bit digital word.
6-954
20V
10V
INPUT INPUT
HI-574A, HI-674A, HI-774
Absolute Maximum Ratings
Thermal Information
Supply Voltage
VCC to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +16.5V
VEE to Digital Common. . . . . . . . . . . . . . . . . . . . . . . 0V to -16.5V
VLOGIC to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +7V
Analog Common to Digital Common±1V
Control Inputs
(CE, CS, AO, 12/8, R/C) to Digital Common . . -0.5V to VLOGIC +0.5V
Analog Inputs
(REFIN, BIPOFF, 10VIN) to Analog Common. . . . . . . . . . ±16.5V
20VIN to Analog Common . . . . . . . . . . . . . . . . . . . . . . . . . . ±24V
REFOUT . . . . Indefinite Short To Common, Momentary Short To VCC
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
CLCC Package . . . . . . . . . . . . . . . . . .
65
14
SBDIP Package . . . . . . . . . . . . . . . . . .
60
18
HI3-574AxN-5, HI3-674AxN-5, HI3-774xN-5 65
N/A
Maximum Junction Temperature
HI3-574AxN-5, HI3-674AxN-5, HI3-774xN-5. . . . . . . . . . . . 150oC
HI1-574AxD-2, HI1-574AxD-5 . . . . . . . . . . . . . . . . . . . . . . . 175oC
HI1-674AxD-2, HI1-674AxD-5 . . . . . . . . . . . . . . . . . . . . . . . 175oC
HI1-774xD-2, HI1-774xD-5 . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Maximum Storage Temperature Range
HI3-574AxN-5, HI3-674AxN-5, HI3-774xN-5. . . . . .-40oC to 85oC
HI1-574AxD-2, HI1-574AxD-5 . . . . . . . . . . . . . . . .-65oC to 150oC
HI1-674AxD-2, HI1-674AxD-5 . . . . . . . . . . . . . . . .-65oC to 150oC
HI1-774xD-2, HI1-774xD-5 . . . . . . . . . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range
HI3-574AxN-5, HI1-574AxD-5 . . . . . . . . . . . . . . . . . .0oC to 75oC
HI3-674AxN-5, HI1-674AxD-5 . . . . . . . . . . . . . . . . . .0oC to 75oC
HI3-774xN-5, HI1-774xD-5 . . . . . . . . . . . . . . . . . . . . .0oC to 75oC
HI1-574AxD-2, HI1-674AxD-2, HI1-774xD-2 . . . . -55oC to 125oC
DC and Transfer Accuracy Specifications
Die Characteristics
Transistor Count
HI-574A, HI-674A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
HI-774 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2117
Typical at 25oC with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V,
Unless Otherwise Specified
TEMPERATURE RANGE
-5 (0oC to 75oC)
PARAMETER
J SUFFIX
K SUFFIX
L SUFFIX
UNITS
12
12
12
Bits
±1
±1/2
±1/2
LSB
±1
±1/
±1/
LSB
HI-574A, HI-674A
12
12
12
Bits
HI-774
11
12
12
Bits
HI-574A, HI-674A
11
12
12
Bits
HI-774
11
12
12
Bits
±2
±1.5
±1
LSB
±4
±4
±3
LSB
±0.15
±0.1
±0.1
% of FS
25oC (Max), With Fixed 50Ω Resistor From REF OUT To REF IN
(Adjustable to Zero)
±0.25
±0.25
±0.15
% of FS
TMIN to TMAX (No Adjustment At 25oC)
±0.475
±0.375
±0.20
% of FS
TMIN to TMAX (With Adjustment To Zero 25oC)
±0.22
±0.12
±0.05
% of FS
DYNAMIC CHARACTERISTICS
Resolution (Max)
Linearity Error
25oC (Max)
0oC to 75oC (Max)
2
2
Max Resolution For Which No Missing Codes Is Guaranteed
25oC
TMIN to TMAX
Unipolar Offset (Max)
Adjustable to Zero
Bipolar Offset (Max)
VIN = 0V (Adjustable to Zero)
VIN = -10V
Full Scale Calibration Error
6-955
HI-574A, HI-674A, HI-774
DC and Transfer Accuracy Specifications
Typical at 25oC with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V,
Unless Otherwise Specified (Continued)
TEMPERATURE RANGE
-5 (0oC to 75oC)
PARAMETER
J SUFFIX
K SUFFIX
L SUFFIX
UNITS
HI-574A, HI-674A
±2
±1
±1
LSB
HI-774
±2
±1
±1
LSB
HI-574A, HI-674A
±2
±1
±1
LSB
HI-774
±2
±2
±1
LSB
HI-574A, HI-674A
±9
±2
±2
LSB
HI-774
±9
±5
±2
LSB
±2
±1
±1
LSB
±1/
±1/
±1/
LSB
Temperature Coefficients
Guaranteed Max Change, TMIN to TMAX (Using Internal Reference)
Unipolar Offset
Bipolar Offset
Full Scale Calibration
Power Supply Rejection
Max Change In Full Scale Calibration
+13.5V < VCC < +16.5V or +11.4V < VCC < +12.6V
+4.5V < VLOGIC < +5.5V
2
±2
-16.5V < VEE < -13.5V or -12.6V < VEE < -11.4V
2
±1
2
±1
LSB
ANALOG INPUTS
Input Ranges
Bipolar
-5 to +5
V
-10 to +10
V
0 to +10
V
0 to +20
V
10V Span
5K, ±25%
Ω
20V Span
10K, ±25%
Ω
+4.5 to +5.5
V
VCC
+11.4 to +16.5
V
VEE
-11.4 to -16.5
V
ILOGIC
7 Typ, 15 Max
mA
ICC +15V Supply
11 Typ, 15 Max
mA
IEE -15V Supply
21 Typ, 28 Max
mA
±15V, +15V
515 Typ, 720 Max
mW
±12V, +5V
385 Typ
mW
+10.00 ±0.05 Max
V
2.0 Max
mA
Unipolar
Input Impedance
POWER SUPPLIES
Operating Voltage Range
VLOGIC
Operating Current
Power Dissipation
Internal Reference Voltage
TMIN to TMAX
Output Current, Available For External Loads (External Load Should
Not Change During Conversion).
6-956
HI-574A, HI-674A, HI-774
DC and Transfer Accuracy Specifications
Typical at 25oC with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V,
Unless Otherwise Specified
TEMPERATURE RANGE
-2 (-55oC to 125oC)
PARAMETER
S SUFFIX
T SUFFIX
U SUFFIX
UNITS
12
12
12
Bits
25oC
±1
±1/2
±1/2
LSB
-55oC to 125oC (Max)
±1
±1
±1
LSB
HI-574A, HI-674A
12
12
12
Bits
HI-774
11
12
12
Bits
HI-574A, HI-674A
11
12
12
Bits
HI-774
11
12
12
Bits
HI-574A, HI-674A
±2
±1.5
±1
LSB
HI-774
±2
±2
±1
LSB
±4
±4
±3
LSB
±0.15
±0.1
±0.1
% of FS
25oC (Max), With Fixed 50Ω Resistor From REF OUT To REF IN
(Adjustable To Zero)
±0.25
±0.25
±0.15
% of FS
TMIN to TMAX (No Adjustment At 25oC)
±0.75
±0.50
±0.275
% of FS
TMIN to TMAX (With Adjustment To Zero At 25oC)
±0.50
±0.25
±0.125
% of FS
Unipolar Offset
±2
±1
±1
LSB
Bipolar Offset
±2
±2
±1
LSB
Full Scale Calibration
±20
±10
±5
LSB
±2
±1
±1
LSB
±1/
±1/
±1/
LSB
DYNAMIC CHARACTERISTICS
Resolution (Max)
Linearity Error
Max Resolution For Which No Missing Codes Is Guaranteed
25oC
TMIN to TMAX
Unipolar Offset (Max)
Adjustable to Zero
Bipolar Offset (Max)
VIN = 0V (Adjustable to Zero)
VIN = -10V
Full Scale Calibration Error
Temperature Coefficients
Guaranteed Max Change, TMIN to TMAX (Using Internal Reference)
Power Supply Rejection
Max Change In Full Scale Calibration
+13.5V < VCC < +16.5V or +11.4V < VCC < +12.6V
+4.5V < VLOGIC < +5.5V
2
±2
-16.5V < VEE < -13.5V or -12.6V < VEE < -11.4V
2
±1
2
±1
LSB
ANALOG INPUTS
Input Ranges
Bipolar
Unipolar
6-957
-5 to +5
V
-10 to +10
V
0 to +10
V
0 to +20
V
HI-574A, HI-674A, HI-774
DC and Transfer Accuracy Specifications
Typical at 25oC with VCC = +15V or +12V, VLOGIC = +5V, VEE = -15V or -12V,
Unless Otherwise Specified (Continued)
TEMPERATURE RANGE
-2 (-55oC to 125oC)
PARAMETER
S SUFFIX
T SUFFIX
U SUFFIX
UNITS
Input Impedance
10V Span
5K, ±25%
Ω
20V Span
10K, ±25%
Ω
+4.5 to +5.5
V
VCC
+11.4 to +16.5
V
VEE
-11.4 to -16.5
V
ILOGIC
7 Typ, 15 Max
mA
ICC +15V Supply
11 Typ, 15 Max
mA
IEE -15V Supply
21 Typ, 28 Max
mA
±15V, +15V
515 Typ, 720 Max
mW
±12V, +5V
385 Typ
mW
+10.00 ±0.05 Max
V
2.0 Max
mA
POWER SUPPLIES
Operating Voltage Range
VLOGIC
Operating Current
Power Dissipation
Internal Reference Voltage
TMIN to TMAX
Output current, available for external loads (External load should not
change during conversion).
Digital Specifications
All Models, Over Full Temperature Range
PARAMETER
MIN
TYP
MAX
Logic “1”
+2.4V
-
+5.5V
Logic “0”
-0.5V
-
+0.8V
Current
-
±0.1µA
±5µA
Capacitance
-
5pF
-
-
-
+0.4V
Logic “1” (ISOURCE - 500µA)
+2.4V
-
-
Logic “1” (ISOURCE - 10µA)
+4.5V
-
-
Leakage (High-Z State, DB11-DB0 Only)
-
±0.1µA
±5µA
Capacitance
-
5pF
-
Logic Inputs (CE, CS, R/C, AO, 412/8)
Logic Outputs (DB11-DB0, STS)
Logic “0” (ISINK - 1.6mA)
Timing Specifications
(HI-574A) 25oC, Note 2, Unless Otherwise Specified
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
-
-
200
ns
CONVERT MODE
tDSC
STS Delay from CE
6-958
HI-574A, HI-674A, HI-774
Timing Specifications
(HI-574A) 25oC, Note 2, Unless Otherwise Specified (Continued)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tHEC
CE Pulse Width
50
-
-
ns
tSSC
CS to CE Setup
50
-
-
ns
tHSC
CS Low During CE High
50
-
-
ns
tSRC
R/C to CE Setup
50
-
-
ns
tHRC
R/C Low During CE High
50
-
-
ns
tSAC
AO to CE Setup
0
-
-
ns
tHAC
AO Valid During CE High
50
-
-
ns
12-Bit Cycle TMIN to TMAX
15
20
25
µs
8-Bit Cycle TMIN to TMAX
10
13
17
µs
-
75
150
ns
25
-
-
ns
-
100
150
ns
tC
Conversion Time
READ MODE
tDD
Access Time from CE
tHD
Data Valid After CE Low
tHL
Output Float Delay
tSSR
CS to CE Setup
50
-
-
ns
tSRR
R/C to CE Setup
0
-
-
ns
tSAR
AO to CE Setup
50
-
-
ns
tHSR
CS Valid After CE Low
0
-
-
ns
tHRR
R/C High After CE Low
0
-
-
ns
tHAR
AO Valid After CE Low
50
-
-
ns
STS Delay After Data Valid
300
-
1200
ns
MIN
TYP
MAX
UNITS
-
-
200
ns
tHS
Timing Specifications
(HI-674A) 25oC, Note 2, Unless Otherwise Specified
SYMBOL
PARAMETER
CONVERT MODE
tDSC
STS Delay from CE
tHEC
CE Pulse Width
50
-
-
ns
tSSC
CS to CE Setup
50
-
-
ns
tHSC
CS Low During CE High
50
-
-
ns
tSRC
R/C to CE Setup
50
-
-
ns
tHRC
R/C Low During CE High
50
-
-
ns
tSAC
AO to CE Setup
0
-
-
ns
tHAC
AO Valid During CE High
50
-
-
ns
12-Bit Cycle TMIN to TMAX
9
12
15
µs
8-Bit Cycle TMIN to TMAX
6
8
10
µs
-
75
150
ns
25
-
-
ns
-
100
150
ns
tC
Conversion Time
READ MODE
tDD
Access Time from CE
tHD
Data Valid After CE Low
tHL
Output Float Delay
6-959
HI-574A, HI-674A, HI-774
Timing Specifications
(HI-674A) 25oC, Note 2, Unless Otherwise Specified (Continued)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tSSR
CS to CE Setup
50
-
-
ns
tSRR
R/C to CE Setup
0
-
-
ns
tSAR
AO to CE Setup
50
-
-
ns
tHSR
CS Valid After CE Low
0
-
-
ns
tHRR
R/C High After CE Low
0
-
-
ns
tHAR
AO Valid After CE Low
50
-
-
ns
STS Delay After Data Valid
25
-
850
ns
tHS
Timing Specifications
(HI-774) 25oC, Into a load with RL = 3kΩ and CL = 50pF, Note 2, Unless Otherwise Specified
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
-
100
200
ns
CONVERT MODE
tDSC
STS Delay from CE
tHEC
CE Pulse Width
50
30
-
ns
tSSC
CS to CE Setup
50
20
-
ns
tHSC
CS Low During CE High
50
20
-
ns
tSRC
R/C to CE Setup
50
0
-
ns
tHRC
R/C Low During CE High
50
20
-
ns
tSAC
AO to CE Setup
0
0
-
ns
tHAC
AO Valid During CE High
50
30
-
ns
12-Bit Cycle TMIN to TMAX (-5)
-
8.0
9
µs
8-Bit Cycle TMIN to TMAX (-5)
-
6.4
6.8
µs
12-Bit Cycle TMIN to TMAX (-2)
-
9
11
µs
8-Bit Cycle TMIN to TMAX (-2)
-
6.8
8.3
µs
-
75
150
ns
25
35
-
ns
-
70
150
ns
tC
Conversion Time
READ MODE
tDD
Access Time from CE
tHD
Data Valid After CE Low
tHL
Output Float Delay
tSSR
CS to CE Setup
50
0
-
ns
tSRR
R/C to CE Setup
0
0
-
ns
tSAR
AO to CE Setup
50
25
-
ns
tHSR
CS Valid After CE Low
0
0
-
ns
tHRR
R/C High After CE Low
0
0
-
ns
tHAR
AO Valid After CE Low
50
25
-
ns
-
90
300
ns
tHS
STS Delay After Data Valid
NOTES:
1. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
2. Time is measured from 50% level of digital transitions. Tested with a 50pF and 3kΩ load.
6-960
HI-574A, HI-674A, HI-774
Definitions of Specifications
Pin Descriptions
DESCRIPTION
Linearity Error
PIN
SYMBOL
1
VLOGIC
2
12/8
Data Mode Select - Selects between
12-bit and 8-bit output modes.
3
CS
Chip Select - Chip Select high disables
the device.
4
AO
Byte Address/Short Cycle - See Table
1 for operation.
5
R/C
Read/Convert - See Table 1 for
operation.
6
CE
Chip Enable - Chip Enable low disables
the device.
7
VCC
Positive Supply (+12V/+15V)
8
REF OUT
+10V Reference
Differential Linearity Error (No Missing Codes)
9
AC
Analog Common
10
REF IN
Reference Input
11
VEE
12
BIP OFF
Bipolar Offset
13
10V Input
10V Input - Used for 0V to 10V and -5V
to +5V input ranges.
A specification which guarantees no missing codes requires
that every code combination appear in a monotonic increasing sequence as the analog input level is increased. Thus
every code must have a finite width. For the HI-X74(A)K and L
grades, which guarantee no missing codes to 12-bit resolution, all 4096 codes must be present over the entire operating
temperature ranges. The HI-X74(A)J grade guarantees no
missing codes to 11-bit resolution over temperature; this
means that all code combinations of the upper 11 bits must be
present; in practice very few of the 12-bit codes are missing.
14
20V Input
20V Input - Used for 0V to 20V and -10V
to +10V input ranges.
Logic supply pin (+5V)
Negative Supply (-12V/-15V).
Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale”. The point
used as “zero” occurs 1/2 LSB (1.22mV for 10V span) before
the first code transition (all zeros to only the LSB “on”). “Full
scale” is defined as a level 11/2 LSB beyond the last code transition (to all ones). The deviation of a code from the true straight
line is measured from the middle of each particular code.
The HI-X74(A)K and L grades are guaranteed for maximum
nonlinearity of ±1/2 LSB. For these grades, this means that an
analog value which falls exactly in the center of a given code
width will result in the correct digital output code. Values nearer
the upper or lower transition of the code width may produce the
next upper or lower digital output code. The HI-X74(A)J is
guaranteed to ±1 LSB max error. For this grade, an analog
value which falls within a given code width will result in either
the correct code for that region or either adjacent one.
Note that the linearity error is not user-adjustable.
Unipolar Offset
The first transition should occur at a level 1/2 LSB above analog
common. Unipolar offset is defined as the deviation of the
actual transition from that point. This offset can be adjusted as
discussed on the following pages. The unipolar offset temperature coefficient specifies the maximum change of the transition
point over temperature, with or without external adjustment.
15
DC
Digital Common
16
DB0
Data Bit 0 (LSB)
17
DB1
Data Bit 1
18
DB2
Data Bit 2
Bipolar Offset
19
DB3
Data Bit 3
20
DB4
Data Bit 4
21
DB5
Data Bit 5
22
DB6
Data Bit 6
Similarly, in the bipolar mode, the major carry transition
(0111 1111 1111 to 1000 0000 0000) should occur for an
analog value 1/2 LSB below analog common. The bipolar
offset error and temperature coefficient specify the initial
deviation and maximum change in the error over temperature.
23
DB7
Data Bit 7
24
DB8
Data Bit 8
25
DB9
Data Bit 9
26
DB10
Data Bit 10
27
DB11
Data Bit 11 (MSB)
28
STS
Status Bit - Status high implies a
conversion is in progress.
Full Scale Calibration Error
The last transition (from 1111 1111 1110 to 1111 1111
1111) should occur for an analog value 11/2 LSB below the
nominal full scale (9.9963V for 10.000V full scale). The full
scale calibration error is the deviation of the actual level at
the last transition from the ideal level. This error, which is
typically 0.05 to 0.1% of full scale, can be trimmed out as
shown in Figures 2 and 3. The full scale calibration error
over temperature is given with and without the initial error
trimmed out. The temperature coefficients for each grade
indicate the maximum change in the full scale gain from the
initial value using the internal 10V reference.
6-961
HI-574A, HI-674A, HI-774
Temperature Coefficients
Power Supplies
The temperature coefficients for full-scale calibration, unipolar offset, and bipolar offset specify the maximum change
from the initial (25oC) value to the value at TMIN or TMAX .
Supply voltages to the HI-X74(A) (+15V, -15V and +5V) must
be “quiet” and well regulated. Voltage spikes on these lines can
affect the converter’s accuracy, causing several LSBs to flicker
when a constant input is applied. Digital noise and spikes from
a switching power supply are especially troublesome. If switching supplies must be used, outputs should be carefully filtered
to assure “quiet” DC voltage at the converter terminals.
Power Supply Rejection
The standard specifications for the HI-X74A assume use of
+5.00V and ±15.00V or ±12.00V supplies. The only effect of
power supply error on the performance of the device will be
a small change in the full scale calibration. This will result in
a linear change in all lower order codes. The specifications
show the maximum change in calibration from the initial
value with the supplies at the various limits.
Code Width
A fundamental quantity for A/D converter specifications is
the code width. This is defined as the range of analog input
values for which a given digital output code will occur. The
nominal value of a code width is equivalent to 1 least significant bit (LSB) of the full scale range or 2.44mV out of 10V for
a 12-bit ADC.
Quantization Uncertainty
Analog-to-digital converters exhibit an inherent quantization
uncertainty of ±1/2 LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be
reduced for a converter of given resolution.
Left-justified Data
The data format used in the HI-X74(A) is left-justified. This
means that the data represents the analog input as a fraction of full-scale, ranging from 0 to 4095 . This implies a
4096
binary point to the left of the MSB.
Applying the HI-X74(A)
For each application of this converter, the ground
connections, power supply bypassing, analog signal source,
digital timing and signal routing on the circuit board must be
optimized to assure maximum performance. These areas
are reviewed in the following sections, along with basic operating modes and calibration requirements.
Physical Mounting and Layout Considerations
Layout
Unwanted, parasitic circuit components, (L, R, and C) can
make 12-bit accuracy impossible, even with a perfect A/D
converter. The best policy is to eliminate or minimize these
parasitics through proper circuit layout, rather than try to
quantify their effects.
The recommended construction is a double-sided printed
circuit board with a ground plane on the component side.
Other techniques, such as wire-wrapping or point-to-point
wiring on vector board, will have an unpredictable effect on
accuracy.
In general, sensitive analog signals should be routed between
ground traces and kept well away from digital lines. If analog
and digital lines must cross, they should do so at right angles.
Further, a bypass capacitor pair on each supply voltage
terminal is necessary to counter the effect of variations in
supply current. Connect one pair from pin 1 to 15 (VLOGIC
supply), one from pin 7 to 9 (VCC to Analog Common) and
one from pin 11 to 9 (VEE to Analog Common). For each
capacitor pair, a 10µF tantalum type in parallel with a 0.1µF
ceramic type is recommended.
Ground Connections
Pins 9 and 15 should be tied together at the package to
guarantee specified performance for the converter. In
addition, a wide PC trace should run directly from pin 9 to
(usually) +15V common, and from pin 15 to (usually) the +5V
Logic Common. If the converter is located some distance from
the system’s “single point” ground, make only these connections to pins 9 and 15: Tie them together at the package, and
back to the system ground with a single path. This path
should have low resistance. (Code dependent currents flow in
the VCC , VEE and VLOGIC terminals, but not through the
HI-X74(A)’s Analog Common or Digital Common).
Analog Signal Source
HI-574A and HI-674A
The device chosen to drive the HI-X74A analog input will see a
nominal load of 5kΩ (10V range) or 10kΩ (20V range).
However, the other end of these input resistors may change
±400mV with each bit decision, creating abrupt changes in current at the analog input. Thus, the signal source must maintain
its output voltage while furnishing these step changes in load
current, which occur at 1.6µs and 950ns intervals for the
HI-574A and HI-674A, respectively. This requires low output
impedance and fast settling by the signal source.
The output impedance of an op amp, for example, has an open
loop value which, in a closed loop, is divided by the loop gain
available at a frequency of interest. The amplifier should have
acceptable loop gain at 600KHz for use with the HI-X74A. To
check whether the output properties of a signal source are
suitable, monitor the HI-X74A’s input (pin 13 or 14) with an oscilloscope while a conversion is in progress. Each of the twelve
disturbances should subside in 1µs or less for the HI-574A and
500ns or less for the HI-674A. (The comparator decision is
made about 1.5µs and 850ns after each code change from the
SAR for the HI-574A and HI-674A, respectively.)
If the application calls for a Sample/Hold to precede the
converter, it should be noted that not all Sample/Holds are
compatible with the HI-574A in the manner described above.
These will require an additional wideband buffer amplifier to
lower their output impedance. A simpler solution is to use the
Intersil HA-5320 Sample/Hold, which was designed for use
with the HI-574A.
6-962
HI-574A, HI-674A, HI-774
The device driving the HI-774 analog input will see a nominal
load of 5kΩ (10V range) or 10kΩ (20V range). However, the
other end of these input resistors may change as much as
±400mV with each bit decision. These input disturbances
are caused by the internal DAC changing codes which
causes a glitch on the summing junction. This creates abrupt
changes in current at the analog input causing a “kick back”
glitch from the input. Because the algorithm starts with the
MSB, the first glitches will be the largest and get smaller as
the conversion proceeds. These glitches can occur at 350ns
intervals so an op amp with a low output impedance and fast
settling is desirable. Ultimately the input must settle to within
the window of Figure 1 at the bit decision points in order to
achieve 12-bit accuracy.
The HI-774 differs from the most high-speed successive
approximation type ADC’s in that it does not require a high
performance buffer or sample and hold. With error correction
the input can settle while the conversion is underway, but
only during the first 4.8µs. The input must be within 10.76%
of the final value when the MSB decision is made. This
occurs approximately 650ns after the conversion has been
initiated. Digital error correction also loosens the bandwidth
requirements of the buffer or sample and hold. As long as
the input “kick back” disturbances settle within the window of
Figure 1 the device will remain accurate. The combined
effect of settling and the “kick back” disturbances must
remain in the Figure 1 window.
direction by up to 15 LSBs. This results in a total correction
range of +31 to -32 LSBs. When an 8-bit conversion is performed, the input must settle to within ±1/2 LSB at 8-bit resolution (which equals ±8 LSBs at 12-bit resolution).
With the HI-774 a conversion can be initiated before the
input has completely settled, as long as it meets the constraints of the Figure 1 window. This allows the user to start
conversion up to 4.8µs earlier than with a typical analog to
digital converter. A typical successive approximation type
ADC must have a constant input during a conversion
because once a bit decision is made it is locked in and cannot change.
32
ALLOWABLE INPUT CHANGE
(LSBs AT 12-BIT RESOLUTION)
HI-774
8-BIT CONVERSION
BIT DECISION POINTS
8
0
~ 4.8µs
-8
LAST BIT
DECISION
(12-BIT)
-16
MSB BIT DECISION
~ 650ns
12-BIT CONVERSION
-31
1
CONVERSION
INITIATED
If the design is being optimized for speed, the input device
should have closed loop bandwidth to 3MHz, and a low output impedance (calculated by dividing the open loop output
resistance by the open loop gain). If the application requires
a high speed sample and hold the Intersil HA-5330 or
HA-5320 are recommended.
2
3
4
5
TIME (µs)
6
7
8
FIGURE 1. HI-774 ERROR CORRECTION WINDOW vs TIME
In any design the input (pin 13 or 14) should be checked
during a conversion to make sure that the input stays within
the correctable window of Figure 1.
Digital Error Correction
OFFSET
R1
100K
HI-774
The HI-774 features the smart successive approximation
register (SSAR) which includes digital error correction. This
has the advantage of allowing the initial input to vary within a
+31 to -32 LSB window about the final value. The input can
move during the first 4.8µs, after which it must remain stable
within ±1/2 LSB. With this feature a conversion can start
before the input has settled completely; however, it must be
within the window as described in Figure 1.
2 12/8
STS 28
3
CS
HIGH BITS
24-27
4
AO
MIDDLE BITS
5
R/C
6
CE
20-23
LOW BITS
+15V
-15V
The conversion cycle starts by making the first 8-bit decisions
very quickly, allowing the internal DAC to settle only to 8-bit
accuracy. Then the converter goes through two error correction cycles. At this point the input must be stable within ±1/2
LSB. These cycles correct the 8-bit word to 12-bit accuracy for
any errors made (up to +16 or -32 LSBs). This is up one count
or down two counts at 8-bit resolution. The converter then
continues to make the 4 LSB decisions, settling out to 12-bit
accuracy. The last four bits can adjust the code in the positive
END OF
CONVERSION
(12 BIT)
±1/2 LSB
16
16-19
GAIN
R2
10 REF IN
100K
100Ω
8
REF OUT
100Ω
12 BIP OFF
+5V
1
0V TO +10V
ANALOG
INPUTS
13 10VIN
+15V 7
14 20VIN€
†
-15V 11
0V TO +20V
9 ANA
COM
DIG COM 15
† When driving the 20V (pin 14) input, minimize capacitance on pin 13.
6-963
FIGURE 2. UNIPOLAR CONNECTIONS
HI-574A, HI-674A, HI-774
2 12/8
STS 28
3 CS
HIGH BITS
24-27
4 AO
MIDDLE BITS
adjustment is complete. Therefore, calibration is performed
in terms of the observable code changes instead of the
midpoint between code changes.
For example, midpoint of the first LSB increment should be
positioned at the origin, with an output code of all 0’s. To do
this, apply an input of +1/2 LSB (+1.22mV for the 10V range;
+2.44mV for the 20V range). Adjust the Offset potentiometer
R1 until the first code transition flickers between
0000 0000 0000 and 0000 0000 0001.
20-23
5 R/C
LOW BITS
GAIN
16-19
6 CE
R2
Next, perform a Gain Adjust at positive full scale. Again, the
ideal input corresponding to the last code change is applied.
This is 11/2 LSBs below the nominal full scale (+9.9963V for
10V range; +19.9927V for 20V range). Adjust the Gain
potentiometer R2 for flicker between codes 1111 1111 1110
and 1111 1111 1111.
10 REF IN
100Ω
8 REF OUT
100Ω
±5V
ANALOG
INPUTS
±10V
12 BIP OFF
R1
OFFSET
+5V 1
+15V 7
13 10VIN
14 20VIN†
9 ANA
COM
Bipolar Connections and Calibration
-15V 11
Refer to Figure 3. The gain and offset errors listed under
Specifications may be adjusted to zero using potentiometers R1 and R2 (see Note). If this isn’t required, either or
both pots may be replaced by a 50Ω, 1% metal film resistor.
DIG COM 15
† When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 3. BIPOLAR CONNECTIONS
Range Connections and Calibration Procedures
The HI-X74(A) is a “complete” A/D converter, meaning it is
fully operational with addition of the power supply voltages, a
Start Convert signal, and a few external components as
shown in Figure 2 and Figure 3. Nothing more is required for
most applications.
Connect the Analog signal to pin 13 for a ±5V range, or to
pin 14 for a ±10V range. Calibration of offset and gain is similar to that for the unipolar ranges as discussed above. First
apply a DC input voltage 1/2 LSB above negative full scale
(i.e., -4.9988V for the ±5V range, or -9.9976V for the ±10V
range). Adjust the offset potentiometer R1 for flicker between
output codes 0000 0000 0000 and 0000 0000 0001. Next,
apply a DC input voltage 11/2 LSBs below positive full scale
(+4.9963V for ±5V range; +9.9927V for ±10V range). Adjust
the Gain potentiometer R2 for flicker between codes 1111
1111 1110 and 1111 1111 1111.
Whether controlled by a processor or operating in the standalone mode, the HI-X74(A) offers four standard input ranges:
0V to +10V, 0V to +20V, ±5V and ±10V. The maximum errors
for gain and offset are listed under Specifications. If required,
however, these errors may be adjusted to zero as explained
below. Power supply and ground connections have been discussed in an earlier section.
NOTE: The 100Ω potentiometer R2 provides Gain Adjust for the 10V
and 20V ranges. In some applications, a full scale of 10.24V (LSB
equals 2.5mV) or 20.48V (LSB equals 5.0mV) is more convenient.
For these, replace R2 by a 50Ω, 1% metal film resistor. Then, to provide Gain Adjust for the 10.24V range, add a 200Ω potentiometer in
series with pin 13. For the 20.48V range, add a 500Ω potentiometer
in series with pin 14.
Unipolar Connections and Calibration
Controlling the HI-X74(A)
Refer to Figure 2. The resistors shown (see Note) are for
calibration of offset and gain. If this is not required, replace
R2 with a 50Ω, 1% metal film resistor and remove the network on pin 12. Connect pin 12 to pin 9. Then, connect the
analog signal to pin 13 for the 0V to 10V range, or to pin 14
for the 0V to 20V range. Inputs to +20V (5V over the power
supply) are no problem - the converter operates normally.
The HI-X74(A) includes logic for direct interface to most
microprocessor systems. The processor may take full control of each conversion, or the converter may operate in the
“stand-alone” mode, controlled only by the R/C input. Full
control consists of selecting an 8-bit or 12-bit conversion
cycle, initiating the conversion, and reading the output data
when ready-choosing either 12 bits at once or 8 followed by
4, in a left-justified format. The five control inputs are all
TTL/CMOS-compatible: (12/8, CS, AO , R/C and CE). Table
1 illustrates the use of these inputs in controlling the
converter’s operations. Also, a simplified schematic of the
internal control logic is shown in Figure 7.
Calibration consists of adjusting the converter’s most
negative output to its ideal value (offset adjustment), then,
adjusting the most positive output to its ideal value (gain
adjustment). To understand the procedure, note that in
principle, one is setting the output with respect to the midpoint of an increment of analog input, as denoted by two
adjacent code changes. Nominal value of an increment is
one LSB. However, this approach is impractical because
nothing “happens” at a midpoint to indicate that an
6-964
HI-574A, HI-674A, HI-774
“Stand-Alone Operation”
Conversion Length
The simplest control interface calls for a singe control line
connected to R/C. Also, CE and 12/8 are wired high, CS and
AO are wired low, and the output data appears in words of
12 bits each.
A Convert Start transition (see Table 1) latches the state of
AO , which determines whether the conversion continues for
12 bits (AO low) or stops with 8 bits (AO high). If all 12 bits are
read following an 8-bit conversion, the last three LSBs will
read ZERO and DB3 will read ONE. AO is latched because it
is also involved in enabling the output buffers (see “Reading
the Output Data”). No other control inputs are latched.
The R/C signal may have any duty cycle within (and
including) the extremes shown in Figures 8 and 9. In general, data may be read when R/C is high unless STS is also
high, indicating a conversion is in progress. Timing parameters particular to this mode of operation are listed below
under “Stand-Alone Mode Timing”.
TABLE 1. TRUTH TABLE FOR HI-X74(A) CONTROL INPUTS
HI-574A STAND-ALONE MODE TIMING
SYMBOL
PARAMETER
MIN
TYP
MAX UNITS
tHRL
Low R/C Pulse Width
50
-
-
ns
tDS
STS Delay from R/C
-
-
200
ns
Data Valid after R/C Low
25
-
-
ns
STS Delay after Data Valid
300
-
1200
ns
tHRH
High R/C Pulse Width
150
-
-
ns
tDDR
Data Access Time
-
-
150
ns
tHDR
tHS
Time is measured from 50% level of digital transitions. Tested with a
50pF and 3kΩ load.
CE
CS
R/C
12/8
AO
0
X
X
X
X
None
X
1
X
X
X
None
↑
0
0
X
0
Initiate 12-bit conversion
↑
0
0
X
1
Initiate 8-bit conversion
1
↓
0
X
0
Initiate 12-bit conversion
1
↓
0
X
1
Initiate 8-bit conversion
1
0
↓
X
0
Initiate 12-bit conversion
1
0
↓
X
1
Initiate 8-bit conversion
1
0
1
1
X
Enable 12-bit Output
1
0
1
0
0
Enable 8 MSBs Only
1
0
1
0
1
Enable 4 LSBs Plus 4 Trailing
Zeroes
HI-674A STAND-ALONE MODE TIMING
SYMBOL
PARAMETER
MIN
TYP
MAX UNITS
tHRL
Low R/C Pulse Width
50
-
-
ns
tDS
STS Delay from R/C
-
-
200
ns
Data Valid after R/C Low
25
-
-
ns
STS Delay after Data Valid
25
-
850
ns
tHRH
High R/C Pulse Width
150
-
-
ns
tDDR
Data Access Time
-
-
150
ns
tHDR
tHS
OPERATION
Conversion Start
A conversion may be initiated as shown in Table 1 by a logic
transition on any of three inputs: CE, CS or R/C. The last of
the three to reach the correct state starts the conversion, so
one, two or all three may be dynamically controlled. The
nominal delay from each is the same, and if necessary, all
three may change state simultaneously. However, to ensure
that a particular input controls the start of conversion, the
other two should be set up at least 50ns earlier. See the
HI-774 Timing Specifications, Convert Mode.
Time is measured from 50% level of digital transitions. Tested with a
50pF and 3kΩ load.
This variety of HI-X74(A) control modes allows a simple
interface in most system applications. The Convert Start
timing relationships are illustrated in Figure 4.
HI-774 STAND-ALONE MODE TIMING
tHRL
Low R/C Pulse Width
50
-
-
ns
tDS
STS Delay from R/C
-
-
200
ns
The output signal STS indicates status of the converter by
going high only while a conversion is in progress. While STS
is high, the output buffers remain in a high impedance state
and data cannot be read. Also, an additional Start Convert
will not reset the converter or reinitiate a conversion while
STS is high.
20
-
-
ns
Reading the Output Data
-
-
850
ns
150
-
-
ns
-
-
150
ns
The output data buffers remain in a high impedance state
until four conditions are met: R/C high, STS low, CE high and
CS low. At that time, data lines become active according to
the state of inputs 12/8 and AO . Timing constraints are
illustrated in Figure 5.
SYMBOL
tHDR
tHS
PARAMETER
Data Valid after R/C Low
STS Delay after Data Valid
tHRH
High R/C Pulse Width
tDDR
Data Access Time
MIN
TYP
MAX UNITS
6-965
HI-574A, HI-674A, HI-774
The 12/8 input will be tied high or low in most applications,
though it is fully TTL/CMOS-compatible. With 12/8 high, all
12 output lines become active simultaneously, for interface to
a 12-bit or 16-bit data bus. The AO input is ignored.
CE
With 12/8 low, the output is organized in two 8-bit bytes,
selected one at a time by AO . This allows an 8-bit data bus
to be connected as shown in Figure 6. AO is usually tied to
the least significant bit of the address bus, for storing the
HI-X74(A) output in two consecutive memory locations.
(With AO low, the 8 MSBs only are enabled. With AO high, 4
MSBs are disabled, bits 4 through 7 are forced low, and the 4
LSBs are enabled). This two byte format is considered “left
justified data,” for which a decimal (or binary!) point is
assumed to the left of byte 1:
BYTE 1
•
X
X
X
X
tHRR
R/C
tSRR
AO
tSAR
STS
X
X
X
X
X
X
MSB
X
0
tHAR
tHS
BYTE 2
X
tHSR
tSSR
CS
0
0
0
DB11-DB0
HIGH IMPEDANCE
tDD
LSB
Further, AO may be toggled at any time without damage to
the converter. Break-before-make action is guaranteed
between the two data bytes, which assures that the outputs
strapped together in Figure 6 will never be enabled at the
same time.
tHD
DATA
VALID
tHL
See HI-774 Timing Specifications for more information.
FIGURE 5. READ CYCLE TIMING
A read operation usually begins after the conversion is
complete and STS is low. For earliest access to the data,
however, the read should begin no later than (tDD + tHS)
before STS goes low. See Figure 5.
AO
2 12/8
tSSC
CS
R/C
tHSC
tSRC
STS 28
1
tHEC
CE
ADDRESS BUS
tHRC
DB11 (MSB) 27
3
26
4 AO
25
5
24
6
23
22
7
AO
8
tSAC
tHAC
STS
tC
tDSC
HIGH IMPEDANCE
DB11-DB0
HI-774
21
9
20
10
19
11
18
12
17
13
DB0 (LSB) 16
DIG. 15
COM.
14
See HI-774 Timing Specifications for more information.
FIGURE 4. CONVERT START TIMING
FIGURE 6. INTERFACE TO AN 8-BIT DATA BUS
6-966
DATA
BUS
HI-574A, HI-674A, HI-774
NIBBLE B ZERO
OVERRIDE
NIBBLE A, B
INPUT BUFFERS
12/8
NIBBLE C
READ CONTROL
CS
AO
STATUS
R/C
CE
CONVERT
CONTROL
EOC9
CURRENT
CONTROLLED
OSCILLATOR
STROBE
CLOCK
CK
D
POWER UP
RESET
Q
Q
RESET
AO LATCH
EOC13
FIGURE 7. HI-774 CONTROL LOGIC
tHRL
R/C
tDS
STS
tC
tHDR
DB11-DB0
tHS
DATA
VALID
DATA
VALID
FIGURE 8. LOW PULSE FOR R/C - OUTPUTS ENABLED AFTER CONVERSION
R/C
tHRH
tDS
STS
tDDR
DB11-DB0
HIGH-Z
tC
tHDR
HIGH-Z
DATA
VALID
FIGURE 9. HIGH PULSE FOR R/C - OUTPUTS ENABLED WHILE R/C HIGH, OTHERWISE HIGH-Z
6-967
HI-574A, HI-674A, HI-774
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Analog: 3070mm x 4610mm
Digital: 1900mm x 4510mm
Type: Nitride Over Silox
Nitride Thickness: 3.5kÅ ±0.5kÅ
Silox Thickness: 12kÅ ±1.5kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Digital Type: Nitrox
Thickness: 10kÅ ±2kÅ
1.3 x 105 A/cm2
Metal 1: AlSiCu
Thickness: 8kÅ ±1kÅ
Metal 2: AlSiCu
Thickness: 16kÅ ±2kÅ
Analog Type: Al
Thickness: 16kÅ ±2kÅ
Metallization Mask Layout
DB11
STS
VLOGIC
VLOGIC
12/8
CS
AO
HI-574A, HI-674A, HI-774
R/C
DB10
CE
VCC
DB9
VREFOUT
ANALOG
COMMON
DB8
ANALOG
COMMON
DB7
ANALOG
COMMON
DB6
VREFIN
DB5
DB4
DB3
DB2
6-968
DB1
DB0
DIGITAL
COMMON
10V
IN
20V
IN
BIPOLAR
OFFSET
VEE
HI-574A, HI-674A, HI-774
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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Intersil Corporation
P. O. Box 883, Mail Stop 53-204
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TEL: (321) 724-7000
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6-969
ASIA
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