AD AD8034 Low cost, 80 mhz fastfet op amp Datasheet

Low Cost, 80 MHz
FastFET Op Amps
AD8033/AD8034
CONNECTION DIAGRAMS
AD8033
8
NC
7
+VS
+IN 3
6
VOUT
–VS 4
5
NC
NC = NO CONNECT
AD8033
VOUT 1
5
+VS
4
–IN
–VS 2
+IN 3
Figure 1. 8-Lead SOIC (R)
02924-002
NC 1
–IN 2
02924-001
FET input amplifier
1 pA typical input bias current
Very low cost
High speed
80 MHz, −3 dB bandwidth (G = +1)
80 V/μs slew rate (G = +2)
Low noise
11 nV/√Hz (f = 100 kHz)
0.7 fA/√Hz (f = 100 kHz)
Wide supply voltage range: 5 V to 24 V
Low offset voltage: 1 mV typical
Single-supply and rail-to-rail output
High common-mode rejection ratio: −100 dB
Low power: 3.3 mA/amplifier typical supply current
No phase reversal
Small packaging: 8-lead SOIC, 8-lead SOT-23, and 5-lead SC70
Figure 2. 5-Lead SC70 (KS)
VOUT1 1
8
+VS
–IN1 2
7
VOUT2
+IN1 3
6
–IN2
–VS 4
5
+IN2
AD8034
02924-003
FEATURES
Figure 3. 8-Lead SOIC (R) and 8-Lead SOT-23 (RJ)
24
21
VOUT = 200mV p-p
G = +10
18
15
APPLICATIONS
12
GAIN (dB)
Instrumentation
Filters
Level shifting
Buffering
G = +5
9
6
G = +2
3
G = +1
0
–3
The AD8033/AD8034 FastFET™ amplifiers are voltage feedback
amplifiers with FET inputs, offering ease of use and excellent
performance. The AD8033 is a single amplifier and the AD8034
is a dual amplifier. The AD8033/AD8034 FastFET op amps in
Analog Devices, Inc., proprietary XFCB process offer significant
performance improvements over other low cost FET amps, such
as low noise (11 nV/√Hz and 0.7 fA/√Hz) and high speed (80 MHz
bandwidth and 80 V/μs slew rate).
With a wide supply voltage range from 5 V to 24 V and fully
operational on a single supply, the AD8033/AD8034 amplifiers
work in more applications than similarly priced FET input
amplifiers. In addition, the AD8033/AD8034 have rail-to-rail
outputs for added versatility.
G = –1
–6
–9
0.1
1
10
FREQUENCY (MHz)
100
1000
02924-004
GENERAL DESCRIPTION
Figure 4. Small Signal Frequency Response
The AD8033/AD8034 amplifiers only draw 3.3 mA/amplifier of
quiescent current while having the capability of delivering up to
40 mA of load current.
The AD8033 is available in a small package 8-lead SOIC and a
small package 5-lead SC70. The AD8034 is also available in a
small package 8-lead SOIC and a small package 8-lead SOT-23.
They are rated to work over the industrial temperature range of
−40°C to +85°C without a premium over commercial grade
products.
Despite their low cost, the amplifiers provide excellent overall
performance. They offer a high common-mode rejection of
−100 dB, low input offset voltage of 2 mV maximum, and low
noise of 11 nV/√Hz.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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IMPORTANT LINKS for the AD8033_8034*
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DOCUMENTATION
PARAMETRIC SELECTION TABLES
AN-649: Using the Analog Devices Active Filter Design Tool
AN-581: Biasing and Decoupling Op Amps in Single Supply
Applications
AN-402: Replacing Output Clamping Op Amps with Input Clamping
Amps
AN-417: Fast Rail-to-Rail Operational Amplifiers Ease Design
Constraints in Low Voltage High Speed Systems
MT-060: Choosing Between Voltage Feedback and Current Feedback
Op Amps
MT-059: Compensating for the Effects of Input Capacitance on VFB
and CFB Op Amps Used in Current-to-Voltage Converters
MT-058: Effects of Feedback Capacitance on VFB and CFB Op Amps
MT-056: High Speed Voltage Feedback Op Amps
MT-053: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR
MT-052: Op Amp Noise Figure: Don’t Be Mislead
MT-050: Op Amp Total Output Noise Calculations for Second-Order
System
MT-049: Op Amp Total Output Noise Calculations for Single-Pole
System
MT-048: Op Amp Noise Relationships: 1/f Noise, RMS Noise, and
Equivalent Noise Bandwidth
MT-047: Op Amp Noise
MT-033: Voltage Feedback Op Amp Gain and Bandwidth
MT-032: Ideal Voltage Feedback (VFB) Op Amp
A Stress-Free Method for Choosing High-Speed Op Amps
FOR THE AD8033
Find Similar Products By Operating Parameters
High Speed Amplifiers Selection Table
AN-357: Operational Integrators
UG-112: Universal Evaluation Board for Single, High Speed Op Amps
Offered in SC-70 Packages
UG-101: Evaluation Board User Guide
FOR THE AD8034
AN-108: JFET-Input Amps are Unrivaled for Speed and Accuracy
AN-356: User’s Guide to Applying and Measuring Operational
Amplifier Specifications
UG-019: Universal Evaluation Board for Dual, High Speed Op Amps
Offered in 8-Lead SOT-23 Packages
UG-128: Universal Evaluation Board for Dual High Speed Op Amps in
SOIC Packages
EVALUATION KITS & SYMBOLS & FOOTPRINTS
View the Evaluation Boards and Kits page for the AD8033
View the Evaluation Boards and Kits page for the AD8034
Symbols and Footprints for the AD8033
Symbols and Footprints for the AD8034
DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE
dBm/dBu/dBv Calculator
Analog Filter Wizard 2.0
Power Dissipation vs Die Temp
ADIsimOpAmp™
OpAmp Stability
AD8033 SPICE Macro-Model
AD8034 SPICE Macro-Model
Photodiode Preamp Error Budget Tutorial for the AD8034
DESIGN COLLABORATION COMMUNITY
Collaborate Online with the ADI support team and other designers
about select ADI products.
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Submit your support request here:
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Quality and Reliability
Lead(Pb)-Free Data
SAMPLE & BUY
AD8033
AD8034
Find Local Distributors
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.
Note: Dynamic changes to the content on this page (labeled 'Important Links') does not
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This content may be frequently modified.
AD8033/AD8034
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Overdrive .......................................................................... 16
Applications ....................................................................................... 1
Input Impedance ........................................................................ 16
General Description ......................................................................... 1
Thermal Considerations............................................................ 16
Connection Diagrams ...................................................................... 1
Layout, Grounding, and Bypassing Considerations .................. 18
Revision History ............................................................................... 2
Bypassing ..................................................................................... 18
Specifications..................................................................................... 3
Grounding ................................................................................... 18
Absolute Maximum Ratings............................................................ 6
Leakage Currents ........................................................................ 18
Maximum Power Dissipation ..................................................... 6
Input Capacitance ...................................................................... 18
Output Short Circuit .................................................................... 6
Applications Information .............................................................. 19
ESD Caution .................................................................................. 6
High Speed Peak Detector ........................................................ 19
Typical Performance Characteristics ............................................. 7
Active Filters ............................................................................... 20
Test Circuits ..................................................................................... 14
Wideband Photodiode Preamp ................................................ 21
Theory of Operation ...................................................................... 16
Outline Dimensions ....................................................................... 23
Output Stage Drive and Capacitive Load Drive ..................... 16
Ordering Guide .......................................................................... 24
REVISION HISTORY
9/08—Rev. C to Rev. D
Deleted Usable Input Range Parameter, Table 1 ........................... 3
Deleted Usable Input Range Parameter, Table 2 ........................... 4
Deleted Usable Input Range Parameter, Table 3 ........................... 5
4/08—Rev. B to Rev. C
Changes to Format ............................................................. Universal
Changes to Features and General Description ............................. 1
Changes to Figure 13 Caption and Figure 14 Caption ................ 8
Changes to Figure 22 and Figure 23 ............................................... 9
Changes to Figure 25 and Figure 28 ............................................. 10
Changes to Input Capacitance Section ........................................ 18
Changes to Active Filters Section ................................................. 21
Changes to Outline Dimensions................................................... 23
Changes to Ordering Guide .......................................................... 24
8/02—Rev. 0 to Rev. A
Added AD8033 ................................................................... Universal
VOUT = 2 V p-p Deleted from Default Conditions ......... Universal
Added SOIC-8 (R) and SC70 (KS) ..................................................1
Edits to General Description Section .............................................1
Changes to Specifications .................................................................2
New Figure 2 ......................................................................................5
Edits to Maximum Power Dissipation Section ..............................5
Changes to Ordering Guide .............................................................5
Change to TPC 3 ...............................................................................6
Change to TPC 6 ...............................................................................6
Change to TPC 9 ...............................................................................7
New TPC 16 .......................................................................................8
New TPC 17 .......................................................................................8
New TPC 31 .................................................................................... 11
New TPC 35 .................................................................................... 11
New Test Circuit 9 .......................................................................... 13
SC70 (KS) Package Added ............................................................ 19
2/03—Rev. A to Rev. B
Changes to Features.......................................................................... 1
Changes to Connection Diagrams ................................................. 1
Changes to Specifications ................................................................ 2
Changes to Absolute Maximum Ratings ....................................... 4
Replaced TPC 31............................................................................. 11
Changes to TPC 35 ......................................................................... 11
Changes to Test Circuit 3 ............................................................... 12
Updated Outline Dimensions ....................................................... 19
Rev. D | Page 2 of 24
AD8033/AD8034
SPECIFICATIONS
TA = 25°C, VS = ±5 V, RL = 1 kΩ, gain = +2, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Input Overdrive Recovery Time
Output Overdrive Recovery Time
Slew Rate (25% to 75%)
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Distortion
Second Harmonic
Third Harmonic
Crosstalk, Output-to-Output
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Conditions
Min
Typ
G = +1, VOUT = 0.2 V p-p
G = +2, VOUT = 0.2 V p-p
G = +2, VOUT = 2 V p-p
−6 V to +6 V input
−3 V to +3 V input, G = +2
G = +2, VOUT = 4 V step
G = +2, VOUT = 2 V step
G = +2, VOUT = 8 V step
65
80
30
21
135
135
80
95
225
MHz
MHz
MHz
ns
ns
V/μs
ns
ns
−82
−85
−70
−81
−86
11
0.7
dBc
dBc
dBc
dBc
dB
nV/√Hz
fA/√Hz
55
fC = 1 MHz, VOUT = 2 V p-p
RL = 500 Ω
RL = 1 kΩ
RL = 500 Ω
RL = 1 kΩ
f = 1 MHz, G = +2
f = 100 kHz
f = 100 kHz
VCM = 0 V
TMIN − TMAX
1
Input Offset Voltage Match
Input Offset Voltage Drift
Input Bias Current
Open-Loop Gain
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
TMIN − TMAX
VOUT = ± 3 V
89
VCM = −3 V to +1.5 V
−89
±4.75
30% overshoot, G = +1, VOUT = 400 mV p-p
4
1.5
50
92
−90
Rev. D | Page 3 of 24
2
3.5
2.5
27
11
Unit
mV
mV
mV
μV/°C
pA
pA
dB
1000||2.3
1000||1.7
GΩ||pF
GΩ||pF
−5.0 to +2.2
−100
V
dB
±4.95
40
35
V
mA
pF
5
VS = ±2 V
Max
3.3
−100
24
3.5
V
mA
dB
AD8033/AD8034
TA = 25°C, VS = 5 V, RL = 1 kΩ, gain = +2, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Input Overdrive Recovery Time
Output Overdrive Recovery Time
Slew Rate (25% to 75%)
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Distortion
Second Harmonic
Third Harmonic
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Conditions
Min
Typ
G = +1, VOUT = 0.2 V p-p
G = +2, VOUT = 0.2 V p-p
G = +2, VOUT = 2 V p-p
−3 V to +3 V input
−1.5 V to +1.5 V input, G = +2
G = +2, VOUT = 4 V step
G = +2, VOUT = 2 V step
70
80
32
21
180
200
70
100
MHz
MHz
MHz
ns
ns
V/μs
ns
−80
−84
−70
−80
−86
11
0.7
dBc
dBc
dBc
dBc
dB
nV/√Hz
fA/√Hz
55
fC = 1 MHz, VOUT = 2 V p-p
RL = 500 Ω
RL = 1 kΩ
RL = 500 Ω
RL = 1 kΩ
f = 1 MHz, G = +2
f = 100 kHz
f = 100 kHz
VCM = 0 V
TMIN − TMAX
1
Input Offset Voltage Match
Input Offset Voltage Drift
Input Bias Current
Open-Loop Gain
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
TMIN − TMAX
VOUT = 0 V to 3 V
87
VCM = 1.0 V to 2.5 V
−80
RL = 1 kΩ
0.16 to 4.83
30% overshoot, G = +1, VOUT = 400 mV p-p
4
1
50
92
−80
Rev. D | Page 4 of 24
2
3.5
2.5
30
10
Unit
mV
mV
mV
μV/°C
pA
pA
dB
1000||2.3
1000||1.7
GΩ||pF
GΩ||pF
0 to 2.0
−100
V
dB
0.04 to 4.95
30
25
V
mA
pF
5
VS = ±1 V
Max
3.3
−100
24
3.5
V
mA
dB
AD8033/AD8034
TA = 25°C, VS = ±12 V, RL = 1 kΩ, gain = +2, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Input Overdrive Recovery Time
Output Overdrive Recovery Time
Slew Rate (25% to 75%)
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Distortion
Second Harmonic
Third Harmonic
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Conditions
Min
Typ
G = +1, VOUT = 0.2 V p-p
G = +2, VOUT = 0.2 V p-p
G = +2, VOUT = 2 V p-p
−13 V to +13 V input
−6.5 V to +6.5 V input, G = +2
G = +2, VOUT = 4 V step
G = +2, VOUT = 2 V step
G = +2, VOUT = 10 V step
65
80
30
21
100
100
80
90
225
MHz
MHz
MHz
ns
ns
V/μs
ns
ns
−80
−82
−70
−82
−86
11
0.7
dBc
dBc
dBc
dBc
dB
nV/√Hz
fA/√Hz
55
fC = 1 MHz, VOUT = 2 V p-p
RL = 500 Ω
RL = 1 kΩ
RL = 500 Ω
RL = 1 kΩ
f = 1 MHz, G = +2
f = 100 kHz
f = 100 kHz
VCM = 0 V
TMIN − TMAX
1
Input Offset Voltage Match
Input Offset Voltage Drift
Input Bias Current
Open-Loop Gain
INPUT CHARACTERISTICS
Common-Mode Input Impedance
Differential Input Impedance
Input Common-Mode Voltage Range
FET Input Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Power Supply Rejection Ratio
TMIN − TMAX
VOUT = ±8 V
VCM = ±5 V
88
−92
±11.52
30% overshoot, G = +1
4
2
50
96
−85
Rev. D | Page 5 of 24
2
3.5
2.5
24
12
Unit
mV
mV
mV
μV/°C
pA
pA
dB
1000||2.3
1000||1.7
GΩ||pF
GΩ||pF
−12.0 to +9.0
−100
V
dB
±11.84
60
35
V
mA
pF
5
VS = ±2 V
Max
3.3
−100
24
3.5
V
mA
dB
AD8033/AD8034
ABSOLUTE MAXIMUM RATINGS
Rating
26.4 V
See Figure 5
26.4 V
1.4 V
−65°C to +125°C
−40°C to +85°C
300°C
PD = (VS × IS) + (VS/4)2/RL
In single-supply operation with RL referenced to VS−, worst case
is VOUT = VS/2.
2.0
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
1.5
SOT-23-8
1.0
SC70-5
0.5
0
–60
The maximum safe power dissipation in the AD8033/AD8034
packages is limited by the associated rise in junction temperature
(TJ) on the die. The plastic that encapsulates the die locally
reaches the junction temperature. At approximately 150°C,
which is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
can change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the AD8033/
AD8034. Exceeding a junction temperature of 175°C for an
extended period can result in changes in silicon devices, potentially
causing failure.
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as
TJ = TA + (PD × θJA)
PD is the sum of the quiescent power dissipation and the power
dissipated in the package due to the load drive for all outputs.
The quiescent power is the voltage between the supply pins (VS)
times the quiescent current (IS). Assuming the load (RL) is
referenced to midsupply, the total drive power is VS/2 × IOUT,
some of which is dissipated in the package and some in the load
(VOUT × IOUT). The difference between the total drive power and
the load power is the drive power dissipated in the package
SOIC-8
–40
–20
0
20
40
60
AMBIENT TEMPERATURE (°C)
80
100
02924-005
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
If the rms signal levels are indeterminate, consider the worst case,
when VOUT = VS/4 for RL to midsupply
MAXIMUM POWER DISSIPATION (W)
Table 4.
Figure 5. Maximum Power Dissipation vs.
Ambient Temperature for a 4-Layer Board
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. Care must be taken to minimize parasitic
capacitances at the input leads of high speed op amps as discussed
in the Layout, Grounding, and Bypassing Considerations section.
Figure 5 shows the maximum power dissipation in the package
vs. the ambient temperature for the 8-lead SOIC (125°C/W),
5-lead SC70 (210°C/W), and 8-lead SOT-23 (160°C/W) packages
on a JEDEC standard 4-layer board. θJA values are approximations.
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8033/AD8034 will likely cause catastrophic failure.
ESD CAUTION
PD = Quiescent Power + (Total Drive Power − Load Power)
PD = [VS × IS] + [(VS/2) × (VOUT/RL)] − [VOUT2/RL]
RMS output voltages should be considered. If RL is referenced
to −VS, as in single-supply operation, the total drive power is
VS × IOUT.
Rev. D | Page 6 of 24
AD8033/AD8034
TYPICAL PERFORMANCE CHARACTERISTICS
Default conditions: VS = ±5 V, CL = 5 pF, RL = 1 kΩ, TA = 25°C.
24
21
8
VOUT = 200mV p-p
G = +10
G = +2
7
18
12
5
GAIN (dB)
9
G = +2
6
VOUT = 1V p-p
4
3
3
G = +1
0
VOUT = 4V p-p
2
–3
G = –1
–9
0.1
1
1
100
10
FREQUENCY (MHz)
1000
VOUT = 2V p-p
0
0.1
02924-006
–6
1
10
FREQUENCY (MHz)
100
02924-009
GAIN (dB)
VOUT = 0.2V p-p
6
G = +5
15
Figure 9. Frequency Response for Various Output Amplitudes (See Figure 45)
Figure 6. Small Signal Frequency Response for Various Gains
8
1
VS = +5V
7
0
VS = ±5V
6
5
VS = ±12V
–2
GAIN (dB)
–3
–4
VS = ±12V
1
G = +1
VOUT = 200mV p-p
0.1
1
10
FREQUENCY (MHz)
100
0
1
10
FREQUENCY (MHz)
100
VS = ±12V
6
VS = ±12V
VS = ±5V
VS = +5V
5
GAIN (dB)
VS = ±5V
VS = +5V
–1
–2
–3
4
3
2
–4
1
–5
1
10
FREQUENCY (MHz)
100
G = +2
VOUT = 2V p-p
02924-008
GAIN (dB)
1
7
G = +1
VOUT = 2V p-p
0
–6
0.1
0.1
Figure 10. Small Signal Frequency Response for Various Supplies
(See Figure 45)
Figure 7. Small Signal Frequency Response for Various Supplies
(See Figure 44)
2
G = +2
VOUT = 200mV p-p
02924-010
–6
3
2
02924-007
–5
VS = ±5V
4
0
0.1
Figure 8. Large Signal Frequency Response for Various Supplies
(See Figure 44)
1
10
FREQUENCY (MHz)
100
Figure 11. Large Signal Frequency Response for Various Supplies
(See Figure 45)
Rev. D | Page 7 of 24
02924-011
GAIN (dB)
–1
VS = +5V
AD8033/AD8034
8
10
VOUT = 200mV p-p
G = +1
CL = 100pF
9
6
VOUT = 200mV p-p
G = +2
CL = 100pF
8
CL = 100pF
RSNUB = 25Ω
2
0
6
5
CL = 33pF
CL = 2pF
3
CL = 2pF
2
–4
1
100
10
0
0.1
02924-012
0.1
Figure 12. Small Signal Frequency Response for Various CL (See Figure 44)
8
CF = 0pF
7
CF = 1pF
100
VOUT = 200mV p-p
G = +2
RL = 1kΩ
7
6
6
5
GAIN (dB)
CF = 1.5pF
5
CF = 2pF
4
RL = 500Ω
4
3
3
2
2
1
10
FREQUENCY (MHz)
100
0
0.1
02924-013
0
0.1
Figure 13. Small Signal Frequency Response for Various CF (See Figure 45)
1
10
FREQUENCY (MHz)
100
Figure 16. Small Signal Frequency Response for Various RL (See Figure 45)
100
VOUT = 200mV p-p
VS = ±12V
180
150
80
10
1
G = +1
60
120
40
90
PHASE
20
60
0
30
PHASE (Degrees)
GAIN
G = +2
GAIN (dB)
IMPEDANCE (Ω)
02924-016
1
1
100
10
FREQUENCY (MHz)
Figure 15. Small Signal Frequency Response for Various CL (See Figure 45)
9
VOUT = 200mV p-p
RF = 3kΩ
8 G = +2
1
02924-015
1
FREQUENCY (MHz)
GAIN (dB)
CL = 33pF
4
–2
–6
CL = 51pF
7
GAIN (dB)
GAIN (dB)
4
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–20
100
02924-014
0.01
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 14. Output Impedance vs. Frequency (See Figure 47)
Figure 17. Open-Loop Response
Rev. D | Page 8 of 24
10M
0
100M
02924-017
0.1
AD8033/AD8034
–40
G = +2
HD3 RL = 500Ω
–50
–60
–60
–70
–70
–80
DISTORTION (dBc)
DISTORTION (dBc)
–50
HD3 RL = 1kΩ
–90
HD2 RL = 500Ω
–100
–110
HD3 G = +2
–90
HD2 G = +2
–100
–110
HD3 G = +1
HD2 RL = 1kΩ
1
FREQUENCY (MHz)
5
–120
0.1
02924-018
–120
0.1
–20
G = +2
HD3 VS = 5V
–50
HD3 VOUT = 10V p-p
–50
–70
DISTORTION (dBc)
DISTORTION (dBc)
G = +2
–40
HD2 V S = 5V
HD3 VS = 24V
–90
5
–30
–60
–80
1
FREQUENCY (MHz)
Figure 21. Harmonic Distortion vs. Frequency for Various Gains
Figure 18. Harmonic Distortion vs. Frequency for Various Loads
(See Figure 45)
–40
HD2 G = +1
–80
02924-021
–40
–100
HD2 VOUT = 20V p-p
HD3 V OUT = 20V p-p
–60
–70
HD2 V OUT = 10V p-p
–80
–90
HD3 VOUT = 2V p-p
–100
HD2 VS = 24V
–110
1
FREQUENCY (MHz)
5
02924-019
–120
0.1
HD2 V OUT = 2V p-p
–120
0.1
Figure 19. Harmonic Distortion vs. Frequency for Various Supply Voltages
(See Figure 45)
1
FREQUENCY (MHz)
Figure 22. Harmonic Distortion vs. Frequency for Various Amplitudes
(See Figure 45), VS = 24 V
1000
80
G = +1
VS = +5V POSITIVE SIDE
PERCENT OVERSHOOT (%)
70
100
60
VS = +5V NEGATIVE SIDE
50
40
VS = ±5V NEGATIVE SIDE
30
20
VS = ±5V POSITIVE SIDE
10
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
1
0M
10M
100M
Figure 20. Voltage Noise vs. Frequency
0
10
30
50
70
CAPACITIVE LOAD (pF)
90
110
Figure 23. Percent Overshoot vs. Capacitive Load (See Figure 44)
Rev. D | Page 9 of 24
02924-023
10
02924-020
NOISE (nV/√Hz)
5
02924-022
–110
AD8033/AD8034
G = +1
20ns/DIV
25mV/DIV
02924-024
38pF
15pF
80mV/DIV
Figure 24. Small Signal Transient Response 5 V (See Figure 44)
80ns/DIV
02924-027
G = +1
Figure 27. Small Signal Transient Response ±5 V (See Figure 44)
G = +1
VOUT = 8V p-p
VOUT = 8V p-p
VOUT = 2V p-p
VOUT = 2V p-p
3V/DIV
320ns/DIV
02924-025
VOUT = 20V p-p
320ns/DIV
3V/DIV
Figure 25. Large Signal Transient Response (See Figure 44)
02924-028
G = +2
VOUT = 20V p-p
Figure 28. Large Signal Transient Response (See Figure 45)
G = –1
G = +1
350ns/DIV
1.5V/DIV
Figure 26. Output Overdrive Recovery (See Figure 46)
VIN
350ns/DIV
Figure 29. Input Overdrive Recovery (See Figure 44)
Rev. D | Page 10 of 24
02924-029
1.5V/DIV
VOUT
VOUT
02924-026
VIN
AD8033/AD8034
VIN = 1V
VIN = 1V
VOUT – 2VIN
+0.1%
+0.1%
02924-030
1.5µs/DIV
2mV/DIV
Figure 33. 0.1% Short-Term Settling Time
7.0
0
6.9
QUIESCENT SUPPLY CURRENT (mA)
–5
–10
–Ib
–20
+Ib
–25
–30
–35
6.6
6.5
VS = ±5V
6.4
6.3
VS = +5V
6.2
6.1
30
35
40
45 50 55 60 65
TEMPERATURE (°C)
70
75
80
85
–20
0
20
40
TEMPERATURE (°C)
80
Figure 34. Quiescent Supply Current vs. Temperature for Various Supply
Voltages
4.0
BJT INPUT RANGE
3.5
30
18
NORMALIZED OFFSET (mV)
–Ib
24
+Ib
12
6
–Ib
VS = ±12V
3.0
2.5
2.0
1.5
1.0
0.5
VS = ±5V
VS = +5V
0
–0.5
0
2
4
6
8
COMMON-MODE VOLTAGE (V)
10
12
02924-032
0
FET INPUT RANGE
10
+Ib
5
0
–5
–10
–15
–20
–25
–30
–12 –10 –8 –6 –4 –2
60
02924-034
25
02924-031
20
5.9
–40
36
Ib (µA)
VS = ±12V
6.0
Figure 31. Ib vs. Temperature
Ib (pA)
6.8
6.7
Figure 32. Ib vs. Common-Mode Voltage Range
–1.0
–14 –12 –10 –8
–6 –4 –2 0
2
4
6
8
COMMON-MODE VOLTAGE (V)
10
12
14
Figure 35. Input Offset Voltage vs. Common-Mode Voltage
Rev. D | Page 11 of 24
02924-035
Ib (pA)
–15
42
–0.1%
20ns/DIV
2mV/DIV
Figure 30. Long-Term Settling Time
–40
VOUT – 2VIN
t=0
02924-033
–0.1%
t=0
AD8033/AD8034
105
–20
100
–30
OPEN-LOOP GAIN (dB)
95
CMRR (dB)
–40
–50
–60
90
RL = 500Ω
85
RL = 1kΩ
RL = 2kΩ
80
75
70
–70
1
10
FREQUENCY (MHz)
100
60
–12 –10
02924-036
–80
0.1
–4 –2
0
2
4
OUTPUT VOLTAGE (V)
6
8
10
12
–40
1.0
–50
0.8
SOT-23 A/B
VCC – VOH
CROSSTALK (dB)
0.6
0.4
VOL – VEE
0.2
–60
SOIC A/B
–70
SOT-23 B/A
SOIC B/A
–80
–90
5
10
15
20
25
30
ILOAD (mA)
–100
0.1
02924-037
0
1
FREQUENCY (MHz)
10
50
02924-040
OUTPUT SATURATION (V)
–6
Figure 39. Open-Loop Gain vs. Output Voltage for Various RL
Figure 36. CMRR vs. Frequency (See Figure 50)
0
–8
02924-039
65
Figure 40. Crosstalk (See Figure 52)
Figure 37. Output Saturation Voltage vs. Load Current
0
180
–10
150
–20
–30
FREQUENCY
PSRR (dB)
–PSRR
–40
–50
+PSRR
–60
120
90
60
–70
–80
30
0.001
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 38. PSRR vs. Frequency (See Figure 49 and Figure 51)
0
–1.5
–1.0
–0.5
0
0.5
VOS (mV)
Figure 41. Initial Offset
Rev. D | Page 12 of 24
1.0
1.5
02924-041
–100
0.0001
02924-038
–90
AD8033/AD8034
VOUT
1µs/DIV
1.2V/DIV
VIN
1µs/DIV
Figure 43. G = +2 Response, VS = ±5 V
Figure 42. G = +1 Response, VS = ±5 V
Rev. D | Page 13 of 24
02924-043
VIN
02924-042
1.2V/DIV
VOUT
AD8033/AD8034
TEST CIRCUITS
+VS
+VS
1µF
1µF
+
+
10nF
10nF
RSNUB
VIN
AD8033/AD8034
49.9Ω
976Ω
CLOAD
VOUT
AD8033/AD8034
49.9Ω
10nF
10nF
VSINE
0.2V p-p
02924-047
–VS
–
+
1µF
02924-044
+
1µF
+
–VS
Figure 47. Output Impedance, G = +1
Figure 44. G = +1
CF
1kΩ
1kΩ
RF
+VS
1kΩ
+VS
1µF
1µF
+
+
10nF
499Ω
VIN
49.9Ω
RSNUB
976Ω
AD8033/AD8034
CLOAD
10nF
VOUT
AD8033/AD8034
49.9Ω
10nF
10nF
VSINE
0.2V p-p
–VS
–VS
Figure 45. G = +2
1kΩ
Figure 48. Output Impedance, G = +2
1kΩ
+VS
1µF
+
10nF
976Ω
AD8033/AD8034
499Ω
VOUT
49.9Ω
10nF
+
1µF
–VS
02924-046
VIN
–
+
1µF
02924-045
+
1µF
+
Figure 46. G = −1
Rev. D | Page 14 of 24
02924-048
1kΩ
AD8033/AD8034
1V p-p
+VS
–
+
+VS AC
1µF
+
+VS
49.9Ω
10nF
AD8033/AD8034
VOUT
VOUT
AD8033/AD8034
10nF
02924-049
49.9Ω
–VS AC
+
1µF
02924-051
–VS
1V p-p
+
–
–VS
Figure 49. Negative PSRR
1kΩ
Figure 51. Positive PSRR
1kΩ
1kΩ
1kΩ
–VS
+VS
–
1µF
TO PORT 1 499Ω
+
50Ω
VIN
–
+
49.9Ω
10nF
976Ω
1kΩ
AD8033/AD8034
VOUT
499Ω
TO PORT 2
1kΩ
–VS
+VS
+
49.9Ω
10nF
+
1µF
1kΩ
–VS
A
–
+VS
02924-050
1kΩ
+ B
1kΩ
Figure 50. CMRR
Figure 52. Crosstalk
Rev. D | Page 15 of 24
1kΩ
02924-052
VIN
AD8033/AD8034
THEORY OF OPERATION
The incorporation of JFET devices into the Analog Devices
high voltage XFCB process has enabled the ability to design the
AD8033/AD8034. The AD8033/AD8034 are voltage feedback
rail-to-rail output amplifiers with FET inputs and a bipolarenhanced common-mode input range. The use of JFET devices in
high speed amplifiers extends the application space into both the
low input bias current and low distortion, high bandwidth areas.
Using N-channel JFETs and a folded cascade input topology,
the common-mode input level operates from 0.2 V below the
negative rail to within 3.0 V of the positive rail. Cascading of
the input stage ensures low input bias current over the entire
common-mode range as well as CMRR and PSRR specifications
that are above 90 dB. Additionally, long-term settling issues that
normally occur with high supply voltages are minimized as a
result of the cascading.
OUTPUT STAGE DRIVE AND CAPACITIVE LOAD
DRIVE
The common emitter output stage adds rail-to-rail output
performance and is compensated to drive 35 pF (30% overshoot
at G = +1). Additional capacitance can be driven if a small snub
resistor is put in series with the capacitive load, effectively
decoupling the load from the output stage, as shown in Figure 12.
The output stage can source and sink 20 mA of current within
500 mV of the supply rails and 1 mA within 100 mV of the
supply rails.
INPUT OVERDRIVE
An additional feature of the AD8033/AD8034 is a bipolar input
pair that adds rail-to-rail common-mode input performance
specifically for applications that cannot tolerate phase inversion
problems.
Under normal common-mode operation, the bipolar input
pair is kept reversed, maintaining Ib at less than 1 pA. When
the input common-mode operation comes within 3.0 V of the
positive supply rail, I1 turns off and I4 turns on, supplying tail
current to the bipolar pair Q25 and Q27. With this configuration,
the inputs can be driven beyond the positive supply rail without
any phase inversion (see Figure 53).
As a result of entering the bipolar mode of operation, an offset
and input bias current shift occurs (see Figure 32 and Figure 35).
After re-entering the JFET common-mode range, the amplifier
recovers in approximately 100 ns (refer to Figure 29 for input
overload behavior). Above and below the supply rails, ESD
protection diodes activate, resulting in an exponentially
increasing input bias current. If the inputs are driven well
beyond the rails, series input resistance should be included
to limit the input bias current to <10 mA.
INPUT IMPEDANCE
The input capacitance of the AD8033/AD8034 forms a pole
with the feedback network, resulting in peaking and ringing
in the overall response. The equivalent impedance of the
feedback network should be kept small enough to ensure that
the parasitic pole falls well beyond the −3 dB bandwidth of the
gain configuration being used. If larger impedance values are
desired, the amplifier can be compensated by placing a small
capacitor in parallel with the feedback resistor. Figure 13 shows
the improvement in frequency response by including a small
feedback capacitor with high feedback resistance values.
THERMAL CONSIDERATIONS
Because the AD8034 operates at up to ±12 V supplies in the
small 8-lead SOT-23 package (160°C/W), power dissipation can
easily exceed package limitations, resulting in permanent shifts
in device characteristics and even failure. Likewise, high supply
voltages can cause an increase in junction temperature even
with light loads, resulting in an input bias current and offset
drift penalty. The input bias current doubles for every 10°C
shown in Figure 31. Refer to the Maximum Power Dissipation
section for an estimation of die temperature based on load and
supply voltage.
Rev. D | Page 16 of 24
AD8033/AD8034
+VS
I2
R2
R3
V2
+
–
Q4
+
–
Q1
Q13
Q7
Q6
VTH
V4
Q14
R14
J1
D4
Q25
J2
Q27
VCC
+IN
–IN
D5
VOUT
Q11
Q9
Q29
R7
I4
I3
R8
02924-053
I1
Q28
–VS
Figure 53. Simplified AD8033/AD8034 Input Stage
Rev. D | Page 17 of 24
AD8033/AD8034
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
BYPASSING
LEAKAGE CURRENTS
Power supply pins are actually inputs, and care must be taken
so that a noise-free stable dc voltage is applied. The purpose of
bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering a
majority of the noise. Decoupling schemes are designed to
minimize the bypassing impedance at all frequencies with a
parallel combination of capacitors. The chip capacitors, 0.01 μF
or 0.001 μF (X7R or NPO), are critical and should be placed as
close as possible to the amplifier package. Larger chip capacitors,
such as the 0.1 μF capacitor, can be shared among a few closely
spaced active components in the same signal path. The 10 μF
tantalum capacitor is less critical for high frequency bypassing, and
in most cases, only one per board is needed at the supply inputs.
Poor PCB layout, contaminants, and the board insulator material
can create leakage currents that are much larger than the input
bias currents of the AD8033/AD8034. Any voltage differential
between the inputs and nearby runs set up leakage currents
through the PCB insulator, for example, 1 V/100 GΩ = 10 pA.
Similarly, any contaminants on the board can create significant
leakage (skin oils are a common problem). To significantly reduce
leakages, put a guard ring (shield) around the inputs and input
leads that is driven to the same voltage potential as the inputs.
This way there is no voltage potential between the inputs and
surrounding area to set up any leakage currents. For the guard
ring to be completely effective, it must be driven by a relatively
low impedance source and should completely surround the input
leads on all sides, above, and below using a multilayer board.
GROUNDING
A ground plane layer is important in densely packed PCBs to
spread the current, thereby minimizing parasitic inductances.
However, an understanding of where the current flows in a
circuit is critical to implementing effective high speed circuit
design. The length of the current path is directly proportional
to the magnitude of the parasitic inductances and, thus, the
high frequency impedance of the path. High speed currents
in an inductive ground return create unwanted voltage noise.
The length of the high frequency bypass capacitor leads is most
critical. A parasitic inductance in the bypass grounding works
against the low impedance created by the bypass capacitor.
Place the ground leads of the bypass capacitors at the same
physical location.
Because load currents flow from the supplies as well, the ground
for the load impedance should be at the same physical location
as the bypass capacitor grounds. For the larger value capacitors
that are intended to be effective at lower frequencies, the current
return path distance is less critical.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the amount
of material between the input leads and the guard ring helps to
reduce the absorption. In addition, low absorption materials
such as Teflon® or ceramic may be necessary in some instances.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and
ground. A few pF of capacitance reduces the input impedance at
high frequencies, in turn it increases the gain of the amplifier
and can cause peaking of the overall frequency response or even
oscillations if severe enough. It is recommended that the external
passive components that are connected to the input pins be placed
as close as possible to the inputs to avoid parasitic capacitance.
The ground and power planes must be kept at a distance of at
least 0.05 mm from the input pins on all layers of the board.
Rev. D | Page 18 of 24
AD8033/AD8034
APPLICATIONS INFORMATION
Using two amplifiers, the difference between the peak and the
current input level is forced across R2 instead of either amplifier’s
input pins. In the event of a rising pulse, the first amplifier
compensates for the drop across D2 and D3, forcing the voltage
at Node 3 equal to Node 1. D1 is off and the voltage drop across
R2 is zero. Capacitor C3 speeds up the loop by providing the
charge required by the input capacitance of the first amplifier,
helping to maintain a minimal voltage drop across R2 in the
sampling mode. A negative going edge results in D2 and D3
turning off and D1 turning on, closing the loop around the
first amplifier and forcing VOUT − VIN across R2. R4 makes
the voltage across D2 zero, minimizing leakage current and
kickback from D3 from affecting the voltage across C2.
HIGH SPEED PEAK DETECTOR
The low input bias current and high bandwidth of the AD8033/
AD8034 make the parts ideal for a fast settling, low leakage peak
detector. The classic fast-low leakage topology with a diode in
the output is limited to ~1.4 V p-p maximum in the case of the
AD8033/AD8034 because of the protection diodes across the
inputs, as shown in Figure 54.
AD8033/
AD8034
VOUT
VIN
02924-054
~1.4V p-p MAX
The rate of the incoming edge must be limited so that the output
of the first amplifier does not overshoot the peak value of VIN
before the output of the second amplifier can provide negative
feedback at the summing junction of the first amplifier. This
is accomplished with the combination of R1 and C1, which
allows the voltage at Node 1 to settle to 0.1% of VIN in 270 ns.
The selection of C2 and R3 is made by considering droop
rate, settling time, and kickback. R3 prevents overshoot from
occurring at Node 3. The time constants of R1, C1 and R3, C2
are roughly equal to achieve the best performance. Slower time
constants can be selected by increasing C2 to minimize droop
rate and kickback at the cost of increased settling time. R1 and
C1 should also be increased to match, reducing the incoming
pulse’s effect on kickback.
Figure 54. High Speed Peak Detector with Limited Input Range
Using the AD8033/AD8034, a unity gain peak detector can
be constructed that captures a 300 ns pulse while still taking
advantage of the low input bias current and wide commonmode input range of the AD8033/AD8034, as shown in Figure 55.
C3
10pF
R2
1kΩ
D1
LS4148
C4
4.7pF
R4
6kΩ
+VS
+VS
1/2
R1
1kΩ
R5
49.9Ω
AD8034
D3
D2
LS4148
LS4148
AD8034
C1
39pF/
120pF
–VS
VOUT
–VS
C2
180pF/
560pF
R3
200Ω
02924-056
VIN
1/2
Figure 55. High Speed, Unity Gain Peak Detector Using AD8034
Rev. D | Page 19 of 24
AD8033/AD8034
The Sallen-Key topology is the least dependent on the active
device, requiring that the bandwidth be flat to beyond the stopband frequency because it is used simply as a gain block. In the
case of high Q filter stages, the peaking must not exceed the openloop bandwidth and the linear input range of the amplifier.
INPUT
OUTPUT
Using an AD8033/AD8034, a 4-pole cascaded Sallen-Key filter
can be constructed with fC = 1 MHz and over 80 dB of stop-band
attenuation, as shown in Figure 58.
2
02924-055
C3
33pF
R1
4.22kΩ
VIN
Figure 56. Peak Detector Response 4 V, 300 ns Pulse
Figure 56 shows the peak detector in Figure 55 capturing a
300 ns, 4 V pulse with 10 mV of kickback and a droop rate of
5 V/s. For larger peak-to-peak pulses, increase the time constants
of R1, C1 and R3, C3 to reduce overshoot. The best droop rate
occurs by isolating parasitic resistances from Node 3, which can
be accomplished using a guard band connected to the output of the
second amplifier that surrounds its summing junction (Node 3).
Increasing both time constants by a factor of 3 permits a larger
peak pulse to be captured and increases the output accuracy.
R2
6.49kΩ
R5
49.9Ω
AD8034
–VS
C1
27pF
C4
82pF
R4
4.99kΩ
+VS
1/2
R3
4.99kΩ
AD8034
–VS
C2
10pF
INPUT
VOUT
02924-058
1V/DIV 100ns/DIV
+VS
1/2
Figure 58. 4-Pole Cascade Sallen-Key Filter
Component values are selected using a normalized cascaded,
2-stage Butterworth filter table and Sallen-Key 2-pole active
filter equations. The overall frequency response is shown in
Figure 59.
OUTPUT
0
–10
2
02924-057
–20
1V/DIV 200ns/DIV
Figure 57. Peak Detector Response 5 V, 1 μs Pulse
Figure 57 shows a 5 V peak pulse being captured in 1 μs with
less than 1 mV of kickback. With this selection of time constants,
up to a 20 V peak pulse can be captured with no overshoot.
REF LEVEL (dB)
–30
–40
–50
–60
–70
–80
ACTIVE FILTERS
–90
–100
10k
Rev. D | Page 20 of 24
100k
1M
10M
FREQUENCY (Hz)
Figure 59. 4-Pole Cascade Sallen-Key Filter Response
02924-059
The response of an active filter varies greatly depending on the
performance of the active device. Open-loop bandwidth and
gain, along with the order of the filter, determines the stop-band
attenuation as well as the maximum cutoff frequency, while
input capacitance can set a limit on which passive components
are used. Topologies for active filters are varied, and some are
more dependent on the performance of the active device than
others are.
AD8033/AD8034
Filter cutoff frequencies can be increased beyond 1 MHz using the
AD8033/AD8034 but limited open-loop gain and input impedance
begin to interfere with the higher Q stages. This can cause early
roll-off of the overall response.
Additionally, the stop-band attenuation decreases with decreasing
open-loop gain.
Keeping these limitations in mind, a 2-pole Sallen-Key Butterworth
filter with fC = 4 MHz can be constructed that has a relatively
low Q of 0.707 while still maintaining 15 dB of attenuation an
octave above fC and 35 dB of stop-band attenuation. The filter
and response are shown in Figure 60 and Figure 61, respectively.
C3
22pF
R2
2.49kΩ
AD8033
VOUT =
I PHOTO × R F
1 + sC F R F
where IPHOTO is the output current of the photodiode, and the
parallel combination of RF and CF sets the signal bandwidth.
CF
RF
IPHOTO
CD
CM
CS
VOUT
–VS
C1
10pF
R5
49.9Ω
The basic transfer function is
RSH = 1011Ω
+VS
R1
2.49kΩ
Figure 62 shows an I/V converter with an electrical model of a
photodiode.
CM
02924-060
VIN
WIDEBAND PHOTODIODE PREAMP
VB
Figure 60. 2-Pole Butterworth Active Filter
CF + CS
VOUT
RF
02924-062
When selecting components, the common-mode input capacitance
must be taken into consideration.
Figure 62. Wideband Photodiode Preamp
5
The stable bandwidth attainable with this preamp is a function
of RF, the gain bandwidth product of the amplifier, and the total
capacitance at the summing junction of the amplifier, including
CS and the amplifier input capacitance. RF and the total capacitance
produce a pole in the loop transmission of the amplifier that
can result in peaking and instability. Adding CF creates a zero
in the loop transmission that compensates for the effect of the
pole and reduces the signal bandwidth. It can be shown that the
signal bandwidth resulting in a 45°phase margin (f(45)) is defined
by the expression
0
–5
–15
–20
–25
–30
–35
f ( 45) =
–40
–45
100k
1M
10M
FREQUENCY (Hz)
Figure 61. 2-Pole Butterworth Active Filter Response
100M
02924-061
GAIN (dB)
–10
f CR
2π × R F × C S
where:
fCR is the amplifier crossover frequency.
RF is the feedback resistor.
CS is the total capacitance at the amplifier summing junction
(amplifier + photodiode + board parasitics).
The value of CF that produces f(45) is
CF =
CS
2π × R F × f CR
The frequency response in this case shows about 2 dB of
peaking and 15% overshoot. Doubling CF and cutting the
bandwidth in half results in a flat frequency response, with
about 5% transient overshoot.
Rev. D | Page 21 of 24
AD8033/AD8034
Keeping the input terminal impedances matched is recommended
to eliminate common-mode noise peaking effects that add to
the output noise.
Integrating the square of the output voltage noise spectral density
over frequency and then taking the square root results in the
total rms output noise of the preamp.
f1 =
1
2πR F (CF + CS + CM + 2CD)
f2 =
1
2πRF CF
f
f3 = (C + C + CR
S
M 2CD + CF)/CF
RF NOISE
f2
VEN (CF + CS + CM + 2CD)/CF
f3
f1
VEN
NOISE DUE TO AMPLIFIER
FREQUENCY (Hz)
Figure 63. Photodiode Voltage Noise Contributions
Rev. D | Page 22 of 24
02924-063
The pole in the loop transmission translates to a zero in the
noise gain of the amplifier, leading to an amplification of the
input voltage noise over frequency. The loop transmission zero
introduced by CF limits the amplification. The bandwidth of the
noise gain extends past the preamp signal bandwidth and is
eventually rolled off by the decreasing loop gain of the amplifier.
VOLTAGE NOISE (nV/√Hz)
The output noise over frequency of the preamp is shown in
Figure 63.
AD8033/AD8034
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 64. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
2.20
2.00
1.80
1.35
1.25
1.15
5
4
1
2
3
PIN 1
2.40
2.10
1.80
0.65 BSC
1.00
0.90
0.70
1.10
0.80
0.30
0.15
0.10 MAX
0.40
0.10
0.46
0.36
0.26
0.22
0.08
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AA
Figure 65. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
2.90 BSC
8
7
6
5
1
2
3
4
1.60 BSC
2.80 BSC
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.45 MAX
0.15 MAX
0.38
0.22
0.22
0.08
SEATING
PLANE
8°
4°
0°
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 66. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
Rev. D | Page 23 of 24
0.60
0.45
0.30
AD8033/AD8034
ORDERING GUIDE
Model
AD8033AR
AD8033AR-REEL
AD8033AR-REEL7
AD8033ARZ 1
AD8033ARZ-REEL1
AD8033ARZ-REEL71
AD8033AKS-R2
AD8033AKS-REEL
AD8033AKS-REEL7
AD8033AKSZ-R21
AD8033AKSZ-REEL1
AD8033AKSZ-REEL71
AD8034AR
AD8034AR-REEL7
AD8034AR-REEL
AD8034ARZ1
AD8034ARZ-REEL1
AD8034ARZ-REEL71
AD8034ART-R2
AD8034ART-REEL
AD8034ART-REEL7
AD8034ARTZ-R21
AD8034ARTZ-REEL1
AD8034ARTZ-REEL71
AD8034CHIPS
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
5-Lead SC70
5-Lead SC70
5-Lead SC70
5-Lead SC70
5-Lead SC70
5-Lead SC70
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
DIE
Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.
©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02924-0-9/08(D)
Rev. D | Page 24 of 24
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
KS-5
KS-5
KS-5
KS-5
KS-5
KS-5
R-8
R-8
R-8
R-8
R-8
R-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
Branding
H3B
H3B
H3B
H3C
H3C
H3C
HZA
HZA
HZA
HZA#
HZA#
HZA#