www.fairchildsemi.com FSDL0365RN, FSDM0365RN Green Mode Fairchild Power Switch (FPSTM) Features • Internal Avalanche Rugged Sense FET • Consumes only 0.65W at 240VAC & 0.3W load with Advanced Burst-Mode Operation • Frequency Modulation for EMI Reduction • Precision Fixed Operating Frequency • Internal Start-up Circuit • Pulse-by-Pulse Current Limiting • Abnormal Over Current Protection (AOCP) • Over Voltage Protection (OVP) • Over Load Protection (OLP) • Internal Thermal Shutdown Function (TSD) • Auto-Restart Mode • Under Voltage Lockout (UVLO) • Low Operating Current (3mA) • Adjustable Peak Current Limit • Built-in Soft Start Applications • SMPS for VCR, SVR, STB, DVD & DVCD Player • SMPS for Printer, Facsimile & Scanner • Adapter for Camcorder Related Application Notes • AN-4137, 4141, 4147(Flyback) / AN-4134(Forward) Description Each product in the FSDx0365RN (x for L, M) family consists of an integrated Pulse Width Modulator (PWM) and Sense FET, and is specifically designed for high performance off-line Switch Mode Power Supplies (SMPS) with minimal external components. Both devices are integrated high voltage power switching regulators which combine an avalanche rugged Sense FET with a current mode PWM control block. The integrated PWM controller features include: a fixed oscillator with frequency modulation for reduced EMI, Under Voltage Lock Out (UVLO) protection, Leading Edge Blanking (LEB), an optimized gate turn-on/turn-off driver, Thermal Shut Down (TSD) protection, Abnormal Over Current Protection (AOCP) and temperature compensated precision current sources for loop compensation and fault protection circuitry. When compared to a discrete MOSFET and controller or RCC switching converter solution, the FSDx0365RN devices reduce total component count, design size, weight while increasing efficiency, productivity and system reliability. Both devices provide a basic platform that is well suited for the design of costFPSTM is a trademark of Fairchild Semiconductor Corporation. ©2005 Fairchild Semiconductor Corporation effective flyback converters. OUTPUT POWER TABLE 230VAC ±15%(3) 85-265VAC PRODUCT Adapter(1) Open Frame(2) Adapter(1) Open Frame(2) FSDL321 11W 17W 8W 12W FSDH321 11W 17W 8W 12W FSDL0165RN 13W 23W 11W 17W FSDM0265RN 16W 27W 13W 20W FSDH0265RN 16W 27W 13W 20W FSDL0365RN 19W 30W 16W 24W FSDM0365RN 19W 30W 16W 24W FSDL321L 11W 17W 8W 12W FSDH321L 11W 17W 8W 12W FSDL0165RL 13W 23W 11W 17W FSDM0265RL 16W 27W 13W 20W FSDH0265RL 16W 27W 13W 20W FSDL0365RL 19W 30W 16W 24W FSDM0365RL 19W 30W 16W 24W Notes: 1. Typical continuous power in a non-ventilated enclosed adapter with sufficient drain pattern as a heat sinker, at 50°C ambient. 2. Maximum practical continuous power in an open frame design with sufficient drain pattern as a heat sinker, at 50°C ambient. 3. 230 VAC or 100/115 VAC with doubler. Typical Circuit AC IN DC OUT Vstr Ipk Drain PWM Vfb Vcc Source Rev.1.0.8 FSDL0365RN, FSDM0365RN Figure 1. Typical Flyback Application Internal Block Diagram Vstr 5 Vcc 2 ICH + V BURH - 8V/12V Vcc good Vcc V BURL /V BURH IBUR(pk) Vcc Drain 6,7,8 Internal Bias Vref Freq. Modulation Vcc OSC IDELAY Vfb I FB Normal 3 2.5R Ipk 4 Soft Start PWM Burst S Q R Q Gate driver R LEB V SD 1 GND Vcc S Q R Q Vovp Vcc good AOCP Vocp TSD Figure 2. Functional Block Diagram of FSDx0365RN 2 FSDL0365RN, FSDM0365RN Pin Definitions Pin Number Pin Name 1 GND Sense FET source terminal on primary side and internal control ground. Vcc Positive supply voltage input. Although connected to an auxiliary transformer winding, current is supplied from pin 5 (Vstr) via an internal switch during startup (see Internal Block Diagram section). It is not until Vcc reaches the UVLO upper threshold (12V) that the internal start-up switch opens and device power is supplied via the auxiliary transformer winding. Vfb The feedback voltage pin is the non-inverting input to the PWM comparator. It has a 0.9mA current source connected internally while a capacitor and optocoupler are typically connected externally. A feedback voltage of 6V triggers over load protection (OLP). There is a time delay while charging external capacitor Cfb from 3V to 6V using an internal 5uA current source. This time delay prevents false triggering under transient conditions, but still allows the protection mechanism to operate under true overload conditions. Ipk This pin adjusts the peak current limit of the Sense FET. The feedback 0.9mA current source is diverted to the parallel combination of an internal 2.8kΩ resistor and any external resistor to GND on this pin to determine the peak current limit. If this pin is tied to Vcc or left floating, the typical peak current limit will be 2.15A. Vstr This pin connects directly to the rectified AC line voltage source. At start up the internal switch supplies internal bias and charges an external storage capacitor placed between the Vcc pin and ground. Once the Vcc reaches 12V, the internal switch is opened. Drain The drain pins are designed to connect directly to the primary lead of the transformer and are capable of switching a maximum of 650V. Minimizing the length of the trace connecting these pins to the transformer will decrease leakage inductance. 2 3 4 5 6, 7, 8 Pin Function Description Pin Configuration 8DIP 8LSOP GND 1 8 Drain Vcc 2 7 Drain Vfb 3 6 Drain Ipk 4 5 Vstr Figure 3. Pin Configuration (Top View) 3 FSDL0365RN, FSDM0365RN Absolute Maximum Ratings (Ta=25°C, unless otherwise specified) Characteristic Symbol Value Unit Drain Pin Voltage VDRAIN 650 V VSTR 650 V IDM 12.0 A Vstr Pin Voltage Drain Current Pulsed (1) (2) EAS 127 mJ Supply Voltage VCC 20 V Feedback Voltage Range VFB -0.3 to VCC V Total Power Dissipation PD 1.56 W Operating Junction Temperature TJ Internally limited °C TA -25 to +85 °C TSTG -55 to +150 °C Single Pulsed Avalanche Energy Operating Ambient Temperature Storage Temperature Note: 1. Repetitive rating: Pulse width is limited by maximum junction temperature 2. L = 51mH, starting Tj = 25°C Thermal Impedance (Ta=25°C, unless otherwise specified) Parameter Symbol Value Unit θJA θJC ψJT 80.01 °C/W 18.85 °C/W 33.70 °C/W 8DIP Junction-to-Ambient Thermal(1) Junction-to-Case Thermal (2) (3) Junction-to-Top Thermal Note: 1. Free standing with no heatsink; Without copper clad. / Measurement Condition : Just before junction temperature TJ enters into OTP. 2. Measured on the DRAIN pin close to plastic interface. 3. Measured on the PKG top surface. - all items are tested with the standards JESD 51-2 and 51-10 (DIP). 4 FSDL0365RN, FSDM0365RN Electrical Characteristics (Ta = 25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit VDS=650V, VGS=0V - - 50 µA VDS=520V, VGS=0V, TC=125°C - - 200 µA - 3.6 315 4.5 - Ω pF - 47 - pF - 9 - - 11.2 - pF ns - 34 - ns - 28.2 32 - ns ns SENSE FET SECTION Zero-Gate-Voltage Drain Current Drain-Source On-State Resistance(1) IDSS RDS(ON) Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Turn-On Delay Time Rise Time td(on) tr Turn-Off Delay Time td(off) Fall Time VGS=10V, ID=0.5A VGS=0V, VDS=25V, f=1MHz VDS=325V, ID=1.0A tf CONTROL SECTION Switching Frequency fOSC Switching Frequency Modulation Switching Frequency ∆fMOD fOSC Switching Frequency Modulation ∆fMOD Switching Frequency Variation(2) ∆fOSC Maximum Duty Cycle DMAX Minimum Duty Cycle DMIN UVLO Threshold Voltage VSTART VSTOP Feedback Source Current IFB Internal Soft Start Time tS/S 61 67 73 KHz ±1.5 45 ±2.0 50 ±2.5 55 KHz KHz ±1.0 - ±1.5 ±5 ±2.0 ±10 KHz % 71 0 77 0 83 0 % % VFB=GND VFB=GND 11 7 12 8 13 9 V V VFB=GND VFB=4V 0.7 10 0.9 15 1.1 20 mA ms FSDM0365R FSDL0365R -25°C ≤ Ta ≤ 85°C BURST MODE SECTION Burst Mode Voltage VBURH - 0.4 0.5 0.6 V VBURL - 0.25 0.35 0.45 V Max. inductor current 1.89 2.15 2.41 A - 500 - ns - 125 5.5 140 6.0 6.5 °C V 18 3.5 19 5.0 6.5 V µA 200 - - ns PROTECTION SECTION Peak Current Limit Current Limit Delay Time ILIM (3) tCLD Thermal Shutdown Temperature TSD Shutdown Feedback Voltage VSD Over Voltage Protection VOVP Shutdown Delay Current IDELAY Leading Edge Blanking Time VFB=4V tLEB TOTAL DEVICE SECTION Operating Supply Current (control part only) Start-Up Charging Current Vstr Supply Voltage IOP ICH VCC=14V VCC=0V 1 0.7 3 0.85 5 1.0 mA mA VSTR VCC=0V 35 - - V Note: 1. Pulse test: Pulse width ≤ 300us, duty ≤ 2% 2. These parameters, although guaranteed, are tested in EDS (wafer test) process 3. These parameters, although guaranteed, are not 100% tested in production 5 FSDL0365RN, FSDM0365RN Comparison Between KA5x0365RN and FSDx0365RN Function 6 KA5x0365RN FSDx0365RN FSDx0365RN Advantages Soft-Start not applicable 15ms • Gradually increasing current limit during soft-start further reduces peak current and voltage stresses • Eliminates external components used for soft-start in most applications • Reduces or eliminates output overshoot External Current Limit not applicable Programmable of default current limit • Smaller transformer • Allows power limiting (constant overload power) • Allows use of larger device for lower losses and higher efficiency. Frequency Modulation not applicable ±2.0KHz @67KHz ±1.5KHz @50KHz • Reduces conducted EMI Burst Mode Operation not applicable Built into controller • Improves light load efficiency • Reduces power consumption at noload • Transformer audible noise reduction Drain Creepage at Package 1.02mm 7.62mm • Greater immunity to arcing provoked by dust, debris and other contaminants FSDL0365RN, FSDM0365RN Typical Performance Characteristics (Control Part) 1.20 1.20 1.00 1.00 0.80 Normalized Normalized (These characteristic graphs are normalized at Ta = 25°C) 0.60 0.40 0.20 0.80 0.60 0.40 0.20 0.00 0.00 -50 0 50 100 -50 150 0 150 Frequency Modulation (∆FMOD) vs. Ta Operating Frequency (Fosc) vs. Ta 1.20 1.20 1.00 1.00 0.80 0.80 Normalized Normalized 100 T emp[℃] T emp[ ℃] 0.60 0.40 0.20 0.60 0.40 0.20 0.00 0.00 -50 0 50 100 150 -50 0 T emp[℃] 50 100 150 T emp[ ℃] Operating Supply Current (IOP) vs. Ta Maximum Duty Cycle (DMAX) vs. Ta 1.20 1.20 1.00 1.00 0.80 0.80 Normalized Normalized 50 0.60 0.40 0.60 0.40 0.20 0.20 0.00 0.00 -50 0 50 100 T emp[℃] Start Threshold Voltage (VSTART) vs. Ta 150 -50 0 50 100 150 T emp[℃] Stop Threshold Voltage (VSTOP) vs. Ta 7 FSDL0365RN, FSDM0365RN 1.20 1.20 1.00 1.00 0.80 Normalized Normalized Typical Performance Characteristics (Continued) 0.60 0.40 0.20 0.80 0.60 0.40 0.20 0.00 0.00 -50 0 50 100 150 -50 0 T emp[℃] 1.20 1.20 1.00 1.00 0.80 0.80 Normalized Normalized 150 Start Up Charging Current (ICH) vs. Ta 0.60 0.40 0.20 0.60 0.40 0.20 0.00 0.00 -50 0 50 100 150 T emp[℃] 1.00 0.80 0.60 0.40 0.20 0.00 0 50 0 50 100 Burst Peak Current (IBUR(pk)) vs. Ta 1.20 -50 -50 T emp[ ℃] Peak Current Limit (ILIM) vs. Ta Normalized 100 T emp[℃] Feedback Source Current (IFB) vs. Ta 100 T emp[℃] Over Voltage Protection (VOVP) vs. Ta 8 50 150 150 FSDL0365RN, FSDM0365RN Functional Description 1. Startup : In previous generations of Fairchild Power Switches (FPSTM) the Vstr pin had an external resistor to the DC input voltage line. In this generation the startup resistor is replaced by an internal high voltage current source and a switch that shuts off when 15ms goes by after the supply voltage, Vcc, gets above 12V. The source turns back on if Vcc drops below 8V. 3. Leading Edge Blanking (LEB) : At the instant the internal Sense FET is turned on, the primary side capacitance and secondary side rectifier diode reverse recovery typically cause a high current spike through the Sense FET. Excessive voltage across the Rsense resistor leads to incorrect feedback operation in the current mode PWM control. To counter this effect, the FPS employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (tLEB) after the Sense FET is turned on. Vin,dc ISTR Vstr Vcc Vcc<8V UVLO on J-FET ICH 15ms after Vcc≥12V UVLO off Figure 4. High Voltage Current Source 2. Feedback Control : The FSDx0365RN employs current mode control, as shown in Figure 5. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. When the KA431 reference pin voltage exceeds the internal reference voltage of 2.5V, the optocoupler LED current increases, the feedback voltage Vfb is pulled down and it reduces the duty cycle. This event typically happens when the input voltage is increased or the output load is decreased. Vcc Vcc 5uA Vo 0.9mA Vfb 3 CFB OSC + VFB - D1 D2 2.5R VFB,in Gate driver R 431 VSD OLP 4. Protection Circuits : The FPS has several protective functions such as over load protection (OLP), over voltage protection (OVP), abnormal over current protection (AOCP), under voltage lock out (UVLO) and thermal shutdown (TSD). Because these protection circuits are fully integrated inside the IC without external components, the reliability is improved without increasing cost. Once a fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage VSTOP (8V), the protection is reset and the internal high voltage current source charges the Vcc capacitor via the Vstr pin. When Vcc reaches the UVLO start voltage VSTART (12V), the FPS resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated. 4.1 Over Load Protection (OLP) : Overload is defined as the load current exceeding a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated in order to protect the SMPS. However, even when the SMPS is operating normally, the over load protection (OLP) circuit can be activated during the load transition. In order to avoid this undesired operation, the OLP circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload situation. In conjunction with the Ipk current limit pin (if used) the current mode feedback path would limit the current in the Sense FET when the maximum PWM duty cycle is attained. If the output consumes more than this maximum power, the output voltage (Vo) decreases below its rating voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (VFB). If VFB exceeds 3V, the feedback input diode is blocked and the 5uA current source (IDELAY) starts to charge Cfb slowly up to Vcc. In this condition, VFB increases until it reaches 6V, when the switching operation is terminated as shown in Figure 6. The shutdown delay time is the time required to charge Cfb from 3V to 6V with 5uA current source. Figure 5. Pulse Width Modulation (PWM) Circuit 9 FSDL0365RN, FSDM0365RN PWM COMPARATOR VFB VFB,in Over Load Protection 6V LEB CLK Drain Gate Driver Vsense AOCP COMPARATOR S Q R 3V VAOCP t12= CFB×(V(t2)-V(t1)) / IDELAY t1 t12 = C FB t2 Rsense t V (t 2 ) − V (t1 ) ; I DELAY = 5 µA, V (t1 ) = 3V , V (t 2 ) = 6V I DELAY Figure 7. Abnormal Over Current Protection (AOCP) Figure 6. Over Load Protection (OLP) 4.2 Thermal Shutdown (TSD) : The Sense FET and the control IC are integrated, making it easier for the control IC to detect the temperature of the Sense FET. When the temperature exceeds approximately 140°C, thermal shutdown is activated. 4.3 Abnormal Over Current Protection (AOCP) : Even though the FPS has OLP (Over Load Protection) and current mode PWM feedback, these are not enough to protect the FPS when a secondary side diode short or a transformer pin short occurs. In addition to start-up, soft-start is also activated at each restart attempt during auto-restart and when restarting after latch mode is activated. The FPS has an internal AOCP (Abnormal Over Current Protection) circuit, as shown in Figure 7. When the gate turn-on signal is applied to the power Sense FET, the AOCP block is enabled and monitors the current through the sensing resistor. The voltage across the resistor is then compared with a preset AOCP level. If the sensing resistor voltage is greater than the AOCP level, pulse-by-pulse AOCP is triggered regardless of uncontrollable LEB time. Here, pulse-by-pulse AOCP stops the Sense FET within 350ns after it is activated. 10 4.4 Over Voltage Protection (OVP) : In the event of a malfunction in the secondary side feedback circuit, or an open feedback loop caused by a soldering defect, the current through the opto-coupler transistor becomes almost zero (refer to Figure 5). Then, VFB climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the SMPS until the over load protection is activated. Because excess energy is provided to the output, the output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over voltage protection (OVP) circuit is employed. In general, Vcc is proportional to the output voltage and the FPS uses Vcc instead of directly monitoring the output voltage. If VCC exceeds 19V, OVP circuit is activated resulting in termination of the switching operation. In order to avoid undesired activation of OVP during normal operation, Vcc should be properly designed to be below 19V. FSDL0365RN, FSDM0365RN 5. Soft Start : The FPS has an internal soft start circuit that slowly increases the feedback voltage together with the Sense FET current after it starts up. The typical soft start time is 15msec, as shown in Figure 8, where progressive increments of the Sense FET current are allowed during the start-up phase. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce the stress on the secondary diode. Burst Operation Burst Operation Normal Operation VFB VBURH VBURL Current Waveform Switching OFF Switching OFF + VBURH - Drain current Vcc VBURL/VBURH 2.15A IBUR(pk) 1ms Vcc 15steps Vfb Current limit Vcc IFB IDELAY 3 0.98A Normal 2.5R PWM Burst R MOSFET Current t Figure 8. Soft Start Function Figure 9. Burst Operation Function 6. Burst Operation : In order to minimize power dissipation in standby mode, the FPS enters burst mode operation. As the load decreases, the feedback voltage decreases. As shown in Figure 9, the device automatically enters burst mode when the feedback voltage drops below VBURH(500mV). Switching still continues but the current limit is set to a fixed limit internally to minimize flux density in the transformer. The fixed current limit is larger than that defined by VFB = VBURH and therefore, VFB is driven down further. Switching continues until the feedback voltage drops below VBURL(350mV). At this point switching stops and the output voltages start to drop at a rate dependent on the standby current load. This causes the feedback voltage to rise. Once it passes VBURH(500mV), switching resumes. The feedback voltage then falls and the process repeats. Burst mode operation alternately enables and disables switching of the power Sense FET thereby reducing switching loss in Standby mode. 7. Frequency Modulation : Modulating the switching frequency of a switched power supply can reduce EMI. Frequency modulation can reduce EMI by spreading the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. The amount of EMI reduction is directly related to the depth of the reference frequency. As can be seen in Figure 10, the frequency changes from 65KHz to 69KHz in 4ms for the FSDM0365RN (48.5KHz to 51.5KHz for FSDL0365RN). Frequency modulation allows the use of a cost effective inductor instead of an AC input mode choke to satisfy the requirements of world wide EMI limits. Drain Current ts fs=1/ts 69kHz 67kHz 65kHz 4ms t Figure 10. Frequency Modulation Waveform 11 FSDL0365RN, FSDM0365RN Amplitude (dBµV) 8. Adjusting Peak Current Limit : As shown in Figure 13, a combined 2.8kΩ internal resistance is connected to the non-inverting lead on the PWM comparator. A external resistance of Rx on the current limit pin forms a parallel resistance with the 2.8kΩ when the internal diodes are biased by the main current source of 900uA. Vcc IDELAY Vfb Vcc 5uA IFB 900uA 2k Ω PWM Comparator 3 0.8kΩ Ipk Frequency (MHz) Figure 11. KA5-series FPS Full Range EMI scan(67KHz, no Frequency Modulation) with DVD Player SET 4 Rx SenseFET Current Sense Figure 13. Peak Current Limit Adjustment Amplitude (dBµV) For example, FSDx0365RN has a typical Sense FET peak current limit (ILIM) of 2.15A. ILIM can be adjusted to 1.5A by inserting Rx between the Ipk pin and the ground. The value of the Rx can be estimated by the following equations: 2.15A : 1.5A = 2.8kΩ : XkΩ , X = Rx || 2.8kΩ . (X represents the resistance of the parallel network) Frequency (MHz) Figure 12. FSDX-series FPS Full Range EMI Scan (67KHz, with Frequency Modulation) with DVD Player SET 12 FSDL0365RN, FSDM0365RN Application Tips 1. Methods of Reducing Audible Noise Switching mode power converters have electronic and magnetic components, which generate audible noises when the operating frequency is in the range of 20~20,000 Hz. Even though they operate above 20 kHz, they can make noise depending on the load condition. Designers can employ several methods to reduce these noises. Here are three of these methods: Glue or Varnish The most common method involves using glue or varnish to tighten magnetic components. The motion of core, bobbin and coil and the chattering or magnetostriction of core can cause the transformer to produce audible noise. The use of rigid glue and varnish helps reduce the transformer noise. But, it also can crack the core. This is because sudden changes in the ambient temperature cause the core and the glue to expand or shrink in a different ratio according to the temperature. Figure 14. Equal Loudness Curves Ceramic Capacitor Using a film capacitor instead of a ceramic capacitor as a snubber capacitor is another noise reduction solution. Some dielectric materials show a piezoelectric effect depending on the electric field intensity. Hence, a snubber capacitor becomes one of the most significant sources of audible noise. It is considerable to use a zener clamp circuit instead of an RCD snubber for higher efficiency as well as lower audible noise. Figure 15. Typical Feedback Network of FPS Adjusting Sound Frequency Moving the fundamental frequency of noise out of 2~4 kHz range is the third method. Generally, humans are more sensitive to noise in the range of 2~4 kHz. When the fundamental frequency of noise is located in this range, one perceives the noise as louder although the noise intensity level is identical. Refer to Figure 14. Equal Loudness Curves. When FPS acts in Burst mode and the Burst operation is suspected to be a source of noise, this method may be helpful. If the frequency of Burst mode operation lies in the range of 2~4 kHz, adjusting feedback loop can shift the Burst operation frequency. In order to reduce the Burst operation frequency, increase a feedback gain capacitor (CF), opto-coupler supply resistor (RD) and feedback capacitor (CB) and decrease a feedback gain resistor (RF) as shown in Figure 15. Typical Feedback Network of FPS. 2. Other Reference Materials AN-4134: Design Guidelines for Off-line Forward Converters Using Fairchild Power Switch (FPSTM) AN-4137: Design Guidelines for Off-line Flyback Converters Using Fairchild Power Switch (FPS) AN-4140: Transformer Design Consideration for Off-line Flyback Converters using Fairchild Power Switch (FPSTM) AN-4141: Troubleshooting and Design Tips for Fairchild Power Switch (FPSTM) Flyback Applications AN-4147: Design Guidelines for RCD Snubber of Flyback AN-4148: Audible Noise Reduction Techniques for FPS Applications 13 FSDL0365RN, FSDM0365RN Typical Application Circuit Application Output power Input voltage Output voltage (Max current) 3.3V (1.0A) DVD Player 21W Universal input 5.1V (0.8A) (85-265Vac) 12V (0.5A) 16V (0.5A) Features • • • • • • High efficiency (>76% at universal input) Low standby mode power consumption (<1W at 230Vac input and 0.6W load) Low component count Enhanced system reliability through various protection functions Low EMI through frequency modulation Internal soft-start (15ms) Key Design Notes • The delay time for over load protection is designed to be about 30ms with C106 of 47nF. If faster/slower triggering of OLP is required, C106 can be changed to a smaller/larger value(eg. 100nF for about 60ms). • Using a resistor R104(39㏀) on Ipk pin (#4), the pule-by-pulse peak current limit level(ILIM) is adjusted to about 2A. • The branch formed by D103, C108 and R106 provides another ILIM adjustment having a negative slope to the input voltage. The ILIM value decreases as the input voltage level increases. 1. Schematic T101 EER2828 RT101 5D-9 R105 200kΩ C104 3.3nF 630V R102 56kΩ C103 47uF 400V 2 1 BD101 L203 10uH 11 1 2 D101 UF 4007 3 4 R106 300kΩ 4 R104 39kΩ C107 47nF 50V C102 100nF AC275V 3 Ipk 8 Drain 7 Drain 6 Drain Vfb Vcc 2 Vstr GND 1 C206 470uF 35V C205 470uF 35V L205 10uH 10 3 12V D204 EGP20D IC101 FSDM0365RN 5 16V D203 EGP20D C207 470uF 35V C208 470uF 35V 12 L207 4.7uH D103 UF 4004 C106 D102 R103 47uF UF 4004 5Ω 50V 6 5.1V D207 SB360 4 C213 1000uF 10V C214 1000uF 10V L206 4.7uH 5 9 C108 1uF 100V 3.3V D205 SB360 C210 1000uF 10V C209 1000uF 10V LF101 55mH 8 C302 2.2nF C101 100nF AC275V R201 510Ω R203 6.2kΩ R202 1kΩ TNR F101 FUSE 14 R204 20kΩ C215 100nF IC302 FOD817A IC301 KA431 R205 6kΩ FSDL0365RN, FSDM0365RN 2. Transformer Schematic Diagram EER2828 12 Np/2 1 Np/2 11 Np/2 2 10 3 N16V N16V N12V N12V 9 N 3.3V Na 4 Na N5.1V 8 6mm 5 3mm N3.3V 7 6 Np/2 N5.1V 3. Winding Specification P in (S → F ) W ire T u rn s W in d in g M e th o d 3 → 2 0 .2 5 φ × 1 50 C e n te r S o le n o id w in d in g N p /2 In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 2 L a ye rs N 3 .3 V 9 → 8 0 .3 3 φ × 2 4 C e n te r S o le n o id w in d in g In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 2 L a ye rs N 5 .1 V 6 → 9 0 .3 3 φ × 1 2 C e n te r S o le n o id w in d in g In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 2 L a ye rs Na 4 → 5 0 .2 5 φ × 1 16 C e n te r S o le n o id w in d in g In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 2 L a ye rs N 12V 10 → 12 0 .3 3 φ × 1 14 C e n te r S o le n o id w in d in g In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 3 L a ye rs N 16V 11 → 12 0 .3 3 φ × 1 18 C e n te r S o le n o id w in d in g In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 2 L a ye rs N p /2 2→ 1 0 .2 5 φ × 1 50 C e n te r S o le n o id w in d in g In s u la tio n : P o ly e s te r T a p e t = 0 .0 5 0 m m , 2 L a ye rs 4. Electrical Characteristics P in Spec. R e m a rk In d u c ta n c e 1－ 3 1 .4 m H ± 1 0 % 100kH z, 1V Leakage 1－ 3 25 uH M ax. S h o r t a ll o t h e r p in s 5. Core & Bobbin Core : EER2828 ( Ae = 86.66 mm2 ) Bobbin : EER2828 15 FSDL0365RN, FSDM0365RN 6. Demo Circuit Part List Part Value Note Part Resistor Note Inductor R102 56K 1W L203 10uH - R103 5 1/4W L205 10uH - R104 39K 1/4W L206 4.7uH - R105 200K 1/4W L207 4.7uH - R106 300K 1/4W R201 510 1/4W D101 UF4007 PN Ultra Fast R202 1K 1/4W D102 UF4004 PN Ultra Fast R203 6.2 K 1/4W D103 UF4004 PN Ultra Fast R204 20K 1/4W D203 EGP20D PN Ultra Fast R205 6K 1/4W D204 EGP20D PN Ultra Fast D205 SB360 Schottky D207 SB360 Schottky Capacitor 16 Value Diode C101 100nF/275AC Box C102 100nF/275AC Box C103 47uF/400V Electrolytic IC101 FSDM0365RN C104 3.3nF/630V Film IC301 KA431(TL431) C106 47uF/50V Electrolytic IC302 FOD817A C107 47nF/50V Ceramic C108 1uF/100V Electrolytic C205 470uF/35V Electrolytic C206 470uF/35V Electrolytic C207 470uF/35V Electrolytic C208 470uF/35V Electrolytic C209 1000uF/10V Electrolytic C210 1000uF/10V Electrolytic C213 1000uF/10V Electrolytic C214 1000uF/10V Electrolytic C215 100nF/50V Ceramic C302 2.2nF AC Ceramic IC FPS™ Voltage reference Opto-Coupler Fuse FUSE 2A/250V NTC RT101 5D-9 Bridge Diode BD101 2KBP06M 2N257 Bridge Diode Line Filter LF101 55mH - FSDL0365RN, FSDM0365RN 7. Layout 7.1 Top image of PCB 7.2 Bottom image of PCB 17 FSDL0365RN, FSDM0365RN Package Dimensions 8DIP 18 FSDL0365RN, FSDM0365RN Package Dimensions (Continued) 8LSOP 19 FSDL0365RN, FSDM0365RN Ordering Information Product Number Package Marking Code BVDSS fOSC RDS(ON) FSDM0365RN 8DIP DM0365R 650V 67KHz 3.6Ω FSDL0365RN 8DIP DL0365R 650V 50KHz 3.6Ω FSDM0365RL 8LSOP DM0365R 650V 67KHz 3.6Ω FSDL0365RL 8LSOP DL0365R 650V 50KHz 3.6Ω DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 9/29/05 0.0m 001 © 2005 Fairchild Semiconductor Corporation