AMD AM79C873KCW Netphyâ ¢ -1 10/100 mbps ethernet physical layer single-chip transceiver with 100base-fx support Datasheet

PRELIMINARY
Am79C873
NetPHY™ -1
10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support
DISTINCTIVE CHARACTERISTICS
■ 100BASE-FX direct interface to industry
standard electrical/optical transceivers
■ 10/100BASE-TX physical-layer, single-chip
transceiver
■ Compliant with the IEEE 802.3u 100BASE-TX
standard
■ Compliant with the ANSI X3T12 TP-PMD 1995
standard
■ Compliant with the IEEE 802.3u AutoNegotiation protocol for automatic link type
selection
■ Supports the MII with serial management
interface
■ Supports Full Duplex operation for 10 Mbps and
100 Mbps
■ High performance 100 Mbps clock generator
and data recovery circuitry
■ Adaptive equalization circuitry for 100 Mbps
receiver
■ Controlled output edge rates in 100 Mbps
■ Supports a 10BASE-T interface without the
need for an external filter
■ Provides Loopback mode for system
diagnostics
■ Includes flexible LED configuration capability
■ Digital clock recovery circuit using advanced
digital algorithm to reduce jitter
■ Low-power, high-performance CMOS process
■ Available in a 100-pin PQFP package
GENERAL DESCRIPTION
The NetPHY-1 device is a physical-layer, single-chip,
low-power transceiver for 100BASE-TX, 100BASE-FX,
and 10BASE-T operations. On the media side, it provides a direct interface to Fiber Media for 100BASE-FX
Fast Ethernet, Unshielded Twisted Pair Category 5
Cable (UTP5) for 100BASE-TX Fast Ethernet, or
UTP5/UTP3 Cable for 10BASE-T Ethernet. Through
the IEEE 802.3u Media Independent Interface (MII),
the NetPHY-1 device connects to the Medium Access
Control (MAC) layer, ensuring a high interoperability
among products from different vendors.
The NetPHY-1 device uses a low-power, high-performance CMOS process. It contains the entire physical
layer functions of 100BASE-FX and 100BASE-TX as
defined by the IEEE 802.3u standard, including the
Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), 100BASE-TX Twisted Pair Physical
Medium Dependent (TP-PMD) sublayer, and a
10BASE-T Encoder/Decoder (ENDEC). The NetPHY-1
device provides strong support for the Auto-Negotiation
function utilizing automatic media speed and protocol
selection. The NetPHY-1 device incorporates an internal wave-shaping filter to control rise/fall time, eliminating the need for external filtering on the 10/100
Mbps signals.
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 22164 Rev: A Amendment/+2
Issue Date: February 1999
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
BLOCK DIAGRAM
25M OSCI
LED1-4
TX CGM
LED
Driver
PECL
Driver
4B/5B
Encoder
Scrambler
NRZ
to
NRZI
Parallel
to Serial
NRZI to
MLT-3
FXTD±
MLT-3
Driver
100TXD±
Rise/Fall
Time
CTL
25M CLK
125M CLK
MII
Signals
MII
Interface/
Control
4B/5B
Decoder
Codegroup
Alignment
Descrambler
Serial to
Parallel
NRZI to
NRZ
MLT-3 to
NRZI
Adaptive
EQ
RXI±
RX
CRM
Digital
Logic
PECL
Receiver
10BASE-T
Module
Register
Collision
Detection
Carrier
Sense
FXRD±
FXSD+
RX
RXI±
TX
10TXD±
AutoNegotiation
22164A-1
2
Am79C873
P R E L I M I N A R Y
AVcc
PHYAD2
PHYAD1
PHYAD0
TESTMODE
RESET
84
83
82
81
DGND
85
DVcc
86
OPMODE1
91
87
OPMODE2
92
PHYAD3
OPMODE3
93
88
RPTR/NODE
94
OPMODE0
BPALIGN
95
PHYAD4
BP4B5B
96
89
BPSCR
97
90
AGND
10BTSER
98
AGND
99
100
CONNECTION DIAGRAM
1
2
80
RX_EN
FXSD-
79
RX_ER/RXD4
FXSD+
3
78
RX_DV
FXRD-
4
77
COL
FXRD+
5
76
CRS
AGND
6
75
RX_CLK
AVcc
7
74
DVcc
AVcc
8
DGND
RXI-
9
73
72
RXI+
10
71
RXD1
AGND
11
70
RXD2
AGND
12
69
RXD3
10TXO-
13
68
DVcc
10TXO+
14
67
DGND
AVcc
15
66
MDIO
AVcc
16
65
MDC
AGND
64
TX_CLK
AGND
17
18
63
TX_EN
Am79C873/KC
NetPHY-1
RXD0
48
49
50
CLK25M
DVcc
FDXLED
COLLED
47
51
LINKSTS
30
46
DGND
X2
NC
52
45
29
DGND
LINKLED
OSCI/X1
RX_LOCK
53
44
28
43
RXLED
AVcc
SPEED10
54
42
27
UTP
TXLED
AVcc
41
55
TRIDRV
26
40
TX_ER/TXD4
100TXO+
DVcc
56
39
25
DGND
TXD3
100TXO-
38
57
DGND
24
37
TXD2
AGND
DGND
58
36
23
BGRET
TXD1
AGND
35
59
34
22
AGND
TXD0
AVcc
BGREF
60
33
21
AVcc
DGND
AVcc
32
DVcc
61
31
62
20
AGND
19
OSC/XTL
FXTDFXTD+
22164A-2
Am79C873
3
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
K
Am79C873
C
\W
ALTERNATE PACKAGING OPTION
\W = Trimmed and formed in a tray
TEMPERATURE RANGE
C = Commercial (0˚C to +70˚C)
PACKAGE TYPE
K = Plastic Quad Flat Pack (PQR100)
SPEED OPTION
Not Applicable
DEVICE NUMBER/DESCRIPTION
Am79C873
NetPHY-1™ 10/100 Mbps Ethernet Physical Layer
Single-Chip Transceiver with 100BASE-FX Support
Valid Combinations
Valid Combinations
Am79C873
4
KC\W
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am79C873
P R E L I M I N A R Y
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Part No.
Description
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PCnet-ISA II Full Duplex Single-Chip Ethernet Controller for ISA Bus
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PCnet-32 Single-Chip 32-Bit Ethernet Controller for 486 and VL Buses
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PCnet-PCI II Full Duplex Single-Chip Ethernet Controller for PCI Local Bus
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PCnet-FAST Single-Chip Full Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
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IEEE 802.3/Ethernet/Cheapernet Transceiver
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Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY™-SD)
Am79C98
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Quad Fast Ethernet Transceiver for 100BASE-X Repeaters (QFEXr™)
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Integrated Repeater/Hub Devices
Am79C981
Integrated Multiport Repeater Plus (IMR+)
Am79C982
Basic Integrated Multiport Repeater (bIMR)
Am79C983
Integrated Multiport Repeater 2 (IMR2™)
Am79C984A
Enhanced Integrated Multiport Repeater (eIMR™)
Am79C985
Enhanced Integrated Multiport Repeater Plus (eIMR+™)
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Hardware Implemented Management Information Base (HIMIB™)
Am79C873
5
P R E L I M I N A R Y
CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device Configuration/Control/Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PHY Address Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
100BASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
100BASE Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4B5B Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Scrambler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Parallel-to-Serial Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
NRZ-to-NRZI Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PECL Driver For 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MLT-3 Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MLT-3 Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
100BASE Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
100BASE-TX Signal Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
100BASE-FX Signal Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Adaptive Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PECL Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MLT-3-to-NRZI Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock Recovery Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
NRZI-to-NRZ Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Serial-to-Parallel Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Code Group Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4B5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10BASE-T Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Collision Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MII Serial Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Key to Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Basic Mode Control Register (BMCR) - Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Basic Mode Status Register (BMSR) - Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PHY ID Identifier Register 1 (PHYIDR1) - Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PHY Identifier Register 2 (PHYIDR2) - Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Auto-Negotiation Advertisement Register(ANAR) - Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Auto-Negotiation Link Partner Ability Register (ANLPAR) - Register 5 . . . . . . . . . . . . . . . . . . . . 25
Auto-Negotiation Expansion Register (ANER) - Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AMD Specified Configuration Register (DSCR) - Register 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AMD Specified Configuration and Status Register (DSCSR) - Register 17. . . . . . . . . . . . . . . . . 29
10BASE-T Configuration/Status (10BTCSRSCR) - Register 18 . . . . . . . . . . . . . . . . . . . . . . . . . 30
6
Am79C873
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
MII 100BASE-TX Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
MII 100BASE-TX Transmit Timing Parameters (Half Duplex) . . . . . . . . . . . . . . . . . . . . . . . . 34
MII 100BASE-TX Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
MII-100BASE-TX Receive Timing Parameter (Half Duplex) . . . . . . . . . . . . . . . . . . . . . . . . . 35
Auto-Negotiation and Fast Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Auto-Negotiation and Fast Link Pulse Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 36
MII 10BASE-T Nibble Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
MII-10BASE-T Nibble Transmit Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
MII 10BASE-T Receive Nibble Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
MII-10BASE-T Receive Nibble Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10BASE-T SQE (Heartbeat) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10BASE-T SQE (Heartbeat) Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10BASE-T Jab and Unjab Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10BASE-T Jab and Unjab Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
MDIO Timing when OUTPUT by STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
MDIO Timing when OUTPUT by NetPHY-1 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
MII Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
MAGNETICS SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CRYSTAL SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
NETPHY-1 MII EXAMPLE SCHEMATIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Am79C873
7
P R E L I M I N A R Y
PIN DESCRIPTIONS
MII Interface
TX_ER/TXD4
RXD[3:0]
Transmit Error
Input
In 100 Mbps mode, if this signal is asserted high and
TX_EN is active, the HALT symbol is substituted for the
actual data nibble. In 10 Mbps mode, this input
is ignored.
In bypass modes (BP4B5B or BPALIGN), TX_ER becomes the TXD4 pin, the fifth TXD data bit.
TXD[3:0]
Transmit Data
Input
These are the transmit data input pins for nibble
data from the MII in 100 Mbps or 10 Mbps nibble
mode (25 MHz for 100 Mbps mode, 2.5 MHz for 10
Mbps nibble mode).
In 10 Mbps serial mode, the TXD0 pin is used as the
serial data input pin. TXD[3:1] are ignored.
TX_EN
Transmit Enable
Input
Active high input indicates the presence of valid nibble data on TXD[3:0] for both 100 Mbps or 10 Mbps
nibble mode.
In 10 Mbps serial mode, active high indicates the presence of valid 10 Mbps data on TXD0.
Receive Data
Output/Z1
Nibble wide receive data (synchronous to RX_CLK - 25
MHz for 100BASE-TX mode, 2.5 MHz for 10BASE-T
nibble mode). Data is driven on the falling edge of
RX_CLK.
In 10 Mbps serial mode, the RXD0 pin is used as the
data output pin. RXD[3:1] are ignored.
RX_CLK
Receive Clock
Output/Z1
Provides the recovered receive clock for different
modes of operation:
- 25 MHz nibble clock in 100 Mbps mode
- 2.5 MHz nibble clock in 10 Mbps nibble mode
- 10 MHz receive clock in 10 Mbps serial mode
CRS
Carrier Sense
Output/Z1
This pin is asserted high to indicate the presence of
carrier due to receive or transmit activities in 10BASET or 100BASE-TX Half Duplex modes.
In Repeater, when Full Duplex or Loopback mode is a
logic 1, it indicates the presence of carrier due only to
receive activity.
COL
- 25 MHz nibble transmit clock derived from transmit Phase Locked Loop (TX PLL) in 100BASE-TX
mode
Collision Detect
Output/Z1
This pin is asserted high to indicate detection of collision conditions in 10 Mbps and 100 Mbps Half Duplexmodes. In 10BASE-T Half Duplex mode with Heartbeat
set active (bit 13, register 18h), it is also asserted for a
duration of approximately 1ms at the end of transmission to indicate heartbeat. In Full Duplex mode, this
signal is always logic 0. There is no heartbeat function
in Full Duplex mode.
- 2.5 MHz transmit clock in 10BASE-T nibble mode
RX_DV
TX_CLK
Transmit Clock
Output/Z1
This pin provides the transmit clock output from the
NetPHY-1 deviceas follows:
- 10 MHz transmit clock in 10BASE-T serial mode
MDC
Management Data Clock
Input
This pin is the synchronous clock to the MDIO management data input/output serial interface which is asynchronous to transmit and receive clocks. The maximum
clock rate is 2.5 MHz.
MDIO
Management Data I/O
Input/Output
This pin is the bidirectional management instruction/
data signal that may be driven by the station management entity or the PHY. This pin requires a 1.5 KΩ pullup resistor.
Receive Data Valid
Output/Z1
This pin is asserted high to indicate that valid data is
present on RXD[3:0].
RX_ER/RXD4
Receive Error
Output/Z1
This pin is asserted high to indicate that an invalid symbol has been detected inside a received packet in 100
Mbps mode.
In a bypass mode (BP4B5B or BPALIGN modes),
RX_ER becomes RXD4, the fifth RXD data bit of the
5B symbols.
1. Goes to high impedance.
8
Am79C873
P R E L I M I N A R Y
RX_EN
Receive Enable
Input
This pin is active high enabled for receive signals
RXD[3:0], RX_CLK, RX_DV and RX_ER. A low on this
input tri-states these output pins. For normal operation
in a NODE application, this pin should be pulled high.
Media Interface
RXI±
100/10 Mbps-TX/T Twisted Pair Differential Input
Pair
Input
These pins are the differential receive input for
10BASE-T and 100BASE-TX. They are capable of receiving 100BASE-TX MLT-3 or 10BASE-T Manchester
encoded data.
FXRD±
100BASE-FX PECL Differential Input Pair Input
These pins are the differential receive input for
1 0 0 B A S E - F X . T h ey a r e c a p a bl e o f r e c e i v i n g
100BASE-FX.
function will change to indicate the Polarity status for 10
Mbps operation. If polarity is inverted, the POLLED will
go ON.
COLLED
Collision LED
Output
This pin indicates the presence of collision activity for
10 Mbps and 100 Mbps operation. This LED has no
meaning for 10 Mbps or 100 Mbps Full Duplex operation (Active low).
LINKLED (TRAFFIC LED)
Link LED
Output
This pin indicates Good Link status for 10 Mbps and
100 Mbps operation (Active low). It functions as the
TRAFFIC LED when bit 5 of register 16 is set to 1. In
TRAFFIC LED mode, it is always ON when the link is
OK. The TRAFFIC LED flashes when transmitting or
receiving.
RXLED
100BASE-FX PECL Signal Detect
Input
These input signals from the FX-PMD transceiver indicate detection of a receive signal from the Fiber Media.
Receive LED
Output Drain
This pin indicates the presence of receive activity for 10
Mbps and 100 Mbps operation (Active low). The NetPHY-1 device incorporates a “monostable” function on
the RXLED output. This ensures that even minimal receive activity will generate an adequate LED ON time.
10TXO±
TXLED
10BASE-T Differential Output Pair
Output
This output pair provides controlled rise and fall times
designed to filter the transmitters output.
Transmit LED
Output Drain
This pin indicates the presence of transmit activity for 10
Mbps and 100 Mbps operation (Active low). The NetPHY-1 device incorporates a “monostable” function on
the TXLED output. This ensures that even minimal
transmit activity will generate an adequate LED ON time.
FXSD±
100TXO±
100BASE-TX Twisted Pair Differential Output Pair
Output
This output pair drives MLT-3 encoded data to the
100 M twisted pair cable and provides controlled rise
and fall times designed to filter the transmitters output,
reducing any associated EMI.
FXTD±
100BASE-FX PECL Differential Output PairOutput
These pins are the differential transmit output for
100BASE-FX. They are capable of transmitting
100BASE-FX
Device Configuration/Control/Status
Interface
UTP
UTP Cable Indication
Output
This pin is the UTP Cable Indication. When UTP=1, it
indicates that the UTP cable is being used.
SPEED10
These outputs can directly drive LEDs or provide status
information to a network management device.
Speed 10 Mbps
Output
When set high, this bit indicates a 10 Mbps operation,
when set low 100 Mbps operation. This pin can drive
a low current LED to indicate that 100 Mbps operation
is selected.
FDXLED (POLLED)
RX_LOCK
Polarity/Full Duplex LED
Output
This pin indicates Full Duplex mode status for 100
Mbps and 10 Mbps operation (Active low). If bit 4 of
Register 16 (FDXLED_MODE) is set, the FDXLED pin
Lock for Clock/Data Recovery PLL
Output
When this pin is high, it indicates that the receiver recovery PLL logic has locked to the input data stream.
LED Interface
Am79C873
9
P R E L I M I N A R Y
LNKSTS
RTPR/NODE
Link Status Register Bit
Output
This pin reflects the status of bit 2 register 1.
Repeater/Node Mode
Input
When set high, this bit selects REPEATER mode; when
set low, it selects NODE. In REPEATER mode or
NODE mode with Full Duplex configured, the Carrier
Sense (CRS) output from the NetPHY-1 device will be
asserted only during receive activity. In NODE mode or
a mode not configured for Full Duplex operation, CRS
will be asserted during receive or transmit activity. At
power-up/reset, the value on this pin is latched into
Register 16, bit 11.
OPMODE0-OPMODE3
OPMODE0-OPMODE3
Input
These pins are used to control the forced or advertised
operating mode of the NetPHY-1 device (see table below). The value is latched into the NetPHY-1 device registers at power-up/rese..
OPOPOPOPMODE3 MODE2 MODE1 MODE0
0
0
0
10
0
0
0
0
0
1
BPALIGN
Function
0
Auto-Negotiation
enable with all
capabilities with
Flow Control
1
Auto-Negotiation
enable without all
capabilities without
Flow Control
0
Auto-Negotiation
100TX FDX with
Flow Control only
0
0
1
1
Auto-Negotiation
100TX FDX/HDX
without Flow
Control
0
1
0
0
Auto-Negotiation
10TP FDX with
Flow Control only
0
1
0
1
Auto-Negotiation
10TX FDX/HDX
without Flow
Control
0
1
1
0
Manual select
100TX FDX
0
1
1
1
Manual select
100TX HDX
1
0
0
0
Manual select
10TX FDX
1
0
0
1
Manual select
10TX HDX
1
0
1
0
Manual select
100FX FDX
1
0
1
1
Manual select
100FX HDX
1
1
1
1
Auto-Negotiation
10/100TX. HDX
only
Bypass Alignment
Input
This pin allows 100 Mbps transmit and receive data
streams to bypass all of the transmit and receive operations when set high. At power-up/reset, the value on
this pin is latched into bit Register 16, bit 13.
BP4B5B
Bypass 4B5B Encoder/Decoder
Input
This pin allows 100 Mbps transmit and receive data
streams to bypass the 4B to 5B encoder and 5B to 4B
decoder circuits when set high. At power-up/reset, the
value on this pin is latched into Register 16, bit 15.
BPSCR
Bypass Scrambler/Descrambler
Input
This pin allows 100 Mbps transmit and receive data
streams to bypass the scrambler and descrambler circuits when set high. At power-up/reset, the value on
this pin is latched into Register 16, bit 14.
10BTSER
Serial/Nibble Select
10 Mbps Serial Operation:
Input
When set high, this input selects a serial data transfer
mode. Manchester encoded transmit and receive data
is exchanged serially with a 10 MHz clock rate on the
least significant bits of the nibble-wide MII data buses,
pin TXD[0] and RXD[0] respectively. This mode is intended for use with the NetPHY-1 device connected to
a device (MAC or Repeater) that has a 10 Mbps serial
interface. Serial operation is not supported in 100 Mbps
mode. For 100 Mbps, this input is ignored.
10 and 100 Mbps Nibble Operation:
When set low, this input selects the MII compliant nibble data transfer mode. Transmit and receive data is exchanged in nibbles on the TXD[3:0] and RXD[3:0] pins
respectively.
At power-up/reset, the value on this pin is latched into
Register 18, bit 10.
Am79C873
P R E L I M I N A R Y
Clock Interface
OSCI/X1
PHYAD4
Crystal or Oscillator Input
Input
This pin should be connected to a 25 MHz (±50 ppm)
crystal if OSC/XTL=0 or a 25 MHz (±50 ppm) external
TTL oscillator input, if OSC/XTLB=1.
X2
Crystal Oscillator Output
Output
An external 25 MHz (±50 ppm) crystal should be connected to this pin if OSC/XTL=0, or left unconnected if
OSC/XTL=1.
OSC/XTL
Crystal or Oscillator Selector Pin
Output
OSC/XTL=0: An external 25 MHz (±50ppm) crystal
should be connected to X1 and X2 pins.
■ OSC/XTL=1: An external 25 MHz (±50ppm) oscillator should be connected to X1 and X2 should be left
unconnected.
PHY Address 4
Input
This pin provides PHY address bit 4 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 4 during power up/reset.
Miscellaneous
NC
No Connect
These pins are to be left unconnected (floating).
BGREF
Bandgap Voltage Reference
Input
Connect a 6.01K Ω, 1% resistor between this pin and
the BGRET pin to provide an accurate current reference for the NetPHY-1 device.
BGRET
Bandgap Voltage Reference Return
Input
This is the return pin for 6.01K Ω resistor connection.
CLK25M
TRIDRV
25 MHz Clock Output
Output/Z
This clock is derived directly from the crystal circuit.
Tri-State Digital Output
Input
When set high, all digital output pins are set to a high
impedance state, and I/O pins, go to input mode.
PHY Address Interface
RESET
The PHYAD[4:0] pins provide up to 32 unique PHY
addresses. An address selection of all zeros (00000)
will result in a PHY isolation condition. See the isolate
bit description in the BMCR, address 00.
PHYAD0
PHY Address 0
Input
This pin provides PHY address bit 0 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 8 during power up/reset.
Reset
Input
This pin is the active low input that initializes the NetPHY1 device. It should remain low for 30 ms after VCC has
stabilized at 5 Vdc (nominal) before it transitions high.
TESTMODE
Test Mode Control Pin
TESTMODE=0: Normal operating mode.
Input
TESTMODE=1: Enable test mode.
PHYAD1
Power and Ground Pins
PHY Address 1
Input
This pin provides PHY address bit 1 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 7 during power up/reset.
The power (VCC) and ground (GND) pins of the NetPHY-1 device are grouped in pairs of two categories Digital Circuitry Power/Ground Pairs and Analog Circuitry Power/Ground Pair.
PHYAD2
DGND
PHY Address 2
Input
This pin provides PHY address bit 2 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 6 during power up/reset.
Digital Logic Ground
These pins are the digital supply pairs.
PHYAD3
PHY Address 3
Input
This pin provides PHY address bit 3 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 5 during power up/reset.
Power
DVCC
Digital Logic Power Supply
These pins are the digital supply pairs.
Power
AGND
Analog Circuit Ground
Power
These pins are the analog circuit supply pairs.
AVCC
Analog Circuit Power Supply
Power
These pins are the analog circuit supply pairs.
Am79C873
11
P R E L I M I N A R Y
FUNCTIONAL DESCRIPTION
The NetPHY-1 device performs all Physical Coding
Sublayer (PCS), Physical Media Access (PMA),
Twisted Pair Physical Medium Dependent (TP-PMD)
sublayer, 10BASE-T Encoder/Decoder, and Twisted
Pair Media Access Unit (TPMAU) functions. Figure 1
shows the major functional blocks implemented in the
NetPHY-1 device.
The NetPHY-1 Fast Ethernet single-chip transceiver,
provides the functionality as specified in the IEEE
802.3u standard, integrates complete 100BASE-FX,
100BASE-TX modules and a complete 10BASE-T
module. The NetPHY-1 device provides a Media Independent Interface (MII) as defined in the IEEE 802.3u
standard (Clause 22).
100Base
Transmitter
100Base
Receiver
10Base-T
Tranceiver
MII Interface
Carrier
Sense
Collision
Detection
Auto
Negotiation
MII Serial
Management
Interface
22164A-3
Figure 1.
Functional Block Diagram
MII Interface
The purpose of the MII interface is to provide a simple,
easy to implement connection between the MAC Reconciliation layer and the PHY. The MII is designed to
make the differences between various media transparent to the MAC sublayer.
The MII consists of a nibble wide receive data bus, a
nibble wide transmit data bus, and control signals to facilitate data transfers between the PHY and the Reconciliation layer.
■ TXD (transmit data) is a nibble (4 bits) of data that
are driven by the reconciliation sublayer synchronously with respect to TX_CLK. For each TX_CLK
period which TX_EN is asserted, TXD (3:0) are accepted for transmission by the PHY.
■ TX_CLK (transmit clock) output to the MAC reconciliation sublayer is a continuous clock that provides
the timing reference for the transfer of the TX_EN,
TXD, and TX_ER signals.
12
■ TX_EN (transmit enable) input from the MAC reconciliation sublayer to indicate nibbles are being
presented on the MII for transmission on the physical
medium. TX_ER (transmit coding error) transitions
synchronously with respect to TX_CLK. If TX_ER is
asserted for one or more clock periods, and TX_EN
is asserted, the PHY will emit one or more symbols
that are not part of the valid data delimiter set somewhere in the frame being transmitted.
■ RXD (receive data) is a nibble (4 bits) of data that
are sampled by the reconciliation sublayer synchronously with respect to RX_CLK. For each
RX_CLK period which RX_DV is asserted, RXD
(3:0) are transferred from the PHY to the MAC
reconciliation sublayer.
■ RX_CLK (receive clock) output to the MAC reconciliation sublayer is a continuous clock that provides
the timing reference for the transfer of the RX_DV,
RXD, and RX_ER signals.
Am79C873
P R E L I M I N A R Y
■ RX_DV (receive data valid) input from the PHY to indicate the PHY is presenting recovered and decoded nibbles to the MAC reconciliation sublayer. To
interpret a receive frame correctly by the reconciliation sublayer, RX_DV must encompass the frame
starting no later than the Start-of-Frame delimiter
and excluding any End-Stream delimiter.
fo r 1 o r m o r e c l o ck p e r i o d s t o i n d i c a t e t o
the reconciliation sublayer that an error was
detected somewhere in the frame being transmitted from the PHY to the reconciliation sublayer.
■ CRS (carrier sense) is asserted by the PHY when
either the transmit or receive medium is non-idle and
deasserted by the PHY when the transmit and receive
medium are idle. Figure 2 depicts the behavior of CRS
during 10BASE-T and 100BASE-TX transmission.
■ RX_ER (receive error) transitions synchronously
with respect to RX_CLK. RX_ER will be asserted
TXD
IDLE
SSD
J/K
Preamble
SFD
ESD
T/R
Data
IDLE
100Base-TX
CRS
TXD
Preamble
Data
SFD
EFD
10Base-T
CRS
22164A-4
Figure 2.
Carrier Sense during 10BASE-T and 100BASE-TX Transmission
100BASE Operation
The 100BASE transmitter receives 4-bit nibble data
clocked in at 25 MHz at the MII and outputs a scrambled 5-bit encoded MLT-3 signal to the media at 100
Mbps. The on-chip clock circuit converts the 25 MHz
clock into a 125 MHz clock for internal use.
The IEEE 802.3u specification defines the Media Independent Interface. The interface specification defines a
dedicated receive data bus and a dedicated transmit
data bus.
These two busses include various controls and signal
indications that facilitate data transfers between the
NetPHY-1 device and the Reconciliation layer.
100BASE Transmit
The 100BASE transmitter consists of the functional
blocks shown in Figure 3. The 100BASE transmit section converts 4-bit synchronous data provided by the
MII to a scrambled MLT-3 125 million symbols per second serial data stream.
Am79C873
13
P R E L I M I N A R Y
25M OSCI
LED1-4#
TX CGM
LED
Driver
PECL
Driver
4B/5B
Encoder
Scrambler
Parallel
to Serial
NRZ
to
NRZI
NRZI to
MLT-3
MLT-3
Driver
FXTD±
100TXD±
Rise/Fall
Time
CTL
MII
Signals
MII
Interface/
Control
10BASE-T
Module
Register
Collision
Detection
Carrier
Sense
RX
RXI±
TX
10TXD±
AutoNegotiation
22164A-5
Figure 3.
100BASE Transmitter Functional Block Diagram
The block diagram in Figure 3 provides an overview of
the functional blocks contained in the transmit section.
The transmitter section contains the following functional blocks:
■ 4B5B Encoder
■ Scrambler
■ Parallel-to-Serial Converter
■ NRZ-to-NRZI Converter
■ PECL Driver (For FX Operation)
■ NRZI to MLT-3 (For TX Operation)
■ MLT-3 Driver (For TX Operation)
4B5B Encoder
The 4B5B encoder converts 4-bit (4B) nibble data generated by the MAC Reconciliation Layer into a 5-bit
(5B) code group for transmission (see Table 1). This
conversion is required for control and packet data to be
14
combined in code groups. The 4B5B encoder substitutes the first 8 bits of the MAC preamble with a J/K
code-group pair (11000 10001) upon transmit.
The 4B5B encoder continues to replace subsequent
4B preamble and data nibbles with corresponding 5B
code-groups. At the end of the transmit packet, upon
the deassertion of the Transmit Enable signal from the
MAC Reconciliation layer, the 4B5B encoder injects the
T/R code-group pair (01101 00111) indicating end of
frame. After the T/R code-group pair, the 4B5B encoder
continuously injects IDLEs into the transmit data
stream until Transmit Enable is asserted and the next
transmit packet is detected.
The NetPHY-1 device includes a Bypass 4B5B conversion option within the 100BASE-TX transmitter for support of applications like 100 Mbps repeaters which do
not require 4B5B conversion.
Am79C873
P R E L I M I N A R Y
Table 1.
4B5B Code Group
the twisted pair cable in 100BASE-TX operation. By
scrambling the data, the total energy presented to the
cable is randomly distributed over a wide frequency
range. Without the scrambler, energy levels on the
cable could peak beyond FCC limitations at frequencies related to repeated 5B sequences like continuous
transmission of IDLE symbols. The scrambler output is
combined with the NRZ 5B data from the code-group
encoder via an XOR logic function. The result is a
scrambled data stream with sufficient randomization to
decrease radiated emissions at critical frequencies.
Since EMI is not a concern in a fiber application, the
scrambler is bypassed in 100BASE-FX.
Symbol
Meaning
4B code
3210
5B Code
43210
0
Data 0
0000
11110
1
Data 1
0001
01001
2
Data 2
0010
10100
3
Data 3
0011
10101
4
Data 4
0100
01010
5
Data 5
0101
01011
6
Data 6
0110
01110
7
Data 7
0111
01111
8
Data 8
1000
10010
9
Data 9
1001
10011
A
Data A
1010
10110
The Parallel-to-Serial Converter receives parallel 5B
scrambled data from the scrambler and serializes it
(i.e., converts it from a parallel to a serial data stream).
The serialized data stream is then presented to the
NRZ-to-NRZI Encoder block
B
Data B
1011
10111
NRZ-to-NRZI Converter
C
Data C
1100
11010
D
Data D
1101
11011
E
Data E
1110
11100
After the transmit data stream has been scrambled and
serialized, the data must be NRZI encoded for compatibility with the TP-PMD standard for 100BASE-TX transmission over Category-5 unshielded twisted pair cable.
F
Data F
1111
11101
PECL Driver For 100BASE-FX
I
Idle
undefined
11111
J
SFD (1)
0101
11000
The PECL driver accepts NRZI coded data and converts
it to PECL signal levels for transmission over fiber media.
K
SFD (2)
0101
10001
T
ESD (1)
undefined
01101
R
ESD (2)
undefined
00111
H
Error
undefined
00100
V
Invalid
undefined
00000
V
Invalid
undefined
00001
V
Invalid
undefined
00010
V
Invalid
undefined
00011
V
Invalid
undefined
00101
V
Invalid
undefined
00110
V
Invalid
undefined
01000
V
Invalid
undefined
01100
V
Invalid
undefined
10000
V
Invalid
undefined
11001
Parallel-to-Serial Converter
The output pair is a differential pseudo ECL (PECL) interface designed to connect directly to a standard fiber
optic PMD. The differential driver for the FXTD± is current mode and is designed to drive resistive termination
in a complementary mode. The FXTD± pins are incapable of sourcing current, this implies that VOH must
be set by the ratios of the Thevenin termination resistors for each of the lines. RIOH is a pull-up resistor connected from the FXTD± output to VCC. RIOL is a pulldown resistor connected from the FXTD± output to
ground. RIOH and RIOL are electrically in parallel from
an AC standpoint. A target impedance of 50 Ω is
needed for the transmission line impedance. A value of
62 Ω for RIOH and a value of 300 Ω for RIOL will yield
a Thevenin equivalent characteristic impedance of
49.7 Ω and a VOH value of VCC-.88 volts, compatible
with PECL circuits. VOL is required to be VDD-1.81 or
greater. A sink current of 19 milli-amps (mA) would
achieve this through the output termination resistors.
MLT-3 Converter
Scrambler
The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across
the frequency spectrum at the media connector and on
The MLT-3 conversion is accomplished by converting the
data stream output from the NRZI encoder into two binary data streams with alternately phased logic
one events.
Am79C873
15
P R E L I M I N A R Y
MLT-3 Driver
■ Signal Detect
The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver which
converts these streams to current sources and alternately drives either side of the transmit transformer primary winding resulting in a minimal current MLT-3
signal. Refer to Figure 4 for the block diagram of the
MLT-3 converter.
■ Adaptive Equalization
100BASE Receiver
■ Code Group Alignment
The 100BASE receiver contains several function
blocks that convert the scrambled 125 Mbps serial data
to synchronous 4-bit nibble data that is then provided to
the MII.
■ 4B5B Decoder
The receive section contains the following functional
blocks:
D
■ MLT-3-to-Binary Decoder
■ Clock Recovery Module
■ NRZI -o-NRZ Decoder
■ Serial-to-Parallel Converter
■ Descrambler
100BASE-TX Signal Detect
The signal detect function meets the specifications mandated by the ANSI XT12 TP-PMD 100BASE-TX standards for both voltage thresholds and timing parameters.
Q
CK
Q
Binary plus
Binary In
Binary minus
Common
Driver
MLT-3
Binary In
MLT-3
22164A-6
Figure 4.
MLT-3 Converter Block Diagram
100BASE-FX Signal Detect
The NetPHY-1 device accepts signal detect information
on the FXSD pin at PECL signal levels from the FX
Optical Module.
Adaptive Equalization
When transmitting data at high speeds over copper
twisted pair cable, attenuation based on frequency becomes a concern. In high speed twisted pair signaling,
the frequency content of the transmitted signal can
vary greatly during normal operation based on the randomness of the scrambled data stream. This variation
16
in signal attenuation caused by frequency variations
must be compensated for to ensure the integrity of the
received data.
In order to ensure quality transmission when employing
MLT-3 encoding, the compensation must be able to
adapt to various cable lengths and cable types depending on the installed environment. The selection of long
cable lengths for a given implementation, requires significant compensation which will be over-kill in a situation that includes shorter, less attenuating cable
lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will
Am79C873
P R E L I M I N A R Y
cause serious under-compensation for longer length
cables. Therefore, the compensation or equalization
must be adaptive to ensure proper conditioning of the
received signal independent of the cable length.
PECL Receiver
The PECL receiver accepts PECL signal-level data
from the FX Optical Module and presents it to the Clock
Recovery Module.
MLT-3-to-NRZI Decoder
The NetPHY-1 device decodes the MLT-3 information
from the Digital Adaptive Equalizer into NRZI data. The
relationship between NRZI and MLT-3 data is shown in
Figure 4.
Clock Recovery Module
The Clock Recovery Module accepts NRZI data from
the MLT-3-to-NRZI decoder or the PECL Receiver. The
Clock Recovery Module locks onto the data stream and
extracts the 125 MHz reference clock. The extracted
and synchronized clock and data are presented to the
NRZI-to-NRZ Decoder.
NRZI-to-NRZ Decoder
The transmit data stream is required to be NRZI encoded in for compatibility with 100BASE transmission
over. This conversion process must be reversed on the
receive end. The NRZI-to-NRZ decoder, receives the
NRZI data stream from the Clock Recovery Module
and converts it to a NRZ data stream to be presented
to the Serial to Parallel conversion block.
Serial-to-Parallel Converter
The Serial-to-Parallel Converter receives a serial data
stream from the NRZI-to-NRZ converter, and converts
the data stream to parallel data to be presented to the
descrambler.
Descrambler
Because of the scrambling process required to control
the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. The
descrambler receives scrambled parallel data streams
from the Serial to Parallel converter, descrambles the
data streams, and presents the data streams to the
Code Group alignment block.
Note: The scrambler is bypassed for 100BASE-FX
operation.
Code Group Alignment
The Code Group Alignment block receives unaligned
5B data from the descrambler and converts it into 5B
code group data. Code Group Alignment occurs after
the J/K is detected, and subsequent data is aligned on
a fixed boundary.
4B5B Decoder
The 4B5B Decoder functions as a look-up table that
translates incoming 5B code groups into 4B (Nibble)
data. When receiving a frame, the first two 5-bit code
groups received are the start-of-frame delimiter (J/K
symbols). The J/K symbol pair is stripped and two nibbles of preamble pattern are substituted. The last two
code groups are the end-of-frame delimiter (T/R symbols).The T/R symbol pair is also stripped from the nibble presented to the Reconciliation layer.
10BASE-T Operation
The 10BASE-T transceiver is IEEE 802.3u compliant.
When the NetPHY-1 device is operating in 10BASE-T
mode, the coding scheme is Manchester. Data processed for transmit is presented to the MII interface in
nibble format, converted to a serial bit stream, then
Manchester encoded. When receiving, the Manchester
encoded bit stream is decoded and converted into nibble format for presentation to the MII interface.
Collision Detection
For Half Duplex operation, a collision is detected when
the transmit and receive channels are active simultaneously. When a collision has been detected, it will be
reported by the COL signal on the MII interface. Collision detection is disabled in Full Duplex operation.
Carrier Sense
Carrier Sense (CRS) is asserted in Half Duplex operation during transmission or reception of data. During
Full Duplex mode, CRS is asser ted only during
receive operations.
Auto-Negotiation
The objective of Auto-Negotiation is to provide a means
to exchange information between segment linked devices and to automatically configure both devices to
take maximum advantage of their abilities. It is important to note that Auto-Negotiation does not test the link
segment characteristics. The Auto-Negotiation function
provides a means for a device to advertise supported
modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes
of operation, and to reject un-shared modes of operation. This allows devices on both ends of a segment to
establish a link at the best common mode of operation.
If more than one common mode exists between the two
devices, a mechanism is provided to allow the devices
to resolve to a single mode of operation using a predetermined priority resolution function.
Auto-Negotiation also provides a parallel detection
function for devices that do not support the Auto-Negotiation feature. During Parallel detection there is no exchange of configuration information, instead, the
receive signal is examined. If it is discovered that the
signal matches a technology that the receiving device
Am79C873
17
P R E L I M I N A R Y
supports, a connection will be automatically established using that technology. This allows devices that
do not support Auto-Negotiation but support a common
mode of operation to establish a link.
(preamble) synchronization clock cycles on MDC. The
Start of Frame Delimiter (SFD) is indicated by a <01>
pattern followed by the operation code (OP):<10> indicates Read operation and <01> indicates Write operation. For read operation, a 2-bit turnaround (TA) filing
between Register Address field and Data field is provided for MDIO to avoid contention. Following the turnaround time, 16-bit data is read from or written onto
management registers.
MII Serial Management
The MII serial management interface consists of a data
interface, basic register set, and a serial management
interface to the register set. Through this interface it is
possible to control and configure multiple PHY devices,
get status and error information, and determine the
type and capabilities of the attached PHY device(s).
Serial Management Interface
The serial control interface uses a simple two-wired serial interface to obtain and control the status of the physical layer through the MII interface. The serial control
interface consists of Management Data Clock (MDC),
and Management Data Input/Output (MDI/O) signals.
The NetPHY-1 devices management functions correspond to MII specification for IEEE 802.3u-1995
(Clause 22) for registers 0 through 6 with vendor-specific registers 16,17, and 18.
The MDIO pin is bidirectional and may be shared by up
to 32 devices.
In read/write operation, the management data frame is
64-bits long and starts with 32 contiguous logic one bits
MDC
MDIO Read
0
32 "1"s
Idle Preamble
1
1
SFD
0
A4
Op Code
A3
A0
PHY Address
R4
R3
R0
Z
Register Address
0
D15
D14
Turn Around
D1
D0
Data
Read
Write
Idle
22164A-7
Figure 5.
Management Interface - Read Frame Structure
MDC
MDIO Write
32 "1"s
Idle
Preamble
0
1
SFD
0
Op Code
1
A4
A3
PHY Address
A0
R4
R3
Register Address
R0
1
0
D15
Turn Around
D14
Data
D1
D0
Idle
Write
22164A-8
Figure 6.
18
Management Interface - Write Frame Structure
Am79C873
P R E L I M I N A R Y
Register Description
Register Address
Register Name
Description
0
BMCR
Basic Mode Control Register
1
BMSR
Basic Mode Status Register
2
PHYIDR1
PHY Identifier Register 1
3
PHYIDR2
PHY Identifier Register 2
4
ANAR
5
ANLPAR
6
ANER
Auto-Negotiation Expansion Register
16
DSCR
AMD Specified Configuration Register
17
DSCSR
18
10BTCSR
10BASE-T Configuration/Status Register
Others
Reserved
Reserved For Future Use-Do Not Read/Write To These Registers
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
AMD Specified Configuration/Status Register
Key to Default
<Access Type>:
In the register description that follows, the default column takes the form:
RO = Read only
<Reset Value>, <Access Type> / <Attribute(s)>
Where
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
<Reset Value>:
P = Value permanently set
1
Bit set to logic one
LL = Latching low
0
Bit set to logic zero
LH = Latching high
X
No default value
(Pin No.)
Value latched in from pin number at reset
Am79C873
19
P R E L I M I N A R Y
Basic Mode Control Register (BMCR) Register 0
Bit
Bit Name
Default
Description
Reset:
1=Software reset
0=Normal operation
0.15
Reset
0, RW/SC
When set this bit configures the PHY status and control registers to their
default states. This bit will return a value of one until the reset process is
complete.
Loopback:
Loopback control register
1=Loopback enabled
0.14
Loopback
0, RW
0=Normal operation
When in 100M operation is selected, setting this bit will cause the
descrambler to lose synchronization. A 720ms “dead time” will occur
before any valid data appears at the MII receive outputs.
Speed Select:
1=100 Mbps
0=10 Mbps
0.13
Speed Selection
1, RW
Link speed may be selected either by this bit or by Auto-Negotiation if bit
12 of this register is set. When Auto-Negotiation is enabled, this bit will
return Auto-Negotiation link speed.
Auto-Negotiation Enable:
1= Auto-Negotiation enabled:
0.12
Auto-Negotiation
Enable
0= Auto-Negotiation disabled:
1, RW
When auto-Negotiation is enabled bits 8 and 13 will contain the AutoNegotiation results. When Auto-Negotiation is disabled bits 8 and 13 will
determine the duplex mode and link speed.
Power Down:
1=Power Down
0.11
Power Down
0, RW
0=Normal Operation
Setting this bit will power down the NetPHY-1 device with the exception of
the crystal oscillator circuit.
Isolate:
1= Isolate
0= Normal Operation
(PHYAD=
0.10
Isolate
00000),
RW
20
When this bit is set the data path will be isolated from the MII interface.
TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL and CRS will be
placed in a high impedance state. The management interface is not
effected by this bit. When the PHY Address is set to 00000 the isolate bit
will be set upon power-up/reset.
Am79C873
P R E L I M I N A R Y
Basic Mode Control Register (BMCR) Register 0 (Continued)
Bit
Bit Name
Default
Description
Restart Auto-Negotiation:
1= Restart Auto-Negotiation.
0= Normal Operation
0.9
Restart AutoNegotiation
0, RW/SC
When this bit is set the Auto-Negotiation process is re-initiated. When
Auto-Negotiation is disabled (bit 12 of this register cleared), this bit has no
function and it should be cleared. This bit is self-clearing and will return a
value of 1 until Auto-Negotiation is initiated. The operation of the AutoNegotiation process will not be affected by the management entity that
clears this bit.
Duplex Mode:
1= Full Duplex operation.
0.8
Duplex Mode
1, RW
0= Normal operation
If Auto-Negotiation is disabled, setting this bit will cause the NetPHY-1
device to operate in Full Duplex mode. When Auto-Negotiation is enabled,
this bit reflects the duplex selected by Auto-Negotiation.
Collision Test:
1= Collision Test enabled.
0.7
Collision Test
0, RW
0= Normal Operation
When set, this bit will cause the COL signal to be asserted in response to
the assertion of TX_EN.
0.6
Reserved
0, RO
Reserved:
Write as 0, ignore on read.
Am79C873
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P R E L I M I N A R Y
Basic Mode Status Register (BMSR) Register 1
Bit
Bit Name
Default
Description
100BASE-T4 Capable:
1.15
100BASE-T4
0,RO/P
1=NetPHY-1 device is able to perform in 100BASE-T4 mode.
0=NetPHY-1 device is not able to perform in 100BASE-T4 mode.
100BASE-TX Full Duplex Capable:
1.14
100BASE-TX
Full Duplex
1,RO/P
1=NetPHY-1 device is able to perform 100BASE-TX in Full Duplex mode.
0=NetPHY-1 device is not able to perform 100BASE-TX in Full Duplex
mode.
100BASE-TX Half Duplex Capable:
1.13
1.12
1.11
100BASE-TX
Half Duplex
10BASE-T
Full Duplex
10BASE-T
Half Duplex
1.10-1.7
Reserved
1.6
MF Preamble
Suppression
1,RO/P
1=NetPHY-1 device is able to perform 100BASE-TX in Half Duplex mode.
0=NetPHY-1 device is not able to perform 100BASE-TX in Half Duplex
mode.
10BASE-T Full Duplex Capable:
1,RO/P
1=NetPHY-1 device is able to perform 10BASE-T in Full Duplex mode.
0=NetPHY-1 device is not able to perform 10BASE-T in Full Duplex mode.
10BASE-T Half Duplex Capable:
1,RO/P
1=NetPHY-1 device is able to perform 10BASE-T in Half Duplex mode.
0=NetPHY-1 device is not able to perform 10BASE-T in Half Duplex mode.
0,RO
Reserved:
Write as 0, ignore on read.
MII Frame Preamble Suppression:
0,RO
1=PHY will accept management frames with preamble suppressed.
0=PHY will not accept management frames with preamble suppressed.
1.5
Auto-Negotiation
Complete
Auto-Negotiation Complete:
0,RO
1=Auto-Negotiation process completed.
0=Auto-Negotiation process not completed.
Remote Fault:
1.4
Remote Fault
0,
RO/LH
1= Remote fault condition detected (cleared on read or by a chip reset).
Fault criteria and detection method is NetPHY-1 device implementation
specific. This bit will set after the RF bit in the ANLPAR (bit 13, register
address 05) is set.
0= No remote fault condition detected.
1.3
Auto-Negotiation
Ability
Auto Configuration Ability:
1,RO/P
1=NetPHY-1 device able to perform Auto-Negotiation.
0=NetPHY-1 device not able to perform Auto-Negotiation.
Link Status:
1=Valid link established (for either 10 Mbps or 100 Mbps operation).
0=Link not established.
1.2
22
Link Status
0,RO/LL
The link status bit is implemented with a latching function, so that the
occurrence of a link failure condition causes the Link Status bit to be
cleared and remain cleared until it is read via the management interface.
Am79C873
P R E L I M I N A R Y
Basic Mode Status Register (BMSR) Register 1
Bit
Bit Name
Default
Description
Jabber Detect:
1=Jabber condition detected.
1.1
Jabber Detect
1.0
Extended
Capability
0,
RO/LH
0=No jabber condition detected.
This bit is implemented with a latching function. Once Jabber conditions
are detected this bit will remain set until a read operation is completed
through a management interface or a NetPHY-1 device reset. This bit
works only in 10 Mbps mode.
Extended Capability:
1,RO/P
1=Extended register capable.
0=Basic register capable only.
PHY ID Identifier Register 1 (PHYIDR1) Register 2
The PHY Identifier Registers 1 and 2 work together in
a single identifier of the NetPHY-1 device. The Identifier
consists of a concatenation of the Organizationally
Bit
Bit Name
Unique Identifier (OUI), a vendor's model number,
and a model revision number. The IEEE assigned OUI
is 00606E.
Default
Description
<0181H>
This register stores bits 3 - 18 of the OUI (00606E) to bits 15 - 0 of this
register, respectively. The most significant two bits of the OUI are ignored
(the IEEE standard refers to these as bit 1 and 2).
OUI Most Significant Bits:
2.15-2.0
OUI_MSB
PHY Identifier Register 2 (PHYIDR2) Register 3
Bit
Bit Name
Default
3.15-3.10
OUI_LSB
<101110>,RO/P
3.9-3.4
VNDR_MDL
<000000>,RO/P
3.3-3.0
MDL_REV
<0001>,RO/P
Description
OUI Least Significant Bits:
Bits 19 - 24 of the OUI (00606E) are mapped to bits 15 - 10 of this register,
respectively.
Vendor Model Number:
Six bits of the vendor model number mapped to bits 9 - 4 (most significant
bit to bit 9).
Model Revision Number:
Four bits of the vendor model revision number mapped to bits 3 - 0 (most
significant bit to bit 3).
Am79C873
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P R E L I M I N A R Y
Auto-Negotiation Advertisement
Register(ANAR) - Register 4
This register contains the advertised abilities of the NetPHY-1 device as they will be transmitted to link partners during Auto-Negotiation.
Bit
Bit Name
Default
Description
Next Page Indication:
0=No next page available
4.15
NP
0,RO/P
1=Next page available
The NetPHY-1 device does not support the next page function. This bit is
permanently set to 0
Acknowledge:
1=Link partner ability data reception acknowledged.
0=Not acknowledged.
4.14
ACK
0,RO
4.13
RF
0, RW
The NetPHY-1 device's Auto-Negotiation state machine will automatically
control this bit in the outgoing FLP bursts and set it at the appropriate time
during the Auto-Negotiation process. Software should not attempt to write
to this bit.
Remote Fault:
1=Local Device senses a fault condition.
0=No fault detected.
4.12-4.11
Reserved
0, RW
Reserved:
Write as 0, ignore on read.
Flow Control Support:
4.10
FCS
0, RW
1=Controller chip supports flow control ability.
0=Controller chip does not support flow control ability.
100BASE-T4 Support:
1=100BASE-T4 supported by the local device.
4.9
T4
0, RO/P
0=100BASE-T4 not supported.
The NetPHY-1 device does not support 100BASE-T4 so this bit is
permanently set to 0.
100BASE-TX Full Duplex Support:
4.8
TX_FDX
1, RW
1=100BASE-TX Full Duplex supported by the local device.
0=100BASE-TX Full Duplex not supported.
100BASE-TX Support:
4.7
TX_HDX
1, RW
1=100BASE-TX supported by the local device.
0=100BASE-TX not supported.
10BASE-T Full Duplex Support:
4.6
10_FDX
1, RW
1=10BASE-T Full Duplex supported by the local device.
0=10BASE-T Full Duplex not supported.
10BASE-T Support:
4.5
10_HDX
1, RW
1=10BASE-T supported by the local device.
0=10BASE-T not supported.
Protocol Selection Bits:
4.4-4.0
Selector
<00001>, RW
These bits contain the binary encoded protocol selector supported by this
node.
<00001> indicates that this device supports IEEE 802.3 CSMA/CD.
24
Am79C873
P R E L I M I N A R Y
Auto-Negotiation Link Partner Ability
Register (ANLPAR) - Register 5
This register contains the advertised abilities of the link partner as they are received during Auto-Negotiation.
Bit
Bit Name
Default
5.15
NP
0, RO
Description
Next Page Indication:
0= Link partner, no next page available.
1= Link partner, next page available.
Acknowledge:
1=Link partner ability data reception acknowledged.
5.14
ACK
0, RO
0=Not acknowledged.
The NetPHY-1 device's Auto-Negotiation state machine will automatically
control this bit from the incoming FLP bursts. Software should not attempt
to write to this bit.
Remote Fault:
5.13
RF
0, RO
1=Remote fault indicated by link partner.
0=No remote fault indicated by link partner.
5.12-5.10
Reserved
0, RO
Reserved:
Write as 0, ignore on read.
100BASE-T4 Support:
5.9
T4
0, RO
1=100BASE-T4 supported by the link partner.
0=100BASE-T4 not supported by the link partner.
100BASE-TX Full Duplex Support:
5.8
TX_FDX
0, RO
1=100BASE-TX Full Duplex supported by the link partner.
0=b 100BASE-TX Full Duplex not supported by the link partner.
100BASE-TX Support:
5.7
TX_HDX
0, RO
1=100BASE-TX Half Duplex supported by the link partner.
0=100BASE-TX Half Duplex not supported by the link partne.r
10BASE-T Full Duplex Support:
5.6
10_FDX
0, RO
1=10BASE-T Full Duplex supported by the link partner.
0=10BASE-T Full Duplex not supported by the link partner.
10BASE-T Support:
5.5
10_HDX
0, RO
1=10BASE-T Half Duplex supported by the link partner.
0=10BASE-T Half Duplex not supported by the link partner.
5.4-5.0
Selector
<00000>, RO
Protocol Selection Bits:
Link partners binary encoded protocol selector.
Am79C873
25
P R E L I M I N A R Y
Auto-Negotiation Expansion Register
(ANER) - Register 6
Bit
Bit Name
Default
6.15-6.5
Reserved
0, RO
6.4
PDF
0, RO/LH
Description
Reserved:
Write as 0, ignore on read.
Local Device Parallel Detection Fault:
PDF=1: A fault detected via parallel detection function.
PDF=0: No fault detected via parallel detection function.
Link Partner Next Page Able:
6.3
LP_NP_ABLE
0, RO
LP_NP_ABLE=1: Link partner, next page available.
LP_NP_ABLE=0: Link partner, no next page.
Local Device Next Page Able:
6.2
NP_ABLE
0,RO/P
NP_ABLE=1: NetPHY-1 device, next page available.
NP_ABLE=0: NetPHY-1 device, no next page.
NetPHY-1 device does not support this function, so this bit is always 0.
New Page Received:
6.1
PAGE_RX
0, RO/LH
A new link code word page received. This bit will be automatically cleared
when the register (Register 6) is read by management.
Link Partner Auto-Negotiation Able:
6.0
26
LP_AN_ABLE
0, RO
LP_AN_ABLE=1 indicates that the link partner supports AutoNegotiation.
Am79C873
P R E L I M I N A R Y
AMD Specified Configuration Register (DSCR) Register 16
Bit
Bit Name
Default
Description
Bypass 4B5B Encoding and 5B4B Decoding:
16.15
BP_4B5B
, RW
1=4B5B encoder and 5B4B decoder function bypassed.
0=Normal 4B5B and 5B4B operation The value of the pin is latched into
this bit at power-up/reset.
Bypass Scrambler/Descrambler Function:
16.14
BP_SCR
Pin 97, RW
1=Scrambler and descrambler function bypassed.
0=Normal scrambler and descrambler operation.
The value of the input pin is latched into this bit at power-up/reset.
Bypass Symbol Alignment Function:
16.13
BP_ALIGN
Pin 98, RW
1= Receive functions (descrambler, symbol alignment and symbol
decoding functions) bypassed. Transmit functions (symbol encoder and
scrambler) bypassed.
0= Normal operation.
The value of the BPALIGN input pin is latched into this bit at power-up/
reset.
16.12
Reserved
0, RW
Reserved:
This bit must be set as 0.
Repeater/Node Mode:
1=Repeater mode.
0=Node mode.
16.11
REPEATER
Pin 94, RW
In Repeater mode, the Carrier Sense (CRS) output from the NetPHY-1
device will be asserted only by receive activity. In NODE mode, or a mode
not configured for Full Duplex operation, CRS will be asserted by either
receive or transmit activity.
The value of the RPTR/NODE input pin is latched into this bit at power-up
reset.
100BASE-TX or FX Mode Control:
16.10
TX
1, RW
1=100BASE-TX operation.
0=100BASE-FX operation.
16.9
UTP
1, RW
UTP Cable Control:
1=The media is a UTP cable, 0=STP.
CLK25M Disable:
1=CLK25M output clock signal tri-stated.
16.8
CLK25MDIS
0, RW
0=CLK25M enabled.
This bit should be set to 1 to disable the 25 MHz output and reduce ground
bounce and power consumption. For applications requiring the CLK25M
output, set this bit to 0.
Force Good Link in 100 Mbps:
16.7
F_LINK_100
1, RW
1=Normal 100 Mbps operation.
0=Force 100 Mbps good link status.
This bit is useful for diagnostic purposes.
Reserved:
16.6
Reserved
0, RW
This bit must be written as 0.
Am79C873
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P R E L I M I N A R Y
AMD Specified Configuration Register (DSCR) Register 16
Bit
Bit Name
Default
Description
LINKLED Mode Select:
0= Link LED output configured to indicate link status only.
16.5
LINKLED_CTL
0, RW
1= Link LED output configured to indicate traffic status: When the link
status is OK, the LED will be on. When the chip is in transmitting or
receiving, it flashes.
FDXLED Mode Select:
16.4
FDXLED_MODE
0, RW
1= FDXLED output configured to indicate polarity in 10BASE-T mode.
0= FDXLED output configured to indicate Full DuplexFull Duplex mode
status for 10 Mbps and 100 Mbps operation.
Reset State Machine:
16.3
SMRST
0, RW
When this bit is set to 1, all state internal machines will be reset. This bit
will clear after reset is completed.
MF Preamble Suppression Control:
16.2
MFPSC
0, RW
1= MF preamble suppression on.
0= MF preamble suppression off.
MII frame preamble suppression control bi.t
Sleep Mode:
16.1
SLEEP
0, RW
16.0
RLOUT
0, RW
Writing a 1 to this bit will cause NetPHY-1 device to enter Sleep mode and
power down all circuits except the oscillator and clock generator circuit. To
exit Sleep mode, write 0 to this bit position. The prior configuration will be
retained when the sleep state is terminated, but the state machine will be
reset.
Remote Loopout Control:
28
When this bit is set to 1, the received data will loop out to the transmit
channel. This is useful for bit error rate testing.
Am79C873
P R E L I M I N A R Y
AMD Specified Configuration and Status
Register (DSCSR) - Register 17
Bit
Bit Name
Default
Description
100 M Full Duplex Operation:
17.15
100FDX
1, RO
After Auto-Negotiation is completed, the results will be written to this bit.
A 1 in this bit position indicates 10 0M Full Duplex operation. The software
can read bits [15:12] to determine which mode is selected after AutoNegotiation. This bit is invalid when Auto-Negotiation is disabled.
100 M Half Duplex Operation:
17.14
100HDX
1, RO
After Auto-Negotiation is completed, the results will be written to this bit.
A 1 in this bit position indicates 100 M Half Duplex operation. The software
can read bits [15:12] to determine which mode is selected after AutoNegotiation. This bit is invalid when Auto-Negotiation is disabled.
10 M Full Duplex Operation:
17.13
10FDX
1, RO
After Auto-Negotiation is completed, the results will be written to this bit.
A 1 in this bit position indicates 10 M Full Duplex operation. The software
can read bits [15:12] to determine which mode is selected after AutoNegotiation. This bit is invalid when Auto-Negotiation is disabled.
10 M Half Duplex Operation:
17.12
10HDX
1, RO
17.1117.10
Reserved
0, RW
After Auto-Negotiation is completed, the results will be written to this bit.
A 1 in this bit position indicates 10M Half Duplex operation. The software
can read bits [15:12] to determine which mode is selected after AutoNegotiation. This bit is invalid when Auto-Negotiation is disabled.
Reserved:
Write as 0, ignore on read.
PHY Address Bit 4:0:
17.8-17.4
PHYAD[4:0]
(PHYAD), RW
Bit
Bit Name
Default
17.3-17.0
ANMB[3:0]
0, RO
The values of the PHYAD[4:0] pins are latched to this register at powerup/reset. The first PHY address bit transmitted or received is the MSB (bit
4). A station management entity connected to multiple PHY entities must
know the appropriate address of each PHY. A PHY address of <00000>
will cause the isolate bit of the BMCR (bit 10, Register Address 00) to be
set.
Description
Auto-Negotiation Monitor Bits:
These bits are for debug only. The Auto-Negotiation status will be written
to these bits.
b3 b2 b1 b0
0
0
0
0
In IDLE state
0
0
0
1
Ability match
0
0
1
0
Acknowledge match
0
0
1
1
Acknowledge match fail
0
1
0
0
Consistency match
0
1
0
1
Consistency match fail
0
1
1
0
Parallel detect signal_link_ready
0
1
1
1
Parallel detect signal_link_ready fail
1
0
0
0
Auto-Negotiation completed successfully
Am79C873
29
P R E L I M I N A R Y
10BASE-T Configuration/Status
(10BTCSRSCR) - Register 18
Bit
Bit Name
Default
18.15
Reserved
0, RO
Description
Reserved:
Write as 0, ignore on read.
Link Pulse Enable:
18.14
LP_EN
1, RW
1=Transmission of link pulses enabled.
0=Link pulses disabled, good link condition forced.
This bit is valid only in 10 Mbps operation.
Heartbeat Enable:
1=Heartbeat function enabled.
18.13
HBE
Inverse Pin 94,
RW
18.12
Reserved
0, RO
0=Heartbeat function disabled.
When the NetPHY-1 device is configured for Full Duplex operation, this bit
will be ignored (the collision/heartbeat function is invalid in Full Duplex
mode). The initial state of this bit is the inverse value of RPTR/NODE input
pin at power on reset.
Reserved:
Write as 0, ignore on read.
Jabber Enable:
1= Jabber function enabled.
18.11
JABEN
1, RW
0= Jabber function disabled.
Enables or disables the Jabber function when the NetPHY-1 device is in
10BASE-T Full Duplex or 10BASE-T Transceiver Loop-back mode.
10BASE-T Serial Mode:
1=10BASE-T serial mode selected.
18.10
10BT_SER
Pin 98, RW
0=10BASE-T nibble mode selected.
The value on the 10BTSER input pin is latched into this bit at power-up/
rese.t
Serial mode not supported for 100 Mbps operation.
18.9-18.1
Reserved
0, RO
18.0
POLR
0, RO
Reserved:
Write as 0, ignore on read.
Polarity Reversed:
30
When this bit is set to 1, it indicates that the 10M cable polarity is reversed.
This bit is set and cleared by 10BASE-T module automatically.
Am79C873
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . . . –0°C to +70°C
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . .0°C to +70°C
Supply Voltage
with Respect to Ground . . . . . . . . . -4.75 V to +5.25 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
DC Input Voltage (VIN) . . . . . . . . –0.5 V to VCC +0.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC Output or I/O Pin Voltage (VOUT) . . . . .–0.5 V to
VCC +0.5 V
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality
at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect
device reliability.
Power Consumption
100BASE-TX Full Duplex . . . . . . . . . . . . . . . . 185 mA
(Measured using Unscrambled IDLE transmission looped
back to RXIN, includes external termination circuitry)
10BASE-T Full Duplex . . . . . . . . . . . . . . . . . . 222 mA
(Measured using Maximum packet size, minimum I.P.G.
transmission looped back to RXIN, includes external termination circuitry)
Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . 165 mA
(Measured during Parallel Detect until link established)
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
(Measured with no link established)
Power Down Mode . . . . . . . . . . . . . . . . . . . . . 40 mA
(Measured while MII Register 0 Bit 11 set true)
DC ELECTRICAL CHARACTERISTICS
(VCC = 5 VDC, ±5%, TA = 0 to 70, unless specified otherwise)
Symbol
Parameter
Conditions
I100TX
Supply Current 100BASE 100BASE-TX
active
Min
Typical
Max
Unit
Vcc = 5.0 V
180
185
mA
Vcc = 5.0 V
120
Supply Current 10BASE-TX active
I10TTP
(Random data, Random IPG and
Random size)
mA
Supply Current 10BASE-TX active
(Max. Packet size, Min. IPG and Worst
case data pattern)
Vcc = 5.0 V
220
mA
IPDM
Supply Current Power Down Mode
Vcc = 5.0 V
40
mA
IAN
Supply Current during Auto-Negotiation
Vcc = 5.0 V
165
mA
IRST
Supply Current during Reset.
Vcc = 5.0 V
115
mA
I10TWC
TTL Inputs
(TXD0-TXD3, TX_CLK, MDIO, TX_EN, TX_DV, TX_ER, TESTMODE, PHYAD0-4, OPMODE0-4, RPTR, BPALIGN, BP4B5B,
BPSCR, 10BTSER, RESET)
VIL
Input Low Voltage
IIL = -400 uA
VIH
Input High Voltage
IIH = 100 uA
2.0
V
IIL
Input Low Current
VIN = 0.4 V
-200
uA
IIH
Input High Current
VIN = 2.7 V
Am79C873
0.8
100
V
uA
31
P R E L I M I N A R Y
DC ELECTRICAL CHARACTERISTICS
(VCC = 5 VDC, ±5%, TA = 0 to 70, unless specified otherwise) (Continued)
Symbol
Parameter
Conditions
Min
Typical
Max
Unit
0.4
V
MII TTL Outputs
(RXD0-3, RX_EN, RX_DV, RX_ER, CRS, COL, MDIO)
VOL
VOH
Output Low Voltage
IOL = 4 mA
Output High Voltage
IOH = -4 mA
2.4
V
Non-MII TTL Outputs
(TXLED, RXLED, LINKLED, COLLED, FDXLED, RX_LOCK)
VOL
Output Low Voltage
IOL = 1 mA
0.4
VOH
Output High Voltage
IOH = -0.1 mA
2.4
VICM
RXI+/RXI- Input Common-Mode Voltage
100 Ω Termination Across
1.5
V
V
2.0
2.5
V
21
mA
56
mA
Twisted Pair Transmitter
ITD100
ITD10
100TX+± 100BASE-TX Mode
Differential Output Current
19
10TX± 10BASE-T Differential Output
Current
44
50
PECL Receiver
VIH - VCC PECL Receiver Voltage - High
-1.16
-0.90
VIL - VCC PECL Receiver Voltage - Low
-1.81
-1.48
VIH - VCC PECL Signal Detect Voltage - High
-1.16
-0.90
VIL - VCC PECL Signal Detect Voltage - Low
-1.81
-1.48
PECL Signal Detect
PECL Transmitter
VOH VCC
PECL Output Voltage - High
-1.05
-0.88
VOL VCC
PECL Output Voltage - Low
-1.85
-1.60
AC ELECTRICAL CHARACTERISTICS
(Over full range of operating conditions unless specified otherwise)
Symbol
Parameter
Conditions
Min
Typical
Max
Unit
Transmitter
32
tTR/F
100TXO+/- Differential Rise/Fall Time
3.0
5.0
ns
tTM
100TXO+/- Differential Rise/Fall Time
Mismatch
-0.5
0.5
ns
tTDC
100TXO+/- Differential Output Duty
Cycle Distortion
-0.5
0.5
ns
tT/T
100TXO+/- Differential Output Peak-toPeak Jitter
XOST
100TXO+/- Differential Voltage
Overshoot
300
ps
5
Am79C873
%
P R E L I M I N A R Y
AC ELECTRICAL CHARACTERISTICS
(Over full range of operating conditions unless specified otherwise) (Continued)
Symbol
Parameter
Conditions
Min
Typical
Max
Unit
PECL Transmitter (FX Transmit Interface)
ptTR/F
100FXTD+/- Differential Rise/Fall Time
1.0
2.0
ns
ptTM
100FXTD+/- Differential Rise/Fall Time
Mismatch
-0.5
0.5
ns
ptTDC
100FXTD+/- Differential Output Duty
Cycle Distortion
-0.5
0.5
ns
ptPPJ
100FXTD+/- Differential Output Peakto-Peak Jitter
300
ps
ptDDJ
100FXTD+/- Differential Output Data
Dependent Jitter
500
ps
Clock Specifications
XNTOL
TX Input Clock Frequency Tolerance
25 MHz Frequency
XBTOL
TX Output Clock Frequency Tolerance
25 MHz Frequency
ppm
-100
+100
ppm
tPWH
OSC Pulse Width High
14
ns
tPWL
OSC Pulse Width Low
14
ns
tRPWH
RX_CLK Pulse Width High
14
ns
tRPWL
RX_CLK Pulse Width Low
14
ns
Am79C873
33
P R E L I M I N A R Y
MII 100BASE-TX Transmit Timing
TX_CLK
tTXs
tTXh
TXD [0:3],
TX_EN, TX_ER
t2
t1
CRS
tTXr/f
tTXpd
100TX±
22164A-9
Figure 7.
MII 100BASE-TX Transmit Timing Diagram
MII 100BASE-TX Transmit Timing Parameters (Half Duplex)
Symbol
Parameter
Conditions
Min
Typical
(Note 1)
Max
Unit
tTXs
TXD[0:3], TX_EN, TX_ER Setup To
TX_CLK High
11
-
-
ns
tTXh
TXD[0:3], TX_EN, TX_ER Hold From
TX_CLK High
0
-
-
ns
t1
TX_EN Sampled To CRS Asserted
-
4
-
BT
t2
TX_EN Sampled To CRS De-asserted
-
4
-
BT
tTXpd
TX_EN Sampled To TPO Out (Tx Latency)
-
8
-
BT
tTXr/f
100TX Driver Rise/Fall Time
3
4
5
ns
90% To 10%, Into
100 Ω Differential
Note:
1. Typical values are at 25 and are for design aid only; not guaranteed and not subject to production testing.
34
Am79C873
P R E L I M I N A R Y
MII 100BASE-TX Receive Timing
RX_CLK
tRXS tRXh
tTXpd
RXD [0:3],
RX_DV, RX_ER
t1
t2
t4
CRS
t3
RXI±
t5
COL
22164A-10
Figure 8.
MII 100BASE-TX Receive Timing Diagram
MII-100BASE-TX Receive Timing Parameter (Half Duplex)
Symbol
Parameter
Conditions
Min
Typical
(Note 1)
Max
Unit
tRXs
RXD[0:3), RX_DV, RX_ER Setup To
RX_CLK High
10
-
-
ns
tRXh
RXD[0:3], RX_DV, RX_ER Hold From
RX_CLK High
10
-
-
ns
tRXpd
RXI In To RXD[0:3] Out (RX Latency)
-
15
-
BT
t1
CRS Asserted To RXD[0:3], RX_DV,
RX_ER
-
4
-
BT
t2
CRS De-asserted To RXD[0:3], RX_DV,
RX_ER
-
0
-
BT
t3
RXI In To CRS Asserted
10
-
14
BT
t4
RXI Quiet To CRS De-asserted
14
-
18
BT
t5
RXI In To COL De-asserted
14
-
18
BT
Note:
1. Typical values are at 25 and are for design aid only; not guaranteed and not subject to production testing.
Am79C873
35
P R E L I M I N A R Y
Auto-Negotiation and Fast Link Pulse Timing
Clock Pulse
Clock Pulse
Data Pulse
t1
Fast Link
Pulses
t2
t3
FLP Burst
FLP Burst
10TX0±
t4
Figure 9.
t5
22164A-11
Auto-Negotiation and Fast Link Pulse Timing Diagram
Auto-Negotiation and Fast Link Pulse Timing Parameters
Symbol
Parameter
Conditions
Min
Typical
Max
Unit
-
100
-
ns
-
62.5
-
us
t1
Clock/Data Pulse Width
t2
Clock Pulse To Data Pulse Period
t3
Clock Pulse To Clock Pulse Period
-
125
-
us
t4
FLP Burst Width
-
2
-
ms
t5
FLP Burst To FLP Burst Period
-
13.93
-
ms
-
Clock/Data Pulses Per Burst
33
33
33
ea
DATA = 1
MII 10BASE-T Nibble Transmit Timing
TX_CLK
tTXh
tTXS
TXD [0:3],
TX_EN, TX_ER
t2
t1
CRS
tTXpd
10TX±
22164A-12
Figure 10.
MII 10BASE-T Nibble Transmit Timing Diagram
MII-10BASE-T Nibble Transmit Timing Parameters
Symbol
Conditions
Min
Typical
Max
Unit
tTXs
TXD[0:3), TX_EN, TX_ER Setup To
TX_CLK High
11
-
-
ns
tTXh
TXD[0:3], TX_EN, TX_ER Hold From
TX_CLK High
0
-
-
ns
t1
TX_EN Sampled To CRS Asserted
-
2
4
BT
t2
TX_EN Sampled To CRS De-asserted
-
15
20
BT
TX_EN Sampled To 10TXO Out (Tx
Latency)
-
2
4
BT
tTXpd
36
Parameter
Am79C873
P R E L I M I N A R Y
MII 10BASE-T Receive Nibble Timing Diagram
RX_CLK
tRXS tRXh
tTXpd
RXD [0:3],
RX_DV, RX_ER
t1
t2
t4
CRS
t3
RXI±
22164A-13
Figure 11.
MII 10BASE-T Receive Nibble Timing Diagram
MII-10BASE-T Receive Nibble Timing Parameters
Symbol
Parameter
Conditions
Min
Typical
Max
Unit
tRXs
RXD[0:3), RX_DV, RX_ER Setup To
RX_CLK High
10
-
-
ns
tRXh
RXD[0:3], RX_DV, RX_ER Hold From
RX_CLK High
10
-
-
ns
tRXpd
RXI In To RXD[0:3] Out (RX Latency)
-
7
-
BT
t1
CRS Asserted To RXD[0:3], RX_DV,
RX_ER
1
14
20
BT
t2
CRS De-asserted To RXD[0:3], RX_DV,
RX_ER
-
-
3
BT
t3
RXI In To CRS Asserted
1
2
4
BT
t4
RXI Quiet To CRS De-asserted
1
10
15
BT
Am79C873
37
P R E L I M I N A R Y
10BASE-T SQE (Heartbeat) Timing
TX_CLK
TX_EN
t1
t2
COL
22164A-14
Figure 12.
10BASE-T SQE (Heartbeat) Timing Diagram
10BASE-T SQE (Heartbeat) Timing Parameters
Symbol
Parameter
Conditions
Min
Typical
Max
Unit
t1
COL (SQE) Delay After TX_EN Off
0.65
1.3
1.6
ms
t2
COL (SQE) Pulse Duration
0.5
1.1
1.5
ms
10BASE-T Jab and Unjab Timing
TX_EN
t1
TDX
COL
t2
22164A-15
Figure 13.
10BASE-T Jab and Unjab Timing Diagram
10BASE-T Jab and Unjab Timing Parameters
Symbol
Parameter
t1
t2
38
Conditions
Min
Typical
Max
Unit
Maximum Transmit Time
20
48
150
ms
Unjab Time
250
505
1500
ms
Am79C873
P R E L I M I N A R Y
MDIO Timing when OUTPUT by STA
MDC
10 ns
10 ns
(Min)
t1
(Min)
t2
MDIO
22164A-16
Figure 14.
MDIO Timing when OUTPUT by STA Timing Diagram
MDIO Timing when OUTPUT by NetPHY-1 Device
MDC
0 - 300 ns
t3
MDIO
22164A-17
Figure 15.
MDIO Timing when OUTPUT by NetPHY-1 Timing Diagram
MII Timing Parameters
Symbol
Parameter
Conditions
Min
Typical
Max
Unit
t1
MDIO Setup Before MDC
When OUTPUT By STA
10
-
-
ns
t2
MDIO Hold After MDC
When OUTPUT By STA
10
-
-
ns
t3
MDC To MDIO Output Delay
When OUTPTU By
NetPHY-1 device
0
-
100
ns
Am79C873
39
P R E L I M I N A R Y
MAGNETICS SELECTION GUIDE
CRYSTAL SELECTION GUIDE
The NetPHY-1 device requires a 1:1 ratio for both the
receive and the transmit transformers. Refer to Table 2
for transformer requirements. Transformers meeting
these requirements are available from a variety of magnetic manufacturers. Designers should test and qualify
all magnetics before using them in an application. The
transformers listed in Table 2 are electrical equivalent,
but may not be pin-to-pin equivalent.
A crystal can be used to generate the 25 MHz reference clock instead of a crystal oscillator. An M-TRON
crystal, part number is 00301-00169, MP-1 Fund, @
25.000000 MHz, ±50 ppm or equivalent may be used.
The crystal must be a fundamental type, parallel resonant. Connect to X1 and X2, shunt each crystal lead
to ground with an 18pf capacitor (see Figure 16).
Transformer Requirements
OSC/XTLB
Part Number
Bel Fuse
S558-5999-01
Delta
LF8200, LF8221
OSCGND
32
31
X2
Manufacturer
X1
Table 2.
AGND
TG22-3506ND, TD223506G1, TG22-S010ND,
HALO Electronics, Inc.
TG22-S012ND,
TG110-S050N2
30
29
Single Port
Y1 25M
Quad Port
TG110-6506NX, TG110S450NX, TG110-S452NX
Nano Pulse Inc.
C18
18 pF
NPI 6181-37, NPI 6120-30,
NPI 6120-37
AGND
C19
18 pF
AGND
22164A-18
NPI 6170-30
Figure 16.
PE-68517, PE-68515,
H1019, H1012 ----Single
Port
Pulse Engineering
H1027, H1028 ---- Dual Port
PE-69037, H1001,
H1036, H1044 ---- Quad
Port
Valor
ST6114, ST6118
YCL
20PMT04, 20PMT05
40
Am79C873
Crystal Circuit Diagram
P R E L I M I N A R Y
Table 3.
Part List for Example Design
Item No
Qty
1
11
C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11,C13
Reference Number
Capacitor, Decoupling, 0.1 µf, 50 V
Part Description
2
1
C12
Capacitor, .01 µf, 2KV
3
4
D1,D2,D3,D4
LED, General Purpose
4
1
J1
Connector, RJ45
5
2
L1,L2
Ferrite, Panasonic EXCCL4532U
6
1
OSC1
Oscillator, Crystal, 25 MHz, ±50 ppm
7
2
Q2,Q1
Transistor, NNP, General Purpose, 2N2222
8
2
R1,R2
Resistor, 470Ω, 5%
9
1
R3
Resistor, 820Ω, 5%
10
1
R4
Resistor, 33Ω, 5%
11
1
R5
Resistor, 510Ω, 5%
12
1
R6
Resistor, 6.01KΩ, 1%
13
4
R7,R8,R14,R15
Resistor, 49.9Ω, 1%
14
1
R9
Resistor, 1.5KΩ, 5%
15
4
R10,R11,R12,R13
Resistor, 75Ω, 1%
16
2
R17,R16
Resistor, 10KΩ, 5%
17
1
U1
NetPHY-1 device, PHY/Transceiver, 100 pin QFP
18
1
U2
Magnetics, Pulse Engineering, PE68515
19
3
R17,R18,R21
Resistor 82Ω, 5%
20
2
R19,R21
Resistor 62Ω, 5%
21
3
R22,R23,R26
Resistor 130Ω, 5%
22
2
R24,R25
Resistor 300Ω, 5%
Am79C873
41
P R E L I M I N A R Y
NetPHY-1 MII Example Schematic
VCC
VCC
R1
R3
220
COLLED#
GND
LILED
RXLED
TXLED
TXER
TXD3
TXD2
TXD1
TXD0
GND
VCC
TXEN
TXCLK
MDC
MDIO
GND
VCC
RXD3
RXD2
RXD1
RXD0
GND
VCC
RXCLK
CRS
COL
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
U1
COLLED#
DGND
LINKLED
TXLED
RXLED
TXD3
TXER
TXD2
TXD1
TXD0
DGND
DVCC
TXEN
TXCLK
MDC
MDIO
DGND
DVCC
RXD3
RXD2
RXD1
RXD0
GND
VCC
RXCLK
CRS
COL
RXDV
RX_EN
RXER
C1
10u
RXDV
RXER
VCC
R9
10K
GND
R2
1.5K
220
VCC
S1
SW SPST
81
TMODE
82
PHAD0
83
PHAD1
84
PHAD2
85
GND
86
VCC
87
PHAD3
88
PHAD4
89
OPMD0
90
OPMD1
91
OPMD2
92
OPMD3
93
NODEB
94
BPAGN
95
BP45B
96
BPSCR
97
10SER
98
GND
99
GND
100
RESET#
TESTMODE
DVCC
PHYAD0
CLK25M
PHYAD1
LINKSTS
PHYAD2
NC
DGND
DGND
DVCC
RX_LOCK
SPEED10
PHYAD3
Am79C873
NetPHY-1
PHYAD4
OPMODE0
OPMODE1
UTP
TRIDRV
DVCC
OPMODE2
DGND
OPMODE3
DGND
RPTR/NODE#
DGND
BPALIGN
BGRET
BP4B5B
BGRES
BPSCR
AGND
10BTSER
AVCC
AGND
OSC/XTL#
AGND
AGND
49 .9 1% R2 8
VCC
29
TXOP
R2 7
46
SD
45
GND
44
RXLOCK
43
SPEED
42
SIGOK
41
GND
40
VCC
39
GND
38
GND
37
GND
36
35
34
GND
33
32
VCC
31
XTLB
#12
DM9101F
30
27
FXTD+
49 .9 1%
47
X2
26
GND
TXOM
28
25
VCC
GND
24
23
VCC
22
21
20
Y1
R38
TP17
TP18
TP19
GND
Am79C873
62
FXSD
#15
25M
C16
18P
GND
TP15 TP16
FXT D-
R40
130
OSCI/X
AVCC
AVCC
AGND
100TXO-
AVCC
AGND
FXTD
.1u
AVCC
GND
FXTD-
300
FXRD-
CLK25M
C17
18P
GND
Load these components
or OSC1+ R12.
VCC
C26
VCC
48
C16, C17
C23
.1u
FXSD R37
R36
82
GND
42
62
49
*
VCC
49.9 1%
FXRD+
R39
130
18
R35
82
FXSD+
19
R33
R29
49.9 1%
R34
GND
300
R30
130
FXTD
VCC
VCC
TXOP
GND
15
17
14
GND
TXOM
16
13
R32
AGND
AGND
AVCC
AVCC
10TXO+
10TXO-
GND
VCC
R24
82
12
RXIP
C18
.1u
AGND
10
11
FXSD-
RXI+
VCC
VCC
RXIM
GND
9
7
8
6
FXRD-
FXSD+
FXRD+
3
VCC
FXSD-
5
2
4
1
GND
VCC
AGND
RXI-
AVCC
AVCC
AGND
FXRD+
FXRD-
FXSD+
AVCC
R30
370
FXSD-
R24
130
100TXO+
VCC
FDXLED
50
FDXLED#
HFBR5103T
FX1
GND
FXTD+
FXTDVCC_T
VCC_R
FXSD
FXRDFXRD+
GND
9
8
7
6
5
4
3
2
1
P R E L I M I N A R Y
NetPHY-1 MII Example Schematic (Continued)
VCC
D1
LED
D3
LILED
LED
D4
COLLED
LED
D5
FDXLED
R4
MDIO
R5
RXD3
R6
33
R8
33
R7
RXD2
470
D6
D7
6
5
4
3
2
1
LED
D8
LED
D9
LED
D10
33
R13 33
RXCLK
R15
33 R14
33
R16
33
RXER
TP5
VCC
TP6
TP7
GND
LED
R12
RXDV
TP4
470
LED
VCC
BYPASS CAPACITOR FOR U1
R11
RXD0
TP3
RP2
CLK25M
SPEED
33
33 R10
33
SD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
33
RXD1
LED
SIGOK
33
MDC
LED
RXLOCK
VCC
J1
TP2
1
2
3
4
5
6
D2
RXLED
VCC
TP1
RP1
TXLED
TP8
TXER
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND
VCC
MII CON
TXCLK
TXEN
TXD0
#74
C2
#49
#62
C3
.1u
.1u
.1u
#86
#73
#40
C5
C4
C7
.1u
.1u
#61
#52
J2
RJ45
#68
C6
TXD1
.1u
#39
TXD2
1
2
3
4
5
6
7
8
#87
#67
TXD3
Digital Ckt Power & Ground Area
Locate near U1’s VCC & Ground Pins
Physically place caps on SOLDER SIDE.
GND
COL
CRS
R18
R19
Pin 43
(SPEED)
75 1%
D11
TP9
TP10
VCC
LED 100M
820
75 1%
R17
C8
.1u/1KV
R20 Q1
510 2N2222
D12
U2
8
7
LED 10M
6
Pin 36
(BGRET)
Pin 35
(BGRES)
GND
R21
5
5.76K 1%
R23
RX CKT POWER/GROUND AREA
No traces or power near this area
4
75 1%
3
GND
C9 TP11
.1u
TP13
RXIM
2
RXIP
1
TX CKT POWER/GROUND AREA
8
9
7
10
6
11
5
12
4
13
3
14
2
15
1
16
9
GND
10
11
R22
12
13
75 1%
14
15
TXOM
TP12
16
TXOP
TP14
PE68515
Place caps as close as
possible to U1 pins.
(SOLDER SIDE)
C10
C11
C12
.01u #18 .1u #24
#21
C13
.1u
#27
VCC
C14
#31 .01u
#34
#28
#33
.1u
GND
SW1
1
2
3
4
5
6
7
8
RP3
16
15
14
13
12
11
10
9
PHAD0
PHAD1
PHAD2
PHAD3
PHAD4
TMODE
XTLB
8
7
6
5
4
3
2
1
VCC
SW DIP-8
Pin 31
(AGND)
OSC1
*
8
33
14
R25
OUT
NC
+VDD
GND
VCC
7
25M
VCC
* Do Not Load
C19 # 01
C20
#7 C21
.1u
#6 .01u
#8 C22
GND
VCC
10u #100
#11
GND
C24
.1u
C25
10u
L1
1uH
C27
.1u
.1u
SW2
1
2
3
4
5
6
7
8
SW DIP-8
L2
10SER
16 BPSCR
BP45B
15
14 BPAGN
NODEB
13
12
OPMD3
11 OPMD2
OPMD1
10
9
OPMD0
GND
10
9
8
7
6
5
4
3
2
1
RP9_1K
1uH
Advanced Micro Devices
C28
GND
VCC_R
RP4
Place caps close to U1 pins # as shown by number
by each cap. Physically place cap on SOLDER SIDE.
1
RP7_1K
GND
Title
NetPHY-1 Evaluation Board
.1u
GND
Size Document Number
B
netphy1_ev_0
VCC_T
Date: Monday, May 04, 1998
Am79C873
Rev
2.0
Sheet
1
of
1
43
P R E L I M I N A R Y
PHYSICAL DIMENSIONS*
PQR100
HD
D
100
81
1
80
E
F
GE
HE
51
30
31
50
GD
b
GD
c
A
A2
L
L1
A1
See Detail F
Seating Plane
~
~
e
0 ~12
Y
Detail F
*For Reference Only
Symbol
A
A1
A2
b
c
D
E
e
F
GD
GE
HD
HE
L
L1
y
q
Dimensions
In Inches
0.130 Max.
0.004 Min.
0.1120.005
0.012
+0.004
-0.002
0.006
+0.004
-0.002
0.551 ±0.005
0.787 ±0.005
0.026 ±0.006
0.742 NOM.
0.693 NOM.
0.929 NOM.
0.740 ±0.012
0.976 ±0.012
0.047 ±0.008
0.095 ±0.008
0.004 Max.
0∞ ~ 12∞
Notes:
Dimensions In mm
3.30 Max.
0.10 Min.
2.85 ±0.13
0.31
+0.10
-0.05
1. Dimension D & E do not include resin fins.
2. Dimension GD & GE are for PC Board surface
mount pad pitch design reference only.
3. All dimensions are based on metric system.
0.15
+0.10
-0.05
14.00 ±0.13
20.00 ±0.13
0.65 ±0.15
18.85 NOM.
17.60 NOM.
23.60 NOM.
18.80 ±0.31
24.79 ±0.31
1.19 ±0.20
2.41 ±0.20
0.15 Max.
0∞ ~ 12∞
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
NetPHY and PCnet are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
44
Am79C873
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