TEMIC DG403DJ Low-power, high-speed cmos analog switch Datasheet

DG401/403/405
Low-Power, High-Speed CMOS Analog Switches
Features
Benefits
Applications
44-V Supply Max Rating
15-V Analog Signal Range
On-Resistance—rDS(on): 20 Low Leakage—ID(on): 40 pA
Fast Switching—tON: 100 ns
Ultra Low Power
Requirements—PD: 0.35 W
TTL, CMOS Compatible
Single Supply Capability
Wide Dynamic Range
Low Signal Errors and Distortion
Break-Before-Make Switching Action
Simple Interfacing
Audio and Video Switching
Sample-and-Hold Circuits
Battery Operation
Test Equipment
Hi-Rel Systems
PBX, PABX
Description
The DG401/403/405 monolithic analog switches were
designed to provide precision, high performance switching of
analog signals. Combining low power (0.35 W, typ) with
high speed (tON: 100 ns, typ), the DG401 series is ideally
suited for portable and battery powered industrial and military
applications.
Built on the Siliconix proprietary high-voltage silicon-gate
process to achieve high voltage rating and superior
switch on/off performance, break-before-make is guaranteed
for the SPDT configurations. An epitaxial layer prevents
latchup.
Each switch conducts equally well in both directions when on,
and blocks up to 30 V peak-to-peak when off. On-resistance
is very flat over the full 15-V analog range, rivaling JFET
performance without the inherent dynamic range limitations.
The three devices in this series are differentiated by the type
of switch action as shown in the functional block diagrams.
Functional Block Diagrams and Pin Configurations
DG401
DG401
Dual-In-Line and SOIC
D1
S1
NC
IN1
NC
V–
NC
NC
NC
NC
D2
Two SPST Switches per Package
NC
GND
NC
GND
VL
NC
NC
V+
NC
VL
IN2
NC
V+
S2
Truth Table
V–
Logic
Switch
0
OFF
1
ON
Logic “0” 0.8 V
Logic “1” 22.44 V
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70049.
Siliconix
S-53748—Rev. E, 05-Jun-97
1
DG401/403/405
Functional Block Diagrams and Pin Configurations (Cont’d)
DG403
DG403
Dual-In-Line and SOIC
D1
S1
NC IN1
D3
V–
S3
S4
D4
GND
VL
V+
IN2
NC
D2
D3
S3
NC
GND
S2
DG405
DG405
IN1
V–
D3
GND
S3
D2
VL
V+
NC
IN2
D4
SW3, SW4
OFF
ON
1
ON
OFF
Logic “0” 0.8 V
Logic “1”
1 2.4 V
Two DPST Switches per Package
Truth Table
V–
GND
NC
VL
V+
S4
S2
SW1, SW2
0
NC
NC
Logic
S1
2
NC
V
L
V+
D4
S4
Truth Table
V–
S4
D1
D4
Two SPDT Switches per Package
Dual-In-Line and SOIC
S3
D3
Logic
Switch
0
OFF
1
ON
Logic “0” 0.8 V
Logic “1”
1 2.4 V
Siliconix
S-53748—Rev. E, 05-Jun-97
DG401/403/405
Ordering Information
Temp Range
Package
Part Number
DG401
–40 to 85_C
–55 to 125_C
16-Pin Plastic DIP
16-Pin CerDIP
LCC-20
DG401DJ
DG401AK
DG401AK/883
DG401AZ/883
DG403
–40 to 85_C
–55 to 125_C
16-Pin Plastic DIP
DG403DJ
16-Pin Narrow SOIC
DG403DY
16-Pin CerDIP
LCC-20
DG403AK
DG403AK/883
5962-8976301M2A
DG405
–40 to 85_C
–55 to 125_C
16-Pin Plastic DIP
DG405DJ
16-Pin Narrow SOIC
DG405DY
16-Pin CerDIP
LCC-20
DG405AK/883
5962-89961012A
Absolute Maximum Ratings
V+ to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
GND to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND – 0.3 V) to (V+) +0.3 V
Digital Inputsa VS, VD . . . . . . . . . . . . . . . . . (V–) –2 V to (V+ plus 2 V)
or 30 mA, whichever occurs first
Current (Any Terminal) Continuous . . . . . . . . . . . . . . . . . . . . . . 30 mA
Current, S or D (Pulsed 1 ms 10% duty) . . . . . . . . . . . . . . . . . . 100 mA
Storage Temperature
(AK, AZ Suffix) . . . . . . . . . . –65 to 150_C
(DJ, DY Suffix) . . . . . . . . . . . –65 to 125_C
Power Dissipation (Package)b
16-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
16-Pin CerDIPd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW
16-Pin SOICe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mW
LCC-20f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW
Siliconix
S-53748—Rev. E, 05-Jun-97
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V– will be clamped by
internal diodes. Limit forward diode current to maximum current
ratings.
b. All leads welded or soldered to PC Board.
c. Derate 6 mW/_C above 75_C
d. Derate 12 mW/_C above 75_C
e. Derate 7.6 mW/_C above 75_C
f. Derate 13 mW/_C above 75_C
3
DG401/403/405
Specificationsa
Test Conditions
Unless Specified
Parameter
Symbol
A Suffix
D Suffix
–55 to 125_C
–40 to 85_C
V+ = 15 V, V– = –15 V
VL = 5 V, VIN = 2.4 V, 0.8 Vf
Tempb
Room
Full
20
35
45
45
55
Room
Full
3
3
5
3
5
Room
Hot
–0.01
–0.25
–20
0.25
20
–0.5
–5
0.5
5
Room
Hot
–0.01
–0.25
–20
0.25
20
–0.5
–5
0.5
5
Typc
Mind
Maxd Mind Maxd Unit
Analog Switch
Analog Signal Rangee
VANALOG
Full
Drain-Source
On-Resistance
rDS(on)
IS = –10 mA, VD = 10 V
V+ = 13.5 V, V– = –13.5 V
D Drain-Source
On-Resistance
DrDS(on)
IS = –10 mA, VD = 5 V, 0 V
V+ = 16.5 V, V– = –16.5 V
Switch Off
L k
Leakage
C
Current
Channel On
Leakage Current
IS(off)
ID(off)
V+ = 16.5,, V– = –16.5 V
VD = 15.5
15 5 V,
V VS = 15.5
15 5 V
–15
15
–15
15
ID(on)
V+ = 16.5 V, V– = –16.5 V
VS = VD = 15.5 V
Room
Hot
–0.04
–0.4
–40
0.4
40
–1
–10
1
10
Input Current VIN Low
IIL
VIN under test = 0.8 V
All Other = 2.4 V
Full
0.005
–1
1
–1
1
Input Current VIN High
IIH
VIN under test = 2.4 V
All Other = 0.8 V
Full
0.005
–1
1
–1
1
Room
100
150
150
Room
60
100
100
V
W
nA
Digital Control
mA
Dynamic Characteristics
Turn-On Time
tON
Turn-Off Time
tOFF
RL = 300 W , CL = 35 pF
p
S
See Fi
Figure 2
Break-Before-Make
Time Delay (DG403)
tD
RL = 300 W , CL = 35 pF
Room
12
Charge Injection
Q
CL = 10,000 pF
Vgen = 0 V, Rgen = 0 W
Room
60
Room
72
Room
90
Room
12
Room
12
CD, CS(on)
Room
39
Positive Supply Current
I+
Room
Full
0.01
Negative Supply Current
I–
Room
Full
–0.01
Logic Supply Current
IL
Room
Full
0.01
Room
Full
–0.01
Off Isolation Reject Ratio
OIRR
Channel-to-Channel Crosstalk
XTALK
Source Off Capacitance
CS(off)
Drain Off Capacitance
CD(off)
Channel On Capacitance
RL = 100 W , CL = 5 pF
f = 1 MHz
f = 1 MHz, VS = 0 V
5
ns
5
pC
dB
pF
Power Supplies
Ground Current
IGND
V+ = 16.5 V,, V– = –16.5 V
VIN = 0 or 5 V
1
5
–1
–5
1
5
–1
–5
1
5
–1
–5
1
5
–1
–5
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
4
Siliconix
S-53748—Rev. E, 05-Jun-97
mA
DG401/403/405
Typical Characteristics
Input Switching Threshold vs. Logic Supply Voltage
Input Switching Threshold vs. Supply Voltages
10
3.5
V+ = 15 V
V– = –15 V
TA = 25_C
3.0
2.5
6
VIN (V)
VT (V)
8
DG403
SW3, 4
4
VL = 7 V
2.0
1.5
VL = 5 V
1.0
2
0.5
0
(V+) 5
(V–) –5
0
0
2
4
6
8
10
12
14
16
18
20
VL – Logic Supply (V)
10
–10
rDS(on) vs. VD and Temperature
30
125_C
25
85_C
25_C
0_C
15
–40_C
–55_C
–10
–5
35
0
40
0
6 V
TA = 25_C
30
10 V
12 V
20
15 V
20 V
22 V
0
5
10
15
–25
–15
VD – Drain Voltage (V)
–5
5
15
26
VD – Drain Voltage (V)
rDS(on) vs. VD and Power Supply Voltage
(V– = 0 V)
Charge Injection vs. Analog Voltage
200
70
TA = 25_C
180
60
V+ = 15 V, V– = –15 V
VL = 5 V
160
7.5 V
CL = 10 k pF
140
50
120
Q (pC)
rDS(on) – Drain-Source On-Resistance ( 30
0
10
10
–15
25
–5
rDS(on) vs. VD and Power Supply Voltage
V+ = 15 V, V– = –15 V
VL = 5 V
20
20
–10
40
rDS(on) – Drain-Source On-Resistance ( rDS(on) – Drain-Source On-Resistance ( 35
15
–15
10 V
40
12 V
15 V
30
80
100 pF
60
20 V
40
22 V
20
1 k pF
100
20
10
0
0
5
10
15
VD – Drain Voltage (V)
Siliconix
S-53748—Rev. E, 05-Jun-97
20
25
–15
–10
–5
0
5
10
15
VS – Source Voltage (V)
5
DG401/403/405
Typical Characteristics (Cont’d)
Leakage Current vs. Temperature
Leakage Current vs. Analog Voltage
90
100 nA
V+ = 15 V
V– = –15 V
VL = 5 V
VD = 14 V
10 nA
60
30
I S , I D (pA)
I D(off)
1 nA
ID(off)
100 pA
ID(on)
0
ID(off), IS(off)
–30
ID(on)
–60
10 pA
–90
1 pA
V+ = 15 V, V– = –15 V
VL = 5 V, TA = 25_C
For ID(off), VS = 0 V
For IS(off), VD = 0 V
–120
0.1 pA
–55 –35 –15
–150
5
25
45
65
85
–15
105 125
Temperature (_C)
Supply Current vs. Temperature
210
I–
100 p
VS = 10 V
120
90
60
I–
30
45
65
85
VS = –10 V
0
105 125
–55 –35 –15
Switching Time vs. Power Supply Voltage*
270
0V
160
240
–5 V
210
–15 V
VS = 5 V
t ON , t OFF (ns)
t ON , t OFF (ns)
VS = –5 V
120
VS = 5 V
100
80
60
40
VL = 5 V
tON
20
”5
”10
”15
VS = 5 V
–15 V
120
0V
–5 V
0V
–15 V
60
30
tOFF
0
”20
V+, V– Positive and Negative Supplies (V)
*Refer to Figure 2 for test conditions.
6
150
0
0
105 125
180
90
VS = –5 V
5
25 45 65
85
TA – Temperature (_C)
Switching Time vs. Positive Supply Voltage*
300
180
140
VS = –10 V
VS = 10 V
TA – Temperature (_C)
200
15
150
IL
25
10
V+ = 15 V, V– = –15 V, VL = 5 V
tOFF
tON
180
t ON , t OFF (ns)
(A)
I+, I–, I
L
1n
5
5
Switching Time vs. Temperature*
IL
1p
–55 –35 –15
0
240
I+
V+ = 15 V, V– = –15 V
VL = 5 V
10.0 p
–5
VD or VS – Drain or Source Voltage (V)
100 n
10 n
–10
”25
tON
0
5
10
15
tOFF
20
25
V+ – Positive Supply (V)
Siliconix
S-53748—Rev. E, 05-Jun-97
DG401/403/405
Schematic Diagram (Typical Channel)
V+
S
VL
V–
Level
Shift/
Drive
VIN
V+
GND
D
V–
Figure 1.
Test Circuits
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of
the output waveform.
tr <20 ns
3V
tf <20 ns
Logic
50%
+5 V
+15 V
Input
0V
VL
V+
D
S
10 V
VO
IN
GND
RL
1 k
V–
VS
VO
90%
CL
35 pF
0V
Switch
Output
Switch
Input*
–15 V
tON
90%
VO
–VS
*VS = 10 V for tON, VS = –10 V for tOFF
CL (includes fixture and stray capacitance)
RL
VO = VS
tOFF
Switch
Input*
Note: Logic input waveform is inverted for switches that
have the opposite logic sense control
RL + rDS(on)
Figure 2. Switching Time
+5 V
+15 V
VL
VS1
VS2
Logic
Input
V+
S1
D1
S2
VO1
Switch
Output
IN
GND
RL1
V–
RL2
CL2
50%
0V
VS1
VO1
VO2
D2
3V
CL1
Switch
Output
0V
VS2
VO2
0V
90%
90%
tD
tD
–15 V
CL (includes fixture and stray capacitance)
Figure 3. Break-Before-Make
Siliconix
S-53748—Rev. E, 05-Jun-97
7
DG401/403/405
Test Circuits (Cont’d)
Rg
+5 V
+15 V
VL
S
V+
D
DVO
VO
IN
Vg
VO
IN
CL
10 nF
3V
GND
On
On
Off
V–
Q = DVO x CL
–15 V
Figure 4. Charge Injection
+5 V
+15 V
C
C
VL
V+
S
VS
D
Rg = 50 W
C
V–
C
VO
D
Rg = 50 W
RL
100 W
IN
0V, 2.4 V
–15 V
Off Isolation = 20 log
V+
VL
S
VS
GND
+15 V
C
RL
100 W
IN
0V, 2.4 V
+5 V
VO
GND
VS
V–
C
VO
C = RF bypass
–15 V
C = RF bypass
Figure 5. Off Isolation
C
+5 V
VL
S1
VS
+15 V
Figure 6. Insertion Loss
C
+5 V
V+
D
C
Rg = 50 W
C
50 W
VO
+15 V
VL
V+
S
S2
Meter
RL
0.8 V
IN
GND
0 V, 2.4 V
IN
C
V–
D
GND
V–
–15 V
XTALK Isolation = 20 log
C = RF bypass
C
f = 1 MHz
VS
VO
Figure 7. Crosstalk
8
HP4192A
Impedance
Analyzer
or Equivalent
–15 V
Figure 8. Capacitances
Siliconix
S-53748—Rev. E, 05-Jun-97
DG401/403/405
Applications
Left
Source 1
Right
Left
+5 V
+15 V
VL
V+
S1
D1
S3
D3
Left
S2
D2
S4
D4
Right
Integrate/
Reset
TTL
Channel
Select
DG403
GND
VL
V+
S1
D1
S3
D3
+
eout
–
C1
S2
D2
S4
D4
C2
IN2
IN2
TTL
+15 V
IN1
IN1
Source 2
Right
ein
+5 V
V–
Slope
Select
DG403
GND
V–
–15 V
–15 V
Figure 9. Stereo Source Selector
Figure 10. Dual Slope Integrator
Stereo Source Selector:
A single logic signal controls the status of all four switches of
the device, simplifying stereo source switching.
The low on-resistance (<35 ) minimizes total harmonic
distortion.
+5 V
+15 V
VL
V+
S1
D1
S3
D3
IN1
Dual Slope Integrators:
ein
The DG403 is well suited to configure a selectable slope
integrator. One control signal selects the timing capacitor
C1 or C2. Another one selects ein or discharges the capacitor
in preparation for the next integration cycle.
S2
D2
S4
D4
IN2
DG403
Clock
GND
Band-Pass Switched Capacitor Filter:
V–
–15 V
+
Single-pole double-throw switches are a common element
for switched capacitor networks and filters. The fast
switching times and low leakage of the DG403 allow for
higher clock rates and consequently higher filter operating
frequencies.
Siliconix
S-53748—Rev. E, 05-Jun-97
–
eout
Figure 11. Band-Pass Switched Capacitor Filter
9
DG401/403/405
Applications (Cont’d)
Peak Detector:
A3 acting as a comparator provides the logic drive for
operating SW1. The output of A2 is fed back to A3 and
compared to the analog input ein. If ein > eout the output of
A3 is high keeping SW1 closed. This allows C1 to charge
up to the analog input voltage. When ein goes below eout A3
goes negative, turning SW1 off. The system will therefore
store the most positive analog input experienced.
Reset
SW2
–
ein
SW1
R1
A1
+
A2
+
–
+
DG401
eout
C1
A3
–
Figure 12. Positive Peak Detector
10
Siliconix
S-53748—Rev. E, 05-Jun-97