IDT ICS853014 Low skew, 1-to-5, differential-to- 2.5v, 3.3v lvpecl/ecl fanout buffer Datasheet

ICS853014
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
General Description
ICS
HiPerClockS™
Features
The ICS853014 is a low skew, high performance
1-to-5, 2.5V/3.3V Differential-to-LVPECL/ECL
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
IDT. The ICS853014 has two selectable clock
inputs.
Guaranteed output and part-to-part skew characteristics make the
ICS853014 ideal for those applications demanding well defined
performance and repeatability.
•
•
•
Five differential LVPECL/ECL outputs
•
•
•
•
•
Maximum output frequency: > 2GHz
•
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
•
•
Block Diagram
D
Output skew: 13ps (typical)
Part-to-part skew: 60ps (typical)
Propagation delay: 460ps (typical)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q
PCLK0 Pulldown
LE
0
PCLK1 Pulldown
PCLK1 Pullup/Pulldown
PCLKx, PCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Pin Assignment
EN Pulldown
PCLK0 Pullup/Pulldown
Two selectable differential LVPECL clock inputs
1
CLK_SEL Pulldown
Q0
Q0
Q1
Q1
Q2
VBB
Q2
20
19
18
17
16
15
14
13
12
11
VCC
EN
VCC
PCLK1
PCLK1
VBB
PCLK0
PCLK0
CLK_SEL
VEE
ICS853014
Q3
20-Lead TSSOP
Q3
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
Q4
Q4
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
1
2
3
4
5
6
7
8
9
10
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
Q0, Q0
Output
Differential output pair. LVPECL/ECL interface levels.
3, 4
Q1, Q1
Output
Differential output pair. LVPECL/ECL interface levels.
5, 6
Q2, Q2
Output
Differential output pair. LVPECL/ECL interface levels.
7, 8
Q3, Q3
Output
Differential output pair. LVPECL/ECL interface levels.
9, 10
Q4, Q4
Output
Differential output pair. LVPECL/ECL interface levels.
11
VEE
Power
Negative supply pin.
12
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects PCLK1/PCLK1 inputs. When LOW,
selects PCLK0/PCLK0 inputs. LVTTL / LVCMOS interface levels.
13
PCLK0
Input
Pulldown
Non-inverting differential LVPECL clock input.
14
PCLK0
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
15
VBB
Output
16
PCLK1
Input
Pulldown
Non-inverting differential LVPECL clock input.
17
PCLK1
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
18, 20
VCC
Power
19
EN
Input
Bias voltage.
Positive supply pins.
Pulldown
Synchronizing clock enable. When LOW, clock outputs follow clock input.
When HIGH, Qx outputs are forced low, Qx outputs are forced high.
LVTTL/LVCMOS interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
RPULLDOWN
Input Pulldown Resistor
75
kΩ
RVCC/2
Pullup/Pulldown Resistors
50
kΩ
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Test Conditions
2
Minimum
Typical
Maximum
Units
ICS853014BG REV. DNOVEMBER 12, 2007
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
EN
CLK_SEL
Selected Source
Q0:Q4
Q0:Q4
1
0
PCLK0, PCLK0
Disabled; Low
Disabled; High
1
1
PCLK1, PCLK1
Disabled; Low
Disabled; High
0
0
PCLK2, PCLK2
Enabled
Enabled
0
1
PCLK3, PCLK3
Enabled
Enabled
After EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the PCLK0/PCLK0 and PCLK1/PCLK1 inputs as described in Table 3B.
Enabled
Disabled
PCLK0, PCLK1
PCLK0, PCLK1
EN
Q0:Q4
Q0:Q4
Figure 1. EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
PCLK0 or PCLK1
PCLK0 or PCLK1
Q0:Q4
Q0:Q4
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
Non-Inverting
1
0
HIGH
LOW
Differential to Differential
Non-Inverting
0
Biased; NOTE 1
LOW
HIGH
Single-Ended to Differential
Non-Inverting
1
Biased; NOTE 1
HIGH
LOW
Single-Ended to Differential
Non-Inverting
Biased; NOTE 1
0
HIGH
LOW
Single-Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single-Ended to Differential
Inverting
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V (LVPECL mode, VEE = 0V)
Negative Supply Voltage, VEE
-4.6V (ECL mode, VCC = 0V)
Inputs, VI (LVPECL mode)
-0.5V to VCC + 0.5V
Inputs, VI (ECL mode)
0.5V to VEE – 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
VBB Sink//Source, IBB
± 0.5mA
Operating Temperature Range, TA
-40°C to +85°C
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Positive Supply Voltage
IEE
Power Supply Current
Test Conditions
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
4
Minimum
Typical
Maximum
Units
2.375
3.3
3.8
V
85
mA
ICS853014BG REV. DNOVEMBER 12, 2007
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Table 4B. DC Characteristics, VCC = 3.3V; VEE = 0V, TA = -40°C to 85°C
-40°C
Symbol
Parameter
VOH
25°C
80°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
Output High Voltage; NOTE 1
2.175
2.275
2.38
2.225
2.295
2.375
2.22
2.295
2.365
V
VOL
Output Low Voltage; NOTE 1
1.405
1.545
1.68
1.425
1.52
1.615
1.44
1.535
1.63
V
VIH
Input High Voltage (Single-ended)
2.075
2.36
2.075
2.36
2.075
2.36
V
VIL
Input Low Voltage (Single-ended)
1.43
1.765
1.43
1.765
1.43
1.765
V
VBB
Output Voltage Reference;
NOTE 2
1.86
1.98
1.86
1.98
1.86
1.98
V
VCMR
Input High Voltage Common
Mode Range; NOTE 3, 4
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input
High Current
PCLK0, PCLK1
PCLK0, PCLK1
150
µA
Input
Low Current
PCLK0, PCLK1
-10
-10
-10
µA
IIL
PCLK0, PCLK1
-150
-150
-150
µA
150
150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLKx, PCLKx is VCC + 0.3V
.Table 4C. LVPECL DC Characteristics, VCC = 2.5V; VEE = 0V, TA = -40°C to 85°C
-40°C
Symbol
Parameter
VOH
25°C
80°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
Output High Voltage; NOTE 1
1.375
1.475
1.58
1.425
1.495
1.57
1.42
1.495
1.565
V
VOL
Output Low Voltage; NOTE 1
0.605
0.745
0.88
0.625
0.72
0.815
0.64
0.735
0.83
V
VIH
Input High Voltage (Single-ended)
1.275
1.56
1.275
1.56
1.275
1.56
V
VIL
Input Low Voltage (Single-ended)
0.63
0.965
0.63
0.965
0.63
0.965
V
VCMR
Input High Voltage Common
Mode Range; NOTE 2, 3
1.2
2.5
1.2
2.5
1.2
2.5
V
IIH
Input
High Current
PCLK0, PCLK1
PCLK0, PCLK1
150
µA
Input
Low Current
PCLK0, PCLK1
-10
-10
-10
µA
IIL
PCLK0, PCLK1
-150
-150
-150
µA
150
150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, PCLKx is VCC + 0.3V.
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Table 4D. ECL DC Characteristics, VCC = 0V; VEE = -3.8V to -2.375V, TA = -40°C to 85°C
-40°C
Symbol
Parameter
VOH
25°C
80°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
Output High Voltage; NOTE 1
-1.125
-1.025
-0.92
-1.075
-1.005
-0.93
-1.08
-1.005
-0.935
V
VOL
Output Low Voltage; NOTE 1
-1.895
-1.755
-1.62
-1.875
-1.78
-1.685
-1.86
-1.765
-1.67
V
VIH
Input High Voltage
(Single-ended)
-1.225
-0.94
-1.225
-0.94
-1.225
-0.94
V
VIL
Input Low Voltage (Single-ended)
-1.87
-1.535
-1.87
-1.535
-1.87
-1.535
V
VBB
Output Voltage Reference;
NOTE 2
-1.44
-1.32
-1.44
-1.32
-1.44
-1.32
V
VCMR
Input High Voltage Common
Mode Range; NOTE 3, 4
VEE+1.2
0
VEE+1.2
0
VEE+1.2
0
V
IIH
Input
High Current
PCLK0, PCLK1
PCLK0, PCLK1
150
µA
Input
Low Current
PCLK0, PCLK1
-10
-10
-10
µA
IIL
PCLK0, PCLK1
-150
-150
-150
µA
150
150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLKx, PCLKx is VCC + 0.3V
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = -3.8V to -2.375V or , VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
-40°C
Min
Max
Min
Parameter
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
tsk(o)
Output Skew; NOTE 2, 5
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
VPP
Peak-to-Peak Input Voltage;
NOTE 4
150
800
1800
150
800
1800
150
tR / tF
Output
Rise/Fall Time
90
150
210
90
150
210
tS
Clock Enable Setup Time
100
50
100
tH
Clock Enable Hold Time
200
140
200
>2
355
Typ
80°C
Symbol
20% to 80%
Typ
25°C
Max
Min
>2
440
525
13
25
376
Typ
Max
>2
460
550
13
25
GHz
500
595
ps
13
25
ps
130
ps
800
1800
mV
90
150
210
ps
50
100
50
ps
140
200
140
ps
105
400
Units
105
All parameters are measured at f ≤ 1GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: The VCMR and VPP levels should be such that input low voltage never goes below VEE.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Parameter Measurement Information
2V
VCC
VCC
Qx
SCOPE
PCLKx
V
Cross Points
PP
V
CMR
PCLKx
LVPECL
nQx
VEE
VEE
-
-1.8V to -0.375V
LVPECL Output Load AC Test Circuit
Differential Input Level
Qx
Par t 1
Qx
Qx
Qx
Qy
Qy
Par t 2
Qy
Qy
tsk(o)
tsk(pp)
Part-to-Part Skew
Output Skew
PCLKx
80%
PCLKx
80%
VSW I N G
Clock
Outputs
Q0:Q4
20%
20%
tR
Q0:Q4
tF
tPD
Output Rise/Fall Time
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Propagation Delay
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Parameter Measurement Information, continued
PCLKx
PCLKx
t HOLD
EN
t SET-UP
Setup and Hold Time
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
PCLKx
V_REF
C1
0.1u
nPCLKx
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
LVPECL Clock Input Interface
most common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
The PCLK/PCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface
examples for the HiPerClockS PCLK/PCLK input driven by the
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
Zo = 50Ω
R2
50
Zo = 50Ω
PCLK
R1
100
PCLK
Zo = 50Ω
nPCLK
Zo = 50Ω
nPCLK
HiPerClockS
PCLK/nPCLK
CML
HiPerClockS
PCLK/nPCLK
CML Built-In Pullup
Figure 3B. HiPerClockS PCLK/PCLK Input
Driven by a Built-In Pullup CML Driver
Figure 3A. HiPerClockS PCLK/PCLK Input
Driven by an Open Collector CML Driver
3.3V
3.3V
3.3V
3.3V
R3
125
3.3V
3.3V
R4
125
R3
84
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
C1
Zo = 50Ω
C2
R4
84
PCLK
PCLK
Zo = 50Ω
nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R1
84
R2
84
R5
100 - 200
R6
100 - 200
R1
125
Figure 3D. HiPerClockS PCLK/PCLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
Figure 3C. HiPerClockS PCLK/PCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
2.5V
3.3V
3.3V
2.5V
R3
120
HiPerClockS
PCLK/nPCLK
R2
125
3.3V
R4
120
R3
1k
Zo = 50Ω
R4
1k
C1
Zo = 60Ω
PCLK
PCLK
R5
100
Zo = 60Ω
R1
120
R2
120
LVDS
HiPerClockS
PCLK/nPCLK
R1
1k
R2
1k
HiPerClockS
PCLK/nPCLK
Figure 3F. HiPerClockS PCLK/PCLK Input
Driven by a 3.3V LVDS Driver
Figure 3E. HiPerClockS PCLK/PCLK Input
Driven by an SSTL Driver
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
nPCLK
Zo = 50Ω
nPCLK
SSTL
C2
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Recommendations for Unused Output Pins
Inputs:
Outputs:
PCLK/PCLK INPUTS
LVPECL Outputs
For applications not requiring the use of a differential input, both
the PCLK and PCLK pins can be left floating. Though not required,
but for additional protection, a 1kW resistor can be tied from PCLK
to ground. For applications
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and FOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
125Ω
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
Figure 4A. 3.3V LVPECL Output Termination
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
84Ω
Figure 4B. 3.3V LVPECL Output Termination
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Termination for 2.5V LVPECL Outputs
ground level. The R3 in Figure 5B can be eliminated and the
termination is shown in Figure 5C.
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
R1
250
R3
250
50Ω
+
50Ω
+
50Ω
–
50Ω
2.5V LVPECL Driver
–
R1
50
2.5V LVPECL Driver
R2
62.5
R2
50
R4
62.5
R3
18
Figure 5A. 2.5V LVPECL Driver Termination Example
Figure 5B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 5C. 2.5V LVPECL Driver Termination Example
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
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Schematic Example
This application note provides general design guide using
ICS853014 LVPECL buffer. Figure 6 shows a schematic example
of the ICS853014 LVPECL clock buffer. In this example, the input
is driven by an LVPECL driver. CLK_SEL is set at logic high to
select PCLK1/PCLK1 input.
Zo = 50
+
Zo = 50
-
3.3V
R12
1K
3.3V
Zo = 50
3.3V
Zo = 50
C2
LVPECL Driv er
R9
50
R10
50
R2
50
U1
0.1u
11
12
13
14
15
16
17
18
19
3.3V 20
C1
0.1u
VEE
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VCC
nEN
VCC
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
10
9
8
7
6
5
4
3
2
1
R3
50
R7
50
C3
0.1u
Zo = 50
+
Zo = 50
-
ICS853014
R5
50
C5
0.1u
R1
50
R4
50
R11
1K
R6
50
C4
0.1u
Figure 6. ICS853014 Example LVPECL Clock Output Buffer Schematic
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS853014.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS853014 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 85mA = 323mW
•
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.94mW = 154.7mW
Total Power_MAX (3.8V, with all outputs switching) = 323mW + 154.7mW = 477.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming 0 air flow
and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.478W * 66.6°C/W = 116.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
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ICS853014BG REV. DNOVEMBER 12, 2007
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
of VCC – 2V.
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.935V
(VCC_MAX – VOH_MAX) = 0.935V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.67V
(VCC_MAX – VOL_MAX) = 1.67V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
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ICS853014BG REV. DNOVEMBER 12, 2007
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Reliability Information
Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
Transistor Count
The transistor count for ICS853014 is: 373
Pin compatible with MC100LVEP14 and SY100EP14U
Package Outline and Package Dimension
Package Outline - G Suffix for 20 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
20
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
6.90 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
α
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Ordering Information
Table 8. Ordering Information
Part/Order Number
ICS853014BG
ICS853014BGT
ICS853014BGLF
CS853014BGLFT
Marking
ICS853014BG
ICS853014BG
ICS853014BGL
ICS853014BGL
Package
20 Lead TSSOP
20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Revision History Sheet
Rev
B
Table
Page
T4B
4
T4C
5
T4D
5
T4B - T4D
C
C
Date
8
10
3.3V LVPECL table - VOH values changed @ 85° to 2.22V min. and
2.295V typical from 2.295V min. and 2.33V typical.
3.3V LVPECL table - VOH values changed @ 85° to 2.22V min. and
2.295V typical from 2.295V min. and 2.33V typical.
3.3V LVPECL table - VOH values changed @ 85° to 2.22V min. and
2.295V typical from 2.295V min. and 2.33V typical.
Revised LVPECL Output Termination drawings.
Revised Figure 5D.
4-5
LVPECL & ECL tables - deleted VPP row.
9/10/03
3/18/04
6
AC Table - added VPP row and changed max. value from 1200mV to
1800mV.
T9
1
16
Features Section - added Lead-Free bullet.
Ordering Information Table - added Lead-Free part number.
5/13/05
4A
4
Power Supply DC Characteristics Table - changed IEE from 75mA max. to
85mA max.
Updated format throughout the datasheet.
7/6/07
D
d
Description of Change
1
Corrected block diagram.
IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
11/12/07
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ICS853014BG REV. DNOVEMBER 12, 2007
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LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
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