Maxim MAX16997AAUA+ High-voltage watchdog timers with adjustable timeout delay Datasheet

19-4000; Rev 1; 4/09
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
The MAX16997/MAX16998 are microprocessor (µP)
supervisory circuits for high-input-voltage and low-quiescent-current applications. These devices detect
downstream circuit failures and provide switchover to
redundant circuitry. See the Selector Guide for the different versions of this product family.
The MAX16997/MAX16998 family has four independent
inputs for reset and watchdog functions. SWT and SRT
inputs independently set the timeout periods of watchdog and reset timers through external capacitors.
RESETIN/EN monitor voltages at respective inputs. A
resistive voltage-divider sets the reset threshold.
The MAX16998A/B/D generate two output signals,
RESET and ENABLE. RESET asserts whenever
RESETIN drops below its threshold voltage or when the
watchdog timer detects a timing fault at WDI. Once
asserted, and after all reset conditions are removed,
RESET remains low for the reset timeout period, tRESET,
and then goes high. The MAX16997A generates one
output signal (ENABLE) based on the voltage level at
EN and the signal at WDI.
The MAX16997A does not have a RESET output. The
watchdog is disabled if the voltage at EN is below its
threshold. The MAX16997A watchdog timer starts timing when the voltage at EN becomes higher than the
preset threshold voltage level. Each time EN rises
above the preset threshold voltage, the initial watchdog
timeout period is 8 times the normal watchdog timeout
period (tWP).
The MAX16997/MAX16998 are available in 8-pin leadfree µMAX® packages and are fully specified over the
-40°C to +125°C automotive temperature range.
Applications
Features
o Wide 5V to 40V Input Voltage Range
o 18µA Quiescent Current (Typical at +125°C)
o Capacitor-Adjustable Timeout Period for
Watchdog and Reset
o Windowed Watchdog Timer Options
(MAX16998B/D)
o External Voltage Monitoring (RESETIN for the
MAX16998A/B/D and EN for the MAX16997A)
o Car Battery-Compatible EN Input
o TTL- and CMOS-Compatible Open-Drain Outputs
o 18V Maximum Open-Drain Reset Output Voltage
o 28V Maximum Open-Drain Enable Output Voltage
o Power-On/Power-Off Reset Functionality
(MAX16998A/B/D Only)
o AECQ-100 Qualified
o -40°C to +125°C Operating Temperature Range
o Small (3mm x 3mm) µMAX Package
o WDI Narrow Pulse Immunity
Ordering Information
PART
TEMP RANGE
MAX16997AAUA+
-40°C to +125°C
8 µMAX
PIN-PACKAGE
MAX16998AAUA+
-40°C to +125°C
8 µMAX
MAX16998BAUA+
-40°C to +125°C
8 µMAX
MAX16998DAUA+
-40°C to +125°C
8 µMAX
+Denotes a lead(Pb)-free/RoHS-compliant package.
Automotive
Industrial
Selector Guide
PART
WATCHDOG
WINDOW SIZE (%)
ENABLE
RESET
EN
RESETIN
MAX16997A
100
✓
—
✓
—
MAX16998A
100
✓
✓
—
✓
MAX16998B
50
✓
✓
—
✓
MAX16998D
75
✓
✓
—
✓
Pin Configurations appear at end of data sheet.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX16997/MAX16998
General Description
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
ABSOLUTE MAXIMUM RATINGS
Junction-to-Case Thermal Resistance (θJC) (Note 1) ......42°C/W
Junction-to-Ambient Thermal Resistance (θJA ) (Note 1).....206.3°C/W
Operating Temperature Range (TA) ..................-40°C to +125°C
Junction Temperature (TJ) ...............................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
(All pins referenced to GND, unless otherwise noted.)
IN, ENABLE ............................................................-0.3V to +45V
WDI, RESET, EN .....................................................-0.3V to +20V
RESETIN .................................................................-0.3V to +20V
SRT, SWT................................................................-0.3V to +12V
Maximum Current (all pins).................................................30mA
Continuous Power Dissipation (TA = +70°C)
8-Pin µMAX (derate 4.8mW/°C above +70°C) ..........387.8mW
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 14V, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
Operating Voltage Range
VIN
Supply Current
IIN
SWT Ramp Current
SRT Ramp Current
SWT/SRT Ramp Threshold
Voltage
CONDITIONS
MIN
TYP
5.0
MAX
UNITS
40.0
V
TA = -40°C to +85°C
18
30
TA = -40°C to +125°C
18
60
450
500
550
nA
410
500
600
nA
1.115
1.235
1.363
V
IRAMP_SWT VSWT = 1.0V
IRAMP_SRT VSRT = 1.0V
VRAMP
µA
RESET TIMER
Power-On Reset Input Threshold
Voltage
VPON
RESETIN Input Leakage Current
ILPON
RESET Output Low Voltage
VOLRST
VRESETIN rising
1.135
1.255
1.383
VRESETIN falling
1.115
1.235
1.363
VRESETIN = 2V
0.1
0.9
VIN = 1.1V, ISINK = 160µA, RESET asserted
0.4
RESET asserted, ISINK = 0.4mA
ILKGR
VRESET = 20V, RESET not asserted
ENABLE Output Low Voltage
VOLEN
ENABLE asserted, ISINK = 5mA
ILKGE
VENABLE = 14V, ENABLE not asserted
ENABLE Leakage Current
Minimum Reset Timeout Period
Reset Timeout Period
Maximum Reset Time Period
V
0.4
0.1
µA
0.4
V
0.1
µA
tRESETmin
CSRT = 390pF (Note 3)
1
ms
tRESET
CSRT = 2000pF (Note 3)
5
ms
116.09
ms
1.5
µs
1
µs
tRESETmax
RESET to ENABLE Delay
tREDL
RESETIN to RESET Delay
tRRDL
2
µA
RESET asserted, ISINK = 1mA
RESET Leakage Current
V
CSRT = 47nF
RESETIN falling below VPON to RESET
falling edge
_______________________________________________________________________________________
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
MAX16997/MAX16998
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 14V, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
WATCHDOG TIMER
VIH
WDI Input Threshold
2.25
VIL
WDI Input Hysteresis
WDIHYST
WDI Minimum Pulse Width
200
tWDImin
WDI Input Current
(Note 4)
IWDI
Minimum Watchdog Timeout
Watchdog Timeout Period
Maximum Watchdog Timeout
mV
6.5
µs
WDI = 0 or 14V
0.1
µA
tWPmin
CSWT = 680pF (Note 3)
6.8
ms
tWP
CSWT = 1200pF (Note 3)
12
ms
tWPmax
Watchdog Window
V
0.9
CSWT = 22nF
DWDI
217.36
ms
MAX16998B
45
50
55
MAX16998D
67.5
75
82.5
%tWP
WDI to ENABLE Output Delay
Start from WDI third wrong trigger
RESET Pullup Resistor Supply
Voltage
(Note 5)
2.25
2.5
18.00
V
ENABLE Pullup Resistor Supply
Voltage
(Note 5)
2.25
2.5
28.00
V
100
µs
Note 2: RRESET and RENABLE are external pullup resistors for open-drain outputs. Connect RRESET and RENABLE to a minimum 2.5V
voltage. Connect RRESET to a maximum voltage of 18V and connect RENABLE to a maximum voltage of 28V.
Note 3: Calculated based on VRAMP = 1.235V and IRAMP = 500nA.
Note 4: WDI pulses narrower than 1µs will be ignored. WDI pulses wider than 6.5µs will be recognized.
Note 5: Not production tested, guaranteed by design.
Typical Operating Characteristics
(CSWT = CSRT = 1500pF, TA = +25°C, unless otherwise noted.)
WATCHDOG TIMEOUT PERIOD
vs. CSWT
100
10
1
1000
100
10
26
MAX16997/98 toc03
IRAMP = 500nA
RESET AND ENABLE NOT
ASSERTED
24
SUPPLY CURRENT (µA)
1000
10,000
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX16997/98 toc02
IRAMP = 500nA
WATCHDOG TIMEOUT PERIOD (ms)
RESET TIMEOUT PERIOD (ms)
10,000
MAX16997/98 toc01
RESET TIMEOUT PERIOD
vs. CSRT
22
20
18
16
14
12
1
0.1
0.1
1
10
CSRT (nF)
100
1000
10
0.1
1
10
CSWT (nF)
100
1000
0
10
20
30
40
50
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
3
Typical Operating Characteristics (continued)
(CSWT = CSRT = 1500pF, TA = +25°C, unless otherwise noted.)
18.0
17.5
17.0
16.5
16.0
1.25
1.23
1.20
1.15
1.13
1.10
1.35
RISING
1.30
1.25
1.20
FALLING
1.15
1.10
1.05
1.00
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
RESETIN TO RESET DELAY
vs. TEMPERATURE
RESETIN/WATCHDOG PERIOD
vs. SUPPLY VOLTAGE
RESETIN/WATCHDOG PERIOD
vs. SUPPLY VOLTAGE
50mV OVERDRIVE
0.50
0
WATCHDOG TIMEOUT
PERIOD (CSWT = 680pF)
6
5
4
RESET TIMEOUT
PERIOD (CSRT = 680pF)
3
2
1
12
16
20
24
28
32
36
110
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
8
100
90
WATCHDOG TIMEOUT
PERIOD (CSWT = 10nF)
80
70
60
50
RESET TIMEOUT
PERIOD (CSRT = 10nF)
40
30
20
10
4
8
12
16
20
24
28
32
36
40
4
8
12
16
20
24
28
32
36
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
IRAMP
vs. TEMPERATURE
RESET OUTPUT VOLTAGE
vs. SINK CURRENT
ENABLE OUTPUT VOLTAGE
vs. SINK CURRENT
505
500
495
490
485
480
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
475
TEMPERATURE (°C)
0.6
0.5
0.4
0.3
0.2
0
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
0.7
0.1
0.1
470
0.8
40
MAX16997/98 toc12
510
1.0
ENABLE OUTPUT VOLTAGE (V)
515
RESET OUTPUT VOLTAGE (V)
MAX16997/98 toc10
520
40
MAX16997/98 toc09
7
4
RESET/WATCHDOG TIMEOUT PERIOD (ms)
100mV OVERDRIVE
8
MAX16997/98 toc08
RESETIN FROM 2V TO 0V
MAX16997/98 toc07
TEMPERATURE (°C)
0.25
4
1.40
-40 -25 -10 5 20 35 50 65 80 95 110 125
1.00
0.75
1.45
-40 -25 -10 5 20 35 50 65 80 95 110 125
1.50
1.25
FALLING
1.18
15.0
1.75
RISING
1.28
1.50
MAX16997/98 toc06
1.30
15.5
2.00
RESETIN TO RESET DELAY (µs)
1.33
RESETIN/EN THRESHOLD VOLTAGE (V)
18.5
RESET/WATCHDOG TIMEOUT PERIOD (ms)
SUPPLY CURRENT (µA)
19.0
1.35
MAX16997/98 toc05
RESET AND ENABLE NOT
ASSERTED
RESETIN/EN THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX16997/98 toc11
19.5
RESETIN/EN THRESHOLD VOLTAGE (V)
20.0
RESETIN/EN THRESHOLD VOLTAGE
vs. TEMPERATURE
MAX16997/98 toc04
SUPPLY CURRENT
vs. TEMPERATURE
IRAMP (nA)
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
0
0.5
1.0
1.5
2.0
SINK CURRENT (mA)
2.5
3.0
0
5
10
15
20
SINK CURRENT (mA)
_______________________________________________________________________________________
25
30
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
PIN
NAME
FUNCTION
MAX16997A
MAX16998A/B/D
1
1
IN
Power-Supply Input. Bypass IN to GND with a 0.1µF capacitor.
2
—
EN
High-Impedance Input to the Enable Comparator. Depending on the voltage level
at EN, the internal watchdog timer is turned on or off (see the EN Input section).
3, 7
—
N.C.
No Connection. Not internally connected.
Watchdog Timeout Adjustment Input. Connect a capacitor between SWT and GND
to set the basic watchdog timeout period. Connect SWT to ground to disable the
watchdog timer function. See the Selecting the Watchdog Timeout Capacitor
section.
4
4
SWT
5
5
GND
Ground
WDI
Watchdog Input.
MAX16997A/MAX16998A (Timeout Watchdog): Two consecutive WDI falling
edges must occur at WDI within the watchdog timeout period or RESET asserts.
The watchdog timer clears when a falling edge occurs on WDI or whenever RESET
is asserted. ENABLE asserts if three consecutive watchdog timeout periods have
expired without a falling edge at WDI. WDI is a high-impedance input. Leaving
WDI unconnected will cause improper operation of the watchdog timer.
MAX16998B/D (Window Watchdog): WDI falling transitions within periods shorter
than the closed window width or longer than the basic watchdog timeout period
force RESET to assert low for the reset timeout period. The watchdog timer begins
to count after RESET is deasserted. The watchdog timer clears when a WDI falling
edge occurs or whenever RESET is asserted. ENABLE asserts if three consecutive
watchdog timeout periods have expired without a falling edge at WDI. WDI is a
high-impedance input. Leaving WDI unconnected will cause improper operation of
the watchdog timer.
ENABLE
Open-Drain Enable Output. ENABLE asserts when three consecutive WDI faults
occur. ENABLE remains low until three consecutive good WDI falling edges occur.
ENABLE does not assert if the voltage at RESETIN (EN) is below its threshold.
These devices are guaranteed to be in correct ENABLE output logic state when
VIN remains greater than 1.1V.
Reset Input. High-impedance input to the reset comparator. When VRESETIN falls
below 1.235V, RESET asserts. RESET remains asserted as long as VRESETIN is low
and for the reset timeout period after RESETIN goes high. Connect VRESETIN to the
center point of an external resistive divider to set the threshold for the externally
monitored voltage. Connect RESETIN to a defined voltage logic-level.
6
8
6
8
—
2
RESETIN
—
3
SRT
Reset Timeout Adjustment Input. Connect a capacitor between SRT and GND to
set the reset timeout period. See the Selecting the Reset Timeout Capacitor
section.
RESET
Open-Drain Reset Output. RESET asserts whenever RESETIN drops below the
selected reset threshold voltage (VPON). RESET remains low for the reset timeout
period after all reset conditions are removed, and then goes high. RESET asserts
for a period of tRESET whenever a WDI fault occurs. Connect RESET to a pullup
resistor connected to a voltage higher than 2.5V (typ).
—
7
_______________________________________________________________________________________
5
MAX16997/MAX16998
Pin Description
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
MAX16997/MAX16998
Functional Diagram
IN
MAX16997/MAX16998
PREG
RESET
VBG
RESETIN (MAX16998)
EN (MAX16997)
WDI
BUFFER
ENABLE
MAX16997A/
MAX16998A/B/D
LOGIC
IRAMP
VBG
SRT
(MAX16998)
IRAMP
VBG
SWT
GND
6
_______________________________________________________________________________________
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
VEN
VHYST
VPON
tWP
tWD
tWDI
tWP INITIAL
tWP
tWP
tWDI
tWP
tWP
tWDI
tWDI
WDI
1
3
2
1
2
3
ENABLE
tWP INITIAL = WATCHDOG TIMEOUT PERIOD x 8
tWP = WATCHDOG TIMEOUT PERIOD
3 CONSECUTIVE tWP WITHOUT TRIGGER ENABLE GOES LOW
tWDI = WDI TRIGGER PERIOD
3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH
Figure 1. MAX16997A Timing Diagram
VRESETIN
VHYST
VPON
tWP
tWP
tWDI
tRESET
tWDI
tWP
tWDI
tWDI
WDI
tWP
1
1
RESET
2
2
3
3
ENABLE
tRESET = RESET TIMEOUT PERIOD
tWP = WATCHDOG TIMEOUT PERIOD
3 CONSECUTIVE RESETS ENABLE GOES ACTIVE LOW
tWDI = WDI TRIGGER PERIOD
3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH
Figure 2. MAX16998A Timing Diagram
_______________________________________________________________________________________
7
MAX16997/MAX16998
Timing Diagrams
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
MAX16997/MAX16998
Timing Diagrams (continued)
VRESETIN
VHYST
VPON
PROPER WATCHDOG TRIGGER RESETS THE INTERNAL ENABLE COUNTER
tOW
tRESET
tWDI
tCW
tWDI
tWP
tWP
tWP
tWDI
tWDI
WDI
tWP
1
1
2
2
3
3
RESET
ENABLE
tRESET = RESET TIMEOUT PERIOD
tOW = T OPEN WINDOW
3 CONSECUTIVE RESETS ENABLE GOES ACTIVE LOW
tCW = T CLOSED WINDOW
tWP = tCW + tOW
tWDI = WDI TRIGGER PERIOD
3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH
Figure 3. MAX16998B/D Timing Diagram
VRESETIN
VHYST
VPON
tRESET
tRESET
tRESET
tRRDL
RESET
VIN = ENABLE
tWP
tCW ≤ tWDI ≤ tWP
1.1V
tWDI tWDI tWDI tWDI tWDI tWDI ENABLE DOES NOT GET ASSERTED IF THE VOLTAGE
AT RESETIN IS BELOW ITS THRESHOLD.
WDI
tCW
t=0
tWP
THE WATCHDOG TIMER CLEARS
WHENEVER RESET IS ASSERTED.
tWDI tWDI
tCW ≤ tWDI ≤ tWP
tOW
Figure 4. RESETIN, RESET, VIN, ENABLE, and WDI Voltage Monitoring
8
_______________________________________________________________________________________
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
The MAX16997/MAX16998 are µP supervisory circuits
for high-input-voltage and low-quiescent-current applications. These devices improve system reliability by
monitoring the sub-system for software code execution
errors. The MAX16997A/MAX16998A/B/D detect downstream circuit failures, and provide switchover to
redundant circuitry. These devices provide complete
adjustability for reset and watchdog functions.
The MAX16998A/B/D generate two output signals,
RESET and ENABLE, that depend on the voltage level
at RESETIN and the signal at WDI. RESET asserts
whenever RESETIN drops below the selected reset
threshold voltage. RESET remains low for the reset
timeout period after all reset conditions are deasserted,
and then goes high. RESET also asserts for a period of
tRESET whenever a WDI fault occurs. The MAX16997A
generates one output signal (ENABLE) based on the
voltage level at EN and the signal at WDI.
The MAX16997A/MAX16998A provide watchdog timeout adjustability with an external capacitor. The
MAX16998A asserts RESET when two consecutive WDI
falling edges do not occur within the watchdog timeout
period. This device also asserts ENABLE if three consecutive watchdog timeout periods have elapsed without a falling edge at WDI. ENABLE remains low until
three consecutive good WDI falling edges occur.
ENABLE does not assert if the voltage at RESETIN (EN)
is below its threshold. For the MAX16997A, the watchdog timer starts timing if the voltage at EN is higher
than a preset threshold level. Each time the voltage at
EN rises from below to above the preset threshold voltage, the initial watchdog timeout period is 8 times the
normal watchdog timeout period (t WP ). Other than
described above, the MAX16997A behaves the same
as the MAX16998A.
The MAX16998B/MAX16998D contain a window watchdog timer that looks for activity outside an expected
window of operation. The window size is factory-set to
50% (MAX16998B) or 75% (MAX16998D) of the adjusted watchdog timeout period.
Reset Output (RESET) (MAX16998A/B/D)
The reset output is typically connected to the reset
input of the µC to start or restart it in a known state. The
MAX16998A/B/D provide an active-low open-drain
reset logic to prevent code execution errors.
For the MAX16998A/B/D, RESET asserts whenever
RESETIN drops below the selected reset threshold voltage (VPON). RESET remains low for the reset timeout
period after RESETIN exceeds the selected threshold
voltage, and then goes high.
The MAX16998A asserts RESET for a period of tRESET
when two consecutive WDI falling edges do not occur
within the adjusted watchdog timeout period. The
MAX16998B/D also assert RESET for a period of tRESET
when a WDI falling edge does not occur within the
open window period.
Anytime reset asserts, the watchdog timer clears. At
the end of the reset timeout period, RESET goes high,
and the watchdog timer is restarted from zero (see the
Selecting the Watchdog Timeout Capacitor section).
Enable Output (ENABLE)
If the µC fails to operate correctly (e.g., the software
execution is stuck in a loop), WDI does not trigger any
more and RESET pulls low, resetting the µC. If the µC
does not work properly in the next loop either, the
device asserts RESET again. After three watchdog
timeout periods elapse with no falling edges at WDI,
ENABLE asserts and flags a backup circuit that can
take over the operation.
ENABLE remains low until three consecutive WDI
falling edges with periods shorter than the watchdog
timeout occur. ENABLE does not assert if the voltage at
RESETIN (EN) is below its threshold. These devices are
guaranteed to be in correct ENABLE output logic state
when VIN remains greater than 1.1V.
Power-On/Power-Off Sequence
Figure 5 shows the power-up and power-down
sequence for RESET and ENABLE for the
MAX16998A/B/D.
On power-up, once V IN reaches 1.1V, RESET goes
logic-low. As RESETIN rises, RESET remains low. When
RESETIN rises above VPON, the reset timer starts and
RESET remains low. When the reset timeout period
ends, RESET goes high.
On power-down, once RESETIN goes below V PON ,
RESET goes low and remains low until VIN drops below
1.1V. Figure 6 shows the detailed power-up sequence
for the MAX16998A/B/D.
_______________________________________________________________________________________
9
MAX16997/MAX16998
Detailed Description
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
VIN
VIN = 1.1V
VRESETIN
VHYST
VPON
tRESET
tRESET
tRESET
tRESET
RESET
ENABLE
tWP
tWP
tWP
tCW ≤ tWDI ≤ tWP
tWDI tWDI tWDI tWDI tWDI tWDI
WDI
tCW
tWDI tWDI
THE THREE CONSECUTIVE RESET COULD BE CAUSED BY THREE
TIMEOUTS AS SHOWN HERE OR BY THREE WDI FALLING EDGE
OUTSIDE THE OPEN WINDOW, OR A COMBINATION OF ANY RESET
CONDITIONS EXCEPT VRESETIN DROPS TOO LOW.
tWP
tCW ≤ tWDI ≤ tWP
tOW
t=0
RESET
WDI
WDT CLEARS AND
STARTS COUNTING
FROM O
Figure 5. Power-On Reset and Power-Down Reset for the MAX16998A/B/D
VIN = VENABLE
VIN = 1.1V
VPON
VHYST
VRESETIN
tRESET
VRESET
Figure 6. Detailed Power-Up Sequence for the MAX16998A/B/D
10
______________________________________________________________________________________
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
VIN
VCC
MAX16998A/B/D
R1
RESETIN
⎡R
⎤
VTH = VPON ⎢ 1 + 1⎥
⎣ R2
⎦
R2
where VTH is the desired reset threshold voltage, and
V PON = 1.235V. To simplify the resistor selection,
choose a value for R2 (< than 1MΩ) and calculate R1.
⎡ V
⎤
R1 = R2 ⎢ TH − 1⎥
⎣ VPON ⎦
EN Input
The MAX16997A provides a high-impedance input (EN)
to the enable comparator. Based on the voltage level at
EN, the watchdog timer is turned on or off. The watchdog timer starts timing if the voltage level at EN is higher than a preset threshold voltage (VPON). Each time
the voltage at EN rises from below to above the preset
threshold voltage, the initial watchdog timeout period is
8 times the normal watchdog timeout period (tWP).
Watchdog Timer
MAX16997A
The watchdog circuit monitors the µC’s activity. For the
MAX16997A, the watchdog timer starts timing once the
voltage at EN is higher than a preset threshold voltage.
ENABLE asserts if three consecutive watchdog timeout
periods have elapsed without a falling edge at WDI.
ENABLE remains low until three consecutive WDI falling
edges with periods shorter than the watchdog timeout
period occur.
Each time the voltage at EN rises from below to above
the preset threshold voltage, the first watchdog timeout
period extends by a factor of 8 (8 x tWP). If a WDI falling
edge occurs during that time, then the watchdog timeout period is immediately switched over to a single tWP.
If no watchdog falling edge occurs during this prolonged watchdog timeout period, ENABLE goes low at
the end of this period and stays low. After this, the first
falling edge at WDI switches the watchdog timeout
period to a single tWP. See Figure 1. The MAX16997A
watchdog timeout period (tWP) is adjustable by a single
capacitor at SWT.
Figure 7. Setting RESETIN Voltage for the MAX16998A/B/D
MAX16998A
The MAX16998A asserts RESET when two consecutive
WDI falling edges do not occur within the adjusted
watchdog timeout period (tWP). RESET remains asserted for the reset timeout period (tRESET) and then goes
high. This device also asserts ENABLE if three consecutive watchdog timeout periods have elapsed without a
falling edge at WDI. ENABLE remains low until three
consecutive WDI falling edges with periods shorter
than the watchdog timeout period occur (see Figure 2).
The internal watchdog timer is cleared by a RESET rising edge or by a falling edge at WDI. The watchdog
timer remains cleared while RESET is asserted; as soon
as RESET is released, the timer starts counting. WDI
falling edges are ignored when RESET is low. If no WDI
falling edge occurs within the watchdog timeout period,
RESET immediately goes low and stays low for the
adjusted reset timeout period.
MAX16998B/D
The MAX16998B/D have a windowed watchdog timer.
The watchdog timeout period (t WP ) is the sum of a
closed window period (tCW) and an open window period
(tOW). If the µC issues a WDI falling edge within the open
window period, RESET stays high. Once a WDI falling
edge occurs within the closed window period, RESET
immediately goes low and stays low for the adjusted
reset timeout period (see Figure 3). If no WDI falling
edge occurs within the watchdog timeout period, RESET
immediately goes low and stays low for the adjusted
reset timeout period. The open window size is factory-set
to 50% of the watchdog timeout period for the
MAX16998B and 75% for the MAX16998D.
Figure 8 shows a WDI falling edge identified as a good or
a bad WDI signal edge. In case 1, the WDI falling edge
occurs within the closed window period and is considered
a bad WDI falling edge (early fault); therefore, it asserts
RESET. Case 2 also shows another fault. In this case, no
______________________________________________________________________________________
11
MAX16997/MAX16998
RESETIN Input (MAX16998A/B/D)
The MAX16998A/B/D monitor the voltage at RESETIN
using an adjustable reset threshold, set with an external
resistive divider (see Figure 7). RESET asserts when
VRESETIN is below 1.235V.
Use the following equations to calculate the externally
monitored voltage (VCC).
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
WDI falling edge occurs within the watchdog timeout
period (tWP) and is considered a late fault that asserts
RESET. In case 3, the WDI falling edge occurs within the
open window period and is considered a good WDI signal falling edge. In this case, RESET stays high. In case
4, the WDI falling edge occurs within the indeterminate
region. In this case, the RESET state is indeterminate.
These devices assert ENABLE after three consecutive
bad WDI falling edges. ENABLE returns high after three
consecutive good WDI signal falling edges (see Figure 3).
Either a rising edge at RESET or a falling edge at WDI
clears the internal watchdog timer. The watchdog timer
remains cleared while RESET is asserted. The watchdog timer begins counting when RESET goes high.
WDI falling edges are ignored when RESET is low.
Applications Information
Leakage currents and stray capacitance (e.g., a scope
probe, which induces both) at SRT may cause errors in
the reset timeout period. If precise time control is
required, use capacitors with low leakage current and
high stability.
Selecting the Watchdog
Timeout Capacitor
The watchdog timeout period is adjustable to accommodate a variety of µP applications. With this feature,
the watchdog timeout can be optimized for software
execution. The programmer determines how often the
watchdog timer should be serviced. Adjust the watchdog timeout period (tWP) by connecting a capacitor
(C SWT ) between SWT and GND. For normal mode
operation, calculate the watchdog timeout capacitance
using the following equation:
CSWT = t WP ×
Selecting the Reset Timeout Capacitor
The reset timeout period is adjustable to accommodate a
variety of µP applications. Adjust the reset timeout period
(tRESET) by connecting a capacitor (CSRT) between SRT
and ground. See the Reset Timeout Period vs. CSRT
graph in the Typical Operating Characteristics. Calculate
the reset timeout capacitance using the equation below:
I
CSRT = tRESET × RAMP
VRAMP
where VRAMP is in volts, tRESET is in seconds, IRAMP is
in nA, and CSRT is in nF.
where VRAMP is in volts, tWP is in seconds, IRAMP is in nA,
and CSWT is in nF. See the Watchdog Timeout Period vs.
CSWT graph in the Typical Operating Characteristics.
For the MAX16998B/MAX16998D, the open window size
is factory-set to 50% (MAX16998B) or 75% (MAX16998D)
of the watchdog period. Leakage currents and stray
capacitance (e.g., a scope probe, which induces both) at
SWT may cause errors in the watchdog timeout period. If
precise time control is required, use capacitors with low
leakage current and high stability. To disable the watchdog timer function, connect SWT to ground and connect
WDI to either the high- or low-logic state.
(50% or 75%) x tWP
tWDImin
tWDImax
RESET RISING EDGE
CLOSED WINDOW
INDETERMINATE
IRAMP
4 × VRAMP
tWP
OPEN WINDOW
CASE 1 (FAST FAULT)
CASE 2 (SLOW FAULT)
CASE 3 (GOOD WDI)
CASE 4 (INDETERMINATE)
Figure 8. The MAX16998B/D Window Watchdog Diagram
12
______________________________________________________________________________________
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
As shown in Figure 9, the open-drain RESET output can
operate in the 2.5V to 18V range. This allows the device
to interface a µP with other logic levels.
WDI Glitch Immunity
For additional glitch immunity, connect an RC lowpass
filter as close as possible to WDI (see Figure 10).
For example, for glitches with duration of 1µs, a 12kΩ
resistor and a 47pF capacitor will provide immunity.
Layout Considerations
SRT and SWT are connected to internal precision current sources. When developing the layout for the application, minimize stray capacitance attached to SRT
and SWT as well as leakage currents that can reach
those nodes. SRT and SWT traces should be as short
as possible. Route traces carrying high-speed digital
signals and traces with large voltage potentials as far
from SRT and SWT as possible. Leakage currents and
stray capacitance (e.g., a scope probe, which induces
both) at these pins may cause errors in the reset and/or
watchdog timeout period. When evaluating these parts,
use clean prototype boards to ensure accurate reset
and watchdog timeout periods.
5V TO 40V
RESETIN is a high-impedance input and a high-impedance resistive divider (e.g., 100kΩ to 1MΩ) sets the
threshold level. Minimize coupling to transient signals
by keeping the connections to this input short. Any DC
leakage current at RESETIN (e.g., a scope probe)
causes errors in the programmed reset threshold.
Typical Operating Circuits
RESET remains asserted as long as RESETIN is below
the regulated voltage and for the reset timeout period
after RESETIN goes high to assure that the monitored
LDO voltage is settled. Then, the µC starts operating
and triggers WDI.
If the µC fails to operate correctly (e.g., the software
execution is stuck in a loop), the WDI signal does not
trigger the watchdog timer any more, and RESET is
pulled low, resetting the µC. If the µC does not work
properly in the next loop either, the device asserts
RESET again. After three watchdog timeout periods
with no WDI falling edges, ENABLE asserts and flags
backup or safety circuits that take over the operation.
2.5V TO 18V
IN
IN
10kΩ
MAX16998A/B/D
VCC
VCC
MAX16998A/B/D
RESET
RESET
R
µP
I/O
WDI
N
µP
C
GND
GND
Figure 9. Interfacing to Other Voltage Levels
GND
GND
Figure 10. Additional WDI Glitch Immunity Circuit
______________________________________________________________________________________
13
MAX16997/MAX16998
Interfacing to Other Voltages for
Logic Compatibility
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
VBATT
IN
SRT
EN
ENABLE
BACKUP CIRCUITRY,
PERIPHERAL
VCC
5V
REGULATOR
MAX16998A/B/D
VCC
R1
RESET
RESET
RESETIN
µC
R2
SWT
I/O
WDI
GND
GND
Figure 11. MAX16998A/B/D Switch Over to Backup Circuitry
VBATT
BACKUP
CIRCUITRY FLAGS
IN
BACKUP CIRCUITRY,
PERIPHERAL
ENABLE
5V
REGULATOR
VCC
MAX16997A
LDO
R1
µC
EN
R2
RESET
SWT
WDI
WATCHDOG
I/O
5V
I/O
GND
GND
SEPARATE
WATCHDOG
Figure 12. MAX16997A Application Diagram
14
______________________________________________________________________________________
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
TOP VIEW
IN
1
EN
2
N.C.
3
SWT
4
+
MAX16997A
IN
1
N.C.
RESETIN
2
6
WDI
SRT
3
5
GND
SWT
4
8
ENABLE
7
8
MAX16998A/B/D
ENABLE
7
RESET
6
WDI
5
GND
µMAX
µMAX
Package Information
Chip Information
PROCESS: BiCMOS
+
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
8 µMAX
U8-1
21-0036
______________________________________________________________________________________
15
MAX16997/MAX16998
Pin Configurations
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
0
2/08
Initial release
1
3/09
Added bullet to Features section, revised Electrical Characteristics table.
PAGES
CHANGED
—
1, 2, 3
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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