Ultralow Distortion IF Dual VGA AD8376 FEATURES FUNCTIONAL BLOCK DIAGRAM A4 A3 A2 A1 A0 Dual independent digitally controlled VGAs Bandwidth of 700 MHz (−3 dB) Gain range: −4 dB to +20 dB Step size: 1 dB ± 0.2 dB Differential input and output Noise figure: 8.7 dB @ maximum gain Output IP3 of ~50 dBm at 200 MHz Output P1dB of 20 dBm at 200 MHz Dual parallel 5-bit control interface Provides constant SFDR vs. gain Power-down control Single 5 V supply operation 32-lead, 5 mm x 5 mm LFCSP VCCA CHANNEL A GAIN DECODER GNDA AD8376 OPA+ IPA+ OPA+ α POST-AMP OPA– IPA– OPA– VCMA ENBA ENBB VCMB OPB+ IPB+ OPB+ α POST-AMP OPB– IPB– APPLICATIONS OPB– B4 B3 B2 B1 B0 VCCB 06725-001 CHANNEL B GAIN DECODER Differential ADC drivers Main and diversity IF sampling receivers Wideband multichannel receivers Instrumentation GNDB Figure 1. GENERAL DESCRIPTION Each channel of the AD8376 can be individually powered on by applying the appropriate logic level to the ENBA and ENBB power enable pins. The quiescent current of the AD8376 is typically 130 mA per channel. When powered down, the –40 65 –50 60 –60 55 OIP3 –70 50 –80 45 HD2 –90 40 HD3 –100 –110 40 60 80 100 120 140 FREQUENCY (MHz) 35 160 180 30 200 OIP3 (dBm), OUTPUT @ 3dBm/TONE The AD8376 provides a broad 24 dB gain range with 1 dB resolution. The gain of each channel is adjusted through dedicated 5-pin control interfaces and can be driven using standard TTL levels. The open-collector outputs provide a flexible interface, allowing the overall signal gain to be set by the loading impedance. Thus, the signal voltage gain is directly proportional to the load. Fabricated on an Analog Devices, Inc., high speed SiGe process, the AD8376 is supplied in a compact, thermally enhanced, 5 mm × 5mm 32-lead LFCSP package and operates over the temperature range of −40°C to +85°C. 06725-052 Using an advanced high speed SiGe process and incorporating proprietary distortion cancellation techniques, the AD8376 achieves 50 dBm output IP3 at 200 MHz. AD8376 consumes less than 5 mA and offers excellent input-tooutput isolation, lower than −50 dB at 200 MHz. HARMONIC DISTORTION (dBc), OUTPUT @ 2V p-p The AD8376 is a dual channel, digitally controlled, variable gain wide bandwidth amplifier that provides precise gain control, high IP3, and low noise figure. The excellent distortion performance and high signal bandwidth make the AD8376 an excellent gain control device for a variety of receiver applications. Figure 2. Harmonic Distortion and Output IP3 vs. Frequency Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. 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AD8376 TABLE OF CONTENTS Features .............................................................................................. 1 Basic Structure ............................................................................ 12 Applications....................................................................................... 1 Applications..................................................................................... 13 Functional Block Diagram .............................................................. 1 Basic Connections...................................................................... 13 General Description ......................................................................... 1 Single-Ended-to-Differential Conversion............................... 13 Revision History ............................................................................... 2 Broadband Operation................................................................ 15 Specifications..................................................................................... 3 ADC Interfacing ......................................................................... 15 Absolute Maximum Ratings............................................................ 5 Layout Considerations............................................................... 18 ESD Caution.................................................................................. 5 Characterization Test Circuits .................................................. 18 Pin Configuration and Function Descriptions............................. 6 Evaluation Board ........................................................................ 19 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 23 Circuit Description......................................................................... 12 Ordering Guide .......................................................................... 23 REVISION HISTORY 10/10—Rev. 0 to Rev. A Changes to Figure 3 and Table 4..................................................... 6 Changes to Figure 36...................................................................... 14 Added Exposed Pad Notation to Outline Dimensions ............. 23 8/07—Revision 0: Initial Version Rev. A | Page 2 of 24 AD8376 SPECIFICATIONS VS = 5 V, T = 25°C, RS = RL = 150 Ω at 140 MHz, 2 V p-p differential output, both channels enabled, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Slew Rate INPUT STAGE Maximum Input Swing Differential Input Resistance Common-Mode Input Voltage CMRR GAIN Amplifier Transconductance Maximum Voltage Gain Minimum Voltage Gain Gain Step Size Gain Flatness Gain Temperature Sensitivity Gain Step Response OUTPUT STAGE Output Voltage Swing Output Impedance Channel Isolation NOISE/HARMONIC PERFORMANCE 46 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point 70 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point 140 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point 200 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point Conditions Min VOUT < 2 V p-p (5.2 dBm) Pin IPA+ and Pin IPA−, Pin IPB+ and Pin IPB− For linear operation (AV = −4 dB) Differential Max 700 5 120 Gain code = 00000 Gain code = 00000 Gain code = 00000 Gain code ≥ 11000 From gain code = 00000 to 11000 All gain codes, 20% fractional bandwidth for fC < 200 MHz Gain code = 00000 For VIN = 100 mV p-p, gain code = 10100 to 00000 Pin OPA+ and Pin OPA−, Pin OPB+ and Pin OPB− At P1dB, gain code = 00000 Differential Measured at differential output for differential input applied to alternate channel (referred to output) Typ 0.060 0.93 8.5 150 1.85 45.5 0.067 20 −4 0.98 0.18 8 5 Unit MHz V/ns 165 0.074 1.02 V p-p Ω V dB S dB dB dB dB mdB/°C ns 13.1 16||0.8 73 V p-p kΩ||pF dB 8.7 −92 −94 50 21.3 dB dBc dBc dBm dBm 8.7 −89 −95 50 21.4 dB dBc dBc dBm dBm 8.7 −87 −97 51 21.6 dB dBc dBc dBm dBm 8.7 −82 −91 50 20.9 dB dBc dBc dBm dBm Gain code = 00000 VOUT = 2 V p-p VOUT = 2 V p-p 2 MHz spacing, 3 dBm per tone Gain code = 00000 VOUT = 2 V p-p VOUT = 2 V p-p 2 MHz spacing, 3 dBm per tone Gain code = 00000 VOUT = 2 V p-p VOUT = 2 V p-p 2 MHz spacing, 3 dBm per tone Gain code = 00000 VOUT = 2 V p-p VOUT = 2 V p-p 2 MHz spacing, 3 dBm per tone Rev. A | Page 3 of 24 AD8376 Parameter POWER INTERFACE Supply Voltage VCC and Output Quiescent Current with Both Channels Enabled vs. Temperature Power-Down Current, Both Channels vs. Temperature POWER-UP/GAIN CONTROL VIH VIL Logic Input Bias Current Conditions Min Typ Max Unit Thermal connection made to exposed paddle under device 4.5 245 5.0 250 5.5 255 V mA 285 mA mA mA −40°C ≤ TA ≤ +85°C ENBA and ENBB Low −40°C ≤ TA ≤ +85°C Pin A0 to Pin A4, Pin B0 to Pin B4, Pin ENBA, and Pin ENBB Minimum voltage for a logic high Maximum voltage for a logic low 5.4 7 1.6 0.8 900 Table 2. Gain Code vs. Voltage Gain Look-Up Table 5-Bit Binary Gain Code 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 Voltage Gain (dB) +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 5-Bit Binary Gain Code 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 >11000 Rev. A | Page 4 of 24 Voltage Gain (dB) +7 +6 +5 +4 +3 +2 +1 0 −1 −2 −3 −4 −4 V V nA AD8376 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage, VPOS ENBA, ENBB, A0 to A4, B0 to B4 Input Voltage, VIN+, VIN− DC Common Mode VCMA, VCMB Internal Power Dissipation θJA (Exposed Paddle Soldered Down) θJC (At Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V −0.6 V to (VPOS + −0.6 V) −0.15 V to +4.15 V VCMA, VCMB ± 0.25 V ± 6 mA 1.6 W 34.6°C/W 3.6°C/W 140°C −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. A | Page 5 of 24 AD8376 32 31 30 29 28 27 26 25 A1 A0 IPA+ IPA– GNDA VCCA OPA+ OPA– PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR AD8376 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 OPA+ OPA– ENBA GNDA GNDB ENBB OPB– OPB+ 06725-002 B1 B0 IPB+ IPB– GNDB VCCB OPB+ OPB– 9 10 11 12 13 14 15 16 A2 A3 A4 VCMA VCMB B4 B3 B2 NOTES 1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO GROUND. SOLDER TO A LOW IMPEDANCE GROUND PLANE. Figure 3. 32-Lead LFCSP Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13, 20 14 15, 17 16, 18 19 21, 28 22 23, 25 24, 26 27 29 30 31 32 Mnemonic A2 A3 A4 VCMA VCMB B4 B3 B2 B1 B0 IPB+ IPB− GNDB VCCB OPB+ OPB− ENBB GNDA ENBA OPA− OPA+ VCCA IPA− IPA+ A0 A1 Exposed Pad Description MSB − 2 for the Gain Control Interface for Channel A. MSB − 1 for the Gain Control Interface for Channel A. MSB for the 5-Bit Gain Control Interface for Channel A. Channel A Input Common-Mode Voltage. Typically bypassed to ground through capacitor. Channel B Input Common-Mode Voltage. Typically bypassed to ground through capacitor. MSB for the 5-Bit Gain Control Interface for Channel B. MSB − 1 for the Gain Control Interface for Channel B. MSB − 2 for the Gain Control Interface for Channel B. LSB + 1 for the Gain Control Interface for Channel B. LSB for the Gain Control Interface for Channel B. Channel B Positive Input. Channel B Negative Input. Device Common (DC Ground) for Channel B. Positive Supply Pin for Channel B. Should be bypassed to ground using suitable bypass capacitor. Positive Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal. Negative Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal. Power Enable Pin for Channel B. Channel B is enabled with a logic high and disabled with a logic low. Device Common (DC Ground) for Channel A. Power Enable Pin for Channel A. Channel A is enabled with a logic high and disabled with a logic low. Negative Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal. Positive Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal. Positive Supply Pins for Channel A. Should be bypassed to ground using suitable bypass capacitor. Channel A Negative Input. Channel A Positive Input. LSB for the Gain Control Interface for Channel A. LSB + 1 for the Gain Control Interface for Channel A. Internally connected to ground. Solder to a low impedance ground plane. Rev. A | Page 6 of 24 AD8376 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, RS = RL = 150 Ω, 2 V p-p output, maximum gain unless otherwise noted. 1.0 25 20 46MHz, +5V 70MHz, +5V 140MHz, +5V 0.8 0.6 GAIN ERROR (dB) GAIN (dB) 15 10 5 0 0.4 0.2 0 –0.2 –0.4 –0.6 –5 –0.8 15 00101 20 00000 –1.0 –4 11000 Figure 4. Gain vs. Gain Code at 46 MHz, 70 MHz, and 140 MHz 10 5 0 –5 –10 10 100 FREQUENCY (MHz) 1000 20 20 00000 INPUT MAX RATING BOUNDARY 200MHz 140MHz 70MHz 46MHz 15 10 5 0 –4 1 6 11 16 21 GAIN (dB) Figure 8. P1dB vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz 25 25°C 85°C –40°C OP1dB (dBm) 20 15 +25°C +85°C –40°C 10 0 10100 5 10 01111 01010 GAIN CODE 15 00101 20 00000 Figure 6. Gain Error over Temperature at 140 MHz 0 46 100 150 200 250 300 350 FREQUENCY (MHz) 400 450 500 06725-008 5 06725-005 10 9 8 7 6 5 4 3 2 1 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –4 11000 15 00101 25 Figure 5. Gain vs. Frequency Response GAIN ERROR (dB) GAIN (dB) 15 20dB 19dB 18dB 17dB 16dB 15dB 14dB 13dB 12dB 11dB 10dB 9dB 8dB 7dB 6dB 5dB 4dB 3dB 2dB 1dB 0dB –1dB –2dB –3dB –4dB OP1dB (dBm) 20 5 10 01111 01010 GAIN CODE Figure 7. Gain Step Error, Frequency 140 MHz 06725-004 25 0 10100 06725-006 5 10 01111 01010 GAIN CODE 06725-007 0 10100 06725-003 –10 –4 11000 Figure 9. P1dB vs. Frequency at Maximum Gain, Three Temperatures Rev. A | Page 7 of 24 AD8376 55 50 AV = +10dB 50 49 AV = 0dB 60 AV = 20dB 45 OIP3 (dBm) 48 OIP3 (dBm) 65 +25°C 20dB –40°C 20dB +85°C 20dB +25°C 0dB –40°C 0dB +85°C 0dB AV = +20dB 51 47 46 45 AV = –4dB 44 55 40 50 AV = 0dB 35 45 30 40 OIP3 (dBm) 52 43 42 41 70 90 110 130 150 FREQUENCY (MHz) 170 190 210 25 –3 –2 –1 0 1 2 3 4 35 POUT PER TONE (dBm) Figure 13. Output Third-Order Intercept vs. Power, Frequency 140 MHz, Three Temperatures Figure 10. Output Third-Order Intercept at Four Gains, Output Level at 3 dBm/Tone –70 52 51 46MHz 70MHz 140MHz 200MHz –75 50 49 –80 47 AV = 0dB AV = +10dB 46 IMD3 (dBc) AV = +20dB 48 OIP3 (dBm) 5 06725-012 50 06725-009 40 30 45 –85 –90 –95 44 43 –100 AV = –4dB 42 –105 –3 –2 –1 0 1 2 POUT (dBm) 3 4 5 6 Figure 11. Output Third-Order Intercept vs. Power at Four Gains, Frequency 140 MHz 70 –70 65 –75 60 –80 IMD3 (dBc) 55 +25°C 50 –40°C +85°C 45 1 6 11 GAIN (dB) 16 Figure 14. Two-Tone Output IMD vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz, Output Level at 3 dBm/Tone –85 +85°C –90 –40°C –95 –100 35 –105 30 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 –110 40 Figure 12. Output Third-Order Intercept vs. Frequency, Three Temperatures, Output Level at 3 dBm/Tone 60 80 100 120 140 FREQUENCY (MHz) 160 180 Figure 15. Two-Tone Output IMD vs. Frequency, Three Temperatures, Output Level at 3 dBm/Tone Rev. A | Page 8 of 24 200 06725-014 +25°C 40 06725-011 OIP3 (dBm) –110 –4 06725-010 40 –4 06725-013 41 AD8376 –65 –85 HD3 –4dB HD3 0dB HD3 +10dB HD3 +20dB –105 –90 –95 –110 –100 60 80 100 120 140 FREQUENCY (MHz) 160 –105 200 180 –95 –85 –100 –90 –120 –5 –100 –80 –105 –85 HD3_+20dB HD3_+10dB HD3_0dB HD3_–4dB –110 –115 –90 –95 –120 –100 –125 –105 –130 –5 –4 –3 –2 –1 0 1 POUT (dBm) 2 3 4 5 0 1 2 3 4 5 –110 –110 30 25 20 15 46MHz 70MHz 140MHz 200MHz 10 5 0 –4 –2 0 2 4 6 8 10 GAIN (dB) 12 14 16 18 20 Figure 20. NF vs. Gain at 46 MHz, 70 MHz, 140 MHz, and 200 MHz Figure 17. Harmonic Distortion vs. Power at Four Gain Codes, Frequency 140 MHz 45 –70 HD2 +25°C HD3 +25°C HD2 –40°C HD3 –40°C HD2 +85°C HD3 +85°C –80 40 AV = –4dB 35 NOISE FIGURE (dB) –75 –85 –90 –95 –100 30 AV = 0dB 25 20 AV = +10dB 15 10 –105 AV = +20dB 5 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 06725-017 –110 40 –1 35 NOISE FIGURE (dB) –75 –2 40 HARMONIC DISTORTION HD3 (dBc) –95 –3 Figure 19. Harmonic Distortion vs. Power, Frequency 140 MHz, Three Temperatures –65 –70 –4 –105 POUT (dBm) 06725-016 –90 HARMONIC DISTORTION HD2 AND HD3 (dBc) HARMONIC DISTORTION HD2 (dBc) –85 –100 HD3 +25°C –115 –60 HD2_+20dB HD2_+10dB HD2_0dB HD2_–M4dB –95 HD3 +85°C –110 Figure 16. Harmonic Distortion vs. Frequency at Four Gain Codes, VOUT = 2 V p-p –80 HD3 –40°C –105 Figure 18. Harmonic Distortion vs. Frequency, Three Temperatures, VOUT = 2 V p-p 0 0 100 200 300 400 500 600 700 FREQUENCY (MHz) Figure 21. NF vs. Frequency Rev. A | Page 9 of 24 800 900 1000 06725-020 –115 40 –80 HD2 +25°C HARMONIC DISTORTION HD3 (dBc) –95 –90 06725-018 –80 –75 HD2 +85°C 06725-019 –75 –90 –100 –70 –85 HARMONIC DISTORTION HD2 (dBc) –85 –70 HARMONIC DISTORTION HD3 (dBc) –80 –80 HD2 –40°C HD2 –4dB HD2 0dB HD2 +10dB HD2 +20dB 06725-015 HARMONIC DISTORTION HD2 (dBc) –75 AD8376 REF3 POSITION –600mV/DIV REF3 SCALE 500mV 0pF 10pF EACH SIDE INPUT 2 R1 R3 M10.0ns 10.0GS/s IT 10.0ps/pt A CH1 960mV M2.5ns 20.0GS/s IT 10.0ps/pt A CH4 28.0mV REF3 500mV 2.5ns Figure 22. Gain Step Time Domain Response 06725-024 CH1 500mV Ω CH2 500mV Ω 06725-021 1 Figure 25. Pulse Response to Capacitive Loading, Gain 20 dB OUTPUT REF1 POSITION –1.08/DIV REF1 SCALE 50mV RISE (C2) 1.339ns FALL(C2) 1.367ns INPUT 2 2 REF1 CH2 500mV REF1 50.0mV Figure 23. ENBL Time Domain Response INPUT M2.5ns 20.0GS/s IT 10.0ps/pt A CH4 28.0mV 06725-023 R1 R3 R4 2.5ns –590mV 0 180 –5 120 –10 60 –15 0 –20 –60 –25 –120 –30 10 100 FREQUENCY (MHz) Figure 27. S11 vs. Frequency Figure 24. Pulse Response to Capacitive Loading, Gain −4 dB Rev. A | Page 10 of 24 –180 1000 06725-026 S11 MAG (dB) 10pF EACH SIDE REF 1 2.0V A CH2 Figure 26. Large Signal Pulse Response REF1 POSITION –420mV/DIV REF1 SCALE 2V 0pF M2.5ns 20Gsps IT 2.5ps/pt S11 PHASE (Degrees) M20.0ns 10.0GS/s IT 20.0ps/pt A CH1 960mV 06725-022 CH1 500mV Ω CH2 500mV Ω 06725-025 1 AD8376 –10 0 –20 –20 –30 –60 –80 AV = –4dB –40 AV = 0dB –50 –60 –70 –100 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) –90 06725-027 –120 AV = +10dB AV = +20dB –80 0 100 200 300 400 500 600 700 FREQUENCY (MHz) 800 900 1000 06725-032 ISOLATION (dB) S12 (dB) –40 Figure 31. Channel Isolation (Output to Output) vs. Frequency Figure 28. Reverse Isolation vs. Frequency 0 60 –10 50 –20 40 –40 CMRR (dB) ISOLATION (dB) –30 –50 –60 30 20 –70 –80 10 100 FREQUENCY (MHz) 1000 0 06725-028 –100 10 1.00E–09 9.00E–10 0dB, 5V, 25°C +10dB, 5V, 25°C +20dB, 5V, 25°C –4dB, 5V, 25°C 6.00E–10 5.00E–10 4.00E–10 3.00E–10 2.00E–10 1.00E–10 0.00E+00 0 100 200 300 400 500 600 700 FREQUENCY (MHz) 800 900 1000 06725-029 DELAY (Seconds) 7.00E–10 100 200 300 400 500 600 700 FREQUENCY (MHz) 800 900 1000 Figure 32. Common-Mode Rejection Ratio vs. Frequency Figure 29. Off-State Isolation vs. Frequency 8.00E–10 0 Figure 30. Group Delay vs. Frequency at Gain Rev. A | Page 11 of 24 06725-031 –90 AD8376 CIRCUIT DESCRIPTION BASIC STRUCTURE The AD8376 is a dual differential variable gain amplifier with each amplifier consisting of a 150 Ω digitally controlled passive attenuator followed by a highly linear transconductance amplifier. 1/2 AD8376 ATTENUATOR MUX BUFFERS IP+ OP+ gm CORE AMP VCM A0 TO A4 DIGITAL SELECT 06725-033 OP– IP– Figure 33. Simplified Schematic Input System The dc voltage level at the inputs of the AD8376 is set by an internal voltage reference circuit to about 2 V. This reference is accessible at VCMA and VCMB and can be used to source or sink 100 μA. For cases where a common-mode signal is applied to the inputs, such as in a single-ended application, an external capacitor between VCMA/VCMB and ground is required. The capacitor improves the linearity performance of the part in this mode. This capacitor should be sized to provide a reactance of 10 Ω or less at the lowest frequency of operation. If the applied common-mode signal is dc, its amplitude should be limited to 0.25 V from VCMA/VCMB (VCMA or VCMB ± 0.25 V). Each device can be powered down by pulling the ENBA or ENBB pin down to below 0.8 V. In the powered down mode, the total current reduces to 3 mA (typical). The dc level at the inputs and at VCMA/VCMB remains at about 2 V, regardless of the state of the ENBA of ENBB pin. Output Amplifier The gain is based on a 150 Ω differential load and varies as RL is changed per the following equations: Voltage Gain = 20 × (log(RL/150) + 1) The dependency of the gain on the load is due to the opencollector architecture of the output stage. The dc current to the outputs of each amplifier is supplied through two external chokes. The inductance of the chokes and the resistance of the load determine the low frequency pole of the amplifier. The parasitic capacitance of the chokes adds to the output capacitance of the part. This total capacitance in parallel with the load resistance sets the high frequency pole of the device. Generally, the larger the inductance of the choke, the higher its parasitic capacitance. Therefore, the value and type of the choke should be chosen keeping this trade-off in mind. For operation frequency of 15 MHz to 700 MHz driving a 150 Ω load, 1 μH chokes with SRF of 160 MHz or higher are recommended (such as 0805LS-102XJBB from Coilcraft). The supply current of each amplifier consists of about 50 mA through the VCC pin and 80 mA through the two chokes combined. The latter increases with temperature at about 2.5 mA per 10°C. Each amplifier has two output pins for each polarity, and they are oriented in an alternating fashion. When designing the board, care should be taken to minimize the parasitic capacitance due to the routing that connects the corresponding outputs together. A good practice is to avoid any ground or power plane under this routing region and under the chokes to minimize the parasitic capacitance. Gain Control Two independent 5-bit binary codes change each attenuator setting in 1 dB steps such that the gain of each amplifier changes from +20 dB (Code 0) to −4 dB (Code 24 and higher). The noise figure of each amplifier is about 8 dB at maximum gain setting, and it increases as the gain is reduced. The increase in noise figure is equal to the reduction in gain. The linearity of the part measured at the output is first-order independent of the gain setting. From 0 dB to 20 dB gain, OIP3 is approximately 50 dBm into 150 Ω load at 140 MHz (3 dBm per tone). At gain settings below 0 dB, it drops to approximately 45 dBm. and Power Gain = 10 × (log(RL/150) + 2) Rev. A | Page 12 of 24 AD8376 APPLICATIONS BASIC CONNECTIONS +5V VCM 0.1µF Figure 36 shows the basic connections for operating the AD8376. A voltage between 4.5 V and 5.5 V should be applied to the supply pins. Each supply pin should be decoupled with at least one low inductance, surface-mount ceramic capacitor of 0.1 μF placed as close as possible to the device. 150Ω 0.1µF 150Ω 06725-035 5 A0 TO A4 Figure 34. Single-Ended-to-Differential Conversion Featuring ½ of the AD8376 –60 –65 Using a single-ended input decreases the power gain by 3 dB and limits distortion cancellation. Consequently, the secondorder distortion is degraded. The third-order distortion remains low to 200 MHz, as shown in Figure 35. Rev. A | Page 13 of 24 HD2 –70 –75 –80 –85 –90 HD3 –95 –100 0 50 100 FREQUENCY (MHz) 150 Figure 35. Harmonic Distortion vs. Frequency of Single-Ended-to-Differential Conversion 200 06725-036 The AD8376 can be configured as a single-ended input to differential output driver, as shown in Figure 34. A 150 Ω resistor in parallel with the input impedance of input pin provides an impedance matching of 50 Ω. The voltage gain and the bandwidth of this configuration, using a 150 Ω load, remains the same as when using a differential input. 1/2 AD8376 0.1µF 37.5Ω HARMONIC DISTORTION (dBc) SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION 1µH 0.1µF 50Ω AC The outputs of the AD8376 are open collectors that need to be pulled up to the positive supply with 1 μH RF chokes. The differential outputs are biased to the positive supply and require accoupling capacitors, preferably 0.1 μF. Similarly, the input pins are at bias voltages of about 2 V above ground and should be accoupled as well. The ac-coupling capacitors and the RF chokes are the principle limitations for operation at low frequencies. To enable each channel of the AD8376, the ENBA or ENBB pin must be pulled high. Taking ENBA or ENBB low puts the channels of the AD8376 in sleep mode, reducing current consumption to approximately 5 mA per channel at ambient. 1µH 0.1µF AD8376 BALANCED SOURCE RS RS AC 2 2 +VS CHANNEL A PARALLEL CONTROL INTERFACE 0.1µF 0.1µF 0.1µF 10µF 1µH 32 31 30 A1 A0 IPA+ 29 28 27 26 1µH 25 IPA– GNDA VCCA OPA+ OPA– 1 A2 OPA+ 24 2 A3 OPA– 23 3 A4 ENBA 22 0.1µF RL BALANCED LOAD RL BALANCED LOAD 0.1µF 0.1µF 4 VCMA GNDA 21 AD8376 5 VCMB GNDB 20 6 B4 ENBB 19 7 B3 OPB– 18 8 B2 OPB+ 17 0.1µF +VS 0.1µF B1 B0 IPB+ 9 10 11 IPB– GNDB VCCB OPB+ OPB– 12 13 14 15 16 0.1µF 1µH 0.1µF 0.1µF 1µH +VS 0.1µF RS RS AC 2 2 10µF 06725-034 CHANNEL B PARALLEL CONTROL INTERFACE BALANCED SOURCE Figure 36. Basic Connections Rev. A | Page 14 of 24 AD8376 For example, in the extreme case where the load is assumed to be high impedance, RL = ∞, the equation for R1 reduces to R1 = 75 Ω. Using the equation for VR, the applied voltage should be VR = 8 V. The measured single-tone low frequency harmonic distortion for a 2 V p-p output using 75 Ω resistive pull-ups is provided in Figure 38. BROADBAND OPERATION The AD8376 uses an open-collector output structure that requires dc bias through an external bias network. Typically, choke inductors are used to provide bias to the open-collector outputs. Choke inductors work well at signal frequencies where the impedance of the choke is substantially larger than the target ac load impedance. In broadband applications, it may not be possible to find large enough choke inductors that offer enough reactance at the lowest frequency of interest while offering a high enough self resonant frequency (SRF) to support the maximum bandwidth available from the device. The circuit in Figure 37 can be used when frequency response below 10 MHz is desired. This circuit replaces the bias chokes with bias resistors. The bias resistor has the disadvantage of a greater IR drop, and requires a supply rail that is several volts above the local 5 V supply used to power the device. Additionally, it is necessary to account for the ac loading effect of the bias resistors when designing the output interface. Whereas the gain of the AD8376 is load dependent, RL in parallel with R1 + R2 should equal the optimum 150 Ω target load impedance to provide the expected ac performance depicted in the data sheet. Additionally, to ensure good output balance and even-order distortion performance, it is essential that R1 = R2. SET TO 5V 37.5Ω R1 AD8376 37.5Ω 0.1µF 75 × R L HARMONIC DISTORTION (dBc) (1) and VR = R1 × 40 × 10 −3 + 5 5 10 FREQUENCY (MHz) 15 (2) B0 TO B4 5V 5 1/2 37.5Ω 0.1µF 37.5Ω AD8376 5 5V 0.1µF 82Ω 1µH 0.1µF L (SERIES) 0.1µF L (SERIES) 0.1µF 33Ω VIN+ AD9445 33Ω 14 14-BIT ADC VIN– 82Ω 06725-039 50Ω 1µH 0.1µF ETC1-1-13 20 06725-038 0 There are several options available to the designer when using the AD8376. The open-collector output provides the capability of driving a variety of loads. Figure 39 shows a simplified wideband interface with the AD8376 driving a AD9445. The AD9445 is a 14-bit 125 MSPS analog-to-digital converter with a buffered wideband input, which presents a 2 kΩ||3 pF differential load impedance and requires a 2 V p-p differential input swing to reach full scale. Using the formula for R1 (Equation 1), the values of R1 = R2 that provide a total presented load impedance of 150 Ω can be found. The required voltage applied to the bias resistors, VR, can be found by using the VR formula (Equation 2). R L − 150 –92 The AD8376 is a high output linearity variable gain amplifier that is optimized for ADC interfacing. The output IP3 and noise floor essentially remain constant vs. the 24 dB available gain range. This is a valuable feature in a variable gain receiver where it is desirable to maintain a constant instantaneous dynamic range as the receiver gain is modified. The output noise density is typically around 20 nV/√Hz, which is comparable to 14-/16bit sensitivity limits. The two-tone IP3 performance of the AD8376 is typically around 50 dBm. This results in SFDR levels of better than 86 dB when driving the AD9445 up to 140 MHz. Figure 37. Single-Ended Broadband Operation with Resistive Pull-Ups R1 = HD3 –90 ADC INTERFACING RL VR A0 TO A4 –88 Figure 38. Harmonic Distortion vs. Frequency Using Resistive Pull-Ups R2 5 –86 –96 06725-037 0.1µF HD2 –84 –94 0.1µF 1/2 50Ω –82 VR 5V 0.1µF ETC1-1-13 –80 A0 TO A4 Figure 39. Wideband ADC Interfacing Example Featuring ½ of the AD8376 and the AD9445 Rev. A | Page 15 of 24 AD8376 1 0 SNR = 64.93dBc SFDR = 86.37dBc NOISE FLOOR = –108.1dB FUND = –1.053dBFs SECOND = –86.18dBc THIRD = –86.22dBc –10 –20 –30 –40 The addition of the series inductors L (series) in Figure 39 extends the bandwidth of the system and provides response flatness. Using 100 nH inductors as L (series), the wideband system response of Figure 41 is obtained. The wideband frequency response is an advantage in broadband applications such as predistortion receiver designs and instrumentation applications. However, by designing for a wide analog input frequency range, the cascaded SNR performance is somewhat degraded due to high frequency noise aliasing into the wanted Nyquist zone. 0 –1 –2 –3 –4 (dBFS) For optimum performance, the AD8376 should be driven differentially using an input balun or impedance transformer. Figure 39 uses a wideband 1:1 transmission line balun followed by two 37.5 Ω resistors in parallel with the 150 Ω input impedance of the AD8376 to provide a 50 Ω differential terminated input impedance. This provides a wideband match to a 50 Ω source. The open-collector outputs of the AD8376 are biased through the two 1 μH inductors and are ac-coupled to the two 82 Ω load resistors. The 82 Ω load resistors in parallel with the series-terminated ADC impedance yields the target 150 Ω differential load impedance, which is recommended to provide the specified gain accuracy of the device. The load resistors are ac-coupled from the AD9445 to avoid common-mode dc loading. The 33 Ω series resistors help to improve the isolation between the AD8376 and any switching currents present at the analog-to-digital sample and hold input circuitry. –6 –8 –10 20 –70 –80 3 2 –90 + –100 4 5 –130 06725-040 –140 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50 FREQUENCY (MHz) 76 104 132 160 188 216 FREQUENCY (MHz) 244 272 300 Figure 41. Measured Frequency Response of Wideband ADC Interface Depicted in Figure 39 6 –110 –120 0 48 06725-041 –9 –60 (dBFS) FIRST POINT = –2.93dBFs END POINT = –9.66dBFs MID POINT = –2.33dBFs MIN = –9.66dBFs MAX = –1.91dBFs –7 –50 –150 –5 Figure 40. Measured Single-Tone Performance of the Circuit in Figure 39 for a 100 MHz Input Signal The circuit depicted in Figure 39 provides variable gain, isolation, and source matching for the AD9445. Using this circuit with the AD8376 in a gain of 20 dB (maximum gain), an SFDR performance of 86 dBc is achieved at 100 MHz, as indicated in Figure 40. An alternative narrow-band approach is presented in Figure 42. By designing a narrow band-pass antialiasing filter between the AD8376 and the target ADC, the output noise of the AD8376 outside of the intended Nyquist zone can be attenuated, helping to preserve the available SNR of the ADC. In general, the SNR improves several dB when including a reasonable order antialiasing filter. In this example, a low loss 1:3 input transformer is used to match the AD8376’s 150 Ω balanced input to a 50 Ω unbalanced source, resulting in minimum insertion loss at the input. Rev. A | Page 16 of 24 AD8376 at dc, which introduces a zero into the transfer function. In addition, the ac coupling capacitors and the bias chokes introduce additional zeros into the transfer function. The final overall frequency response takes on a band-pass characteristic, helping to reject noise outside of the intended Nyquist zone. Table 5 provides initial suggestions for prototyping purposes. Some empirical optimization may be needed to help compensate for actual PCB parasitics. Figure 42 is optimized for driving some of Analog Devices popular unbuffered ADCs, such as the AD9246, AD9640, and AD6655. Table 5 includes antialiasing filter component recommendations for popular IF sampling center frequencies. Inductor L5 works in parallel with the on-chip ADC input capacitance and a portion of the capacitance presented by C4 to form a resonant tank circuit. The resonant tank helps to ensure the ADC input looks like a real resistance at the target center frequency. Additionally, the L5 inductor shorts the ADC inputs 1:3 1µH 1nF 1nF 1/2 1nF AD8376 5 301Ω L3 C4 C2 165Ω CML L5 165Ω 1µH 1nF L1 AD9246 AD9640 AD6655 L3 06725-042 50Ω L1 A0 TO A4 Figure 42. Narrow-Band IF Sampling Solution for Unbuffered ADC Applications Table 5. Interface Filter Recommendations for Various IF Sampling Frequencies Center Frequency 96 MHz 140 MHz 170 MHz 211 MHz 1 dB Bandwidth 27 MHz 30 MHz 32 MHz 32 MHz L1 390 nH 330 nH 270 nH 220 nH C2 5.6 pF 3.3 pF 2.7 pF 2.2 pF Rev. A | Page 17 of 24 L3 390 nH 330 nH 270 nH 220 nH C4 25 pF 20 pF 20 pF 18 pF L5 100 nH 56 nH 39 nH 27 nH AD8376 +9V LAYOUT CONSIDERATIONS Each amplifier has two output pins for each polarity, and they are oriented in an alternating fashion. When designing the board, care should be taken to minimize the parasitic capacitance due to the routing that connects the corresponding outputs together. A good practice is to avoid any ground or power plane under this routing region and under the chokes to minimize the parasitic capacitance. 96Ω TC3-1T 0.1µF 0.1µF 330Ω 25Ω 1/2 T1 50Ω 96Ω 50Ω AD8376 AC 0.1µF 330Ω 0.1µF 25Ω 06725-051 5 A0 TO A4 Figure 44. Test Circuit for Time Domain Measurements CHARACTERIZATION TEST CIRCUITS Differential-to-Differential Characterization The S-parameter characterization for the AD8376 was performed using a dedicated differential input to differential output characterization board. Figure 45 shows the layout of the characterization board. The board was designed for optimum impedance matching into a 75 Ω system. Because both the input and output impedances of the AD8376 are 150 Ω differentially, 75 Ω impedance runs were used to match 75 Ω network analyzer port impedances. On-board 1 μH inductors were used for output biasing, and the output board traces were designed for minimum capacitance. +5V L1 1µH 75Ω AC 75Ω TRACES AD8376 0.1µF 75Ω 0.1µF 5 A0 TO A4 Figure 43. Test Circuit for S-Parameters on Dedicated 75 Ω Differential-to-Differential Board 06275-044 75Ω 75Ω TRACES 1/2 Figure 45. Differential-to-Differential Characterization Board Circuit Side Layout +5V TC3-1T 50Ω AC L1 1µH C1 0.1µF 1/2 AD8376 T1 C2 0.1µF 5 L2 1µH C3 0.1µF R1 62Ω R4 25Ω ETC1-1-13 PAD LOSS = 11dB C4 0.1µF R2 62Ω R3 25Ω A0 TO A4 Figure 46. Test Circuit for Distortion, Gain, and Noise Rev. A | Page 18 of 24 T2 50Ω 06725-043 AC 0.1µF 0.1µF 06725-050 75Ω L2 1µH AD8376 EVALUATION BOARD Figure 47 shows the schematic of the AD8376 evaluation board. The silkscreen and layout of the component and circuit sides are shown in Figure 48 through Figure 51. The board is powered by a single supply in the 4. 5 V to 5.5 V range. The power supply is decoupled by 10 μF and 0.1 μF capacitors at each power supply pin. Additional decoupling, in the form of a series resistor or inductor at the supply pins, can also be added. Table 6 details the various configuration options of the evaluation board. The output pins of the AD8376 require supply biasing with 1 μH RF chokes. Both the input and output pins must be accoupled. These pins are converted to single-ended with a pair of baluns (Mini-Circuits® TC3-1T+ and M/A-COM ETC1-1-13). The baluns at the input, T1 and T2, are used to transform 50 Ω source impedances to the desired 150 Ω reference levels. The output baluns, T3 and T4, and the matching components are configured to provide 150 Ω to 50 Ω impedance transformations with insertion losses of about 11 dB. Rev. A | Page 19 of 24 Figure 47. AD8376 Evaluation Board Schematic Rev. A | Page 20 of 24 06725-045 VPOS VPOS 1 0 0 1 WB4 WA4 1 0 0 1 WB3 WA3 1 0 0 1 WB2 C12 0.1µF C11 0.1µF WA2 1 0 0 1 27 26 C13 0.1µF 25 AD8376 IPA– GNDA VCCA OPA+ OPA– 28 VPOS C66 0.1µF WB1 INPB 1 WB0 10 0 B0 R3 C61 0.1µF R73 R11 0Ω C3 0.1µF 11 R74 13 C4 0.1µF R4 0Ω T2 TC3-1T+ R75 R12 0Ω 12 INNB VPOS 14 C14 0.1µF 15 16 IPB– GNDB VCCB OPB+ OPB– C64 0.1µF OPB+ 17 8 B2 9 OPB– 18 7 B3 B1 ENBB 19 6 B4 GNDB 20 GNDA 21 4 VCMA 5 VCMB ENBA 22 3 A4 OPA– 23 IPB+ IPA+ 29 C1 0.1µF R9 0Ω R70 INNA 2 A3 A0 A1 30 R71 T1 TC3-1T+ OPA+ 24 31 WA0 32 0 C2 0.1µF R10 0Ω R72 C60 0.1µF R1 0Ω 1 A2 WA1 1 INPA R2 C6 R17 0Ω C65 0.1µF C10 R22 0.1µF 61.9Ω R21 61.9Ω PUB C9 0.1µF L3 1µH R14 0Ω PUA R19 C7 0.1µF 61.9Ω R20 61.9Ω C67 0.1µF C8 0.1µF L1 1µH R15 0Ω R13 0Ω C5 VXB R18 0Ω L4 1µH L2 1µH R16 0Ω VPOS R90 0Ω R91 0Ω VXB VXA VXA R28 30.9Ω R27 R26 30.9Ω VPOS R23 30.9Ω R24 R25 30.9Ω C20 10µF C22 0.1µF C63 0.1µF R63 T4 ETC1-1-13 C62 0.1µF R62 T3 ETC1-1-13 C21 0.1µF VPOS R29 0Ω R32 0Ω R31 VPOS R30 OUTNB OUTPB OUTNA OUTPA AD8376 AD8376 Table 6. Evaluation Board Configuration Options Components C13, C14, C20 to C22, C64 to C67, R90, R91 Function Power Supply Decoupling. Nominal supply decoupling consists a 10 μF capacitor to ground followed by 0.1 μF capacitors to ground positioned as close to the device as possible. T1, T2, C1 to C4, C61, C62, R1 to R4, R9 to R12, R70 to R75 Input Interface. T1 and T2 are 3:1 impedance ratio baluns to transform a 50 Ω single-ended input into a 150 Ω balanced differential signal. R1 and R4 ground one side of the differential drive interface for single-ended applications. R9 to R12 and R70 to R75 are provided for generic placement of matching components. C1 to C4 are dc blocks. Output Interface. C7 to C10 are dc blocks. L1 to L4 provide dc biases for the outputs. R19 to R28 are provided for generic placement of matching components. The evaluation board is configured to provide a 150 Ω to 50 Ω impedance transformation with an insertion loss of about 11 dB. T3 and T4 are 1:1 impedance ratio baluns to transform the balanced differential signals to single-ended signals. R29 and R32 ground one side of the differential output interface for single-ended applications. T3, T4, C7 to C10, L1 to L4, R15 to R32, R62, R63, C62, C63 PUA, PUB, R13, R14, C5, C6 WA0 to WA4, WB0 to WB4 C11, C12 Enable Interface. The AD8376 is enabled by applying a logic high voltage to the ENBA pin for Channel A or the ENBB pin for Channel B. Channel A is enabled when the PUA switch is set in the up position, connecting the ENBA pin to VPOS. Likewise, Channel B is enabled when the PUB switch is set in the up position, connecting the ENBB pin to VPOS. Both channels are disabled by setting the switches to the down position, connecting the ENBA and ENBB pins to GND. Parallel Interface Control. Used to hardwire A0 through A4 and B0 through B4 to the desired gain. The bank of switches WA0 to WA4 set the binary gain code for Channel A. The bank of switches WB0 to WB4 set the binary gain code for Channel B. WA0 and WB0 represent the LSB for each of the respective channels. Voltage Reference. Input common-mode voltage ac-coupled to ground by 0.1 μF capacitors, C11 and C12. Rev. A | Page 21 of 24 Default Conditions C20 = 10 μF (size 3528) C13, C14 = 0.1 μF (size 0402) C21, C22, C64 to C67 = 0.1 μF (size 0603) R90, R91 = 0 Ω (size 0603) T1, T2 = TC3-1+ (Mini-Circuits) C1 to C4, C60, C61 = 0.1 μF (size 0402) R1, R4, R9 to R12 = 0 Ω (size 0402) R2, R3, R70 to R75 = open (size 0402) C7 to C10 = 0.1 μF (size 0402) L1 to L4 = 1 μH (size 0805) T3, T4 = ETC1-1-13 (M/A-COM) R19 to R22 = 61.9 Ω (size 0402) R23, R25, R26, R28 = 30.9 Ω (size 0402) R15 to R18 = 0 Ω (size 0603) R29, R32 = 0 Ω (size 0402) R24, R27, R30, R31, R62, R63 = open (size 0402) C62, C63 = 0.1 μF (size 0402) PUA, PUB = installed R13, R14 = 0 Ω (size 0603) C5, C6 = open (size 0603) WA0 to WA4, WB0 to WB4 = installed C11, C12 = 0.1 μF (size 0402) Figure 48. Component Side Silkscreen Figure 50. Component Side Layout 06725-047 06725-049 \ 06725-048 06725-046 AD8376 Figure 51. Circuit Side Layout Figure 49. Circuit Side Silkscreen Rev. A | Page 22 of 24 AD8376 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 12° MAX 17 16 0.80 MAX 0.65 TYP 0.30 0.23 0.18 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) 9 8 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 1 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 011708-A TOP VIEW 1.00 0.85 0.80 PIN 1 INDICATOR 32 25 24 Figure 52. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model1 AD8376ACPZ-WP AD8376ACPZ-R7 AD8376-EVALZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] , Waffle Pack 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 23 of 24 Package Option CP-32-2 CP-32-2 AD8376 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06725-0-10/10(A) Rev. A | Page 24 of 24