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FAN73894 3-Phase Half-Bridge Gate-Drive IC Features Description Floating Channel for Bootstrap Operation to +600 V Extended Allowable Negative VS Swing to -9.8 V for Signal Propagation at VDD=VBS=15 V Outputs Out of Phase with Input Signals Common-Mode dVs/dt Noise-Canceling Circuit Typically 350 mA/650 mA Sourcing/Sinking Current-Driving Capability for All Channels Over-Current Shutdown Turns Off All Six Drivers Matched Propagation Delay for All Channels 3.3 V and 5.0 V Input Logic Compatible Adjustable Fault-Clear Timing Signal Interlocking of Every Phase to Prevent Cross-Conduction Built-in Advanced Input Filter Built-in Soft Turn-Off Function Built-in Under-Voltage Lockout (UVLO) Functions for All Channels The FAN73894 is a monolithic three-phase half-bridge gate-drive IC designed for high-voltage, high-speed, driving MOSFETs and IGBTs operating up to +600 V. Fairchild’s high-voltage process and common-mode noise-canceling technique provide stable operation of high-side drivers under high-dVs/dt noise circumstances. An advanced level-shift circuit allows high-side gate driver operation up to VS = -9.8 V (typical) for VBS =15 V. The protection functions include under-voltage lockout, inter-lock function and inverter over-current trip with an automatic fault-clear function. Over-current protection that terminates all six outputs can be derived from an external current-sense resistor. An open-drain fault signal is provided to indicate that an over-current or under-voltage shutdown has occurred. The UVLO circuits prevent malfunction when VDD and VBS are lower than the threshold voltage. Output drivers typically source and sink 350 mA and 650 mA, respectively; which is suitable for three-phase half-bridge applications in motor drive systems. 28-SOIC Applications 3-Phase Motor Inverter Driver Industrial Inverter – Sewing Machine, Power Tool Air Conditioner, Washing Machine, Refrigerator, Dish Washer General-Purpose Three-Phase Inverter Ordering Information Part Number (1) FAN73894MX Package 28-Lead, Small Outline Integrated Circuit, (SOIC) Operating Temperature Packing Method -40 to +125°C Tape & Reel Note: 1. These devices passed wave-soldering test by JESD22A-111. © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 www.fairchildsemi.com FAN73894 — 3-Phase Half-Bridge Gate-Drive IC January 2016 FAN73894 — 3-Phase Half-Bridge Gate-Drive IC Typical Application Diagram VDD VMOTOR VDD VB1 28 2 HIN1 HO1 27 Uup UL 3 HIN2 VS1 26 VS1 VU 4 HIN3 NC 25 UL 5 LIN1 VB2 24 WU 6 LIN2 WL 7 LIN3 8 FO 9 CS Uup CONTROL FAN73894 3-Phase BLDC Motor Controller 1 UU HO2 23 Vup VS2 22 VS2 NC 21 VB3 20 10 EN 11 RCIN 12 VSS NC 17 13 COM LO1 16 14 LO3 LO2 15 Vup Wup VS1 U 3-Phase Inverter V VS2 HO3 19 Wup VS3 18 VS3 CRCIN W VS3 Udn Vdn Udn Vdn Wdn Wdn RCS Figure 1. 3-Phase BLDC Motor Drive Application Internal Block Diagram VB1 50K HIN1 UVLO HIN2 10K 50K INPUT NOISE FILTER {TFLTIN=250ns} Q S HO1 VS1 VDD 10K UVLO SHOOT THOUGH PREVENTION ULIN VSS-COM LEVELSHIFTER DRIVER LIN1 R R VDD HIN3 50K NOISE CANCELLER DRIVER UHIN 50K PULSE GENERATOR 10K DELAY LO1 10K 50K LIN2 COM DEAD-TIME {DT=320ns} U Phase Driver UVLO ISOFT 10K 10K VB2 VDD 50K LIN3 VHIN ENABLE INPUT FILTER {TFLTEN=250ns} VH V Phase Driver VLIN VS2 LO2 FO COM ISOFT VSS EN VB3 VDD LEB WHIN WLIN HO3 W Phase Driver VS3 ENABLE 150K LO3 COM ISOFT VDD_UVLO SOFT-OFF VREF CS iRCIN VRCIN,TH = 3.3V VRCIN,HYS= 0.7V RCIN CS_COMP Q LATCH S LEB R 100K 0.5V 3.3V Protection Circuit Figure 2. Functional Block Diagram © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 www.fairchildsemi.com 2 FAN73894 — 3-Phase Half-Bridge Gate-Drive IC 17 NC 16 LO1 12 13 14 VSS COM LO3 15 LO2 18 VS3 11 RCIN 19 HO3 10 EN 20 VB3 21 NC 22 VS2 23 HO2 24 VB2 25 NC 26 VS1 27 HO1 28 VB1 Pin Configuration 6 7 8 9 LIN3 FO CS 4 HIN3 LIN2 3 HIN2 5 2 HIN1 LIN1 1 VDD FAN73894MX Figure 3. Pin Assignments Pin Definitions Pin Name Description 1 VDD Logic and low-side gate driver power supply voltage 2 HIN1 Logic Input 1 for high-side gate 1 driver 3 HIN2 Logic Input 2 for high-side gate 2 driver 4 HIN3 Logic Input 3 for high-side gate 3 driver 5 LIN1 Logic Input 1 for low-side gate 1 driver 6 LIN2 Logic Input 2 for low-side gate 2 driver 7 LIN3 Logic Input 3 for low-side gate 3 driver 8 Fault output with open drain (indicates over-current and low-side under-voltage) 9 FO CS 10 EN Logic input for shutdown functionality 11 RCIN Analog input for over-current shutdown An external RC network input used to define the fault-clear delay 12 VSS 13 COM Logic ground Low-side driver return 14 LO3 Low-side gate driver 3 output 15 LO2 Low-side gate driver 2 output 16 LO1 Low-side gate driver 1 output 17, 21, 25 NC No connect 18 VS3 High-side driver 3 floating supply offset voltage 19 HO3 High-side driver 3 gate driver output 20 VB3 High-side driver 3 floating supply 22 VS2 High-side driver 2 floating supply offset voltage 23 HO2 High-side driver 2 gate driver output 24 VB2 High-side driver 2 floating supply 26 VS1 High-side driver 1 floating supply offset voltage 27 HO1 High-side driver 1 gate driver output 28 VB1 High-side driver 1 floating supply © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 www.fairchildsemi.com 3 Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified. Symbol Parameter Min. Max. Unit VS High-Side Floating Offset Voltage VB1,2,3-25 VB1,2,3+0.3 V VB High-Side Floating Supply Voltage -0.3 625.0 V VDD Low-Side and Logic-Fixed supply voltage -0.3 25.0 V VHO High-Side Floating Output Voltage VHO1,2,3 VS1,2,3-0.3 VB1,2,3+0.3 V VLO Low-Side Floating Output Voltage VLO1,2,3 -0.3 VDD+0.3 V VSS - 0.3 VSS + 5.5 V -0.3 VDD+0.3 V ±50 V/ns 1.4 W 70 °C/W 150 °C 150 °C VIN Input Voltage ( HINx , LINx , CS, and EN) VFO Fault Output Voltage ( FO ) dVS/dt (2) Allowable Offset Voltage Slew Rate (3,4) PD Power Dissipation θJA Thermal Resistance TJ Junction Temperature TSTG Storage Temperature -55 Notes: 2. All input voltage ( HINx , LINx , CS, and EN) are referenced to VSS and do not exceed maximum voltage rating. 3. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). Refer to the following standards: JESD51-2: Integral circuit’s thermal test method environmental conditions, natural convection; JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages. 4. Do not exceed maximum power dissipation (PD) under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VB1,2,3 High-Side Floating Supply Voltage VS1,2,3 High-Side Floating Supply Offset Voltage VDD Low-Side and Logic Fixed Supply Voltage Min. Max. Unit VS1,2,3+10 VS1,2,3+20 V 6-VDD 600 V 12 20 V VHO1,2,3 High-Side Output Voltage VS1,2,3 VB1,2,3 V VLO1,2,3 Low-Side Output Voltage COM VDD V VFO Fault Output Voltage ( FO ) VSS VDD V VCS Current-Sense Pin Input Voltage VSS VSS + 5 V VIN Logic Input Voltage ( HIN1,2,3 and LIN1,2,3 ) VSS VSS + 5 V VSS Logic Ground -5 5 V TA Ambient Temperature -40 +125 °C © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 www.fairchildsemi.com 4 FAN73894 — 3-Phase Half-Bridge Gate-Drive IC Absolute Maximum Ratings VBIAS (VDD, VBS1,2,3) = 15.0 V and TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to VSS and are applicable to all six channels. The VO and IO parameters are referenced to VS1,2,3 and COM and are applicable to the respective output leads: HO1,2,3 and LO1,2,3. The V DDUV parameters are referenced to VSS. The VBSUV parameters are referenced to VS1,2,3. Symbol Parameter Condition Min. Typ. Max. Unit Low-Side Power Supply Section IQDD Quiescent VDD Supply Current VLIN1,2,3=5 V or open, EN=0 V 250 400 A IPDD Operating VDD Supply Current fLIN1,2,3=20 kHz, rms Value 550 750 A VDDUV+ VDD Supply Under-Voltage Positive-Going Threshold VDD=Sweep 9.7 11.0 12.0 V VDDUV- VDD Supply Under-Voltage Negative-Going Threshold VDD=Sweep 9.2 10.5 11.4 V VDDHYS VDD Supply Under-Voltage Lockout Hysteresis VDD=Sweep 0.5 V Bootstrapped Power Supply Section VBSUV+ VBS Supply Under-Voltage Positive-Going Threshold VBS1,2,3=Sweep 9.7 11.0 12.0 V VBSUV- VBS Supply Under-Voltage Negative-Going Threshold VBS1,2,3=Sweep 9.2 10.5 11.4 V VBSHYS VBS Supply Under-Voltage Lockout Hysteresis VBS1,2,3=Sweep ILK Offset Supply Leakage Current VB1,2,3=VS1,2,3=600 V IQBS Quiescent VBS Supply Current VHIN1,2,3=0 V or 5 V, EN=0 V 10 IPBS Operating VBS Supply Current fHIN1,2,3=20 kHz, rms Value 200 0.5 V 10 A 50 80 A 320 480 A Gate Driver Output Section VOH High-Level Output voltage, VBIAS-VO IO=0 mA (No Load) 100 mV VOL Low-Level Output voltage, VO IO=0 mA (No Load) 100 mV IO+ Output HIGH Short-Circuit Pulse Current IO- Output LOW Short-Circuit Pulsed Current VS Allowable Negative VS Pin Voltage for HIN Signal Propagation to HO (5) (5) VO=0 V, VIN=0 V with PW10 µs 250 350 mA VO=15 V, VIN=5 V with PW10 µs 500 650 mA -9.8 -9.0 V Logic Input Section VIH Logic "0" Input Voltage HIN1,2,3 , LIN1,2,3 VIL Logic "1" Input Voltage HIN1,2,3 , LIN1,2,3 2.5 IIN+ Logic Input Bias Current (HO=LO=HIGH) VIN=0 V IIN- Logic Input Bias Current (HO=LO=LOW) VIN=5 V RIN Logic Input Pull-Up Resistance 77 35 V 0.8 V 100 143 A 8.5 25.0 A 50 65 K Enable Control Section (EN) VEN+ Enable Positive-Going Threshold Voltage VEN- Enable Negative-Going Threshold Voltage IEN+ Logic Enable “1” Input Bias Current VEN=5 V (Pull-Down=150K) IEN- Logic Enable “0” Input Bias Current VEN=0 V REN Logic Input Pull-Down Resistance © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 2.5 15 100 V 33 150 0.8 V 50 A 2 A 333 K www.fairchildsemi.com 5 FAN73894 — 3-Phase Half-Bridge Gate-Drive IC Electrical Characteristics VBIAS (VDD, VBS1,2,3) = 15.0 V and TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to VSS and are applicable to all six channels. The VO and IO parameters are referenced to VS1,2,3 and COM and are applicable to the respective output leads: HO1,2,3 and LO1,2,3. The V DDUV parameters are referenced to VSS. The VBSUV parameters are referenced to VS1,2,3. Symbol Parameter Condition Min. Typ. Max. Unit Over-Current Protection Section VCSTH+ Over-Current Detect Positive Threshold VCSTH- Over-Current Detect Negative Threshold 440 mV VCSHYS Over-Current Detect Hysteresis 60 mV ICSIN Short-Circuit Input Current ISOFT Soft Turn-Off Sink Current 450 VCSIN=1 V 500 550 mV 5 10 15 A 25 40 55 mA 2.7 3.3 3.9 V Fault Output Section VRCINTH+ RCIN Positive-Going Threshold Voltage VRCINTH- RCIN Negative-Going Threshold Voltage VRCINHYS RCIN Hysteresis Voltage (5) 2.6 (5) 0.7 IRCIN RCIN Internal Current Source CRCIN=2 nF VFOL Fault Output Low Level Voltage VCS=1 V, IFO=1.5 mA RCIN On Resistance IRCIN=1.5 mA Fault Output On Resistance IFO=1.5 mA RDSRCIN RDSFO V 3 V 5 7 µA 0.2 0.5 V 50 75 100 90 130 170 Note: 5. These parameters are guaranteed by design. Dynamic Electrical Characteristics TA=25C, VBIAS (VDD, VBS1,2,3) =15.0 V,VS1,2,3 =COM=VSS, CRCIN=2 nF, and CLoad = 1000 pF unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit tON Turn-On Propagation Delay VLIN1,2,3=VHIN1,2,3=0 V, VS1,2,3=0 V 350 500 650 ns tOFF Turn-Off Propagation Delay VLIN1,2,3=VHIN1,2,3=5 V, VS1,2,3=0 V 350 500 650 ns tR Turn-On Rise Time VLIN1,2,3=VHIN1,2,3=0 V 20 50 100 ns tF Turn-Off Fall Time VLIN1,2,3=VHIN1,2,3=5 V 10 30 80 ns tEN Enable LOW to Output Shutdown Delay 400 500 600 ns tCSBLT CS Pin Leading-Edge Blanking Time 400 650 850 ns tCSFO Time from CS Triggering to FO From VCSC=1 V to FO Turn-Off 850 1300 ns tCSOFF Time from CS Triggering to Low-Side Gate Outputs Turn-Off From VCSC=1 V to Starting Gate Turn-Off 850 1300 ns tFLTIN Input Filtering Time 250 330 ns 1.30 2.35 ms 320 tFLTCLR DT MDT MT PM (6) ( HINx , LINx ,,EN) Fault-Clear Time 170 CRCIN = 2 nF Dead Time 400 ns Dead-Time Matching (All Six Channels) 50 ns Delay Matching (All Six Channels) 50 ns 100 ns Output Pulse-Width Matching 230 (7) PW IN > 1 µs 50 Notes: 6. The minimum width of the input pulse should exceed 500 ns to ensure the filtering time of the input filter is exceeded. 7. PM is defined as PW IN-PW OUT. © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 www.fairchildsemi.com 6 FAN73894 — 3-Phase Half-Bridge Gate-Drive IC Electrical Characteristics 650 600 600 550 550 tOFF [ns] tON [ns] 650 500 450 450 400 350 -40 500 400 High-Side Low-Side -20 0 20 40 60 80 100 350 -40 120 High-Side Low-Side -20 0 Temperature [°C] 100 100 90 90 80 80 70 70 60 50 80 100 120 50 40 30 30 20 20 High-Side Low-Side 10 -20 0 20 40 60 80 100 High-Side Low-Side 10 0 -40 120 -20 0 Temperature [°C] 20 40 60 80 100 120 Temperature [°C] Figure 6. Turn-On Rise Time vs. Temperature Figure 7. Turn-Off Fall Time vs. Temperature 600 2.0 1.8 tFLTCLR [ms] 550 tEN [ns] 60 60 40 500 450 400 -40 40 Figure 5. Turn-Off Propagation Delay vs. Temperature tF [ns] tR [ns] Figure 4. Turn-On Propagation Delay vs. Temperature 0 -40 20 Temperature [°C] 1.6 1.4 1.2 -20 0 20 40 60 80 100 1.0 -40 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 8. Enable LOW to Output Shutdown Delay vs. Temperature © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 -20 Figure 9. Fault-Clear Time vs. Temperature www.fairchildsemi.com 7 FAN73894 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics 50 350 25 MDT [ns] DT [ns] 400 300 250 0 -25 DT1 DT2 200 -40 -20 0 20 40 60 80 100 -50 -40 120 -20 0 Temperature [°C] Figure 10. Dead Time vs. Temperature 40 60 80 100 120 Figure 11. Dead-Time Matching vs. Temperature -7 50 40 MTON MTOFF 30 -8 20 -9 VS [V] Delay Matching [ns] 20 Temperature [°C] 10 0 -10 -10 -11 -20 -30 -12 -40 -50 -40 -20 0 20 40 60 80 100 -13 -40 120 -20 0 Temperature [°C] 20 40 60 80 100 120 Temperature [°C] Figure 12. Delay Matching vs. Temperature Figure 13. Allowable Negative VS Voltage vs. Temperature 400 100 350 80 IQBS [A] IQDD [A] 300 250 200 60 40 150 20 100 50 -40 -20 0 20 40 60 80 100 0 -40 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 14. Quiescent VDD Supply Current vs. Temperature © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 -20 Figure 15. Quiescent VBS Supply Current vs. Temperature www.fairchildsemi.com 8 FAN73894 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics (Continued) 700 600 600 500 500 IPBS [A] IPDD [A] 700 400 400 300 300 200 200 100 -40 -20 0 20 40 60 80 100 100 -40 120 -20 0 Temperature [°C] 12.0 11.5 11.5 11.0 11.0 10.5 80 100 120 10.0 -20 0 20 40 60 80 100 9.5 -40 120 -20 0 20 40 60 80 100 120 Temperature [°C] Figure 18. VDD UVLO+ vs. Temperature Figure 19. VDD UVLO- vs. Temperature 12.0 11.5 11.5 11.0 VBSUV- [V] VBSUV+ [V] 60 10.5 Temperature [°C] 11.0 10.5 10.0 -40 40 Figure 17. Operating VBS Supply Current vs. Temperature VDDUV- [V] VDDUV+ [V] Figure 16. Operating VDD Supply Current vs. Temperature 10.0 -40 20 Temperature [°C] 10.5 10.0 -20 0 20 40 60 80 100 9.5 -40 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 20. VBS UVLO+ vs. Temperature © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 -20 Figure 21. VBS UVLO- vs. Temperature www.fairchildsemi.com 9 FAN73894 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics (Continued) 100 100 High-Side Low-Side 60 40 High-Side Low-Side 80 VOL [mV] VOH [mV] 80 20 60 40 20 0 -40 -20 0 20 40 60 80 100 0 -40 120 -20 0 Temperature [°C] Figure 22. High-Level Output Voltage vs. Temperature 40 60 80 100 120 Figure 23. Low-Level Output Voltage vs. Temperature 3.0 3.0 2.5 VIL [V] 2.5 VIH [V] 20 Temperature [°C] 2.0 2.0 1.5 1.5 1.0 1.0 -40 -20 0 20 40 60 80 100 0.5 -40 120 -20 0 Temperature [°C] 20 40 60 80 100 120 Temperature [°C] Figure 24. Logic HIGH Input Voltage vs. Temperature Figure 25. Logic LOW Input Voltage vs. Temperature 160 20 18 140 16 IIN- [A] IIN+ [A] 14 120 100 12 10 8 6 80 4 2 60 -40 -20 0 20 40 60 80 100 0 -40 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 26. Logic Input HIGH Bias Current vs. Temperature © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 -20 Figure 27. Logic Input LOW Bias Current vs. Temperature www.fairchildsemi.com 10 FAN73894 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics (Continued) 200 80 180 REN [K] RIN [K] 100 60 40 20 0 10 160 140 120 12 14 16 18 100 10 20 12 14 Supply Voltage [V] 16 18 20 Supply Voltage [V] Figure 28. Input Pull-Down Resistance vs. Supply Voltage Figure 29. Enable Pin Pull-Down Resistance vs. Supply Voltage 400 100 350 80 IQBS [A] IQDD [A] 300 250 200 60 40 150 20 100 50 10 12 14 16 18 0 10 20 12 14 Supply Voltage [V] 700 700 600 600 500 500 400 300 200 200 16 18 100 12 20 Supply Voltage [V] 14 16 18 20 Supply Voltage [V] Figure 32. Operating VDD Supply Current vs. Supply Voltage © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 20 400 300 14 18 Figure 31. Quiescent VBS Supply Current vs. Supply Voltage IPBS [A] IPDD [A] Figure 30. Quiescent VDD Supply Current vs. Supply Voltage 100 12 16 Supply Voltage [V] Figure 33. Operating VBS Supply Current vs. Supply Voltage www.fairchildsemi.com 11 FAN73894 — 3-Phase Half-Bridge Gate-Drive IC Typical Characteristics (Continued) FAN73894 — 3-Phase Half-Bridge Gate-Drive IC Switching Time Definitions HINx 50% 50% (LINx) tON tR tOFF 90% tF 90% HOx (LOx) 10% 10% Figure 34. Switching Time Waveform Definitions A B C E D F HINx LINx EN Shutdown CS Shutdown FO VRCIN LOx keep high-state this event HOx Shoot-Through Prevent Shoot-Through Prevent Over-Current Protection LOx HOx keep high-state this event Figure 35. Input / Output Timing Diagram Interval B CS VCS,TH+ Interval C VCS,TH+ 50% FO 50% tCSFO VRCIN,TH VRCIN tFLTCLR 90% Any Output tCSOFF Figure 36. Detailed View of B and C Intervals During Over-Current Protection © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 www.fairchildsemi.com 12 FAN73894 — 3-Phase Half-Bridge Gate-Drive IC Applications Information 1. Dead Time HINx Dead time is automatically inserted whenever the dead time of the external two input signals (between HINx and LINx signals) is shorter than internal fixed dead times (DT1 and DT2). Otherwise, external dead times larger than internal dead times are not modified by the gate driver and internal dead-time waveform definition is shown in Figure 37. LINx Shoot-Through Prevent HOx LINx After DT 50% 50% LOx HINx After DT Example A 50% 50% HINx LOx DT1 HOx DT2 50% LINx 50% Shoot-Through Prevent Figure 37. Internal Dead-Time Definitions 2. Protection Function HOx 2.1 Fault Out ( FO ) and Under-Voltage Lockout The high- and low-side drivers include under-voltage lockout (UVLO) protection circuitry that monitors the supply voltage for VDD and VBS independently. It can be designed to prevent malfunction when VDD and VBS are lower than the specified threshold voltage. The UVLO hysteresis prevents chattering during power-supply transitions. Moreover, the fault signal (power supply voltage FO ) goes to LOW state to operate reliably during power-on events when the power supply (VDD) is below the under-voltage lockout high threshold voltage for the circuit (during t1 ~ t2). The UVLO circuit is not otherwise activated; shown Figure 38. If VDD is lower than 3.5V, the fault signal cannot be driven to LOW state because VDD is not enough to drive internal circuit. UVLO+ UVLOVDD < 3.5V VDD LOx Example B Figure 39. Shoot-Through Protection An interlock function is a device used to prevent both high- and low-side switches from conducting at the same time as shown Figure 40. In most applications an interlock is used to help prevent a device from harming its operator or damaging itself by when two input signals of a same leg are activated simultaneously, only one output is activated. HINx LINx Lower Voltage FO Lower Voltage HOx VRCINTH+ RCIN LOx S1 S2 S3 S4 S5 LO t0 t1 t2 t3 t4 Figure 38. Waveforms for Under-Voltage Lockout S1 : High-side first S2 : Low-side noise S3 : High-side noise S4 : Low-side first S5 : In-phase mode Figure 40. Interlock Function 2.2 Shoot-Through Protection The shoot-through protection circuitry prevents both high- and low-side switches from conducting at the same time, as shown Figure 39. © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 à First input output mode à No LOx output mode à No HOx output mode à First input output mode à No HOx output www.fairchildsemi.com 13 EN VDD LEB Input Stage ON 150K RFO To low side output FO ISOFT Fault SOFT-OFF VREF RCIN To COM VDD_UVLO iRCIN VRCIN,TH = 3.3V VRCIN,HYS= 0.7V CS_COMP Q Latch S LEB R 100K 0.5V 3.3V CRCIN CS VSS Protection Circuit 50% EN Figure 42. Over-Current Protection tEN 90% HOx LOx Figure 41. Output Enable Timing Waveform 2.4 Fault-Out ( FO ) and Over-Current Protection FAN73894 provides an integrated fault output (FO) and an adjustable fault-clear timer (tFLTCLR). There are two situations that cause the gate driver to report a fault via the FO pin. The first is an under-voltage condition of low-side gate driver supply voltage (VDD) and the second is when the current-sense pin (CS) recognizes a fault. If a fault condition occurs, the FO pin is internally pulled to COM, the fault-clear timer is activated, and all outputs (HO1, 2, 3 and LO1, 2, 3) of the gate driver are turned off. The fault output stays LOW until the fault condition has been removed and the fault-clear timer expires. Once the fault-clear timer expires, the voltage on the FO pin returns to pull-up voltage. The fault-clear time (tFLTCLR) is determined by an internal current source (IRCIN=5 A) and an external CRCIN at the RCIN pin, as shown as: t FLTCLR C RCIN VRCIN,TH I RCIN [s ] (1) The RDSRCIN of the MOSFET is a characteristic discharge curve with respect to the external capacitor CRCIN. The time constant is defined by the external capacitor CRCIN and the RDSRCIN of the MOSFET. The output of current-sense comparator (CS_COMP) passes a noise filter, which inhibits an over-current shutdown caused by parasitic voltage spikes of VCS. This corresponds to a voltage level at the comparator of VCSTH+ - VCSHYS= 500 mV - 60 mV =440 mV, where VCSHYS=60 mV is the hysteresis of the current comparator (CS_COMP), as shown in Figure 42. © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 Figure 43 shows the waveform definitions of RCIN, FO , and the low-side driver; which uses a soft turn-off method when an under-voltage condition of the low-side gate driver supply voltage (VDD) or the current-sense pin (CS) recognizes a fault. If a fault condition occurs, the FO Pin is internally pulled to COM and all outputs (HO1,2,3 and LO1,2,3) of the gate driver are turned off. Low-side outputs decline linearly by the internal sink current source (ISOFT=40 mA) for soft turn-off, as shown in Figure 43. LINx Leading Edge Branking Time VCSC 440mV 500mV tCSBLT FO tFLTCLR tCSFO VRCINTH+ VRCIN LO tCSOFF 90% Figure 43. RCIN and Fault-Clear Waveform Definition 3. Noise Filter 3.1 Input Noise Filter Figure 44 shows the input noise filter method, which has symmetry duration between the input signal (t INPUT) and the output signal (tOUTPUT) and helps to reject noise spikes and short pulses. This input filter is applied to the HINx, LINx, and EN inputs. The upper pair of waveforms (Example A) shows input signal duration (tINPUT) much longer than input filter time (tFLTIN); it is approximately the same duration between the input signal time (tINPUT) and the output signal time (tOUTPUT). The lower pair of waveforms (Example B) shows an input signal time (tINPUT) slightly longer than input filter time (tFLTIN); it is approximately the same duration between input signal time (tINPUT) and the output signal time (tOUTPUT). www.fairchildsemi.com 14 FAN73894 — 3-Phase Half-Bridge Gate-Driver IC 2.3 Enable Input When the EN pin is in HIGH state, the gate driver operates normally. When a condition occurs that should shut down the gate driver, the EN pin should be LOW. The enable circuitry has an input filter; the minimum input duration is specified by tFLTIN (typically 250 ns). Figure 46 shows the characteristics of the input filters while receiving narrow ON and OFF pulses. If input signal pulse duration, PW IN, is less than input filter time, tFLTIN; the output pulse, PW OUT, is zero. The input signal is rejected by input filter. Once the input signal pulse duration, PW IN, exceeds input filter time, tFLTIN, the output pulse durations, PW OUT, matches the input pulse durations, PW IN. FAN73894 input filter time, tFLTIN, is about 250 ns for the high- and low-side outputs. tFLTIN tINPUT tOUTPUT OUTx 1000 tFLTIN Input Pulse Output Pulse 900 tINPUT tOUTPUT Output duration is same as input duration OUTx Figure 44. Input Noise Filter Definition 3.2. Short-Pulsed Input Noise Rejection Method The input filter circuitry provides protection against short-pulsed input signals ( HINx , LINx , and EN) on the input signal lines by applied noise signal. Output Pulse Width [ns] Example B INx 700 600 500 400 300 200 If the input signal duration is less than input filter time (tFLTIN), the output does not change states. Example A and B of the Figure 45 show the input and output waveforms with short-pulsed noise spikes with a duration less than input filter time; the output does not change states. 800 100 0 100 200 300 400 500 600 700 800 900 1000 Input Pulse Width [ns] Figure 46. Input Filter Characteristic of Narrow ON Example A INx tFLTIN tFLTIN tFLTIN tFLTIN tFLTIN tFLTIN OUTx (LOW) Example B INx OUTx (HIGH) Figure 45. Noise Rejecting Input Filter Definition © 2015 Fairchild Semiconductor Corporation FAN73894 • Rev.1.1 www.fairchildsemi.com 15 FAN73894 — 3-Phase Half-Bridge Gate-Driver IC Example A INx A 16.51 16.510 28 15 B 10.325 9.400 2.00 1 14 0.51 0.35 1.27 0.635 1.270 0.25 M 0.60 C B A TOP VIEW RECOMMENDED LAND PATTERN 2.65 MAX 0.75 0.25 (R0.10) C GAGE PLANE 0.10 C SEATING PLANE (R0.10) SIDE VIEW 28 0.25 28 28 SEATING PLANE 0.40~1.27 (1.40) DETAIL A SCALE: 2:1 NOTES: PIN #1 INDICATOR PIN #1 INDICATOR A. THIS PACKAGE DOES NOT FULLY CONFORM TO JEDEC REGISTRATION, MS-013. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009. 1 OPTION 1 HALF MOON & PIN 1 1 OPTION 2 HALF MOON ONLY 1 PIN #1 INDICATOR SEE DETAIL A 0.33 0.20 SEATING PLANE PIN#1 IDENTIFICATION OPTIONS D. DIMENSIONS DO NOT INCLUDE MOLD FLASH AND BURRS. OPTION 3 PIN 1 ONLY E. LAND PATTERN STANDARD : SOIC127P1030X265-28N F. DRAWING FILENAME: MKT-M28Brev4. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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