Ramtron FM1107 Nonvolatile 3v dual state saver Datasheet

Preliminary
FM1107
Nonvolatile 3V Dual State Saver
Features
Nonvolatile State Saver
• Logic States Retained in Absence of Power
• Outputs Automatically Restored at Power-up
• Unlimited Number of State Changes
• Max tPD 50ns at 2.7V
• Max Frequency 1 MHz
Low Power Operation
• Supply voltage of 2.7V to 3.6V
• 0.5 µA Standby Current
Overview
Pin Configuration
The FM1107 is an innovative FRAM-based device
that stores inputs like conventional logic and retains
the stored state in the absence of power. This product
solves three basic problems in an elegant fashion.
First, it provides continuous access to nonvolatile
system settings without performing a memory read
operation or using dedicated processor I/O pins.
Second, it allows the storage of signals that may
change frequently and possibly without notice. Third,
it allows the nonvolatile storage of a system setting
without the system overhead and extra pins of a serial
memory.
Functionally, the inputs are stored and passed to the
output on the rising edge of the clock CLK. This
unique product serves a variety of applications. Here
are a few applications:
!
!
!
!
!
Control relays or valves with automatic setting
on power-up without processor intervention
Interface to soft/momentary front-panel switch
and indicator lamp. Capture switch settings and
drive LEDs without processor intervention
Replaces jumpers & control signal routing
Initialize state of I/O card signals
Eliminate the overhead of serial memory for
systems needing only a bit of data
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.2
Aug. 2007
Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin “Green”/RoHS SOT-23 Package
Pin Names
DN
QN
EN
CLK
VDD
VSS
Function
Data In
Data Out
Enable
Clock
Supply Voltage
Ground
Ordering Information
FM1107
Dual State Saver,
8-pin “Green”/RoHS SOT-23
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 8
FM1107 NV Dual State Saver
Block Diagram and Truth Table
DN
NV
State
Saver
CLK
EN
QN
EN
H
H
H
L
L
H
X
↑
Q0
INPUTS
CLK
↑
↑
H or L
X
Dn
L
H
X
X
OUTPUT
Qn
L
H
Q0
Hi-Z
Low voltage level
High voltage level
Don’t Care
CLK rising edge
Previous output state before CLK ↑
Pin Descriptions
Pin Name
D 0, D 1
Q 0, Q 1
CLK
EN
VDD
VSS
Rev. 1.2
Aug. 2007
I/O
I
O
I
I
Supply
Supply
Description
Data inputs
Data outputs
Clock: On a rising edge of CLK, the DN inputs are transferred to the QN outputs. While
CLK is high or low, the QN outputs do not change regardless of the state of the data
inputs. See truth table.
Enable. This active-high input enables the device. When low, inputs are ignored and
updates to the nonvolatile cells are prevented. When high, the device operates
normally. Do not tie this pin to VDD.
Power Supply (2.7V to 3.6V)
Ground
Page 2 of 8
FM1107 NV Dual State Saver
Description
Use of Enable Pin
Nonvolatile storage applied to logic is a
revolutionary concept. The FM1107 simplifies the
design of system control functions. This product is
unique because it remembers the stored output
values in the absence of power. Any change in the
latched state is automatically written to a nonvolatile
ferroelectric latch. This function is possible due to
the fast write time and extremely high write
endurance of the underlying ferroelectric memory
technology.
The FM1107 has an enable pin that is intended to be
used in conjunction with a system reset. An activelow reset may be tied directly to the EN pin. At
power-up, /RESET will be held low for some time
during which the data input and CLK pins will be
ignored. Once the system comes out of reset and EN
goes high, the outputs QN drive to the state that were
previously latched and the device operates normally.
When the EN pin is low, the outputs QN are tristated.
The enable pin must not be tied to VDD because the
device does not have any power management circuits
to monitor VDD. The enable input must be held low
during power cycles.
Rev. 1.2
Aug. 2007
Page 3 of 8
FM1107 NV Dual State Saver
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
VDD
Power Supply Voltage with respect to VSS
VIN
Voltage on any signal pin with respect to VSS
TSTG
TLEAD
Storage temperature
Lead temperature (Soldering, 10 seconds)
Ratings
-1.0V to +5.0V
-1.0V to +5.0V
and VIN < VDD+1.0V
-55°C to + 125°C
300° C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
Notes
VDD
Power Supply Voltage
2.7
3.6
V
ISB
Standby Current
0.5
µA
1
CPD
Power Dissipation Capacitance
165
pF
2
ILO
Output Leakage Current
3
±1
µA
VIL
Input Low Voltage
-0.3
0.3 VDD
V
VIH
Input High Voltage
0.7 VDD
VDD + 0.3
V
VOH
Output High Voltage
@ IOH = -1 mA
VDD – 0.5
V
VOL
Output Low Voltage
0.4
V
@ IOL = 1 mA (VDD=2.7V)
@ IOL = 10 mA (VDD=2.7V)
0.8
V
VHYS
Input Hysteresis (CLK, DN, EN)
0.05 VDD
V
4
Notes
1. CLK = VSS, all other inputs at VDD or VSS.
2. To calculate device power dissipation, PD = CPD*VDD2*fi + CL*VDD2*fo, where fi is the input clk freq, fo is the output freq,
3.
4.
and CL is the output load capacitance. Active current IDD may be calculated as IDD = CPD*VDD*fi, assuming outputs are
floating.
VIN or VOUT = VSS to VDD.
This parameter is characterized but not tested.
Rev. 1.2
Aug. 2007
Page 4 of 8
FM1107 NV Dual State Saver
AC Parameters (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V, CL = 30 pF unless otherwise specified)
Symbol
Parameter
Min
Max
fMAX
Maximum Clock Frequency
1
tLOW
CLK Low Period
0.3
tHIGH
CLK High Period
0.3
tPD
Propagation delay CLK to QN
50
tHZ
EN Low to QN Hi-Z
25
tR
Input Rise Time
100
tF
Input Fall Time
100
tDS
Data (DN) Setup Time to CLK ↑
5
tDH
Data (DN) Hold Time after CLK ↑
10
tEHD
EN Hold Time (EN High after CLK ↑)
0
the
EN High Time
5
tEL
EN Low Time
2
Notes
1. This parameter is characterized but not tested.
Units
MHz
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
Power Cycling and Data Retention (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V, unless otherwise specified)
Symbol
Parameter
Min
Max
Units
Nonvolatile Data Retention Time
45
years
tVDR
VDD Rise Time
0.1
µs/V
tVDF
VDD Fall Time
0.1
µs/V
tRES
EN High to QN Restore Time
0.5
µs
tPDS
EN Low to Power Down Time
1
µs
tEHFC
EN High to First Clock (CLK ↑) after Power Up
4
µs
Notes
1.
2.
3.
1
1
1
Notes
1
1
2
3
Slope measured at any point on VDD waveform.
After power up, when EN goes high the nonvolatile latches are read and the values restored to the outputs QN.
After power up, this is the minimum time required before a state change operation may occur. EN and VDD may be
coincident at power up, and in this case tEHFC time is referenced to VDD (min) and CLK ↑.
Capacitance (TA = 25° C , f=1.0 MHz, VDD = 3.3V)
Symbol
Parameter
CI
Input Capacitance
Notes
1.
Notes
Min
-
Max
8
Units
pF
Notes
1
This parameter is characterized but not tested.
Rev. 1.2
Aug. 2007
Page 5 of 8
FM1107 NV Dual State Saver
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load Capacitance
0.1 VDD to 0.9 VDD
10 ns
0.5 VDD
30pF
FM1107 Signal Timing
tEL
EN
1/fMAX
tEHD
tHIGH
tLOW
tEH
CLK
tDS
tHZ
tDH
D1
D0
DN
tPD
QN
tRES
tPD
previous
Q0
Q1
Q1
t=0
Power Cycle Timing
D8
DLAST
Q7
Q8
QLAST
tPDS
~
~
EN
VDD
D0
~
~
QN
D7
D1
~
~
DN
~
~
CLK
VDD (MIN)
QLAST
Q0
Q1
tRES
tEHFC
VDD (MIN)
~
~
Rev. 1.2
Aug. 2007
Page 6 of 8
FM1107 NV Dual State Saver
Mechanical Drawing
8-pin SOT-23
1.75
1.50
3.00
2.60
Pin 1
3.00
2.80
0.70
0.50
1.30
0.90
1.45
0.90
SEATING PLANE
0.65 BSC
0.38
0.28
0° to 8°
0.10
Note: All dimensions in millimeters.
SOT-23 Package Marking Scheme
PYLL
Legend:
P= Product code: X=1105, Y=1106, Z=1107
Y= Year: A=2007, B=2008, C=2009, etc.
LL= Lot code: A0=lot 1, A1=lot 2, etc.
Example: “Green” SOT23 package, FM1107, Year 2007, Lot 0001
ZAA0
Rev. 1.2
Aug. 2007
Page 7 of 8
FM1107 NV Dual State Saver
Revision History
Revision
1.0
1.1
1.2
Rev. 1.2
Aug. 2007
Date
5/17/07
8/6/07
8/22/07
Summary
Initial Release.
Added pin names to Input Hysteresis spec. Fixed Retention Time typo.
Reduced ISB spec.
Page 8 of 8
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